1 /* 2 * BCM43XX Sonics SiliconBackplane PCMCIA core hardware definitions. 3 * 4 * Copyright (C) 1999-2019, Broadcom. 5 * 6 * Unless you and Broadcom execute a separate written software license 7 * agreement governing use of this software, this software is licensed to you 8 * under the terms of the GNU General Public License version 2 (the "GPL"), 9 * available at http://www.broadcom.com/licenses/GPLv2.php, with the 10 * following added to such license: 11 * 12 * As a special exception, the copyright holders of this software give you 13 * permission to link this software with independent modules, and to copy and 14 * distribute the resulting executable under terms of your choice, provided that 15 * you also meet, for each linked independent module, the terms and conditions 16 * of the license of that module. An independent module is a module which is 17 * not derived from this software. The special exception does not apply to any 18 * modifications of the software. 19 * 20 * Notwithstanding the above, under no circumstances may you combine this 21 * software in any way with any other Broadcom software provided under a license 22 * other than the GPL, without Broadcom's express prior written consent. 23 * 24 * 25 * <<Broadcom-WL-IPTag/Open:>> 26 * 27 * $Id: sbpcmcia.h 647676 2016-07-07 02:59:05Z $ 28 */ 29 30 #ifndef _SBPCMCIA_H 31 #define _SBPCMCIA_H 32 33 /* All the addresses that are offsets in attribute space are divided 34 * by two to account for the fact that odd bytes are invalid in 35 * attribute space and our read/write routines make the space appear 36 * as if they didn't exist. Still we want to show the original numbers 37 * as documented in the hnd_pcmcia core manual. 38 */ 39 40 /* PCMCIA Function Configuration Registers */ 41 #define PCMCIA_FCR (0x700 / 2) 42 43 #define FCR0_OFF 0 44 #define FCR1_OFF (0x40 / 2) 45 #define FCR2_OFF (0x80 / 2) 46 #define FCR3_OFF (0xc0 / 2) 47 48 #define PCMCIA_FCR0 (0x700 / 2) 49 #define PCMCIA_FCR1 (0x740 / 2) 50 #define PCMCIA_FCR2 (0x780 / 2) 51 #define PCMCIA_FCR3 (0x7c0 / 2) 52 53 /* Standard PCMCIA FCR registers */ 54 55 #define PCMCIA_COR 0 56 57 #define COR_RST 0x80 58 #define COR_LEV 0x40 59 #define COR_IRQEN 0x04 60 #define COR_BLREN 0x01 61 #define COR_FUNEN 0x01 62 63 #define PCICIA_FCSR (2 / 2) 64 #define PCICIA_PRR (4 / 2) 65 #define PCICIA_SCR (6 / 2) 66 #define PCICIA_ESR (8 / 2) 67 68 #define PCM_MEMOFF 0x0000 69 #define F0_MEMOFF 0x1000 70 #define F1_MEMOFF 0x2000 71 #define F2_MEMOFF 0x3000 72 #define F3_MEMOFF 0x4000 73 74 /* Memory base in the function fcr's */ 75 #define MEM_ADDR0 (0x728 / 2) 76 #define MEM_ADDR1 (0x72a / 2) 77 #define MEM_ADDR2 (0x72c / 2) 78 79 /* PCMCIA base plus Srom access in fcr0: */ 80 #define PCMCIA_ADDR0 (0x072e / 2) 81 #define PCMCIA_ADDR1 (0x0730 / 2) 82 #define PCMCIA_ADDR2 (0x0732 / 2) 83 84 #define MEM_SEG (0x0734 / 2) 85 #define SROM_CS (0x0736 / 2) 86 #define SROM_DATAL (0x0738 / 2) 87 #define SROM_DATAH (0x073a / 2) 88 #define SROM_ADDRL (0x073c / 2) 89 #define SROM_ADDRH (0x073e / 2) 90 #define SROM_INFO2 (0x0772 / 2) /* Corerev >= 2 && <= 5 */ 91 #define SROM_INFO (0x07be / 2) /* Corerev >= 6 */ 92 93 /* Values for srom_cs: */ 94 #define SROM_IDLE 0 95 #define SROM_WRITE 1 96 #define SROM_READ 2 97 #define SROM_WEN 4 98 #define SROM_WDS 7 99 #define SROM_DONE 8 100 101 /* Fields in srom_info: */ 102 #define SRI_SZ_MASK 0x03 103 #define SRI_BLANK 0x04 104 #define SRI_OTP 0x80 105 106 #define SROM16K_BANK_SEL_MASK (3 << 11) 107 #define SROM16K_BANK_SHFT_MASK 11 108 #define SROM16K_ADDR_SEL_MASK ((1 << SROM16K_BANK_SHFT_MASK) - 1) 109 #define SROM_PRSNT_MASK 0x1 110 #define SROM_SUPPORT_SHIFT_MASK 30 111 #define SROM_SUPPORTED (0x1 << SROM_SUPPORT_SHIFT_MASK) 112 #define SROM_SIZE_MASK 0x00000006 113 #define SROM_SIZE_2K 2 114 #define SROM_SIZE_512 1 115 #define SROM_SIZE_128 0 116 #define SROM_SIZE_SHFT_MASK 1 117 118 /* Standard tuples we know about */ 119 120 #define CISTPL_NULL 0x00 121 #define CISTPL_END 0xff /* End of the CIS tuple chain */ 122 123 #define CISTPL_BRCM_HNBU 0x80 124 125 #define HNBU_BOARDREV 0x02 /* One byte board revision */ 126 127 #define HNBU_BOARDTYPE 0x1b /* 2 bytes; boardtype */ 128 129 #define HNBU_HNBUCIS 0x1d /* what follows is proprietary HNBU CIS format */ 130 131 /* sbtmstatelow */ 132 #define SBTML_INT_ACK 0x40000 /* ack the sb interrupt */ 133 #define SBTML_INT_EN 0x20000 /* enable sb interrupt */ 134 135 /* sbtmstatehigh */ 136 #define SBTMH_INT_STATUS 0x40000 /* sb interrupt status */ 137 #endif /* _SBPCMCIA_H */ 138