1 /* 2 * SiliconBackplane System Memory core 3 * 4 * Copyright (C) 1999-2019, Broadcom. 5 * 6 * Unless you and Broadcom execute a separate written software license 7 * agreement governing use of this software, this software is licensed to you 8 * under the terms of the GNU General Public License version 2 (the "GPL"), 9 * available at http://www.broadcom.com/licenses/GPLv2.php, with the 10 * following added to such license: 11 * 12 * As a special exception, the copyright holders of this software give you 13 * permission to link this software with independent modules, and to copy and 14 * distribute the resulting executable under terms of your choice, provided that 15 * you also meet, for each linked independent module, the terms and conditions 16 * of the license of that module. An independent module is a module which is 17 * not derived from this software. The special exception does not apply to any 18 * modifications of the software. 19 * 20 * Notwithstanding the above, under no circumstances may you combine this 21 * software in any way with any other Broadcom software provided under a license 22 * other than the GPL, without Broadcom's express prior written consent. 23 * 24 * 25 * <<Broadcom-WL-IPTag/Open:>> 26 * 27 * $Id: sbsysmem.h 563229 2015-06-12 04:50:06Z $ 28 */ 29 30 #ifndef _SBSYSMEM_H 31 #define _SBSYSMEM_H 32 33 #ifndef _LANGUAGE_ASSEMBLY 34 35 /* cpp contortions to concatenate w/arg prescan */ 36 #ifndef PAD 37 #define _PADLINE(line) pad##line 38 #define _XSTR(line) _PADLINE(line) 39 #define PAD _XSTR(__LINE__) 40 #endif /* PAD */ 41 42 /* sysmem core registers */ 43 typedef volatile struct sysmemregs { 44 uint32 coreinfo; 45 uint32 bwalloc; 46 uint32 extracoreinfo; 47 uint32 biststat; 48 uint32 bankidx; 49 uint32 standbyctrl; 50 51 uint32 errlogstatus; 52 uint32 errlogaddr; 53 54 uint32 cambankidx; 55 uint32 cambankstandbyctrl; 56 uint32 cambankpatchctrl; 57 uint32 cambankpatchtblbaseaddr; 58 uint32 cambankcmdreg; 59 uint32 cambankdatareg; 60 uint32 cambankmaskreg; 61 uint32 PAD[1]; 62 uint32 bankinfo; 63 uint32 PAD[15]; 64 uint32 extmemconfig; 65 uint32 extmemparitycsr; 66 uint32 extmemparityerrdata; 67 uint32 extmemparityerrcnt; 68 uint32 extmemwrctrlandsize; 69 uint32 PAD[84]; 70 uint32 workaround; 71 uint32 pwrctl; 72 uint32 PAD[133]; 73 uint32 sr_control; 74 uint32 sr_status; 75 uint32 sr_address; 76 uint32 sr_data; 77 } sysmemregs_t; 78 79 #endif /* _LANGUAGE_ASSEMBLY */ 80 81 /* Register offsets */ 82 #define SR_COREINFO 0x00 83 #define SR_BWALLOC 0x04 84 #define SR_BISTSTAT 0x0c 85 #define SR_BANKINDEX 0x10 86 #define SR_BANKSTBYCTL 0x14 87 #define SR_PWRCTL 0x1e8 88 89 /* Coreinfo register */ 90 #define SRCI_PT_MASK 0x00070000 /* port type[18:16] */ 91 #define SRCI_PT_SHIFT 16 92 /* port types : SRCI_PT_<processorPT>_<backplanePT> */ 93 #define SRCI_PT_OCP_OCP 0 94 #define SRCI_PT_AXI_OCP 1 95 #define SRCI_PT_ARM7AHB_OCP 2 96 #define SRCI_PT_CM3AHB_OCP 3 97 #define SRCI_PT_AXI_AXI 4 98 #define SRCI_PT_AHB_AXI 5 99 100 #define SRCI_LSS_MASK 0x00f00000 101 #define SRCI_LSS_SHIFT 20 102 #define SRCI_LRS_MASK 0x0f000000 103 #define SRCI_LRS_SHIFT 24 104 105 /* In corerev 0, the memory size is 2 to the power of the 106 * base plus 16 plus to the contents of the memsize field plus 1. 107 */ 108 #define SRCI_MS0_MASK 0xf 109 #define SR_MS0_BASE 16 110 111 /* 112 * In corerev 1 the bank size is 2 ^ the bank size field plus 14, 113 * the memory size is number of banks times bank size. 114 * The same applies to rom size. 115 */ 116 #define SYSMEM_SRCI_ROMNB_MASK 0x3e0 117 #define SYSMEM_SRCI_ROMNB_SHIFT 5 118 #define SYSMEM_SRCI_SRNB_MASK 0x1f 119 #define SYSMEM_SRCI_SRNB_SHIFT 0 120 121 /* Standby control register */ 122 #define SRSC_SBYOVR_MASK 0x80000000 123 #define SRSC_SBYOVR_SHIFT 31 124 #define SRSC_SBYOVRVAL_MASK 0x60000000 125 #define SRSC_SBYOVRVAL_SHIFT 29 126 #define SRSC_SBYEN_MASK 0x01000000 127 #define SRSC_SBYEN_SHIFT 24 128 129 /* Power control register */ 130 #define SRPC_PMU_STBYDIS_MASK 0x00000010 131 #define SRPC_PMU_STBYDIS_SHIFT 4 132 #define SRPC_STBYOVRVAL_MASK 0x00000008 133 #define SRPC_STBYOVRVAL_SHIFT 3 134 #define SRPC_STBYOVR_MASK 0x00000007 135 #define SRPC_STBYOVR_SHIFT 0 136 137 /* Extra core capability register */ 138 #define SRECC_NUM_BANKS_MASK 0x000000F0 139 #define SRECC_NUM_BANKS_SHIFT 4 140 #define SRECC_BANKSIZE_MASK 0x0000000F 141 #define SRECC_BANKSIZE_SHIFT 0 142 143 #define SRECC_BANKSIZE(value) (1 << (value)) 144 145 /* CAM bank patch control */ 146 #define SRCBPC_PATCHENABLE 0x80000000 147 148 #define SRP_ADDRESS 0x0001FFFC 149 #define SRP_VALID 0x8000 150 151 /* CAM bank command reg */ 152 #define SRCMD_WRITE 0x00020000 153 #define SRCMD_READ 0x00010000 154 #define SRCMD_DONE 0x80000000 155 156 #define SRCMD_DONE_DLY 1000 157 158 /* bankidx and bankinfo reg defines */ 159 #define SYSMEM_BANKINFO_SZMASK 0x7f 160 #define SYSMEM_BANKIDX_ROM_MASK 0x80 161 162 #define SYSMEM_BANKINFO_REG 0x40 163 #define SYSMEM_BANKIDX_REG 0x10 164 #define SYSMEM_BANKINFO_STDBY_MASK 0x200 165 #define SYSMEM_BANKINFO_STDBY_TIMER 0x400 166 167 #define SYSMEM_BANKINFO_SLPSUPP_SHIFT 14 168 #define SYSMEM_BANKINFO_SLPSUPP_MASK 0x4000 169 #define SYSMEM_BANKINFO_PDASZ_SHIFT 16 170 #define SYSMEM_BANKINFO_PDASZ_MASK 0x001F0000 171 172 /* extracoreinfo register */ 173 #define SYSMEM_DEVRAMBANK_MASK 0xF000 174 #define SYSMEM_DEVRAMBANK_SHIFT 12 175 176 /* bank info to calculate bank size */ 177 #define SYSMEM_BANKINFO_SZBASE 8192 178 #define SYSMEM_BANKSIZE_SHIFT 13 /* SYSMEM_BANKINFO_SZBASE */ 179 180 #endif /* _SBSYSMEM_H */ 181