1 /* 2 * SDIO spec header file 3 * Protocol and standard (common) device definitions 4 * 5 * Copyright (C) 1999-2019, Broadcom. 6 * 7 * Unless you and Broadcom execute a separate written software license 8 * agreement governing use of this software, this software is licensed to you 9 * under the terms of the GNU General Public License version 2 (the "GPL"), 10 * available at http://www.broadcom.com/licenses/GPLv2.php, with the 11 * following added to such license: 12 * 13 * As a special exception, the copyright holders of this software give you 14 * permission to link this software with independent modules, and to copy and 15 * distribute the resulting executable under terms of your choice, provided that 16 * you also meet, for each linked independent module, the terms and conditions 17 * of the license of that module. An independent module is a module which is 18 * not derived from this software. The special exception does not apply to any 19 * modifications of the software. 20 * 21 * Notwithstanding the above, under no circumstances may you combine this 22 * software in any way with any other Broadcom software provided under a license 23 * other than the GPL, without Broadcom's express prior written consent. 24 * 25 * 26 * <<Broadcom-WL-IPTag/Open:>> 27 * 28 * $Id: sdio.h 689948 2017-03-14 05:21:03Z $ 29 */ 30 31 #ifndef _SDIO_H 32 #define _SDIO_H 33 34 #ifdef BCMSDIO 35 36 /* CCCR structure for function 0 */ 37 typedef volatile struct { 38 uint8 cccr_sdio_rev; /* RO, cccr and sdio revision */ 39 uint8 sd_rev; /* RO, sd spec revision */ 40 uint8 io_en; /* I/O enable */ 41 uint8 io_rdy; /* I/O ready reg */ 42 uint8 intr_ctl; /* Master and per function interrupt enable control */ 43 uint8 intr_status; /* RO, interrupt pending status */ 44 uint8 io_abort; /* read/write abort or reset all functions */ 45 uint8 bus_inter; /* bus interface control */ 46 uint8 capability; /* RO, card capability */ 47 48 uint8 cis_base_low; /* 0x9 RO, common CIS base address, LSB */ 49 uint8 cis_base_mid; 50 uint8 cis_base_high; /* 0xB RO, common CIS base address, MSB */ 51 52 /* suspend/resume registers */ 53 uint8 bus_suspend; /* 0xC */ 54 uint8 func_select; /* 0xD */ 55 uint8 exec_flag; /* 0xE */ 56 uint8 ready_flag; /* 0xF */ 57 58 uint8 fn0_blk_size[2]; /* 0x10(LSB), 0x11(MSB) */ 59 60 uint8 power_control; /* 0x12 (SDIO version 1.10) */ 61 62 uint8 speed_control; /* 0x13 */ 63 } sdio_regs_t; 64 65 /* SDIO Device CCCR offsets */ 66 #define SDIOD_CCCR_REV 0x00 67 #define SDIOD_CCCR_SDREV 0x01 68 #define SDIOD_CCCR_IOEN 0x02 69 #define SDIOD_CCCR_IORDY 0x03 70 #define SDIOD_CCCR_INTEN 0x04 71 #define SDIOD_CCCR_INTPEND 0x05 72 #define SDIOD_CCCR_IOABORT 0x06 73 #define SDIOD_CCCR_BICTRL 0x07 74 #define SDIOD_CCCR_CAPABLITIES 0x08 75 #define SDIOD_CCCR_CISPTR_0 0x09 76 #define SDIOD_CCCR_CISPTR_1 0x0A 77 #define SDIOD_CCCR_CISPTR_2 0x0B 78 #define SDIOD_CCCR_BUSSUSP 0x0C 79 #define SDIOD_CCCR_FUNCSEL 0x0D 80 #define SDIOD_CCCR_EXECFLAGS 0x0E 81 #define SDIOD_CCCR_RDYFLAGS 0x0F 82 #define SDIOD_CCCR_BLKSIZE_0 0x10 83 #define SDIOD_CCCR_BLKSIZE_1 0x11 84 #define SDIOD_CCCR_POWER_CONTROL 0x12 85 #define SDIOD_CCCR_SPEED_CONTROL 0x13 86 #define SDIOD_CCCR_UHSI_SUPPORT 0x14 87 #define SDIOD_CCCR_DRIVER_STRENGTH 0x15 88 #define SDIOD_CCCR_INTR_EXTN 0x16 89 90 /* Broadcom extensions (corerev >= 1) */ 91 #define SDIOD_CCCR_BRCM_CARDCAP 0xf0 92 #define SDIOD_CCCR_BRCM_CARDCAP_CMD14_SUPPORT 0x02 93 #define SDIOD_CCCR_BRCM_CARDCAP_CMD14_EXT 0x04 94 #define SDIOD_CCCR_BRCM_CARDCAP_CMD_NODEC 0x08 95 #define SDIOD_CCCR_BRCM_CARDCTL 0xf1 96 #define SDIOD_CCCR_BRCM_SEPINT 0xf2 97 98 /* cccr_sdio_rev */ 99 #define SDIO_REV_SDIOID_MASK 0xf0 /* SDIO spec revision number */ 100 #define SDIO_REV_CCCRID_MASK 0x0f /* CCCR format version number */ 101 #define SDIO_SPEC_VERSION_3_0 0x40 /* SDIO spec version 3.0 */ 102 103 /* sd_rev */ 104 #define SD_REV_PHY_MASK 0x0f /* SD format version number */ 105 106 /* io_en */ 107 #define SDIO_FUNC_ENABLE_1 0x02 /* function 1 I/O enable */ 108 #define SDIO_FUNC_ENABLE_2 0x04 /* function 2 I/O enable */ 109 #if defined(BT_OVER_SDIO) 110 #define SDIO_FUNC_ENABLE_3 0x08 /* function 2 I/O enable */ 111 #define SDIO_FUNC_DISABLE_3 0xF0 /* function 2 I/O enable */ 112 #endif /* defined (BT_OVER_SDIO) */ 113 114 /* io_rdys */ 115 #define SDIO_FUNC_READY_1 0x02 /* function 1 I/O ready */ 116 #define SDIO_FUNC_READY_2 0x04 /* function 2 I/O ready */ 117 118 /* intr_ctl */ 119 #define INTR_CTL_MASTER_EN 0x1 /* interrupt enable master */ 120 #define INTR_CTL_FUNC1_EN 0x2 /* interrupt enable for function 1 */ 121 #define INTR_CTL_FUNC2_EN 0x4 /* interrupt enable for function 2 */ 122 #if defined(BT_OVER_SDIO) 123 #define INTR_CTL_FUNC3_EN 0x8 /* interrupt enable for function 3 */ 124 #endif /* defined (BT_OVER_SDIO) */ 125 /* intr_status */ 126 #define INTR_STATUS_FUNC1 0x2 /* interrupt pending for function 1 */ 127 #define INTR_STATUS_FUNC2 0x4 /* interrupt pending for function 2 */ 128 129 /* io_abort */ 130 #define IO_ABORT_RESET_ALL 0x08 /* I/O card reset */ 131 #define IO_ABORT_FUNC_MASK 0x07 /* abort selction: function x */ 132 133 /* bus_inter */ 134 #define BUS_CARD_DETECT_DIS 0x80 /* Card Detect disable */ 135 #define BUS_SPI_CONT_INTR_CAP 0x40 /* support continuous SPI interrupt */ 136 #define BUS_SPI_CONT_INTR_EN 0x20 /* continuous SPI interrupt enable */ 137 #define BUS_SD_DATA_WIDTH_MASK 0x03 /* bus width mask */ 138 #define BUS_SD_DATA_WIDTH_4BIT 0x02 /* bus width 4-bit mode */ 139 #define BUS_SD_DATA_WIDTH_1BIT 0x00 /* bus width 1-bit mode */ 140 141 /* capability */ 142 #define SDIO_CAP_4BLS 0x80 /* 4-bit support for low speed card */ 143 #define SDIO_CAP_LSC 0x40 /* low speed card */ 144 #define SDIO_CAP_E4MI \ 145 0x20 /* enable interrupt between block of data in 4-bit mode */ 146 #define SDIO_CAP_S4MI \ 147 0x10 /* support interrupt between block of data in 4-bit mode */ 148 #define SDIO_CAP_SBS 0x08 /* support suspend/resume */ 149 #define SDIO_CAP_SRW 0x04 /* support read wait */ 150 #define SDIO_CAP_SMB 0x02 /* support multi-block transfer */ 151 #define SDIO_CAP_SDC \ 152 0x01 /* Support Direct commands during multi-byte transfer */ 153 154 /* power_control */ 155 #define SDIO_POWER_SMPC 0x01 /* supports master power control (RO) */ 156 #define SDIO_POWER_EMPC \ 157 0x02 /* enable master power control (allow > 200mA) (RW) */ 158 159 /* speed_control (control device entry into high-speed clocking mode) */ 160 #define SDIO_SPEED_SHS 0x01 /* supports high-speed [clocking] mode (RO) */ 161 #define SDIO_SPEED_EHS 0x02 /* enable high-speed [clocking] mode (RW) */ 162 #define SDIO_SPEED_UHSI_DDR50 0x08 163 164 /* for setting bus speed in card: 0x13h */ 165 #define SDIO_BUS_SPEED_UHSISEL_M BITFIELD_MASK(3) 166 #define SDIO_BUS_SPEED_UHSISEL_S 1 167 168 /* for getting bus speed cap in card: 0x14h */ 169 #define SDIO_BUS_SPEED_UHSICAP_M BITFIELD_MASK(3) 170 #define SDIO_BUS_SPEED_UHSICAP_S 0 171 172 /* for getting driver type CAP in card: 0x15h */ 173 #define SDIO_BUS_DRVR_TYPE_CAP_M BITFIELD_MASK(3) 174 #define SDIO_BUS_DRVR_TYPE_CAP_S 0 175 176 /* for setting driver type selection in card: 0x15h */ 177 #define SDIO_BUS_DRVR_TYPE_SEL_M BITFIELD_MASK(2) 178 #define SDIO_BUS_DRVR_TYPE_SEL_S 4 179 180 /* for getting async int support in card: 0x16h */ 181 #define SDIO_BUS_ASYNCINT_CAP_M BITFIELD_MASK(1) 182 #define SDIO_BUS_ASYNCINT_CAP_S 0 183 184 /* for setting async int selection in card: 0x16h */ 185 #define SDIO_BUS_ASYNCINT_SEL_M BITFIELD_MASK(1) 186 #define SDIO_BUS_ASYNCINT_SEL_S 1 187 188 /* brcm sepint */ 189 #define SDIO_SEPINT_MASK \ 190 0x01 /* route sdpcmdev intr onto separate pad (chip-specific) */ 191 #define SDIO_SEPINT_OE 0x02 /* 1 asserts output enable for above pad */ 192 #define SDIO_SEPINT_ACT_HI \ 193 0x04 /* use active high interrupt level instead of active low */ 194 195 /* FBR structure for function 1-7, FBR addresses and register offsets */ 196 typedef volatile struct { 197 uint8 devctr; /* device interface, CSA control */ 198 uint8 ext_dev; /* extended standard I/O device type code */ 199 uint8 pwr_sel; /* power selection support */ 200 uint8 PAD[6]; /* reserved */ 201 202 uint8 cis_low; /* CIS LSB */ 203 uint8 cis_mid; 204 uint8 cis_high; /* CIS MSB */ 205 uint8 csa_low; /* code storage area, LSB */ 206 uint8 csa_mid; 207 uint8 csa_high; /* code storage area, MSB */ 208 uint8 csa_dat_win; /* data access window to function */ 209 210 uint8 fnx_blk_size[2]; /* block size, little endian */ 211 } sdio_fbr_t; 212 213 /* Maximum number of I/O funcs */ 214 #define SDIOD_MAX_FUNCS 8 215 #define SDIOD_MAX_IOFUNCS 7 216 217 /* SDIO Device FBR Start Address */ 218 #define SDIOD_FBR_STARTADDR 0x100 219 220 /* SDIO Device FBR Size */ 221 #define SDIOD_FBR_SIZE 0x100 222 223 /* Macro to calculate FBR register base */ 224 #define SDIOD_FBR_BASE(n) ((n)*0x100) 225 226 /* Function register offsets */ 227 #define SDIOD_FBR_DEVCTR 0x00 /* basic info for function */ 228 #define SDIOD_FBR_EXT_DEV 0x01 /* extended I/O device code */ 229 #define SDIOD_FBR_PWR_SEL 0x02 /* power selection bits */ 230 231 /* SDIO Function CIS ptr offset */ 232 #define SDIOD_FBR_CISPTR_0 0x09 233 #define SDIOD_FBR_CISPTR_1 0x0A 234 #define SDIOD_FBR_CISPTR_2 0x0B 235 236 /* Code Storage Area pointer */ 237 #define SDIOD_FBR_CSA_ADDR_0 0x0C 238 #define SDIOD_FBR_CSA_ADDR_1 0x0D 239 #define SDIOD_FBR_CSA_ADDR_2 0x0E 240 #define SDIOD_FBR_CSA_DATA 0x0F 241 242 /* SDIO Function I/O Block Size */ 243 #define SDIOD_FBR_BLKSIZE_0 0x10 244 #define SDIOD_FBR_BLKSIZE_1 0x11 245 246 /* devctr */ 247 #define SDIOD_FBR_DEVCTR_DIC 0x0f /* device interface code */ 248 #define SDIOD_FBR_DECVTR_CSA 0x40 /* CSA support flag */ 249 #define SDIOD_FBR_DEVCTR_CSA_EN 0x80 /* CSA enabled */ 250 /* interface codes */ 251 #define SDIOD_DIC_NONE 0 /* SDIO standard interface is not supported */ 252 #define SDIOD_DIC_UART 1 253 #define SDIOD_DIC_BLUETOOTH_A 2 254 #define SDIOD_DIC_BLUETOOTH_B 3 255 #define SDIOD_DIC_GPS 4 256 #define SDIOD_DIC_CAMERA 5 257 #define SDIOD_DIC_PHS 6 258 #define SDIOD_DIC_WLAN 7 259 #define SDIOD_DIC_EXT 0xf /* extended device interface, read ext_dev register \ 260 */ 261 262 /* pwr_sel */ 263 #define SDIOD_PWR_SEL_SPS 0x01 /* supports power selection */ 264 #define SDIOD_PWR_SEL_EPS 0x02 /* enable power selection (low-current mode) */ 265 266 /* misc defines */ 267 #define SDIO_FUNC_0 0 268 #define SDIO_FUNC_1 1 269 #define SDIO_FUNC_2 2 270 #define SDIO_FUNC_4 4 271 #define SDIO_FUNC_5 5 272 #define SDIO_FUNC_6 6 273 #define SDIO_FUNC_7 7 274 275 #define SD_CARD_TYPE_UNKNOWN 0 /* bad type or unrecognized */ 276 #define SD_CARD_TYPE_IO 1 /* IO only card */ 277 #define SD_CARD_TYPE_MEMORY 2 /* memory only card */ 278 #define SD_CARD_TYPE_COMBO 3 /* IO and memory combo card */ 279 280 #define SDIO_MAX_BLOCK_SIZE \ 281 2048 /* maximum block size for block mode operation */ 282 #define SDIO_MIN_BLOCK_SIZE 1 /* minimum block size for block mode operation \ 283 */ 284 285 /* Card registers: status bit position */ 286 #define CARDREG_STATUS_BIT_OUTOFRANGE 31 287 #define CARDREG_STATUS_BIT_COMCRCERROR 23 288 #define CARDREG_STATUS_BIT_ILLEGALCOMMAND 22 289 #define CARDREG_STATUS_BIT_ERROR 19 290 #define CARDREG_STATUS_BIT_IOCURRENTSTATE3 12 291 #define CARDREG_STATUS_BIT_IOCURRENTSTATE2 11 292 #define CARDREG_STATUS_BIT_IOCURRENTSTATE1 10 293 #define CARDREG_STATUS_BIT_IOCURRENTSTATE0 9 294 #define CARDREG_STATUS_BIT_FUN_NUM_ERROR 4 295 296 #define SD_CMD_GO_IDLE_STATE 0 /* mandatory for SDIO */ 297 #define SD_CMD_SEND_OPCOND 1 298 #define SD_CMD_MMC_SET_RCA 3 299 #define SD_CMD_IO_SEND_OP_COND 5 /* mandatory for SDIO */ 300 #define SD_CMD_SELECT_DESELECT_CARD 7 301 #define SD_CMD_SEND_CSD 9 302 #define SD_CMD_SEND_CID 10 303 #define SD_CMD_STOP_TRANSMISSION 12 304 #define SD_CMD_SEND_STATUS 13 305 #define SD_CMD_GO_INACTIVE_STATE 15 306 #define SD_CMD_SET_BLOCKLEN 16 307 #define SD_CMD_READ_SINGLE_BLOCK 17 308 #define SD_CMD_READ_MULTIPLE_BLOCK 18 309 #define SD_CMD_WRITE_BLOCK 24 310 #define SD_CMD_WRITE_MULTIPLE_BLOCK 25 311 #define SD_CMD_PROGRAM_CSD 27 312 #define SD_CMD_SET_WRITE_PROT 28 313 #define SD_CMD_CLR_WRITE_PROT 29 314 #define SD_CMD_SEND_WRITE_PROT 30 315 #define SD_CMD_ERASE_WR_BLK_START 32 316 #define SD_CMD_ERASE_WR_BLK_END 33 317 #define SD_CMD_ERASE 38 318 #define SD_CMD_LOCK_UNLOCK 42 319 #define SD_CMD_IO_RW_DIRECT 52 /* mandatory for SDIO */ 320 #define SD_CMD_IO_RW_EXTENDED 53 /* mandatory for SDIO */ 321 #define SD_CMD_APP_CMD 55 322 #define SD_CMD_GEN_CMD 56 323 #define SD_CMD_READ_OCR 58 324 #define SD_CMD_CRC_ON_OFF 59 /* mandatory for SDIO */ 325 #define SD_ACMD_SD_STATUS 13 326 #define SD_ACMD_SEND_NUM_WR_BLOCKS 22 327 #define SD_ACMD_SET_WR_BLOCK_ERASE_CNT 23 328 #define SD_ACMD_SD_SEND_OP_COND 41 329 #define SD_ACMD_SET_CLR_CARD_DETECT 42 330 #define SD_ACMD_SEND_SCR 51 331 332 /* argument for SD_CMD_IO_RW_DIRECT and SD_CMD_IO_RW_EXTENDED */ 333 #define SD_IO_OP_READ 0 /* Read_Write: Read */ 334 #define SD_IO_OP_WRITE 1 /* Read_Write: Write */ 335 #define SD_IO_RW_NORMAL 0 /* no RAW */ 336 #define SD_IO_RW_RAW 1 /* RAW */ 337 #define SD_IO_BYTE_MODE 0 /* Byte Mode */ 338 #define SD_IO_BLOCK_MODE 1 /* BlockMode */ 339 #define SD_IO_FIXED_ADDRESS 0 /* fix Address */ 340 #define SD_IO_INCREMENT_ADDRESS 1 /* IncrementAddress */ 341 342 /* build SD_CMD_IO_RW_DIRECT Argument */ 343 #define SDIO_IO_RW_DIRECT_ARG(rw, raw, func, addr, data) \ 344 ((((rw)&1) << 31) | (((func)&0x7) << 28) | (((raw)&1) << 27) | \ 345 (((addr)&0x1FFFF) << 9) | ((data)&0xFF)) 346 347 /* build SD_CMD_IO_RW_EXTENDED Argument */ 348 #define SDIO_IO_RW_EXTENDED_ARG(rw, blk, func, addr, inc_addr, count) \ 349 ((((rw)&1) << 31) | (((func)&0x7) << 28) | (((blk)&1) << 27) | \ 350 (((inc_addr)&1) << 26) | (((addr)&0x1FFFF) << 9) | ((count)&0x1FF)) 351 352 /* SDIO response parameters */ 353 #define SD_RSP_NO_NONE 0 354 #define SD_RSP_NO_1 1 355 #define SD_RSP_NO_2 2 356 #define SD_RSP_NO_3 3 357 #define SD_RSP_NO_4 4 358 #define SD_RSP_NO_5 5 359 #define SD_RSP_NO_6 6 360 361 /* Modified R6 response (to CMD3) */ 362 #define SD_RSP_MR6_COM_CRC_ERROR 0x8000 363 #define SD_RSP_MR6_ILLEGAL_COMMAND 0x4000 364 #define SD_RSP_MR6_ERROR 0x2000 365 366 /* Modified R1 in R4 Response (to CMD5) */ 367 #define SD_RSP_MR1_SBIT 0x80 368 #define SD_RSP_MR1_PARAMETER_ERROR 0x40 369 #define SD_RSP_MR1_RFU5 0x20 370 #define SD_RSP_MR1_FUNC_NUM_ERROR 0x10 371 #define SD_RSP_MR1_COM_CRC_ERROR 0x08 372 #define SD_RSP_MR1_ILLEGAL_COMMAND 0x04 373 #define SD_RSP_MR1_RFU1 0x02 374 #define SD_RSP_MR1_IDLE_STATE 0x01 375 376 /* R5 response (to CMD52 and CMD53) */ 377 #define SD_RSP_R5_COM_CRC_ERROR 0x80 378 #define SD_RSP_R5_ILLEGAL_COMMAND 0x40 379 #define SD_RSP_R5_IO_CURRENTSTATE1 0x20 380 #define SD_RSP_R5_IO_CURRENTSTATE0 0x10 381 #define SD_RSP_R5_ERROR 0x08 382 #define SD_RSP_R5_RFU 0x04 383 #define SD_RSP_R5_FUNC_NUM_ERROR 0x02 384 #define SD_RSP_R5_OUT_OF_RANGE 0x01 385 386 #define SD_RSP_R5_ERRBITS 0xCB 387 388 /* ------------------------------------------------ 389 * SDIO Commands and responses 390 * 391 * I/O only commands are: 392 * CMD0, CMD3, CMD5, CMD7, CMD14, CMD15, CMD52, CMD53 393 * ------------------------------------------------ 394 */ 395 396 /* SDIO Commands */ 397 #define SDIOH_CMD_0 0 398 #define SDIOH_CMD_3 3 399 #define SDIOH_CMD_5 5 400 #define SDIOH_CMD_7 7 401 #define SDIOH_CMD_11 11 402 #define SDIOH_CMD_14 14 403 #define SDIOH_CMD_15 15 404 #define SDIOH_CMD_19 19 405 #define SDIOH_CMD_52 52 406 #define SDIOH_CMD_53 53 407 #define SDIOH_CMD_59 59 408 409 /* SDIO Command Responses */ 410 #define SDIOH_RSP_NONE 0 411 #define SDIOH_RSP_R1 1 412 #define SDIOH_RSP_R2 2 413 #define SDIOH_RSP_R3 3 414 #define SDIOH_RSP_R4 4 415 #define SDIOH_RSP_R5 5 416 #define SDIOH_RSP_R6 6 417 418 /* 419 * SDIO Response Error flags 420 */ 421 #define SDIOH_RSP5_ERROR_FLAGS 0xCB 422 423 /* ------------------------------------------------ 424 * SDIO Command structures. I/O only commands are: 425 * 426 * CMD0, CMD3, CMD5, CMD7, CMD15, CMD52, CMD53 427 * ------------------------------------------------ 428 */ 429 430 #define CMD5_OCR_M BITFIELD_MASK(24) 431 #define CMD5_OCR_S 0 432 433 #define CMD5_S18R_M BITFIELD_MASK(1) 434 #define CMD5_S18R_S 24 435 436 #define CMD7_RCA_M BITFIELD_MASK(16) 437 #define CMD7_RCA_S 16 438 439 #define CMD14_RCA_M BITFIELD_MASK(16) 440 #define CMD14_RCA_S 16 441 #define CMD14_SLEEP_M BITFIELD_MASK(1) 442 #define CMD14_SLEEP_S 15 443 444 #define CMD_15_RCA_M BITFIELD_MASK(16) 445 #define CMD_15_RCA_S 16 446 447 #define CMD52_DATA_M \ 448 BITFIELD_MASK(8) /* Bits [7:0] - Write Data/Stuff bits of CMD52 \ 449 */ 450 #define CMD52_DATA_S 0 451 #define CMD52_REG_ADDR_M \ 452 BITFIELD_MASK(17) /* Bits [25:9] - register address */ 453 #define CMD52_REG_ADDR_S 9 454 #define CMD52_RAW_M BITFIELD_MASK(1) /* Bit 27 - Read after Write flag \ 455 */ 456 #define CMD52_RAW_S 27 457 #define CMD52_FUNCTION_M BITFIELD_MASK(3) /* Bits [30:28] - Function number \ 458 */ 459 #define CMD52_FUNCTION_S 28 460 #define CMD52_RW_FLAG_M BITFIELD_MASK(1) /* Bit 31 - R/W flag */ 461 #define CMD52_RW_FLAG_S 31 462 463 #define CMD53_BYTE_BLK_CNT_M \ 464 BITFIELD_MASK(9) /* Bits [8:0] - Byte/Block Count of CMD53 */ 465 #define CMD53_BYTE_BLK_CNT_S 0 466 #define CMD53_REG_ADDR_M \ 467 BITFIELD_MASK(17) /* Bits [25:9] - register address */ 468 #define CMD53_REG_ADDR_S 9 469 #define CMD53_OP_CODE_M \ 470 BITFIELD_MASK(1) /* Bit 26 - R/W Operation Code */ 471 #define CMD53_OP_CODE_S 26 472 #define CMD53_BLK_MODE_M BITFIELD_MASK(1) /* Bit 27 - Block Mode */ 473 #define CMD53_BLK_MODE_S 27 474 #define CMD53_FUNCTION_M BITFIELD_MASK(3) /* Bits [30:28] - Function number \ 475 */ 476 #define CMD53_FUNCTION_S 28 477 #define CMD53_RW_FLAG_M BITFIELD_MASK(1) /* Bit 31 - R/W flag */ 478 #define CMD53_RW_FLAG_S 31 479 480 /* ------------------------------------------------------ 481 * SDIO Command Response structures for SD1 and SD4 modes 482 * ----------------------------------------------------- 483 */ 484 #define RSP4_IO_OCR_M \ 485 BITFIELD_MASK(24) /* Bits [23:0] - Card's OCR Bits [23:0] */ 486 #define RSP4_IO_OCR_S 0 487 488 #define RSP4_S18A_M BITFIELD_MASK(1) /* Bits [23:0] - Card's OCR Bits [23:0] \ 489 */ 490 #define RSP4_S18A_S 24 491 492 #define RSP4_STUFF_M BITFIELD_MASK(3) /* Bits [26:24] - Stuff bits */ 493 #define RSP4_STUFF_S 24 494 #define RSP4_MEM_PRESENT_M BITFIELD_MASK(1) /* Bit 27 - Memory present \ 495 */ 496 #define RSP4_MEM_PRESENT_S 27 497 #define RSP4_NUM_FUNCS_M \ 498 BITFIELD_MASK(3) /* Bits [30:28] - Number of I/O funcs */ 499 #define RSP4_NUM_FUNCS_S 28 500 #define RSP4_CARD_READY_M BITFIELD_MASK(1) /* Bit 31 - SDIO card ready \ 501 */ 502 #define RSP4_CARD_READY_S 31 503 504 #define RSP6_STATUS_M \ 505 BITFIELD_MASK(16) /* Bits [15:0] - Card status bits [19,22,23,12:0] \ 506 */ 507 #define RSP6_STATUS_S 0 508 #define RSP6_IO_RCA_M BITFIELD_MASK(16) /* Bits [31:16] - RCA bits[31-16] */ 509 #define RSP6_IO_RCA_S 16 510 511 #define RSP1_AKE_SEQ_ERROR_M \ 512 BITFIELD_MASK(1) /* Bit 3 - Authentication seq error */ 513 #define RSP1_AKE_SEQ_ERROR_S 3 514 #define RSP1_APP_CMD_M BITFIELD_MASK(1) /* Bit 5 - Card expects ACMD */ 515 #define RSP1_APP_CMD_S 5 516 #define RSP1_READY_FOR_DATA_M \ 517 BITFIELD_MASK(1) /* Bit 8 - Ready for data (buff empty) */ 518 #define RSP1_READY_FOR_DATA_S 8 519 #define RSP1_CURR_STATE_M \ 520 BITFIELD_MASK(4) /* Bits [12:9] - State of card \ 521 * when Cmd was received \ 522 */ 523 #define RSP1_CURR_STATE_S 9 524 #define RSP1_EARSE_RESET_M BITFIELD_MASK(1) /* Bit 13 - Erase seq cleared */ 525 #define RSP1_EARSE_RESET_S 13 526 #define RSP1_CARD_ECC_DISABLE_M \ 527 BITFIELD_MASK(1) /* Bit 14 - Card ECC disabled */ 528 #define RSP1_CARD_ECC_DISABLE_S 14 529 #define RSP1_WP_ERASE_SKIP_M \ 530 BITFIELD_MASK(1) /* Bit 15 - Partial blocks erased due to W/P */ 531 #define RSP1_WP_ERASE_SKIP_S 15 532 #define RSP1_CID_CSD_OVERW_M \ 533 BITFIELD_MASK(1) /* Bit 16 - Illegal write to CID or R/O bits \ 534 * of CSD \ 535 */ 536 #define RSP1_CID_CSD_OVERW_S 16 537 #define RSP1_ERROR_M BITFIELD_MASK(1) /* Bit 19 - General/Unknown error */ 538 #define RSP1_ERROR_S 19 539 #define RSP1_CC_ERROR_M \ 540 BITFIELD_MASK(1) /* Bit 20 - Internal Card Control error */ 541 #define RSP1_CC_ERROR_S 20 542 #define RSP1_CARD_ECC_FAILED_M \ 543 BITFIELD_MASK(1) /* Bit 21 - Card internal ECC failed \ 544 * to correct data \ 545 */ 546 #define RSP1_CARD_ECC_FAILED_S 21 547 #define RSP1_ILLEGAL_CMD_M \ 548 BITFIELD_MASK(1) /* Bit 22 - Cmd not legal for the card state */ 549 #define RSP1_ILLEGAL_CMD_S 22 550 #define RSP1_COM_CRC_ERROR_M \ 551 BITFIELD_MASK(1) /* Bit 23 - CRC check of previous command failed \ 552 */ 553 #define RSP1_COM_CRC_ERROR_S 23 554 #define RSP1_LOCK_UNLOCK_FAIL_M \ 555 BITFIELD_MASK(1) /* Bit 24 - Card lock-unlock Cmd Seq error */ 556 #define RSP1_LOCK_UNLOCK_FAIL_S 24 557 #define RSP1_CARD_LOCKED_M \ 558 BITFIELD_MASK(1) /* Bit 25 - Card locked by the host */ 559 #define RSP1_CARD_LOCKED_S 25 560 #define RSP1_WP_VIOLATION_M \ 561 BITFIELD_MASK(1) /* Bit 26 - Attempt to program \ 562 * write-protected blocks \ 563 */ 564 #define RSP1_WP_VIOLATION_S 26 565 #define RSP1_ERASE_PARAM_M \ 566 BITFIELD_MASK(1) /* Bit 27 - Invalid erase blocks */ 567 #define RSP1_ERASE_PARAM_S 27 568 #define RSP1_ERASE_SEQ_ERR_M \ 569 BITFIELD_MASK(1) /* Bit 28 - Erase Cmd seq error */ 570 #define RSP1_ERASE_SEQ_ERR_S 28 571 #define RSP1_BLK_LEN_ERR_M BITFIELD_MASK(1) /* Bit 29 - Block length error \ 572 */ 573 #define RSP1_BLK_LEN_ERR_S 29 574 #define RSP1_ADDR_ERR_M BITFIELD_MASK(1) /* Bit 30 - Misaligned address */ 575 #define RSP1_ADDR_ERR_S 30 576 #define RSP1_OUT_OF_RANGE_M \ 577 BITFIELD_MASK(1) /* Bit 31 - Cmd arg was out of range */ 578 #define RSP1_OUT_OF_RANGE_S 31 579 580 #define RSP5_DATA_M BITFIELD_MASK(8) /* Bits [0:7] - data */ 581 #define RSP5_DATA_S 0 582 #define RSP5_FLAGS_M BITFIELD_MASK(8) /* Bit [15:8] - Rsp flags */ 583 #define RSP5_FLAGS_S 8 584 #define RSP5_STUFF_M BITFIELD_MASK(16) /* Bits [31:16] - Stuff bits */ 585 #define RSP5_STUFF_S 16 586 587 /* ---------------------------------------------- 588 * SDIO Command Response structures for SPI mode 589 * ---------------------------------------------- 590 */ 591 #define SPIRSP4_IO_OCR_M \ 592 BITFIELD_MASK(16) /* Bits [15:0] - Card's OCR Bits [23:8] */ 593 #define SPIRSP4_IO_OCR_S 0 594 #define SPIRSP4_STUFF_M BITFIELD_MASK(3) /* Bits [18:16] - Stuff bits */ 595 #define SPIRSP4_STUFF_S 16 596 #define SPIRSP4_MEM_PRESENT_M \ 597 BITFIELD_MASK(1) /* Bit 19 - Memory present */ 598 #define SPIRSP4_MEM_PRESENT_S 19 599 #define SPIRSP4_NUM_FUNCS_M \ 600 BITFIELD_MASK(3) /* Bits [22:20] - Number of I/O funcs */ 601 #define SPIRSP4_NUM_FUNCS_S 20 602 #define SPIRSP4_CARD_READY_M \ 603 BITFIELD_MASK(1) /* Bit 23 - SDIO card ready */ 604 #define SPIRSP4_CARD_READY_S 23 605 #define SPIRSP4_IDLE_STATE_M BITFIELD_MASK(1) /* Bit 24 - idle state \ 606 */ 607 #define SPIRSP4_IDLE_STATE_S 24 608 #define SPIRSP4_ILLEGAL_CMD_M \ 609 BITFIELD_MASK(1) /* Bit 26 - Illegal Cmd error */ 610 #define SPIRSP4_ILLEGAL_CMD_S 26 611 #define SPIRSP4_COM_CRC_ERROR_M \ 612 BITFIELD_MASK(1) /* Bit 27 - COM CRC error */ 613 #define SPIRSP4_COM_CRC_ERROR_S 27 614 #define SPIRSP4_FUNC_NUM_ERROR_M \ 615 BITFIELD_MASK(1) /* Bit 28 - Function number error \ 616 */ 617 #define SPIRSP4_FUNC_NUM_ERROR_S 28 618 #define SPIRSP4_PARAM_ERROR_M \ 619 BITFIELD_MASK(1) /* Bit 30 - Parameter Error Bit */ 620 #define SPIRSP4_PARAM_ERROR_S 30 621 #define SPIRSP4_START_BIT_M BITFIELD_MASK(1) /* Bit 31 - Start Bit */ 622 #define SPIRSP4_START_BIT_S 31 623 624 #define SPIRSP5_DATA_M BITFIELD_MASK(8) /* Bits [23:16] - R/W Data */ 625 #define SPIRSP5_DATA_S 16 626 #define SPIRSP5_IDLE_STATE_M BITFIELD_MASK(1) /* Bit 24 - Idle state \ 627 */ 628 #define SPIRSP5_IDLE_STATE_S 24 629 #define SPIRSP5_ILLEGAL_CMD_M \ 630 BITFIELD_MASK(1) /* Bit 26 - Illegal Cmd error */ 631 #define SPIRSP5_ILLEGAL_CMD_S 26 632 #define SPIRSP5_COM_CRC_ERROR_M \ 633 BITFIELD_MASK(1) /* Bit 27 - COM CRC error */ 634 #define SPIRSP5_COM_CRC_ERROR_S 27 635 #define SPIRSP5_FUNC_NUM_ERROR_M \ 636 BITFIELD_MASK(1) /* Bit 28 - Function number error \ 637 */ 638 #define SPIRSP5_FUNC_NUM_ERROR_S 28 639 #define SPIRSP5_PARAM_ERROR_M \ 640 BITFIELD_MASK(1) /* Bit 30 - Parameter Error Bit */ 641 #define SPIRSP5_PARAM_ERROR_S 30 642 #define SPIRSP5_START_BIT_M BITFIELD_MASK(1) /* Bit 31 - Start Bit */ 643 #define SPIRSP5_START_BIT_S 31 644 645 /* RSP6 card status format; Pg 68 Physical Layer spec v 1.10 */ 646 #define RSP6STAT_AKE_SEQ_ERROR_M \ 647 BITFIELD_MASK(1) /* Bit 3 - Authentication seq error \ 648 */ 649 #define RSP6STAT_AKE_SEQ_ERROR_S 3 650 #define RSP6STAT_APP_CMD_M BITFIELD_MASK(1) /* Bit 5 - Card expects ACMD */ 651 #define RSP6STAT_APP_CMD_S 5 652 #define RSP6STAT_READY_FOR_DATA_M \ 653 BITFIELD_MASK(1) /* Bit 8 - Ready for data \ 654 * (buff empty) \ 655 */ 656 #define RSP6STAT_READY_FOR_DATA_S 8 657 #define RSP6STAT_CURR_STATE_M \ 658 BITFIELD_MASK(4) /* Bits [12:9] - Card state at \ 659 * Cmd reception \ 660 */ 661 #define RSP6STAT_CURR_STATE_S 9 662 #define RSP6STAT_ERROR_M \ 663 BITFIELD_MASK(1) /* Bit 13 - General/Unknown error Bit 19 \ 664 */ 665 #define RSP6STAT_ERROR_S 13 666 #define RSP6STAT_ILLEGAL_CMD_M \ 667 BITFIELD_MASK(1) /* Bit 14 - Illegal cmd for \ 668 * card state Bit 22 \ 669 */ 670 #define RSP6STAT_ILLEGAL_CMD_S 14 671 #define RSP6STAT_COM_CRC_ERROR_M \ 672 BITFIELD_MASK(1) /* Bit 15 - CRC previous command \ 673 * failed Bit 23 \ 674 */ 675 #define RSP6STAT_COM_CRC_ERROR_S 15 676 677 #define SDIOH_XFER_TYPE_READ SD_IO_OP_READ 678 #define SDIOH_XFER_TYPE_WRITE SD_IO_OP_WRITE 679 680 /* command issue options */ 681 #define CMD_OPTION_DEFAULT 0 682 #define CMD_OPTION_TUNING 1 683 684 #endif /* def BCMSDIO */ 685 #endif /* _SDIO_H */ 686