1 /*
2 * Copyright (C) 2021–2022 Beijing OSWare Technology Co., Ltd
3 * This file contains confidential and proprietary information of
4 * OSWare Technology Co., Ltd
5 *
6 * Licensed under the Apache License, Version 2.0 (the "License");
7 * you may not use this file except in compliance with the License.
8 * You may obtain a copy of the License at
9 *
10 * http://www.apache.org/licenses/LICENSE-2.0
11 *
12 * Unless required by applicable law or agreed to in writing, software
13 * distributed under the License is distributed on an "AS IS" BASIS,
14 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
15 * See the License for the specific language governing permissions and
16 * limitations under the License.
17 */
18
19 #include <sound/core.h>
20 #include <sound/pcm.h>
21 #include <sound/pcm_params.h>
22 #include <sound/soc.h>
23 #include <sound/initval.h>
24 #include <sound/tlv.h>
25 #include <sound/wm8904.h>
26 #include <linux/clk.h>
27 #include <linux/module.h>
28 #include <linux/moduleparam.h>
29 #include <linux/init.h>
30 #include <linux/delay.h>
31 #include <linux/pm.h>
32 #include <linux/i2c.h>
33 #include <linux/regmap.h>
34 #include <linux/regulator/consumer.h>
35 #include <linux/slab.h>
36 #include "gpio_if.h"
37 #include "i2c_if.h"
38 #include "audio_device_log.h"
39 #include "wm8904_log.h"
40 #include "wm8904.h"
41
42 #include "audio_codec_base.h"
43 #include "audio_core.h"
44
45 struct wm8904_priv *gpwm8904;
46 DevHandle g_wm8904_i2c_handle = NULL;
47
48 DevHandle WM8904I2cOpen(void);
49 void WM8904I2cClose(DevHandle handle);
50
51 int WM8904RegRead(DevHandle i2cHandle, unsigned int reg, unsigned int *val, unsigned int dataLen);
52 int WM8904RegWrite(DevHandle i2cHandle, unsigned int reg, unsigned int val, unsigned int dataLen);
53 int WM8904RegUpdateBits(DevHandle i2cHandle, unsigned int reg,
54 unsigned int mask, unsigned int val, unsigned int dataLen);
55 int32_t Wm8904DaiStart(const struct AudioCard *card, const struct DaiDevice *device);
56 int32_t Wm8904DaiHwParamsSet(const struct AudioCard *card, const struct AudioPcmHwParams *param);
57 int32_t Wm8904DaiDevInit(struct AudioCard *card, const struct DaiDevice *device);
58 int32_t Wm8904DevInit(struct AudioCard *audioCard, const struct CodecDevice *device);
59
60 #define AUDIO_DRV_PCMIOCTL_CAPUTRE_START 7
61 #define AUDIO_DRV_PCM_IOCTL_RENDER_START 5
62 #define AUDIO_DRV_PCM_IOCTL_RENDER_STOP 6
63 #define AUDIO_DRV_PCM_IOCTL_CAPTURE_STOP 8
64 #define AUDIO_DRV_PCM_IOCTL_CAPTURE_PAUSE 10
65 #define AUDIO_DRV_PCM_IOCTL_RENDER_PAUSE 9
66
67 #define SLEEP_TIME (50)
68 #define SLEEP_TIME_1 (1)
69 #define SLEEP_TIME_10 (10)
70 #define SLEEP_TIME_120 (120)
71
72 #define BYTE_NUM (2)
73 #define BYTE_NUM_1 (1)
74 #define BYTE_NUM_4 (4)
75 #define BYTE_NUM_8 (8)
76 #define OUT_PGA_90 (90)
77 #define OUT_PGA_94 (94)
78 #define NUM_256 (256)
79 #define TIMEOUT_20 (20)
80 #define TIMEOUT_500 (500)
81
82 enum wm8904_type {
83 WM8904,
84 WM8912,
85 };
86
87 #define WM8904_NUM_DCS_CHANNELS 4
88 #define WM8904_NUM_SUPPLIES 5
89 static const char *wm8904_supply_names[WM8904_NUM_SUPPLIES] = {
90 "DCVDD",
91 "DBVDD",
92 "AVDD",
93 "CPVDD",
94 "MICVDD",
95 };
96
97 /* codec private data */
98 struct wm8904_priv {
99 struct regmap *regmap;
100 struct clk *mclk;
101
102 enum wm8904_type devtype;
103
104 struct regulator_bulk_data supplies[WM8904_NUM_SUPPLIES];
105
106 struct wm8904_pdata *pdata;
107
108 int deemph;
109
110 /* Platform provided DRC configuration */
111 const char **drc_texts;
112 int drc_cfg;
113 struct soc_enum drc_enum;
114
115 /* Platform provided ReTune mobile configuration */
116 int num_retune_mobile_texts;
117 const char **retune_mobile_texts;
118 int retune_mobile_cfg;
119 struct soc_enum retune_mobile_enum;
120
121 /* FLL setup */
122 int fll_src;
123 int fll_fref;
124 int fll_fout;
125
126 /* Clocking configuration */
127 unsigned int mclk_rate;
128 int sysclk_src;
129 unsigned int sysclk_rate;
130
131 int tdm_width;
132 int tdm_slots;
133 int bclk;
134 int fs;
135
136 /* DC servo configuration - cached offset values */
137 int dcs_state[WM8904_NUM_DCS_CHANNELS];
138 };
139
140 static const struct reg_default wm8904_reg_defaults[] = {
141 { 4, 0x0018 }, /* R4 - Bias Control 0 */
142 { 5, 0x0000 }, /* R5 - VMID Control 0 */
143 { 6, 0x0000 }, /* R6 - Mic Bias Control 0 */
144 { 7, 0x0000 }, /* R7 - Mic Bias Control 1 */
145 { 8, 0x0001 }, /* R8 - Analogue DAC 0 */
146 { 9, 0x9696 }, /* R9 - mic Filter Control */
147 { 10, 0x0001 }, /* R10 - Analogue ADC 0 */
148 { 12, 0x0000 }, /* R12 - Power Management 0 */
149 { 14, 0x0000 }, /* R14 - Power Management 2 */
150 { 15, 0x0000 }, /* R15 - Power Management 3 */
151 { 18, 0x0000 }, /* R18 - Power Management 6 */
152 { 20, 0x945E }, /* R20 - Clock Rates 0 */
153 { 21, 0x0C05 }, /* R21 - Clock Rates 1 */
154 { 22, 0x0006 }, /* R22 - Clock Rates 2 */
155 { 24, 0x0050 }, /* R24 - Audio Interface 0 */
156 { 25, 0x000A }, /* R25 - Audio Interface 1 */
157 { 26, 0x00E4 }, /* R26 - Audio Interface 2 */
158 { 27, 0x0040 }, /* R27 - Audio Interface 3 */
159 { 30, 0x00C0 }, /* R30 - DAC Digital Volume Left */
160 { 31, 0x00C0 }, /* R31 - DAC Digital Volume Right */
161 { 32, 0x0000 }, /* R32 - DAC Digital 0 */
162 { 33, 0x0008 }, /* R33 - DAC Digital 1 */
163 { 36, 0x00C0 }, /* R36 - ADC Digital Volume Left */
164 { 37, 0x00C0 }, /* R37 - ADC Digital Volume Right */
165 { 38, 0x0010 }, /* R38 - ADC Digital 0 */
166 { 39, 0x0000 }, /* R39 - Digital Microphone 0 */
167 { 40, 0x01AF }, /* R40 - DRC 0 */
168 { 41, 0x3248 }, /* R41 - DRC 1 */
169 { 42, 0x0000 }, /* R42 - DRC 2 */
170 { 43, 0x0000 }, /* R43 - DRC 3 */
171 { 44, 0x0085 }, /* R44 - Analogue Left Input 0 */
172 { 45, 0x0085 }, /* R45 - Analogue Right Input 0 */
173 { 46, 0x0044 }, /* R46 - Analogue Left Input 1 */
174 { 47, 0x0044 }, /* R47 - Analogue Right Input 1 */
175 { 57, 0x002D }, /* R57 - Analogue OUT1 Left */
176 { 58, 0x002D }, /* R58 - Analogue OUT1 Right */
177 { 59, 0x0039 }, /* R59 - Analogue OUT2 Left */
178 { 60, 0x0039 }, /* R60 - Analogue OUT2 Right */
179 { 61, 0x0000 }, /* R61 - Analogue OUT12 ZC */
180 { 67, 0x0000 }, /* R67 - DC Servo 0 */
181 { 69, 0xAAAA }, /* R69 - DC Servo 2 */
182 { 71, 0xAAAA }, /* R71 - DC Servo 4 */
183 { 72, 0xAAAA }, /* R72 - DC Servo 5 */
184 { 90, 0x0000 }, /* R90 - Analogue HP 0 */
185 { 94, 0x0000 }, /* R94 - Analogue Lineout 0 */
186 { 98, 0x0000 }, /* R98 - Charge Pump 0 */
187 { 104, 0x0004 }, /* R104 - Class W 0 */
188 { 108, 0x0000 }, /* R108 - Write Sequencer 0 */
189 { 109, 0x0000 }, /* R109 - Write Sequencer 1 */
190 { 110, 0x0000 }, /* R110 - Write Sequencer 2 */
191 { 111, 0x0000 }, /* R111 - Write Sequencer 3 */
192 { 112, 0x0000 }, /* R112 - Write Sequencer 4 */
193 { 116, 0x0000 }, /* R116 - FLL Control 1 */
194 { 117, 0x0007 }, /* R117 - FLL Control 2 */
195 { 118, 0x0000 }, /* R118 - FLL Control 3 */
196 { 119, 0x2EE0 }, /* R119 - FLL Control 4 */
197 { 120, 0x0004 }, /* R120 - FLL Control 5 */
198 { 121, 0x0014 }, /* R121 - GPIO Control 1 */
199 { 122, 0x0010 }, /* R122 - GPIO Control 2 */
200 { 123, 0x0010 }, /* R123 - GPIO Control 3 */
201 { 124, 0x0000 }, /* R124 - GPIO Control 4 */
202 { 126, 0x0000 }, /* R126 - Digital Pulls */
203 { 128, 0xFFFF }, /* R128 - Interrupt Status Mask */
204 { 129, 0x0000 }, /* R129 - Interrupt Polarity */
205 { 130, 0x0000 }, /* R130 - Interrupt Debounce */
206 { 134, 0x0000 }, /* R134 - EQ1 */
207 { 135, 0x000C }, /* R135 - EQ2 */
208 { 136, 0x000C }, /* R136 - EQ3 */
209 { 137, 0x000C }, /* R137 - EQ4 */
210 { 138, 0x000C }, /* R138 - EQ5 */
211 { 139, 0x000C }, /* R139 - EQ6 */
212 { 140, 0x0FCA }, /* R140 - EQ7 */
213 { 141, 0x0400 }, /* R141 - EQ8 */
214 { 142, 0x00D8 }, /* R142 - EQ9 */
215 { 143, 0x1EB5 }, /* R143 - EQ10 */
216 { 144, 0xF145 }, /* R144 - EQ11 */
217 { 145, 0x0B75 }, /* R145 - EQ12 */
218 { 146, 0x01C5 }, /* R146 - EQ13 */
219 { 147, 0x1C58 }, /* R147 - EQ14 */
220 { 148, 0xF373 }, /* R148 - EQ15 */
221 { 149, 0x0A54 }, /* R149 - EQ16 */
222 { 150, 0x0558 }, /* R150 - EQ17 */
223 { 151, 0x168E }, /* R151 - EQ18 */
224 { 152, 0xF829 }, /* R152 - EQ19 */
225 { 153, 0x07AD }, /* R153 - EQ20 */
226 { 154, 0x1103 }, /* R154 - EQ21 */
227 { 155, 0x0564 }, /* R155 - EQ22 */
228 { 156, 0x0559 }, /* R156 - EQ23 */
229 { 157, 0x4000 }, /* R157 - EQ24 */
230 { 161, 0x0000 }, /* R161 - Control Interface Test 1 */
231 { 204, 0x0000 }, /* R204 - Analogue Output Bias 0 */
232 { 247, 0x0000 }, /* R247 - FLL NCO Test 0 */
233 { 248, 0x0019 }, /* R248 - FLL NCO Test 1 */
234 };
235
236 #define WM8904InitRegCount 93
WM8904I2cAllRegDefautInit(DevHandle handle)237 int WM8904I2cAllRegDefautInit(DevHandle handle)
238 {
239 int i = 0;
240 for (i = 0; i < WM8904InitRegCount; i++) {
241 WM8904RegWrite(handle, wm8904_reg_defaults[i].reg, wm8904_reg_defaults[i].def, BYTE_NUM);
242 }
243 return 0;
244 }
245
WM8904I2cAllRegDump(DevHandle handle)246 int WM8904I2cAllRegDump(DevHandle handle)
247 {
248 int i = 0, val = 0;
249 for (i = 0; i < NUM_256; i++) {
250 WM8904RegRead(g_wm8904_i2c_handle, i, &val, BYTE_NUM);
251 WM8904_CODEC_LOG_ERR("dump1_reg(0x%x) val=0x%x", i, val);
252 }
253 return 0;
254 }
255
WM8904StateInit(DevHandle handle)256 int WM8904StateInit(DevHandle handle)
257 {
258 WM8904RegUpdateBits(handle, WM8904_MIC_BIAS_CONTROL_0, 0x1, 0, BYTE_NUM);
259 WM8904RegUpdateBits(handle, WM8904_ANALOGUE_LEFT_INPUT_0, 0x1f, 0x18, BYTE_NUM);
260 WM8904RegUpdateBits(handle, WM8904_ANALOGUE_RIGHT_INPUT_0, 0x1f, 0x18, BYTE_NUM);
261
262 WM8904RegUpdateBits(handle, WM8904_ANALOGUE_LEFT_INPUT_0, 0x80, 0, BYTE_NUM);
263 WM8904RegUpdateBits(handle, WM8904_ANALOGUE_RIGHT_INPUT_0, 0x80, 0, BYTE_NUM);
264 WM8904RegUpdateBits(handle, WM8904_EQ2, 0x1f, 0xc, BYTE_NUM);
265
266 WM8904RegUpdateBits(handle, WM8904_EQ3, 0x1f, 0xc, BYTE_NUM);
267 WM8904RegUpdateBits(handle, WM8904_EQ4, 0x1f, 0xc, BYTE_NUM);
268 WM8904RegUpdateBits(handle, WM8904_EQ5, 0x1f, 0xc, BYTE_NUM);
269 WM8904RegUpdateBits(handle, WM8904_EQ6, 0x1f, 0xc, BYTE_NUM);
270
271 WM8904RegUpdateBits(handle, WM8904_ADC_DIGITAL_VOLUME_LEFT, 0xfe, 0xc0, BYTE_NUM);
272 WM8904RegUpdateBits(handle, WM8904_ADC_DIGITAL_VOLUME_RIGHT, 0xfe, 0xc0, BYTE_NUM);
273 WM8904RegUpdateBits(handle, WM8904_ANALOGUE_LEFT_INPUT_1, 0x3, 0x0, BYTE_NUM);
274 WM8904RegUpdateBits(handle, WM8904_ANALOGUE_RIGHT_INPUT_1, 0x3, 0x0, BYTE_NUM);
275
276 WM8904RegUpdateBits(handle, WM8904_ADC_DIGITAL_0, 0x10, 0x10, BYTE_NUM);
277 WM8904RegUpdateBits(handle, WM8904_ADC_DIGITAL_0, 0x60, 0x0, BYTE_NUM);
278 WM8904RegUpdateBits(handle, WM8904_ANALOGUE_ADC_0, 0x1, 0x1, BYTE_NUM);
279 WM8904RegUpdateBits(handle, WM8904_ADC_TEST_0, 0x5, 0x0, BYTE_NUM);
280
281 WM8904RegUpdateBits(handle, WM8904_ANALOGUE_OUT1_RIGHT, 0x3f, 0x2d, BYTE_NUM);
282 WM8904RegUpdateBits(handle, WM8904_ANALOGUE_OUT1_LEFT, 0x100, 0x0, BYTE_NUM);
283 WM8904RegUpdateBits(handle, WM8904_ANALOGUE_OUT1_RIGHT, 0x100, 0x0, BYTE_NUM);
284 WM8904RegUpdateBits(handle, WM8904_ANALOGUE_OUT1_LEFT, 0x40, 0x40, BYTE_NUM);
285 WM8904RegUpdateBits(handle, WM8904_ANALOGUE_OUT1_RIGHT, 0x40, 0x40, BYTE_NUM);
286
287 WM8904RegUpdateBits(handle, WM8904_ANALOGUE_OUT2_LEFT, 0x3f, 0x39, BYTE_NUM);
288 WM8904RegUpdateBits(handle, WM8904_ANALOGUE_OUT2_RIGHT, 0x3f, 0x39, BYTE_NUM);
289 WM8904RegUpdateBits(handle, WM8904_ANALOGUE_OUT2_LEFT, 0x100, 0x0, BYTE_NUM);
290 WM8904RegUpdateBits(handle, WM8904_ANALOGUE_OUT2_RIGHT, 0x100, 0x0, BYTE_NUM);
291 WM8904RegUpdateBits(handle, WM8904_ANALOGUE_OUT2_LEFT, 0x40, 0x40, BYTE_NUM);
292
293 WM8904RegUpdateBits(handle, WM8904_ANALOGUE_OUT2_RIGHT, 0x40, 0x40, BYTE_NUM);
294 WM8904RegUpdateBits(handle, WM8904_EQ1, 0x1, 0x0, BYTE_NUM);
295 WM8904RegUpdateBits(handle, WM8904_DRC_0, 0x8000, 0x0, BYTE_NUM);
296 WM8904RegUpdateBits(handle, WM8904_DRC_0, 0x4000, 0x0, BYTE_NUM);
297 WM8904RegUpdateBits(handle, WM8904_DAC_DIGITAL_1, 0x40, 0x0, BYTE_NUM);
298 WM8904RegUpdateBits(handle, WM8904_DAC_DIGITAL_1, 0x6, 0x0, BYTE_NUM);
299 WM8904RegUpdateBits(handle, WM8904_DAC_DIGITAL_0, 0xff0, 0x0, BYTE_NUM);
300
301 return 0;
302 }
303
304 #define SYSCLK_RATE (13500000)
WM8904_Configure_Clocking(void)305 static int WM8904_Configure_Clocking(void)
306 {
307 unsigned int clock0 = 0, clock2 = 0, rate = 0;
308 int ret = 0;
309 /* Gate the clock while we're updating to avoid misclocking */
310 ret = WM8904RegRead(g_wm8904_i2c_handle, WM8904_CLOCK_RATES_2, &clock2, BYTE_NUM);
311 if (ret < 0) {
312 return -1;
313 }
314 WM8904RegUpdateBits(g_wm8904_i2c_handle, WM8904_CLOCK_RATES_2, WM8904_SYSCLK_SRC, 0, BYTE_NUM);
315
316 /* This should be done on init() for bypass paths */
317 switch (gpwm8904->sysclk_src) {
318 case WM8904_CLK_MCLK:
319 WM8904_CODEC_LOG_DEBUG("Using %dHz MCLK", gpwm8904->mclk_rate);
320
321 clock2 &= ~WM8904_SYSCLK_SRC;
322 rate = gpwm8904->mclk_rate;
323
324 /* Ensure the FLL is stopped */
325 WM8904RegUpdateBits(g_wm8904_i2c_handle, WM8904_FLL_CONTROL_1,
326 WM8904_FLL_OSC_ENA | WM8904_FLL_ENA, 0, BYTE_NUM);
327 break;
328
329 case WM8904_CLK_FLL:
330 WM8904_CODEC_LOG_DEBUG("Using %dHz FLL clock",
331 gpwm8904->fll_fout);
332
333 clock2 |= WM8904_SYSCLK_SRC;
334 rate = gpwm8904->fll_fout;
335 break;
336
337 default:
338 WM8904_CODEC_LOG_ERR("System clock not configured");
339 return -EINVAL;
340 }
341
342 /* SYSCLK shouldn't be over 13.5MHz */
343 if (rate > SYSCLK_RATE) {
344 clock0 = WM8904_MCLK_DIV;
345 gpwm8904->sysclk_rate = rate / BYTE_NUM;
346 } else {
347 clock0 = 0;
348 gpwm8904->sysclk_rate = rate;
349 }
350
351 WM8904RegUpdateBits(g_wm8904_i2c_handle, WM8904_CLOCK_RATES_0, WM8904_MCLK_DIV,
352 clock0, BYTE_NUM);
353
354 WM8904RegUpdateBits(g_wm8904_i2c_handle, WM8904_CLOCK_RATES_2,
355 WM8904_CLK_SYS_ENA | WM8904_SYSCLK_SRC, clock2, BYTE_NUM);
356
357 WM8904_CODEC_LOG_DEBUG("CLK_SYS is %dHz\n", gpwm8904->sysclk_rate);
358
359 return 0;
360 }
361
WM8904_Set_Retune_Mobile(void)362 static void WM8904_Set_Retune_Mobile(void)
363 {
364 struct wm8904_pdata *pdata = gpwm8904->pdata;
365 int best = 0, best_val = 0, save = 0, i = 0, cfg = 0, ret = 0;
366
367 if (!pdata || !gpwm8904->num_retune_mobile_texts) {
368 return;
369 }
370
371 /* Find the version of the currently selected configuration
372 * with the nearest sample rate. */
373 cfg = gpwm8904->retune_mobile_cfg;
374 best = 0;
375 best_val = INT_MAX;
376 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
377 if (strcmp(pdata->retune_mobile_cfgs[i].name,
378 gpwm8904->retune_mobile_texts[cfg]) == 0 &&
379 abs(pdata->retune_mobile_cfgs[i].rate
380 - gpwm8904->fs) < best_val) {
381 best = i;
382 best_val = abs(pdata->retune_mobile_cfgs[i].rate
383 - gpwm8904->fs);
384 }
385 }
386
387 WM8904_CODEC_LOG_DEBUG("ReTune Mobile %s/%dHz for %dHz sample rate\n",
388 pdata->retune_mobile_cfgs[best].name,
389 pdata->retune_mobile_cfgs[best].rate,
390 gpwm8904->fs);
391
392 /* The EQ will be disabled while reconfiguring it, remember the
393 * current configuration
394 */
395 ret = WM8904RegRead(g_wm8904_i2c_handle, WM8904_EQ1, &save, BYTE_NUM);
396
397 for (i = 0; i < WM8904_EQ_REGS; i++) {
398 WM8904RegUpdateBits(g_wm8904_i2c_handle, WM8904_EQ1 + i, 0xffff,
399 pdata->retune_mobile_cfgs[best].regs[i], BYTE_NUM);
400 }
401
402 WM8904RegUpdateBits(g_wm8904_i2c_handle, WM8904_EQ1, WM8904_EQ_ENA, save, BYTE_NUM);
403 }
404
405 static int deemph_settings[] = { 0, 32000, 44100, 48000 };
406
WM8904_Set_Deemph(void)407 static int WM8904_Set_Deemph(void)
408 {
409 int val = 0, i = 0, best = 0;
410
411 /* If we're using deemphasis select the nearest available sample
412 * rate.
413 */
414 if (gpwm8904->deemph) {
415 best = 1;
416 for (i = BYTE_NUM; i < ARRAY_SIZE(deemph_settings); i++) {
417 if (abs(deemph_settings[i] - gpwm8904->fs) <
418 abs(deemph_settings[best] - gpwm8904->fs)) {
419 best = i;
420 }
421 }
422
423 val = best << WM8904_DEEMPH_SHIFT;
424 } else {
425 val = 0;
426 }
427
428 WM8904_CODEC_LOG_DEBUG("Set deemphasis %d", val);
429
430 return WM8904RegUpdateBits(g_wm8904_i2c_handle, WM8904_DAC_DIGITAL_1,
431 WM8904_DEEMPH_MASK, val, BYTE_NUM);
432 }
433
434 typedef struct dcs_params {
435 int reg;
436 int dcs_mask;
437 int dcs_l;
438 int dcs_r;
439 int dcs_l_reg;
440 int dcs_r_reg;
441 int pwr_reg;
442 } stDcsParam;
443
DapmPrePMU(stDcsParam dcsParam)444 static int DapmPrePMU(stDcsParam dcsParam)
445 {
446 int val = 0;
447 int reg = dcsParam.reg;
448 int dcs_mask = dcsParam.dcs_mask;
449 int dcs_l = dcsParam.dcs_l, dcs_r = dcsParam.dcs_r;
450 int dcs_l_reg = dcsParam.dcs_l_reg, dcs_r_reg = dcsParam.dcs_r_reg;
451 int timeout = 0;
452 int pwr_reg = dcsParam.pwr_reg;
453
454 /* Power on the PGAs */
455 WM8904RegUpdateBits(g_wm8904_i2c_handle, pwr_reg,
456 WM8904_HPL_PGA_ENA | WM8904_HPR_PGA_ENA,
457 WM8904_HPL_PGA_ENA | WM8904_HPR_PGA_ENA, BYTE_NUM);
458
459 /* Power on the amplifier */
460 WM8904RegUpdateBits(g_wm8904_i2c_handle, reg,
461 WM8904_HPL_ENA | WM8904_HPR_ENA,
462 WM8904_HPL_ENA | WM8904_HPR_ENA, BYTE_NUM);
463
464 /* Enable the first stage */
465 WM8904RegUpdateBits(g_wm8904_i2c_handle, reg,
466 WM8904_HPL_ENA_DLY | WM8904_HPR_ENA_DLY,
467 WM8904_HPL_ENA_DLY | WM8904_HPR_ENA_DLY, BYTE_NUM);
468
469 /* Power up the DC servo */
470 WM8904RegUpdateBits(g_wm8904_i2c_handle, WM8904_DC_SERVO_0,
471 dcs_mask, dcs_mask, BYTE_NUM);
472
473 /* Either calibrate the DC servo or restore cached state
474 * if we have that.
475 */
476 if (gpwm8904->dcs_state[dcs_l] || gpwm8904->dcs_state[dcs_r]) {
477 WM8904_CODEC_LOG_DEBUG("Restoring DC servo state");
478
479 WM8904RegWrite(g_wm8904_i2c_handle, dcs_l_reg,
480 gpwm8904->dcs_state[dcs_l], BYTE_NUM);
481 WM8904RegWrite(g_wm8904_i2c_handle, dcs_r_reg,
482 gpwm8904->dcs_state[dcs_r], BYTE_NUM);
483
484 WM8904RegWrite(g_wm8904_i2c_handle, WM8904_DC_SERVO_1, dcs_mask, BYTE_NUM);
485
486 timeout = TIMEOUT_20;
487 } else {
488 WM8904_CODEC_LOG_DEBUG("Calibrating DC servo");
489
490 WM8904RegWrite(g_wm8904_i2c_handle, WM8904_DC_SERVO_1,
491 dcs_mask << WM8904_DCS_TRIG_STARTUP_0_SHIFT, BYTE_NUM);
492
493 timeout = TIMEOUT_500;
494 }
495
496 /* Wait for DC servo to complete */
497 dcs_mask <<= WM8904_DCS_CAL_COMPLETE_SHIFT;
498 do {
499 WM8904RegRead(g_wm8904_i2c_handle, WM8904_DC_SERVO_READBACK_0, &val, BYTE_NUM);
500 if ((val & dcs_mask) == dcs_mask) {
501 break;
502 }
503 msleep(SLEEP_TIME_1);
504 } while (--timeout);
505
506 if ((val & dcs_mask) != dcs_mask) {
507 WM8904_CODEC_LOG_DEBUG("DC servo timed out");
508 } else {
509 WM8904_CODEC_LOG_DEBUG("DC servo ready");
510 }
511
512 /* Enable the output stage */
513 WM8904RegUpdateBits(g_wm8904_i2c_handle, reg,
514 WM8904_HPL_ENA_OUTP | WM8904_HPR_ENA_OUTP,
515 WM8904_HPL_ENA_OUTP | WM8904_HPR_ENA_OUTP, BYTE_NUM);
516
517 return 0;
518 }
519
DapmPostPMD(stDcsParam dcsParam)520 static int DapmPostPMD(stDcsParam dcsParam)
521 {
522 int reg = dcsParam.reg;
523 int dcs_mask = dcsParam.dcs_mask;
524 int dcs_l = dcsParam.dcs_l;
525 int dcs_l_reg = dcsParam.dcs_l_reg, dcs_r_reg = dcsParam.dcs_r_reg;
526 int pwr_reg = dcsParam.pwr_reg;
527
528 /* Cache the DC servo configuration; this will be
529 * invalidated if we change the configuration. */
530 WM8904RegRead(g_wm8904_i2c_handle, dcs_l_reg, &(gpwm8904->dcs_state[dcs_l]), BYTE_NUM);
531 WM8904RegRead(g_wm8904_i2c_handle, dcs_r_reg, &(gpwm8904->dcs_state[dcs_l]), BYTE_NUM);
532
533 WM8904RegUpdateBits(g_wm8904_i2c_handle, WM8904_DC_SERVO_0,
534 dcs_mask, 0, BYTE_NUM);
535
536 /* Disable the amplifier input and output stages */
537 WM8904RegUpdateBits(g_wm8904_i2c_handle, reg,
538 WM8904_HPL_ENA | WM8904_HPR_ENA |
539 WM8904_HPL_ENA_DLY | WM8904_HPR_ENA_DLY |
540 WM8904_HPL_ENA_OUTP | WM8904_HPR_ENA_OUTP,
541 0, BYTE_NUM);
542
543 /* PGAs too */
544 WM8904RegUpdateBits(g_wm8904_i2c_handle, pwr_reg,
545 WM8904_HPL_PGA_ENA | WM8904_HPR_PGA_ENA,
546 0, BYTE_NUM);
547 return 0;
548 }
549
getRegValue(int reg,int * dcs_r_reg,int * dcs_l_reg,int * dcs_l,int * dcs_r)550 static int getRegValue(int reg, int *dcs_r_reg, int* dcs_l_reg, int* dcs_l, int* dcs_r)
551 {
552 if (dcs_r_reg == NULL || dcs_l_reg == NULL || dcs_l == NULL || dcs_r == NULL) {
553 return HDF_FAILURE;
554 }
555
556 switch (reg) {
557 case WM8904_ANALOGUE_HP_0:
558 *dcs_r_reg = WM8904_DC_SERVO_8;
559 *dcs_l_reg = WM8904_DC_SERVO_9;
560 *dcs_l = 0x0;
561 *dcs_r = 0x1;
562 break;
563
564 case WM8904_ANALOGUE_LINEOUT_0:
565 *dcs_r_reg = WM8904_DC_SERVO_6;
566 *dcs_l_reg = WM8904_DC_SERVO_7;
567 *dcs_l = BYTE_NUM;
568 *dcs_r = 0x3;
569 break;
570
571 default:
572 // nothing
573 break;
574 }
575 return 0;
576 }
577
578
out_pga(int reg,int event)579 int out_pga(int reg, int event)
580 {
581 int dcs_mask = 0, dcs_l = 0, dcs_r = 0;
582 int dcs_r_reg = 0, pwr_reg = 0, dcs_l_reg = 0;
583 stDcsParam dcsParam = {0};
584
585 /* This code is shared between HP and LINEOUT; we do all our
586 * power management in stereo pairs to avoid latency issues so
587 * we reuse shift to identify which rather than strcmp() the
588 * name. */
589 switch (reg) {
590 case WM8904_ANALOGUE_HP_0:
591 pwr_reg = WM8904_POWER_MANAGEMENT_2;
592 dcs_mask = WM8904_DCS_ENA_CHAN_0 | WM8904_DCS_ENA_CHAN_1;
593 break;
594 case WM8904_ANALOGUE_LINEOUT_0:
595 pwr_reg = WM8904_POWER_MANAGEMENT_3;
596 dcs_mask = WM8904_DCS_ENA_CHAN_2 | WM8904_DCS_ENA_CHAN_3;
597 break;
598 default:
599 return -EINVAL;
600 }
601 getRegValue(reg, &dcs_r_reg, &dcs_l_reg, &dcs_l, &dcs_r);
602
603 dcsParam.reg = reg;
604 dcsParam.dcs_mask = dcs_mask;
605 dcsParam.dcs_l = dcs_l;
606 dcsParam.dcs_r = dcs_r;
607 dcsParam.dcs_l_reg = dcs_l_reg;
608 dcsParam.dcs_r_reg = dcs_r_reg;
609 dcsParam.pwr_reg = pwr_reg;
610
611 switch (event) {
612 case SND_SOC_DAPM_PRE_PMU:
613 DapmPrePMU(dcsParam);
614 break;
615
616 case SND_SOC_DAPM_POST_PMU:
617 /* Unshort the output itself */
618 WM8904RegUpdateBits(g_wm8904_i2c_handle, reg,
619 WM8904_HPL_RMV_SHORT | WM8904_HPR_RMV_SHORT,
620 WM8904_HPL_RMV_SHORT | WM8904_HPR_RMV_SHORT, BYTE_NUM);
621 break;
622
623 case SND_SOC_DAPM_PRE_PMD:
624 /* Short the output */
625 WM8904RegUpdateBits(g_wm8904_i2c_handle, reg,
626 WM8904_HPL_RMV_SHORT | WM8904_HPR_RMV_SHORT, 0, BYTE_NUM);
627 break;
628
629 case SND_SOC_DAPM_POST_PMD:
630 DapmPostPMD(dcsParam);
631 break;
632 default:
633 // nothing to do
634 break;
635 }
636
637 return 0;
638 }
639
640 static struct {
641 int ratio;
642 unsigned int clk_sys_rate;
643 } clk_sys_rates[] = {
644 { 64, 0 },
645 { 128, 1 },
646 { 192, 2 },
647 { 256, 3 },
648 { 384, 4 },
649 { 512, 5 },
650 { 786, 6 },
651 { 1024, 7 },
652 { 1408, 8 },
653 { 1536, 9 },
654 };
655
656 static struct {
657 int rate;
658 int sample_rate;
659 } sample_rates[] = {
660 { 8000, 0 },
661 { 11025, 1 },
662 { 12000, 1 },
663 { 16000, 2 },
664 { 22050, 3 },
665 { 24000, 3 },
666 { 32000, 4 },
667 { 44100, 5 },
668 { 48000, 5 },
669 };
670
671 static struct {
672 int div; /* *10 due to .5s */
673 int bclk_div;
674 } bclk_divs[] = {
675 { 10, 0 },
676 { 15, 1 },
677 { 20, 2 },
678 { 30, 3 },
679 { 40, 4 },
680 { 50, 5 },
681 { 55, 6 },
682 { 60, 7 },
683 { 80, 8 },
684 { 100, 9 },
685 { 110, 10 },
686 { 120, 11 },
687 { 160, 12 },
688 { 200, 13 },
689 { 220, 14 },
690 { 240, 16 },
691 { 200, 17 },
692 { 320, 18 },
693 { 440, 19 },
694 { 480, 20 },
695 };
696
697 #define BIT_WIDTH_16 (16)
698 #define BIT_WIDTH_20 (20)
699 #define BIT_WIDTH_24 (24)
700 #define BIT_WIDTH_32 (32)
Frame_To_Bit_Width(enum AudioFormat format,int * bitWidth)701 static int Frame_To_Bit_Width(enum AudioFormat format, int *bitWidth)
702 {
703 switch (format) {
704 case AUDIO_FORMAT_TYPE_PCM_16_BIT:
705 *bitWidth = BIT_WIDTH_16;
706 break;
707 case AUDIO_FORMAT_TYPE_PCM_24_BIT:
708 case AUDIO_FORMAT_TYPE_PCM_32_BIT:
709 *bitWidth = BIT_WIDTH_32;
710 break;
711 default:
712 WM8904_CODEC_LOG_ERR("format: %d is not define", format);
713 return HDF_FAILURE;
714 }
715
716 return HDF_SUCCESS;
717 }
718
719 static int WM8904_Set_Sysclk(int clk_id, unsigned int freq);
720 static int WM8904_Set_Fmt(unsigned int fmt);
721 int WM8904_SET_BIAS_LEVEL(enum snd_soc_bias_level level);
722 int g_wm8904HwPara = 0;
723 struct AudioPcmHwParams g_PcmParams = {0};
724 #define FORMAT_HW (16385)
725 #define RATE_MULTIPLE (10)
726 #define LOW_SAMPLE_RATES (24000)
WM8904GetAif1(int width,unsigned int * aif1)727 int WM8904GetAif1(int width, unsigned int *aif1)
728 {
729 switch (width) {
730 case BIT_WIDTH_16:
731 break;
732 case BIT_WIDTH_20:
733 *aif1 |= 0x40;
734 break;
735 case BIT_WIDTH_24:
736 *aif1 |= 0x80;
737 break;
738 case BIT_WIDTH_32:
739 *aif1 |= 0xc0;
740 break;
741 default:
742 return -EINVAL;
743 }
744 return HDF_SUCCESS;
745 }
746
WM8904HwParamsGetClkRate(unsigned int * dac_digital1,unsigned int * aif2,unsigned int * aif3,unsigned int * clock1)747 void WM8904HwParamsGetClkRate(unsigned int *dac_digital1, unsigned int *aif2, unsigned int *aif3, unsigned int *clock1)
748 {
749 int i = 0, best = 0, best_val = 0, cur_val = 0;
750 /* Select nearest CLK_SYS_RATE */
751 best_val = abs((gpwm8904->sysclk_rate / clk_sys_rates[0].ratio) - gpwm8904->fs);
752 for (i = 1; i < ARRAY_SIZE(clk_sys_rates); i++) {
753 cur_val = abs((gpwm8904->sysclk_rate / clk_sys_rates[i].ratio) - gpwm8904->fs);
754 if (cur_val < best_val) {
755 best = i;
756 best_val = cur_val;
757 }
758 }
759 *clock1 |= (clk_sys_rates[best].clk_sys_rate << WM8904_CLK_SYS_RATE_SHIFT);
760
761 /* SAMPLE_RATE */
762 best = 0;
763 best_val = abs(gpwm8904->fs - sample_rates[0].rate);
764 for (i = 1; i < ARRAY_SIZE(sample_rates); i++) {
765 /* Closest match */
766 cur_val = abs(gpwm8904->fs - sample_rates[i].rate);
767 if (cur_val < best_val) {
768 best = i;
769 best_val = cur_val;
770 }
771 }
772 WM8904_CODEC_LOG_DEBUG("Selected SAMPLE_RATE of %dHz", sample_rates[best].rate);
773 *clock1 |= (sample_rates[best].sample_rate << WM8904_SAMPLE_RATE_SHIFT);
774
775 /* Enable sloping stopband filter for low sample rates */
776 if (gpwm8904->fs <= LOW_SAMPLE_RATES) {
777 *dac_digital1 |= WM8904_DAC_SB_FILT;
778 }
779
780 /* BCLK_DIV */
781 best = 0;
782 best_val = INT_MAX;
783 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
784 cur_val = ((gpwm8904->sysclk_rate * RATE_MULTIPLE) / bclk_divs[i].div) - gpwm8904->bclk;
785 if (cur_val < 0) { /* Table is sorted */
786 break;
787 }
788 if (cur_val < best_val) {
789 best = i;
790 best_val = cur_val;
791 }
792 }
793 gpwm8904->bclk = (gpwm8904->sysclk_rate * RATE_MULTIPLE) / bclk_divs[best].div;
794 *aif2 |= bclk_divs[best].bclk_div;
795 *aif3 |= gpwm8904->bclk / gpwm8904->fs;
796 }
797
Wm8904DaiHwParamsSet(const struct AudioCard * card,const struct AudioPcmHwParams * param)798 int Wm8904DaiHwParamsSet(const struct AudioCard *card, const struct AudioPcmHwParams *param)
799 {
800 int fs = 0, width = 0, channel = 0, slots = 1, dir = 0, ret = 0, errno = 0;
801 unsigned int aif1 = 0, aif2 = 0, aif3 = 0, clock1 = 0, dac_digital1 = 0;
802
803 errno = memcpy_s(&g_PcmParams, sizeof(struct AudioPcmHwParams), param, sizeof(struct AudioPcmHwParams));
804 if (errno != 0) {
805 WM8904_CODEC_LOG_ERR("Memcpy pcm parameters failed!");
806 }
807
808 fs = param->rate;
809 channel = param->channels;
810 dir = param->streamType == AUDIO_RENDER_STREAM ? 1 : 0;
811 Frame_To_Bit_Width(param->format, &width);
812
813 WM8904_Set_Fmt(FORMAT_HW);
814 msleep(SLEEP_TIME_10);
815 WM8904_Set_Sysclk(1, 0);
816 msleep(SLEEP_TIME_10);
817
818 /* What BCLK do we need? */
819 gpwm8904->fs = fs;
820 gpwm8904->bclk = fs * width * channel * slots;
821
822 ret = WM8904GetAif1(width, &aif1);
823 if (ret != 0) {
824 return ret;
825 }
826
827 ret = WM8904_Configure_Clocking();
828 if (ret != 0) {
829 return ret;
830 }
831 WM8904HwParamsGetClkRate(&dac_digital1, &aif2, &aif3, &clock1);
832
833 /* Apply the settings */
834 WM8904RegUpdateBits(g_wm8904_i2c_handle, WM8904_DAC_DIGITAL_1, WM8904_DAC_SB_FILT, dac_digital1, BYTE_NUM);
835 WM8904RegUpdateBits(g_wm8904_i2c_handle, WM8904_AUDIO_INTERFACE_1, WM8904_AIF_WL_MASK, aif1, BYTE_NUM);
836 WM8904RegUpdateBits(g_wm8904_i2c_handle, WM8904_AUDIO_INTERFACE_2, WM8904_BCLK_DIV_MASK, aif2, BYTE_NUM);
837 WM8904RegUpdateBits(g_wm8904_i2c_handle, WM8904_AUDIO_INTERFACE_3, WM8904_LRCLK_RATE_MASK, aif3, BYTE_NUM);
838 WM8904RegUpdateBits(g_wm8904_i2c_handle, WM8904_CLOCK_RATES_1,
839 WM8904_SAMPLE_RATE_MASK | WM8904_CLK_SYS_RATE_MASK, clock1, BYTE_NUM);
840
841 /* Update filters for the new settings */
842 WM8904_Set_Retune_Mobile();
843 WM8904_Set_Deemph();
844
845 g_wm8904HwPara = 1;
846 return 0;
847 }
848
849 #define BITS_8 (8)
TriggerRenderStart(void)850 static int TriggerRenderStart(void)
851 {
852 unsigned int val = 0;
853
854 WM8904_SET_BIAS_LEVEL(SND_SOC_BIAS_STANDBY);
855 msleep(SLEEP_TIME_10);
856 WM8904_SET_BIAS_LEVEL(SND_SOC_BIAS_PREPARE);
857 msleep(SLEEP_TIME_120);
858 WM8904RegUpdateBits(g_wm8904_i2c_handle, WM8904_CLOCK_RATES_2, 0x7, 0x7, BYTE_NUM);
859 WM8904RegUpdateBits(g_wm8904_i2c_handle, WM8904_CHARGE_PUMP_0, 0x1, 0x1, BYTE_NUM);
860 msleep(SLEEP_TIME_120);
861 WM8904RegUpdateBits(g_wm8904_i2c_handle, WM8904_CLASS_W_0, 0xc, 0xc, BYTE_NUM);
862 out_pga(OUT_PGA_90, BYTE_NUM_1);
863 WM8904RegRead(g_wm8904_i2c_handle, OUT_PGA_90, &val, BYTE_NUM);
864 msleep(SLEEP_TIME);
865 out_pga(OUT_PGA_94, BYTE_NUM_1);
866 msleep(SLEEP_TIME);
867 out_pga(OUT_PGA_90, BYTE_NUM);
868 msleep(SLEEP_TIME_10);
869 out_pga(OUT_PGA_94, BYTE_NUM);
870 msleep(SLEEP_TIME_10);
871 WM8904_SET_BIAS_LEVEL(SND_SOC_BIAS_ON);
872 WM8904RegWrite(g_wm8904_i2c_handle, WM8904_POWER_MANAGEMENT_6, 0xc, BYTE_NUM);
873 msleep(SLEEP_TIME_10);
874 WM8904RegUpdateBits(g_wm8904_i2c_handle, WM8904_DAC_DIGITAL_1, WM8904_DAC_MUTE, 0x0, BYTE_NUM);
875
876 return 0;
877 }
878
TriggerCaptureStart(void)879 static int TriggerCaptureStart(void)
880 {
881 WM8904_SET_BIAS_LEVEL(SND_SOC_BIAS_STANDBY);
882 msleep(SLEEP_TIME_10);
883 WM8904RegUpdateBits(g_wm8904_i2c_handle, WM8904_MIC_BIAS_CONTROL_0, 0x1, 0x1, BYTE_NUM);
884 msleep(SLEEP_TIME);
885 WM8904RegUpdateBits(g_wm8904_i2c_handle, WM8904_CLOCK_RATES_2, 0x6, 0x6, BYTE_NUM);
886 msleep(SLEEP_TIME);
887 WM8904RegUpdateBits(g_wm8904_i2c_handle, WM8904_POWER_MANAGEMENT_0, 0x3, 0x3, BYTE_NUM);
888 msleep(SLEEP_TIME);
889 WM8904RegUpdateBits(g_wm8904_i2c_handle, WM8904_POWER_MANAGEMENT_6, 0x3, 0x3, BYTE_NUM);
890 msleep(SLEEP_TIME);
891 WM8904_SET_BIAS_LEVEL(SND_SOC_BIAS_STANDBY);
892 msleep(SLEEP_TIME);
893 WM8904_SET_BIAS_LEVEL(SND_SOC_BIAS_PREPARE);
894 msleep(SLEEP_TIME);
895 WM8904_SET_BIAS_LEVEL(SND_SOC_BIAS_ON);
896 msleep(SLEEP_TIME);
897 WM8904RegWrite(g_wm8904_i2c_handle, WM8904_ANALOGUE_LEFT_INPUT_1, 0x45, BYTE_NUM);
898 msleep(SLEEP_TIME);
899 WM8904RegWrite(g_wm8904_i2c_handle, WM8904_ANALOGUE_RIGHT_INPUT_1, 0x45, BYTE_NUM);
900
901 return 0;
902 }
903
TriggerPause(void)904 static int TriggerPause(void)
905 {
906 WM8904RegUpdateBits(g_wm8904_i2c_handle, WM8904_DAC_DIGITAL_1, WM8904_DAC_MUTE, BITS_8, BYTE_NUM);
907 msleep(SLEEP_TIME);
908 out_pga(OUT_PGA_90, BYTE_NUM_4);
909 msleep(SLEEP_TIME);
910 out_pga(OUT_PGA_94, BYTE_NUM_4);
911 msleep(SLEEP_TIME);
912 out_pga(OUT_PGA_90, BYTE_NUM_8);
913 msleep(SLEEP_TIME);
914 out_pga(OUT_PGA_94, BYTE_NUM_8);
915 msleep(SLEEP_TIME);
916
917 WM8904RegWrite(g_wm8904_i2c_handle, WM8904_POWER_MANAGEMENT_6, 0, BYTE_NUM);
918 msleep(SLEEP_TIME);
919 WM8904RegWrite(g_wm8904_i2c_handle, WM8904_CLOCK_RATES_2, 0, BYTE_NUM);
920 msleep(SLEEP_TIME);
921 WM8904RegWrite(g_wm8904_i2c_handle, WM8904_FLL_CONTROL_1, 0, BYTE_NUM);
922 msleep(SLEEP_TIME);
923 WM8904RegWrite(g_wm8904_i2c_handle, WM8904_CHARGE_PUMP_0, 0, BYTE_NUM);
924 msleep(SLEEP_TIME);
925
926 WM8904_SET_BIAS_LEVEL(SND_SOC_BIAS_PREPARE);
927 msleep(SLEEP_TIME);
928 WM8904_SET_BIAS_LEVEL(SND_SOC_BIAS_STANDBY);
929 msleep(SLEEP_TIME);
930 WM8904_SET_BIAS_LEVEL(SND_SOC_BIAS_OFF);
931
932 return 0;
933 }
Wm8904DaiTrigger(const struct AudioCard * audioCard,int cmd,const struct DaiDevice * dai)934 int32_t Wm8904DaiTrigger(const struct AudioCard *audioCard, int cmd, const struct DaiDevice *dai)
935 {
936 WM8904_CODEC_LOG_ERR("cmd = %d ", cmd);
937
938 switch (cmd) {
939 case AUDIO_DRV_PCM_IOCTL_RENDER_START:
940 TriggerRenderStart();
941 break;
942
943 case AUDIO_DRV_PCMIOCTL_CAPUTRE_START:
944 // record
945 TriggerCaptureStart();
946 break;
947
948 case AUDIO_DRV_PCM_IOCTL_RENDER_PAUSE:
949 case AUDIO_DRV_PCM_IOCTL_RENDER_STOP:
950 /* code */
951 TriggerPause();
952 break;
953
954 case AUDIO_DRV_PCM_IOCTL_CAPTURE_PAUSE:
955 case AUDIO_DRV_PCM_IOCTL_CAPTURE_STOP:
956 WM8904_SET_BIAS_LEVEL(SND_SOC_BIAS_PREPARE);
957 msleep(SLEEP_TIME);
958
959 WM8904RegWrite(g_wm8904_i2c_handle, WM8904_POWER_MANAGEMENT_6, 0, BYTE_NUM);
960 msleep(SLEEP_TIME);
961 WM8904RegWrite(g_wm8904_i2c_handle, WM8904_POWER_MANAGEMENT_0, 0, BYTE_NUM);
962 msleep(SLEEP_TIME);
963 WM8904RegWrite(g_wm8904_i2c_handle, WM8904_CLOCK_RATES_2, 0, BYTE_NUM);
964 msleep(SLEEP_TIME);
965 WM8904RegWrite(g_wm8904_i2c_handle, WM8904_FLL_CONTROL_1, 0, BYTE_NUM);
966 msleep(SLEEP_TIME);
967
968 WM8904_SET_BIAS_LEVEL(SND_SOC_BIAS_STANDBY);
969 msleep(SLEEP_TIME);
970 WM8904_SET_BIAS_LEVEL(SND_SOC_BIAS_OFF);
971 break;
972 default:
973 break;
974 }
975 return HDF_SUCCESS;
976 }
977
WM8904_Set_Sysclk(int clk_id,unsigned int freq)978 static int WM8904_Set_Sysclk(int clk_id, unsigned int freq)
979 {
980 struct wm8904_priv *priv = gpwm8904;
981
982 switch (clk_id) {
983 case WM8904_CLK_MCLK:
984 priv->sysclk_src = clk_id;
985 priv->mclk_rate = freq;
986 break;
987
988 case WM8904_CLK_FLL:
989 priv->sysclk_src = clk_id;
990 break;
991
992 default:
993 return -EINVAL;
994 }
995
996 WM8904_CODEC_LOG_DEBUG("Clock source is %d at %uHz\n", clk_id, freq);
997
998 WM8904_Configure_Clocking();
999
1000 return 0;
1001 }
1002
Wm8904ChkMasterFormatMask(unsigned int fmt,unsigned int * aif1,unsigned int * aif3)1003 static int Wm8904ChkMasterFormatMask(unsigned int fmt, unsigned int *aif1, unsigned int *aif3)
1004 {
1005 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1006 case SND_SOC_DAIFMT_CBS_CFS:
1007 break;
1008 case SND_SOC_DAIFMT_CBS_CFM:
1009 *aif3 |= WM8904_LRCLK_DIR;
1010 break;
1011 case SND_SOC_DAIFMT_CBM_CFS:
1012 *aif1 |= WM8904_BCLK_DIR;
1013 break;
1014 case SND_SOC_DAIFMT_CBM_CFM:
1015 *aif1 |= WM8904_BCLK_DIR;
1016 *aif3 |= WM8904_LRCLK_DIR;
1017 break;
1018 default:
1019 return -EINVAL;
1020 }
1021
1022 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1023 case SND_SOC_DAIFMT_DSP_B:
1024 *aif1 |= 0x3 | WM8904_AIF_LRCLK_INV;
1025 /* fall through */
1026 case SND_SOC_DAIFMT_DSP_A:
1027 *aif1 |= 0x3;
1028 break;
1029 case SND_SOC_DAIFMT_I2S:
1030 *aif1 |= 0x2;
1031 break;
1032 case SND_SOC_DAIFMT_RIGHT_J:
1033 /* nothing */
1034 break;
1035 case SND_SOC_DAIFMT_LEFT_J:
1036 *aif1 |= 0x1;
1037 break;
1038 default:
1039 return -EINVAL;
1040 }
1041
1042 return 0;
1043 }
1044
WM8904_Set_Fmt(unsigned int fmt)1045 static int WM8904_Set_Fmt(unsigned int fmt)
1046 {
1047 unsigned int aif1 = 0;
1048 unsigned int aif3 = 0;
1049
1050 Wm8904ChkMasterFormatMask(fmt, &aif1, &aif3);
1051
1052 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1053 case SND_SOC_DAIFMT_DSP_A:
1054 case SND_SOC_DAIFMT_DSP_B:
1055 /* frame inversion not valid for DSP modes */
1056 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1057 case SND_SOC_DAIFMT_NB_NF:
1058 break;
1059 case SND_SOC_DAIFMT_IB_NF:
1060 aif1 |= WM8904_AIF_BCLK_INV;
1061 break;
1062 default:
1063 return -EINVAL;
1064 }
1065 break;
1066
1067 case SND_SOC_DAIFMT_I2S:
1068 case SND_SOC_DAIFMT_RIGHT_J:
1069 case SND_SOC_DAIFMT_LEFT_J:
1070 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1071 case SND_SOC_DAIFMT_NB_NF:
1072 break;
1073 case SND_SOC_DAIFMT_IB_IF:
1074 aif1 |= WM8904_AIF_BCLK_INV | WM8904_AIF_LRCLK_INV;
1075 break;
1076 case SND_SOC_DAIFMT_IB_NF:
1077 aif1 |= WM8904_AIF_BCLK_INV;
1078 break;
1079 case SND_SOC_DAIFMT_NB_IF:
1080 aif1 |= WM8904_AIF_LRCLK_INV;
1081 break;
1082 default:
1083 return -EINVAL;
1084 }
1085 break;
1086 default:
1087 return -EINVAL;
1088 }
1089
1090 WM8904RegUpdateBits(g_wm8904_i2c_handle, WM8904_AUDIO_INTERFACE_1,
1091 WM8904_AIF_BCLK_INV | WM8904_AIF_LRCLK_INV |
1092 WM8904_AIF_FMT_MASK | WM8904_BCLK_DIR, aif1, BYTE_NUM);
1093 WM8904RegUpdateBits(g_wm8904_i2c_handle, WM8904_AUDIO_INTERFACE_3,
1094 WM8904_LRCLK_DIR, aif3, BYTE_NUM);
1095
1096 return 0;
1097 }
1098
1099 struct _fll_div {
1100 u16 fll_fratio;
1101 u16 fll_outdiv;
1102 u16 fll_clk_ref_div;
1103 u16 n;
1104 u16 k;
1105 };
1106
1107 /* The size in bits of the FLL divide multiplied by 10
1108 * to allow rounding later */
1109 #define FIXED_FLL_SIZE ((1 << 16) * 10)
1110
1111 int g_cur_bias_level = SND_SOC_BIAS_OFF;
1112
1113 #define WM8904_RATES SNDRV_PCM_RATE_8000_96000
1114
1115 #define WM8904_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
1116 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
1117
1118 int WM8904_SET_BIAS_LEVEL(enum snd_soc_bias_level level);
1119 int find_i2c_client(struct device *dev, void *data);
1120
1121 /* HdfDriverEntry implementations */
CodecDriverBind(struct HdfDeviceObject * device)1122 static int32_t CodecDriverBind(struct HdfDeviceObject *device)
1123 {
1124 if (device == NULL) {
1125 WM8904_CODEC_LOG_ERR("input para is NULL.");
1126 return HDF_FAILURE;
1127 }
1128
1129 struct CodecHost *codecHost = (struct CodecHost *)OsalMemCalloc(sizeof(*codecHost));
1130 if (codecHost == NULL) {
1131 WM8904_CODEC_LOG_ERR("malloc codecHost fail!");
1132 return HDF_FAILURE;
1133 }
1134 codecHost->device = device;
1135 device->service = &codecHost->service;
1136 return HDF_SUCCESS;
1137 }
1138
1139 struct CodecData g_g8904_codec_data = {
1140 .Init = Wm8904DevInit,
1141 .Read = CodecDeviceRegI2cRead,
1142 .Write = CodecDeviceRegI2cWrite,
1143 };
1144
1145 struct AudioDaiOps g_g8904_codec_dai_device_ops = {
1146 .Startup = Wm8904DaiStart,
1147 .HwParams = Wm8904DaiHwParamsSet,
1148 .Trigger = Wm8904DaiTrigger,
1149 };
1150
1151 struct DaiData g_g8904_codec_dai_data = {
1152 .drvDaiName = "wm8904_codec_dai",
1153 .DaiInit = Wm8904DaiDevInit,
1154 .ops = &g_g8904_codec_dai_device_ops,
1155 };
1156
1157 #define FINDFLAG 1
1158 #define WM8904_STR_LEN (6)
find_i2c_client(struct device * dev,void * data)1159 int find_i2c_client(struct device *dev, void *data)
1160 {
1161 struct i2c_client *client = to_i2c_client(dev);
1162 if (client != NULL) {
1163 if (!strncmp(client->name, "wm8904", WM8904_STR_LEN)) {
1164 *((struct i2c_client **) data) = client;
1165 return FINDFLAG;
1166 } else {
1167 return !FINDFLAG;
1168 }
1169 } else {
1170 return !FINDFLAG;
1171 }
1172 }
1173
WM8904_set_soc_bias_on(void)1174 static int WM8904_set_soc_bias_on(void)
1175 {
1176 WM8904RegUpdateBits(g_wm8904_i2c_handle, WM8904_ANALOGUE_LEFT_INPUT_1,
1177 WM8904_L_MODE_MASK, 0x01, BYTE_NUM);
1178 WM8904RegUpdateBits(g_wm8904_i2c_handle, WM8904_ANALOGUE_RIGHT_INPUT_1,
1179 WM8904_R_MODE_MASK, 0x01, BYTE_NUM);
1180 WM8904RegUpdateBits(g_wm8904_i2c_handle, WM8904_MIC_BIAS_CONTROL_0,
1181 WM8904_MIC_DET_EINT, 0x01, BYTE_NUM);
1182 g_cur_bias_level = SND_SOC_BIAS_STANDBY;
1183
1184 return 0;
1185 }
1186
WM8904_SET_BIAS_LEVEL(enum snd_soc_bias_level level)1187 int WM8904_SET_BIAS_LEVEL(enum snd_soc_bias_level level)
1188 {
1189 int ret = 0;
1190
1191 switch (level) {
1192 case SND_SOC_BIAS_ON:
1193 WM8904_set_soc_bias_on();
1194 break;
1195 case SND_SOC_BIAS_PREPARE:
1196 /* VMID resistance BYTE_NUM*50k */
1197 WM8904RegUpdateBits(g_wm8904_i2c_handle, WM8904_VMID_CONTROL_0,
1198 WM8904_VMID_RES_MASK,
1199 0x1 << WM8904_VMID_RES_SHIFT, BYTE_NUM);
1200
1201 /* Normal bias current */
1202 WM8904RegUpdateBits(g_wm8904_i2c_handle, WM8904_BIAS_CONTROL_0,
1203 WM8904_ISEL_MASK, BYTE_NUM << WM8904_ISEL_SHIFT, BYTE_NUM);
1204 g_cur_bias_level = SND_SOC_BIAS_PREPARE;
1205 break;
1206
1207 case SND_SOC_BIAS_STANDBY:
1208 if (g_cur_bias_level == SND_SOC_BIAS_OFF) {
1209 ret = regulator_bulk_enable(ARRAY_SIZE(gpwm8904->supplies),
1210 gpwm8904->supplies);
1211 if (ret != 0) {
1212 WM8904_CODEC_LOG_ERR("Failed to enable supplies: %d", ret);
1213 return ret;
1214 }
1215
1216 /* Enable bias */
1217 WM8904RegUpdateBits(g_wm8904_i2c_handle, WM8904_BIAS_CONTROL_0,
1218 WM8904_BIAS_ENA, WM8904_BIAS_ENA, BYTE_NUM);
1219 /* Enable VMID, VMID buffering, 2*5k resistance */
1220 WM8904RegUpdateBits(g_wm8904_i2c_handle, WM8904_VMID_CONTROL_0,
1221 WM8904_VMID_ENA |
1222 WM8904_VMID_RES_MASK,
1223 WM8904_VMID_ENA |
1224 (0x3 << WM8904_VMID_RES_SHIFT), BYTE_NUM);
1225 /* Let VMID ramp */
1226 msleep(SLEEP_TIME_1);
1227 }
1228
1229 /* Maintain VMID with 2*250k */
1230 WM8904RegUpdateBits(g_wm8904_i2c_handle, WM8904_VMID_CONTROL_0,
1231 WM8904_VMID_RES_MASK,
1232 (0x2 << WM8904_VMID_RES_SHIFT), BYTE_NUM);
1233
1234 /* Bias current *0.5 */
1235 WM8904RegUpdateBits(g_wm8904_i2c_handle, WM8904_BIAS_CONTROL_0,
1236 WM8904_ISEL_MASK, 0, BYTE_NUM);
1237 g_cur_bias_level = SND_SOC_BIAS_STANDBY;
1238
1239 break;
1240
1241 case SND_SOC_BIAS_OFF:
1242 /* Turn off VMID */
1243 WM8904RegUpdateBits(g_wm8904_i2c_handle, WM8904_VMID_CONTROL_0,
1244 (WM8904_VMID_RES_MASK | WM8904_VMID_ENA), 0, BYTE_NUM);
1245
1246 /* Stop bias generation */
1247 WM8904RegUpdateBits(g_wm8904_i2c_handle, WM8904_BIAS_CONTROL_0,
1248 WM8904_BIAS_ENA, 0, BYTE_NUM);
1249
1250 regulator_bulk_disable(ARRAY_SIZE(gpwm8904->supplies),
1251 gpwm8904->supplies);
1252 clk_disable_unprepare(gpwm8904->mclk);
1253 g_cur_bias_level = SND_SOC_BIAS_OFF;
1254 break;
1255 }
1256 return 0;
1257 }
1258
Wm8904RegConfig(void)1259 static int Wm8904RegConfig(void)
1260 {
1261 int ret = 0;
1262 unsigned int val = 0;
1263
1264 ret = WM8904RegRead(g_wm8904_i2c_handle, WM8904_SW_RESET_AND_ID, &val, BYTE_NUM);
1265 if (ret < 0) {
1266 regulator_bulk_disable(ARRAY_SIZE(gpwm8904->supplies), gpwm8904->supplies);
1267 return 0;
1268 }
1269
1270 if (val != 0x8904) {
1271 regulator_bulk_disable(ARRAY_SIZE(gpwm8904->supplies), gpwm8904->supplies);
1272 return -EINVAL;
1273 }
1274
1275 ret = WM8904RegRead(g_wm8904_i2c_handle, WM8904_REVISION, &val, BYTE_NUM);
1276 if (ret < 0) {
1277 regulator_bulk_disable(ARRAY_SIZE(gpwm8904->supplies), gpwm8904->supplies);
1278 return 0;
1279 }
1280
1281 ret = WM8904RegWrite(g_wm8904_i2c_handle, WM8904_SW_RESET_AND_ID, 0, BYTE_NUM);
1282 if (ret < 0) {
1283 regulator_bulk_disable(ARRAY_SIZE(gpwm8904->supplies), gpwm8904->supplies);
1284 return 0;
1285 }
1286
1287 return 0;
1288 }
1289
Wm8904UpdateReg(void)1290 static int Wm8904UpdateReg(void)
1291 {
1292 unsigned int i = 0;
1293
1294 /* Change some default settings - latch VU and enable ZC */
1295 WM8904RegUpdateBits(g_wm8904_i2c_handle, WM8904_ADC_DIGITAL_VOLUME_LEFT,
1296 WM8904_ADC_VU, WM8904_ADC_VU, BYTE_NUM);
1297 WM8904RegUpdateBits(g_wm8904_i2c_handle, WM8904_ADC_DIGITAL_VOLUME_RIGHT,
1298 WM8904_ADC_VU, WM8904_ADC_VU, BYTE_NUM);
1299 WM8904RegUpdateBits(g_wm8904_i2c_handle, WM8904_DAC_DIGITAL_VOLUME_LEFT,
1300 WM8904_DAC_VU, WM8904_DAC_VU, BYTE_NUM);
1301 WM8904RegUpdateBits(g_wm8904_i2c_handle, WM8904_DAC_DIGITAL_VOLUME_RIGHT,
1302 WM8904_DAC_VU, WM8904_DAC_VU, BYTE_NUM);
1303 WM8904RegUpdateBits(g_wm8904_i2c_handle, WM8904_ANALOGUE_OUT1_LEFT,
1304 WM8904_HPOUT_VU | WM8904_HPOUTLZC,
1305 WM8904_HPOUT_VU | WM8904_HPOUTLZC, BYTE_NUM);
1306 WM8904RegUpdateBits(g_wm8904_i2c_handle, WM8904_ANALOGUE_OUT1_RIGHT,
1307 WM8904_HPOUT_VU | WM8904_HPOUTRZC,
1308 WM8904_HPOUT_VU | WM8904_HPOUTRZC, BYTE_NUM);
1309 WM8904RegUpdateBits(g_wm8904_i2c_handle, WM8904_ANALOGUE_OUT2_LEFT,
1310 WM8904_LINEOUT_VU | WM8904_LINEOUTLZC,
1311 WM8904_LINEOUT_VU | WM8904_LINEOUTLZC, BYTE_NUM);
1312 WM8904RegUpdateBits(g_wm8904_i2c_handle, WM8904_ANALOGUE_OUT2_RIGHT,
1313 WM8904_LINEOUT_VU | WM8904_LINEOUTRZC,
1314 WM8904_LINEOUT_VU | WM8904_LINEOUTRZC, BYTE_NUM);
1315 WM8904RegUpdateBits(g_wm8904_i2c_handle, WM8904_CLOCK_RATES_0,
1316 WM8904_SR_MODE, 0, BYTE_NUM);
1317
1318 /* Apply configuration from the platform data. */
1319 if (gpwm8904->pdata) {
1320 for (i = 0; i < WM8904_GPIO_REGS; i++) {
1321 if (!gpwm8904->pdata->gpio_cfg[i]) {
1322 continue;
1323 }
1324
1325 WM8904RegUpdateBits(g_wm8904_i2c_handle, WM8904_GPIO_CONTROL_1 + i,
1326 0xffff, gpwm8904->pdata->gpio_cfg[i], BYTE_NUM);
1327 }
1328
1329 /* Zero is the default value for these anyway */
1330 for (i = 0; i < WM8904_MIC_REGS; i++) {
1331 WM8904RegUpdateBits(g_wm8904_i2c_handle, WM8904_MIC_BIAS_CONTROL_0 + i,
1332 0xffff, gpwm8904->pdata->mic_cfg[i], BYTE_NUM);
1333 }
1334 }
1335
1336 /* Set Class W by default - this will be managed by the Class
1337 * G widget at runtime where bypass paths are available.
1338 */
1339 WM8904RegUpdateBits(g_wm8904_i2c_handle, WM8904_CLASS_W_0,
1340 WM8904_CP_DYN_PWR, WM8904_CP_DYN_PWR, BYTE_NUM);
1341
1342 /* Use normal bias source */
1343 WM8904RegUpdateBits(g_wm8904_i2c_handle, WM8904_BIAS_CONTROL_0,
1344 WM8904_POBCTRL, 0, BYTE_NUM);
1345
1346 return 0;
1347 }
1348
Wm8904DriverInit(struct HdfDeviceObject * device)1349 static int32_t Wm8904DriverInit(struct HdfDeviceObject *device)
1350 {
1351 struct i2c_client **data;
1352 int ret = 0, i = 0;
1353 data = (struct i2c_client **)kzalloc(sizeof(struct i2c_client *), GFP_KERNEL);
1354
1355 bus_for_each_dev(&i2c_bus_type, NULL, (void*)(data), find_i2c_client);
1356
1357 struct i2c_client *i2c = *data;
1358 if (i2c != NULL) {
1359 WM8904_CODEC_LOG_DEBUG("find kernel %s device", i2c->name);
1360 } else {
1361 WM8904_CODEC_LOG_ERR("wm8904 i2c dev not exist");
1362 return HDF_ERR_INVALID_OBJECT;
1363 }
1364
1365 gpwm8904 = devm_kzalloc(&i2c->dev, sizeof(struct wm8904_priv), GFP_KERNEL);
1366 if (gpwm8904 == NULL) {
1367 return -ENOMEM;
1368 }
1369
1370 g_wm8904_i2c_handle = WM8904I2cOpen();
1371 ret = WM8904I2cAllRegDefautInit(g_wm8904_i2c_handle);
1372
1373 gpwm8904->mclk = devm_clk_get(&i2c->dev, "mclk");
1374 if (IS_ERR(gpwm8904->mclk)) {
1375 ret = PTR_ERR(gpwm8904->mclk);
1376 WM8904_CODEC_LOG_ERR("Failed to get MCLK\n");
1377 return ret;
1378 }
1379
1380 i2c_set_clientdata(i2c, gpwm8904);
1381 gpwm8904->pdata = i2c->dev.platform_data;
1382
1383 for (i = 0; i < ARRAY_SIZE(gpwm8904->supplies); i++) {
1384 gpwm8904->supplies[i].supply = wm8904_supply_names[i];
1385 }
1386
1387 ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(gpwm8904->supplies),
1388 gpwm8904->supplies);
1389 if (ret != 0) {
1390 WM8904_CODEC_LOG_ERR("Failed to request supplies: %d", ret);
1391 return ret;
1392 }
1393 ret = regulator_bulk_enable(ARRAY_SIZE(gpwm8904->supplies), gpwm8904->supplies);
1394 if (ret != 0) {
1395 WM8904_CODEC_LOG_ERR("Failed to enable supplies: %d", ret);
1396 return ret;
1397 }
1398
1399 Wm8904RegConfig();
1400
1401 Wm8904UpdateReg();
1402
1403 regulator_bulk_disable(ARRAY_SIZE(gpwm8904->supplies), gpwm8904->supplies);
1404
1405 WM8904StateInit(g_wm8904_i2c_handle);
1406
1407 return HDF_SUCCESS;
1408 }
1409
CodecDriverInit(struct HdfDeviceObject * device)1410 static int32_t CodecDriverInit(struct HdfDeviceObject *device)
1411 {
1412 int32_t ret = 0;
1413
1414 WM8904_CODEC_LOG_DEBUG("Success.");
1415 if (device == NULL) {
1416 WM8904_CODEC_LOG_ERR("device is NULL.");
1417 return HDF_ERR_INVALID_OBJECT;
1418 }
1419 ret = CodecGetConfigInfo(device, &g_g8904_codec_data);
1420 if (ret != HDF_SUCCESS) {
1421 WM8904_CODEC_LOG_ERR("get config info failed.");
1422 return ret;
1423 }
1424
1425 if (CodecSetConfigInfoOfControls(&g_g8904_codec_data, &g_g8904_codec_dai_data) != HDF_SUCCESS) {
1426 WM8904_CODEC_LOG_ERR("set config info failed.");
1427 return HDF_FAILURE;
1428 }
1429 ret = CodecGetServiceName(device, &g_g8904_codec_data.drvCodecName);
1430 if (ret != HDF_SUCCESS) {
1431 WM8904_CODEC_LOG_ERR("get service name fail");
1432 return ret;
1433 }
1434
1435 ret = AudioRegisterCodec(device, &g_g8904_codec_data, &g_g8904_codec_dai_data);
1436 if (ret != HDF_SUCCESS) {
1437 WM8904_CODEC_LOG_ERR("register dai fail.");
1438 return ret;
1439 }
1440
1441 ret = Wm8904DriverInit(device);
1442 if (ret != HDF_SUCCESS) {
1443 WM8904_CODEC_LOG_ERR("accessory init fail");
1444 return ret;
1445 }
1446
1447 WM8904_CODEC_LOG_ERR("success!");
1448 return HDF_SUCCESS;
1449 }
1450
CodecDriverRelease(struct HdfDeviceObject * device)1451 static void CodecDriverRelease(struct HdfDeviceObject *device)
1452 {
1453 if (device == NULL) {
1454 WM8904_CODEC_LOG_ERR("device is NULL");
1455 return;
1456 }
1457 }
1458
1459 struct HdfDriverEntry g_g8904_codec_driver_entry = {
1460 .moduleVersion = 1,
1461 .moduleName = "CODEC_WM8904",
1462 .Bind = CodecDriverBind,
1463 .Init = CodecDriverInit,
1464 .Release = CodecDriverRelease,
1465 };
1466 HDF_INIT(g_g8904_codec_driver_entry);
1467
1468