1 /* 2 * Copyright (C) 2021–2022 Beijing OSWare Technology Co., Ltd 3 * This file contains confidential and proprietary information of 4 * OSWare Technology Co., Ltd 5 * 6 * Licensed under the Apache License, Version 2.0 (the "License"); 7 * you may not use this file except in compliance with the License. 8 * You may obtain a copy of the License at 9 * 10 * http://www.apache.org/licenses/LICENSE-2.0 11 * 12 * Unless required by applicable law or agreed to in writing, software 13 * distributed under the License is distributed on an "AS IS" BASIS, 14 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 * See the License for the specific language governing permissions and 16 * limitations under the License. 17 */ 18 19 #ifndef SAI_DRIVER_H 20 #define SAI_DRIVER_H 21 22 #include "audio_platform_if.h" 23 24 /* 25 * DAI hardware audio formats. 26 * 27 * Describes the physical PCM data formating and clocking. Add new formats 28 * to the end. 29 */ 30 #define SND_SOC_DAIFMT_I2S (1) /* I2S mode */ 31 #define SND_SOC_DAIFMT_RIGHT_J (2) /* Right Justified mode */ 32 #define SND_SOC_DAIFMT_LEFT_J (3) /* Left Justified mode */ 33 #define SND_SOC_DAIFMT_DSP_A (4) /* L data MSB after FRM LRC */ 34 #define SND_SOC_DAIFMT_DSP_B (5) /* L data MSB during FRM LRC */ 35 #define SND_SOC_DAIFMT_AC97 (6) /* AC97 */ 36 #define SND_SOC_DAIFMT_PDM (7) /* Pulse density modulation */ 37 38 /* left and right justified also known as MSB and LSB respectively */ 39 #define SND_SOC_DAIFMT_MSB SND_SOC_DAIFMT_LEFT_J 40 #define SND_SOC_DAIFMT_LSB SND_SOC_DAIFMT_RIGHT_J 41 42 /* 43 * DAI hardware signal inversions. 44 * 45 * Specifies whether the DAI can also support inverted clocks for the specified 46 * format. 47 */ 48 #define SND_SOC_DAIFMT_NB_NF (1 << 8) /* normal bit clock + frame */ 49 #define SND_SOC_DAIFMT_NB_IF (2 << 8) /* normal BCLK + inv FRM */ 50 #define SND_SOC_DAIFMT_IB_NF (3 << 8) /* invert BCLK + nor FRM */ 51 #define SND_SOC_DAIFMT_IB_IF (4 << 8) /* invert BCLK + FRM */ 52 53 /* 54 * DAI hardware clock masters. 55 * 56 * This is wrt the codec, the inverse is true for the interface 57 * i.e. if the codec is clk and FRM master then the interface is 58 * clk and frame slave. 59 */ 60 #define SND_SOC_DAIFMT_CBM_CFM (1 << 12) /* codec clk & FRM master */ 61 #define SND_SOC_DAIFMT_CBS_CFM (2 << 12) /* codec clk slave & FRM master */ 62 #define SND_SOC_DAIFMT_CBM_CFS (3 << 12) /* codec clk master & frame slave */ 63 #define SND_SOC_DAIFMT_CBS_CFS (4 << 12) /* codec clk & FRM slave */ 64 65 #define SND_SOC_DAIFMT_FORMAT_MASK (0x000f) 66 #define SND_SOC_DAIFMT_CLOCK_MASK (0x00f0) 67 #define SND_SOC_DAIFMT_INV_MASK (0x0f00) 68 #define SND_SOC_DAIFMT_MASTER_MASK (0xf000) 69 70 #define FSL_SAI_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \ 71 SNDRV_PCM_FMTBIT_S24_LE | \ 72 SNDRV_PCM_FMTBIT_S32_LE | \ 73 SNDRV_PCM_FMTBIT_DSD_U8 | \ 74 SNDRV_PCM_FMTBIT_DSD_U16_LE | \ 75 SNDRV_PCM_FMTBIT_DSD_U32_LE) 76 77 /* SAI Register Map Register */ 78 #define FSL_SAI_VERID (0x00) /* SAI Version ID Register */ 79 #define FSL_SAI_PARAM (0x04) /* SAI Parameter Register */ 80 #define FSL_SAI_TCSR(offset) (0x00 + (offset)) /* SAI Transmit Control */ 81 #define FSL_SAI_TCR1(offset) (0x04 + (offset)) /* SAI Transmit Configuration 1 */ 82 #define FSL_SAI_TCR2(offset) (0x08 + (offset)) /* SAI Transmit Configuration 2 */ 83 #define FSL_SAI_TCR3(offset) (0x0c + (offset)) /* SAI Transmit Configuration 3 */ 84 #define FSL_SAI_TCR4(offset) (0x10 + (offset)) /* SAI Transmit Configuration 4 */ 85 #define FSL_SAI_TCR5(offset) (0x14 + (offset)) /* SAI Transmit Configuration 5 */ 86 #define FSL_SAI_TDR0 (0x20) /* SAI Transmit Data */ 87 #define FSL_SAI_TDR1 (0x24) /* SAI Transmit Data */ 88 #define FSL_SAI_TDR2 (0x28) /* SAI Transmit Data */ 89 #define FSL_SAI_TDR3 (0x2C) /* SAI Transmit Data */ 90 #define FSL_SAI_TDR4 (0x30) /* SAI Transmit Data */ 91 #define FSL_SAI_TDR5 (0x34) /* SAI Transmit Data */ 92 #define FSL_SAI_TDR6 (0x38) /* SAI Transmit Data */ 93 #define FSL_SAI_TDR7 (0x3C) /* SAI Transmit Data */ 94 #define FSL_SAI_TFR0 (0x40) /* SAI Transmit FIFO */ 95 #define FSL_SAI_TFR1 (0x44) /* SAI Transmit FIFO */ 96 #define FSL_SAI_TFR2 (0x48) /* SAI Transmit FIFO */ 97 #define FSL_SAI_TFR3 (0x4C) /* SAI Transmit FIFO */ 98 #define FSL_SAI_TFR4 (0x50) /* SAI Transmit FIFO */ 99 #define FSL_SAI_TFR5 (0x54) /* SAI Transmit FIFO */ 100 #define FSL_SAI_TFR6 (0x58) /* SAI Transmit FIFO */ 101 #define FSL_SAI_TFR7 (0x5C) /* SAI Transmit FIFO */ 102 #define FSL_SAI_TMR (0x60) /* SAI Transmit Mask */ 103 #define FSL_SAI_TTCTL (0x70) /* SAI Transmit Timestamp Control Register */ 104 #define FSL_SAI_TTCTN (0x74) /* SAI Transmit Timestamp Counter Register */ 105 #define FSL_SAI_TBCTN (0x78) /* SAI Transmit Bit Counter Register */ 106 #define FSL_SAI_TTCAP (0x7C) /* SAI Transmit Timestamp Capture */ 107 108 #define FSL_SAI_RCSR(offset) (0x80 + (offset)) /* SAI Receive Control */ 109 #define FSL_SAI_RCR1(offset) (0x84 + (offset)) /* SAI Receive Configuration 1 */ 110 #define FSL_SAI_RCR2(offset) (0x88 + (offset)) /* SAI Receive Configuration 2 */ 111 #define FSL_SAI_RCR3(offset) (0x8c + (offset)) /* SAI Receive Configuration 3 */ 112 #define FSL_SAI_RCR4(offset) (0x90 + (offset)) /* SAI Receive Configuration 4 */ 113 #define FSL_SAI_RCR5(offset) (0x94 + (offset)) /* SAI Receive Configuration 5 */ 114 #define FSL_SAI_RDR0 (0xa0) /* SAI Receive Data */ 115 #define FSL_SAI_RDR1 (0xa4) /* SAI Receive Data */ 116 #define FSL_SAI_RDR2 (0xa8) /* SAI Receive Data */ 117 #define FSL_SAI_RDR3 (0xac) /* SAI Receive Data */ 118 #define FSL_SAI_RDR4 (0xb0) /* SAI Receive Data */ 119 #define FSL_SAI_RDR5 (0xb4) /* SAI Receive Data */ 120 #define FSL_SAI_RDR6 (0xb8) /* SAI Receive Data */ 121 #define FSL_SAI_RDR7 (0xbc) /* SAI Receive Data */ 122 #define FSL_SAI_RFR0 (0xc0) /* SAI Receive FIFO */ 123 #define FSL_SAI_RFR1 (0xc4) /* SAI Receive FIFO */ 124 #define FSL_SAI_RFR2 (0xc8) /* SAI Receive FIFO */ 125 #define FSL_SAI_RFR3 (0xcc) /* SAI Receive FIFO */ 126 #define FSL_SAI_RFR4 (0xd0) /* SAI Receive FIFO */ 127 #define FSL_SAI_RFR5 (0xd4) /* SAI Receive FIFO */ 128 #define FSL_SAI_RFR6 (0xd8) /* SAI Receive FIFO */ 129 #define FSL_SAI_RFR7 (0xdc) /* SAI Receive FIFO */ 130 #define FSL_SAI_RMR (0xe0) /* SAI Receive Mask */ 131 #define FSL_SAI_RTCTL (0xf0) /* SAI Receive Timestamp Control Register */ 132 #define FSL_SAI_RTCTN (0xf4) /* SAI Receive Timestamp Counter Register */ 133 #define FSL_SAI_RBCTN (0xf8) /* SAI Receive Bit Counter Register */ 134 #define FSL_SAI_RTCAP (0xfc) /* SAI Receive Timestamp Capture */ 135 136 #define FSL_SAI_MCTL (0x100) /* SAI MCLK Control Register */ 137 #define FSL_SAI_MDIV (0x104) /* SAI MCLK Divide Register */ 138 139 #define FSL_SAI_xCSR(tx, off) ((tx) ? FSL_SAI_TCSR(off) : FSL_SAI_RCSR(off)) 140 #define FSL_SAI_xCR1(tx, off) ((tx) ? FSL_SAI_TCR1(off) : FSL_SAI_RCR1(off)) 141 #define FSL_SAI_xCR2(tx, off) ((tx) ? FSL_SAI_TCR2(off) : FSL_SAI_RCR2(off)) 142 #define FSL_SAI_xCR3(tx, off) ((tx) ? FSL_SAI_TCR3(off) : FSL_SAI_RCR3(off)) 143 #define FSL_SAI_xCR4(tx, off) ((tx) ? FSL_SAI_TCR4(off) : FSL_SAI_RCR4(off)) 144 #define FSL_SAI_xCR5(tx, off) ((tx) ? FSL_SAI_TCR5(off) : FSL_SAI_RCR5(off)) 145 #define FSL_SAI_xMR(tx) ((tx) ? FSL_SAI_TMR : FSL_SAI_RMR) 146 147 /* SAI Transmit/Receive Control Register */ 148 #define FSL_SAI_CSR_TERE BIT(31) 149 #define FSL_SAI_CSR_SE BIT(30) 150 #define FSL_SAI_CSR_FR BIT(25) 151 #define FSL_SAI_CSR_SR BIT(24) 152 #define FSL_SAI_CSR_xF_SHIFT (16) 153 #define FSL_SAI_CSR_xF_W_SHIFT (18) 154 #define FSL_SAI_CSR_xF_MASK (0x1f << FSL_SAI_CSR_xF_SHIFT) 155 #define FSL_SAI_CSR_xF_W_MASK (0x7 << FSL_SAI_CSR_xF_W_SHIFT) 156 #define FSL_SAI_CSR_WSF BIT(20) 157 #define FSL_SAI_CSR_SEF BIT(19) 158 #define FSL_SAI_CSR_FEF BIT(18) 159 #define FSL_SAI_CSR_FWF BIT(17) 160 #define FSL_SAI_CSR_FRF BIT(16) 161 #define FSL_SAI_CSR_xIE_SHIFT (8) 162 #define FSL_SAI_CSR_xIE_MASK (0x1f << FSL_SAI_CSR_xIE_SHIFT) 163 #define FSL_SAI_CSR_WSIE BIT(12) 164 #define FSL_SAI_CSR_SEIE BIT(11) 165 #define FSL_SAI_CSR_FEIE BIT(10) 166 #define FSL_SAI_CSR_FWIE BIT(9) 167 #define FSL_SAI_CSR_FRIE BIT(8) 168 #define FSL_SAI_CSR_FRDE BIT(0) 169 170 /* SAI Transmit and Receive Configuration 1 Register */ 171 #define FSL_SAI_CR1_RFW_MASK (0x1f) 172 173 /* SAI Transmit and Receive Configuration 2 Register */ 174 #define FSL_SAI_CR2_SYNC BIT(30) 175 #define FSL_SAI_CR2_MSEL_MASK (0x3 << 26) 176 #define FSL_SAI_CR2_MSEL_BUS (0) 177 #define FSL_SAI_CR2_MSEL_MCLK1 BIT(26) 178 #define FSL_SAI_CR2_MSEL_MCLK2 BIT(27) 179 #define FSL_SAI_CR2_MSEL_MCLK3 (BIT(26) | BIT(27)) 180 #define FSL_SAI_CR2_MSEL(ID) ((ID) << 26) 181 #define FSL_SAI_CR2_BCP BIT(25) 182 #define FSL_SAI_CR2_BCD_MSTR BIT(24) 183 #define FSL_SAI_CR2_BYP BIT(23) /* BCLK bypass */ 184 #define FSL_SAI_CR2_DIV_MASK (0xff) 185 186 /* SAI Transmit and Receive Configuration 3 Register */ 187 #define FSL_SAI_CR3_TRCE_MASK (0xff << 16) 188 #define FSL_SAI_CR3_TRCE(x) ((x) << 16) 189 #define FSL_SAI_CR3_WDFL(x) (x) 190 #define FSL_SAI_CR3_WDFL_MASK (0x1f) 191 192 /* SAI Transmit and Receive Configuration 4 Register */ 193 194 #define FSL_SAI_CR4_FCONT BIT(28) 195 #define FSL_SAI_CR4_FCOMB_SHIFT BIT(26) 196 #define FSL_SAI_CR4_FCOMB_SOFT BIT(27) 197 #define FSL_SAI_CR4_FCOMB_MASK (0x3 << 26) 198 #define FSL_SAI_CR4_FPACK_8 (0x2 << 24) 199 #define FSL_SAI_CR4_FPACK_16 (0x3 << 24) 200 #define FSL_SAI_CR4_FRSZ(x) (((x) - 1) << 16) 201 #define FSL_SAI_CR4_FRSZ_MASK (0x1f << 16) 202 #define FSL_SAI_CR4_SYWD(x) (((x) - 1) << 8) 203 #define FSL_SAI_CR4_SYWD_MASK (0x1f << 8) 204 #define FSL_SAI_CR4_CHMOD (1 << 5) 205 #define FSL_SAI_CR4_CHMOD_MASK (1 << 5) 206 #define FSL_SAI_CR4_MF BIT(4) 207 #define FSL_SAI_CR4_FSE BIT(3) 208 #define FSL_SAI_CR4_FSP BIT(1) 209 #define FSL_SAI_CR4_FSD_MSTR BIT(0) 210 211 /* SAI Transmit and Receive Configuration 5 Register */ 212 #define FSL_SAI_CR5_WNW(x) (((x) - 1) << 24) 213 #define FSL_SAI_CR5_WNW_MASK (0x1f << 24) 214 #define FSL_SAI_CR5_W0W(x) (((x) - 1) << 16) 215 #define FSL_SAI_CR5_W0W_MASK (0x1f << 16) 216 #define FSL_SAI_CR5_FBT(x) ((x) << 8) 217 #define FSL_SAI_CR5_FBT_MASK (0x1f << 8) 218 219 /* SAI MCLK Control Register */ 220 #define FSL_SAI_MCTL_MCLK_EN BIT(30) /* MCLK Enable */ 221 #define FSL_SAI_MCTL_MSEL_MASK (0x3 << 24) 222 #define FSL_SAI_MCTL_MSEL(ID) ((ID) << 24) 223 #define FSL_SAI_MCTL_MSEL_BUS (0) 224 #define FSL_SAI_MCTL_MSEL_MCLK1 BIT(24) 225 #define FSL_SAI_MCTL_MSEL_MCLK2 BIT(25) 226 #define FSL_SAI_MCTL_MSEL_MCLK3 (BIT(24) | BIT(25)) 227 #define FSL_SAI_MCTL_DIV_EN BIT(23) 228 #define FSL_SAI_MCTL_DIV_MASK (0xFF) 229 230 /* SAI VERID Register */ 231 #define FSL_SAI_VER_ID_SHIFT (16) 232 #define FSL_SAI_VER_ID_MASK (0xFFFF << FSL_SAI_VER_ID_SHIFT) 233 #define FSL_SAI_VER_EFIFO_EN BIT(0) 234 #define FSL_SAI_VER_TSTMP_EN BIT(1) 235 236 /* SAI PARAM Register */ 237 #define FSL_SAI_PAR_SPF_SHIFT (16) 238 #define FSL_SAI_PAR_SPF_MASK (0x0F << FSL_SAI_PAR_SPF_SHIFT) 239 #define FSL_SAI_PAR_WPF_SHIFT (8) 240 #define FSL_SAI_PAR_WPF_MASK (0x0F << FSL_SAI_PAR_WPF_SHIFT) 241 #define FSL_SAI_PAR_DLN_MASK (0x0F) 242 243 /* SAI MCLK Divide Register */ 244 #define FSL_SAI_MDIV_MASK (0xFFFFF) 245 246 /* SAI type */ 247 #define FSL_SAI_DMA BIT(0) 248 #define FSL_SAI_USE_AC97 BIT(1) 249 #define FSL_SAI_NET BIT(2) 250 #define FSL_SAI_TRA_SYN BIT(3) 251 #define FSL_SAI_REC_SYN BIT(4) 252 #define FSL_SAI_USE_I2S_SLAVE BIT(5) 253 254 #define FSL_FMT_TRANSMITTER (0) 255 #define FSL_FMT_RECEIVER (1) 256 257 /* SAI clock sources */ 258 #define FSL_SAI_CLK_BUS (0) 259 #define FSL_SAI_CLK_MAST1 (1) 260 #define FSL_SAI_CLK_MAST2 (2) 261 #define FSL_SAI_CLK_MAST3 (3) 262 263 #define FSL_SAI_MCLK_MAX (4) 264 265 /* SAI data transfer numbers per DMA request */ 266 #define FSL_SAI_MAXBURST_TX (6) 267 #define FSL_SAI_MAXBURST_RX (6) 268 269 #define SAI_FLAG_PMQOS BIT(0) 270 271 /* SAI timestamp and bitcounter */ 272 #define FSL_SAI_xTCTL_TSEN BIT(0) 273 #define FSL_SAI_xTCTL_TSINC BIT(1) 274 #define FSL_SAI_xTCTL_RTSC BIT(8) 275 #define FSL_SAI_xTCTL_RBC BIT(9) 276 277 #define FSL_REG_OFFSET (8) 278 279 #define CLK_ENABLED (1) 280 #define PLAYBACK (2) 281 282 #define TX (1) 283 #define RX (0) 284 285 #define SOC_CLOCK_IN (0) 286 #define SOC_CLOCK_OUT (1) 287 288 struct fsl_sai_verid { 289 u32 id; 290 bool timestamp_en; 291 bool extfifo_en; 292 bool loaded; 293 }; 294 295 struct fsl_sai_param { 296 u32 spf; /* max slots per frame */ 297 u32 wpf; /* words in fifo */ 298 u32 dln; /* number of datalines implemented */ 299 }; 300 301 struct fsl_sai_dl_cfg { 302 unsigned int pins; 303 unsigned int mask[2]; 304 unsigned int offset[2]; 305 }; 306 307 struct fsl_sai { 308 struct regmap *regmap; 309 struct clk *bus_clk; 310 struct clk *mclk_clk[FSL_SAI_MCLK_MAX]; 311 struct clk *pll8k_clk; 312 struct clk *pll11k_clk; 313 314 char *sai_name; 315 316 uint8_t reg_offset; 317 uint32_t dataline; 318 uint32_t fifo_depth; 319 320 bool slave_mode[2]; 321 bool is_lsb_first; 322 bool is_dsp_mode; 323 bool is_multi_lane; 324 bool synchronous[2]; 325 bool is_stream_opened[2]; 326 bool is_dsd; 327 328 int pcm_dl_cfg_cnt; 329 int dsd_dl_cfg_cnt; 330 struct fsl_sai_dl_cfg *pcm_dl_cfg; 331 struct fsl_sai_dl_cfg *dsd_dl_cfg; 332 333 unsigned int masterflag[2]; 334 335 unsigned int mclk_id[2]; 336 unsigned int mclk_streams; 337 unsigned int slots; 338 unsigned int slot_width; 339 unsigned int bitclk_ratio; 340 341 struct pinctrl *pinctrl; 342 struct pinctrl_state *pins_state; 343 344 struct fsl_sai_verid verid; 345 struct fsl_sai_param param; 346 }; 347 348 int32_t SaiSetDaiFmt(const struct PlatformData *pd, unsigned int fmt); 349 int32_t SaiSetDaiTdmSlot(const struct PlatformData *pd, int32_t tx_mask, 350 int32_t rx_mask, int32_t slots, int32_t slot_width); 351 int32_t SaiSetSysclk(const struct PlatformData *pd, int clk_id, unsigned int freq, int dir); 352 int32_t SaiSetHwParams(const struct PlatformData *pd, const enum AudioStreamType streamType); 353 int32_t SaiDriverInit(struct PlatformData *pd); 354 int32_t SaiTrigger(const struct DaiData *pd, int cmd, int isTx); 355 int32_t SaiRuntimeResume(const struct PlatformData *platformData); 356 int32_t SaiRuntimeSuspend(const struct DaiData *platformData); 357 int32_t SaiDaiProbe(const struct PlatformData *platformData); 358 int32_t SaiWrite(const struct PlatformData *platformData, int i); 359 360 #endif 361