1 /******************************************************************************
2 *
3 * Copyright(c) 2007 - 2017 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26 /*@************************************************************
27 * include files
28 ************************************************************/
29 #include "mp_precomp.h"
30 #include "phydm_precomp.h"
31
32 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
33 #if WPP_SOFTWARE_TRACE
34 #include "PhyDM_Adaptivity.tmh"
35 #endif
36 #endif
37 #ifdef PHYDM_SUPPORT_ADAPTIVITY
38 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
39 boolean
phydm_check_channel_plan(void * dm_void)40 phydm_check_channel_plan(void *dm_void)
41 {
42 struct dm_struct *dm = (struct dm_struct *)dm_void;
43 struct phydm_adaptivity_struct *adapt = &dm->adaptivity;
44 void *adapter = dm->adapter;
45 PMGNT_INFO mgnt_info = &((PADAPTER)adapter)->MgntInfo;
46
47 if (mgnt_info->RegEnableAdaptivity != 2)
48 return false;
49
50 if (!dm->carrier_sense_enable) { /*@check domain Code for adaptivity or CarrierSense*/
51 if ((*dm->band_type == ODM_BAND_5G) &&
52 !(adapt->regulation_5g == REGULATION_ETSI || adapt->regulation_5g == REGULATION_WW)) {
53 PHYDM_DBG(dm, DBG_ADPTVTY,
54 "adaptivity skip 5G domain code : %d\n",
55 adapt->regulation_5g);
56 return true;
57 } else if ((*dm->band_type == ODM_BAND_2_4G) &&
58 !(adapt->regulation_2g == REGULATION_ETSI || adapt->regulation_2g == REGULATION_WW)) {
59 PHYDM_DBG(dm, DBG_ADPTVTY,
60 "adaptivity skip 2.4G domain code : %d\n",
61 adapt->regulation_2g);
62 return true;
63 } else if ((*dm->band_type != ODM_BAND_2_4G) && (*dm->band_type != ODM_BAND_5G)) {
64 PHYDM_DBG(dm, DBG_ADPTVTY,
65 "adaptivity neither 2G nor 5G band, return\n");
66 return true;
67 }
68 } else {
69 if ((*dm->band_type == ODM_BAND_5G) &&
70 !(adapt->regulation_5g == REGULATION_MKK || adapt->regulation_5g == REGULATION_WW)) {
71 PHYDM_DBG(dm, DBG_ADPTVTY,
72 "CarrierSense skip 5G domain code : %d\n",
73 adapt->regulation_5g);
74 return true;
75 } else if ((*dm->band_type == ODM_BAND_2_4G) &&
76 !(adapt->regulation_2g == REGULATION_MKK || adapt->regulation_2g == REGULATION_WW)) {
77 PHYDM_DBG(dm, DBG_ADPTVTY,
78 "CarrierSense skip 2.4G domain code : %d\n",
79 adapt->regulation_2g);
80 return true;
81 } else if ((*dm->band_type != ODM_BAND_2_4G) && (*dm->band_type != ODM_BAND_5G)) {
82 PHYDM_DBG(dm, DBG_ADPTVTY,
83 "CarrierSense neither 2G nor 5G band, return\n");
84 return true;
85 }
86 }
87
88 return false;
89 }
90
91 boolean
phydm_soft_ap_special_set(void * dm_void)92 phydm_soft_ap_special_set(void *dm_void)
93 {
94 struct dm_struct *dm = (struct dm_struct *)dm_void;
95 struct phydm_adaptivity_struct *adapt = &dm->adaptivity;
96 boolean disable_ap_adapt_setting = false;
97
98 if (dm->soft_ap_mode != NULL) {
99 if (*dm->soft_ap_mode != 0 &&
100 (dm->soft_ap_special_setting & BIT(0)))
101 disable_ap_adapt_setting = true;
102 else
103 disable_ap_adapt_setting = false;
104 PHYDM_DBG(dm, DBG_ADPTVTY,
105 "soft_ap_setting = %x, soft_ap = %d, dis_ap_adapt = %d\n",
106 dm->soft_ap_special_setting, *dm->soft_ap_mode,
107 disable_ap_adapt_setting);
108 }
109
110 return disable_ap_adapt_setting;
111 }
112
113 boolean
phydm_ap_num_check(void * dm_void)114 phydm_ap_num_check(void *dm_void)
115 {
116 struct dm_struct *dm = (struct dm_struct *)dm_void;
117 struct phydm_adaptivity_struct *adapt = &dm->adaptivity;
118 boolean dis_adapt = false;
119
120 if (dm->ap_total_num > adapt->ap_num_th)
121 dis_adapt = true;
122 else
123 dis_adapt = false;
124
125 PHYDM_DBG(dm, DBG_ADPTVTY, "AP total num = %d, AP num threshold = %d\n",
126 dm->ap_total_num, adapt->ap_num_th);
127 return dis_adapt;
128 }
129
phydm_check_adaptivity(void * dm_void)130 void phydm_check_adaptivity(void *dm_void)
131 {
132 struct dm_struct *dm = (struct dm_struct *)dm_void;
133 struct phydm_adaptivity_struct *adapt = &dm->adaptivity;
134 boolean disable_adapt = false;
135
136 if (!adapt->mode_cvrt_en)
137 return;
138
139 if (phydm_check_channel_plan(dm) || phydm_ap_num_check(dm) ||
140 phydm_soft_ap_special_set(dm))
141 disable_adapt = true;
142
143 if (*dm->edcca_mode == PHYDM_EDCCA_ADAPT_MODE && disable_adapt)
144 *dm->edcca_mode = PHYDM_EDCCA_NORMAL_MODE;
145 else if (*dm->edcca_mode == PHYDM_EDCCA_NORMAL_MODE && !disable_adapt)
146 *dm->edcca_mode = PHYDM_EDCCA_ADAPT_MODE;
147 }
148
phydm_set_l2h_th_ini_win(void * dm_void)149 void phydm_set_l2h_th_ini_win(void *dm_void)
150 {
151 struct dm_struct *dm = (struct dm_struct *)dm_void;
152
153 /*@ [New Format: JGR3]IGI-idx:45 = RSSI:35 = -65dBm*/
154 if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
155 if (dm->support_ic_type & (ODM_RTL8822C | ODM_RTL8723F))
156 dm->th_l2h_ini = 45;
157 else if (dm->support_ic_type & (ODM_RTL8814B | ODM_RTL8814C))
158 dm->th_l2h_ini = 49;
159 } else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
160 /*@ [Old Format] -11+base(50) = IGI_idx:39 = RSSI:29 = -71dBm*/
161 if (dm->support_ic_type & (ODM_RTL8821 | ODM_RTL8812)) {
162 dm->th_l2h_ini = -17;
163 } else {
164 if (*dm->band_type == ODM_BAND_5G)
165 dm->th_l2h_ini = -14;
166 else if (*dm->band_type == ODM_BAND_2_4G)
167 dm->th_l2h_ini = -9;
168 }
169 } else { /*ODM_IC_11N_SERIES*/
170 dm->th_l2h_ini = -9;
171 }
172 }
173
phydm_l2h_ini_recorder_reset(void * dm_void)174 void phydm_l2h_ini_recorder_reset(void *dm_void)
175 {
176 struct dm_struct *dm = (struct dm_struct *)dm_void;
177 struct phydm_adaptivity_struct *adapt = &dm->adaptivity;
178 struct phydm_l2h_ini_recorder_strcut *adapt_rc = &adapt->l2h_ini_recorder_t;
179
180 PHYDM_DBG(dm, DBG_ADPTVTY, "%s ======>\n", __func__);
181
182 odm_memory_set(dm, &adapt_rc->l2h_ini_bitmap, 0,
183 sizeof(struct phydm_l2h_ini_recorder_strcut));
184 }
185
186
phydm_l2h_ini_recorder(void * dm_void)187 void phydm_l2h_ini_recorder(void *dm_void)
188 {
189 struct dm_struct *dm = (struct dm_struct *)dm_void;
190 struct phydm_adaptivity_struct *adapt = &dm->adaptivity;
191 struct phydm_l2h_ini_recorder_strcut *adapt_rc = &adapt->l2h_ini_recorder_t;
192 u32 low_rate_tx_fail_cnt = dm->low_rate_tx_fail_cnt;
193 s8 l2h_ini_curr = dm->th_l2h_ini;
194 s8 l2h_ini_pre = adapt_rc->l2h_ini_hist[0];
195 s8 l2h_ini_down = 0;
196
197 if (!dm->is_linked || adapt->is_adapt_by_dig || adapt->rts_drop_en)
198 return;
199
200 PHYDM_DBG(dm, DBG_ADPTVTY, "%s ======>\n", __func__);
201
202 if (dm->first_connect) {
203 phydm_l2h_ini_recorder_reset(dm);
204 adapt_rc->l2h_ini_hist[0] = l2h_ini_curr;
205 return;
206 }
207
208 l2h_ini_down = (l2h_ini_curr < l2h_ini_pre) ? 1 : 0;
209 adapt_rc->l2h_ini_bitmap = ((adapt_rc->l2h_ini_bitmap << 1) & 0xfe) | l2h_ini_down;
210
211 adapt_rc->l2h_ini_hist[3] = adapt_rc->l2h_ini_hist[2];
212 adapt_rc->l2h_ini_hist[2] = adapt_rc->l2h_ini_hist[1];
213 adapt_rc->l2h_ini_hist[1] = adapt_rc->l2h_ini_hist[0];
214 adapt_rc->l2h_ini_hist[0] = l2h_ini_curr;
215
216 adapt_rc->low_rate_tx_fail_hist[3] = adapt_rc->low_rate_tx_fail_hist[2];
217 adapt_rc->low_rate_tx_fail_hist[2] = adapt_rc->low_rate_tx_fail_hist[1];
218 adapt_rc->low_rate_tx_fail_hist[1] = adapt_rc->low_rate_tx_fail_hist[0];
219 adapt_rc->low_rate_tx_fail_hist[0] = low_rate_tx_fail_cnt;
220
221 PHYDM_DBG(dm, DBG_ADPTVTY, "l2h_ini_hist[3:0] = {0x%x, 0x%x, 0x%x, 0x%x}\n",
222 adapt_rc->l2h_ini_hist[3], adapt_rc->l2h_ini_hist[2],
223 adapt_rc->l2h_ini_hist[1], adapt_rc->l2h_ini_hist[0]);
224 PHYDM_DBG(dm, DBG_ADPTVTY, "low_rate_tx_fail_hist[3:0] = {%d, %d, %d, %d}\n",
225 adapt_rc->low_rate_tx_fail_hist[3], adapt_rc->low_rate_tx_fail_hist[2],
226 adapt_rc->low_rate_tx_fail_hist[1], adapt_rc->low_rate_tx_fail_hist[0]);
227 PHYDM_DBG(dm, DBG_ADPTVTY, "l2h_ini_bitmap = {%d, %d, %d, %d} = 0x%x\n",
228 (u8)((adapt_rc->l2h_ini_bitmap & BIT(3)) >> 3),
229 (u8)((adapt_rc->l2h_ini_bitmap & BIT(2)) >> 2),
230 (u8)((adapt_rc->l2h_ini_bitmap & BIT(1)) >> 1),
231 (u8)(adapt_rc->l2h_ini_bitmap & BIT(0)),
232 adapt_rc->l2h_ini_bitmap);
233 }
234
phydm_rts_drop_chk(void * dm_void)235 void phydm_rts_drop_chk(void *dm_void)
236 {
237 struct dm_struct *dm = (struct dm_struct *)dm_void;
238 struct phydm_adaptivity_struct *adapt = &dm->adaptivity;
239 u32 time_tmp = 0;
240
241 if (!dm->is_linked || adapt->is_adapt_by_dig)
242 return;
243
244 PHYDM_DBG(dm, DBG_ADPTVTY, "%s ======>\n", __func__);
245
246 if (dm->rts_drop_cnt > 0) {
247 adapt->rts_drop_en = 1;
248 adapt->rts_drop_limit_time = dm->phydm_sys_up_time;
249 }
250
251 /*@== Fix l2h_ini to l2h_ini_range_min================================*/
252 if (adapt->rts_drop_en) {
253 PHYDM_DBG(dm, DBG_ADPTVTY,
254 "[RTS DROP!] rts_drop_limit_time=%d, phydm_sys_up_time=%d\n",
255 adapt->rts_drop_limit_time, dm->phydm_sys_up_time);
256
257 time_tmp = adapt->rts_drop_limit_time + L2H_INI_LIMIT_PERIOD;
258 dm->th_l2h_ini = adapt->l2h_ini_range_min;
259
260 if (time_tmp < dm->phydm_sys_up_time && dm->rts_drop_cnt == 0) {
261 adapt->rts_drop_en = 0;
262 PHYDM_DBG(dm, DBG_ADPTVTY, "rts_drop_cnt=%d\n",
263 dm->rts_drop_cnt);
264 }
265 }
266 return;
267 }
268
269
phydm_l2h_ini_damping_chk(void * dm_void)270 void phydm_l2h_ini_damping_chk(void *dm_void)
271 {
272 struct dm_struct *dm = (struct dm_struct *)dm_void;
273 struct phydm_adaptivity_struct *adapt = &dm->adaptivity;
274 struct phydm_l2h_ini_recorder_strcut *adapt_rc = &adapt->l2h_ini_recorder_t;
275 u8 l2h_ini_bitmap_4bit = adapt_rc->l2h_ini_bitmap & 0xf;
276 s8 diff1 = 0, diff2 = 0, min_l2h_ini = 0x7f;
277 u32 tx_fail_low_th = adapt->low_rate_tx_fail_th[0];
278 u32 tx_fail_high_th = adapt->low_rate_tx_fail_th[1];
279 u32 tx_fail_high_th2 = adapt->low_rate_tx_fail_th[2];
280 u8 tx_fail_pattern_match = 0;
281 u32 time_tmp = 0;
282 u8 i = 0;
283
284 if (!dm->is_linked || adapt->is_adapt_by_dig || adapt->rts_drop_en)
285 return;
286
287 PHYDM_DBG(dm, DBG_ADPTVTY, "%s ======>\n", __func__);
288
289 /*@== Release Damping ================================================*/
290 if (adapt_rc->damping_limit_en) {
291 PHYDM_DBG(dm, DBG_ADPTVTY,
292 "[Damping Limit!] limit_time=%d, phydm_sys_up_time=%d\n",
293 adapt_rc->limit_time, dm->phydm_sys_up_time);
294
295 time_tmp = adapt_rc->limit_time + L2H_INI_LIMIT_PERIOD;
296
297 if (DIFF_2(dm->low_rate_tx_fail_cnt, adapt_rc->limit_low_rate_tx_fail) > 3 ||
298 time_tmp < dm->phydm_sys_up_time) {
299 adapt_rc->damping_limit_en = 0;
300 PHYDM_DBG(dm, DBG_ADPTVTY, "low_rate_tx_fail_cnt=%d, limit_low_rate_tx_fail=%d\n",
301 dm->low_rate_tx_fail_cnt, adapt_rc->limit_low_rate_tx_fail);
302 }
303 return;
304 }
305
306 /*@== Damping Pattern Check===========================================*/
307 PHYDM_DBG(dm, DBG_ADPTVTY, "low_rate_tx_fail_th{H, L}= {%d,%d}\n", tx_fail_high_th, tx_fail_low_th);
308
309 switch (l2h_ini_bitmap_4bit) {
310 case 0x5:
311 /*@ 4b'0101
312 * L2H_INI: [3]up(40) ->[2]down(38)->[1]up(40) ->[0]down(38)->[new](Lock @ 38)
313 * low_rate_tx_fail_cnt: [3] >high1 ->[2] <low ->[1] >high1 ->[0] <low ->[new] <low
314 *
315 * L2H_INI: [3]up(45) ->[2]down(40)->[1]up(42) ->[0]down(37)->[new](Lock @ 37)
316 * low_rate_tx_fail_cnt: [3] >high2 ->[2] <low ->[1] >high2 ->[0] <low ->[new] <low
317 */
318 if (adapt_rc->l2h_ini_hist[0] < adapt_rc->l2h_ini_hist[1])
319 diff1 = adapt_rc->l2h_ini_hist[1] - adapt_rc->l2h_ini_hist[0];
320
321 if (adapt_rc->l2h_ini_hist[2] < adapt_rc->l2h_ini_hist[3])
322 diff2 = adapt_rc->l2h_ini_hist[3] - adapt_rc->l2h_ini_hist[2];
323
324 if (adapt_rc->low_rate_tx_fail_hist[0] < tx_fail_low_th &&
325 adapt_rc->low_rate_tx_fail_hist[1] > tx_fail_high_th &&
326 adapt_rc->low_rate_tx_fail_hist[2] < tx_fail_low_th &&
327 adapt_rc->low_rate_tx_fail_hist[3] > tx_fail_high_th) {
328 /*@Check each rts drop element*/
329 tx_fail_pattern_match = 1;
330 }
331 break;
332 case 0x9:
333 /*@ 4b'1001
334 * L2H_INI: [3]down(40)->[2]up(42)->[1]up(44) ->[0]down(39)->[new](Lock @ 39)
335 * low_rate_tx_fail_cnt: [3] <low ->[2] <low ->[1] >high2 ->[0] <low ->[new] <low
336 */
337 if (adapt_rc->l2h_ini_hist[0] < adapt_rc->l2h_ini_hist[1])
338 diff1 = adapt_rc->l2h_ini_hist[1] - adapt_rc->l2h_ini_hist[0];
339
340 if (adapt_rc->l2h_ini_hist[2] > adapt_rc->l2h_ini_hist[3])
341 diff2 = adapt_rc->l2h_ini_hist[2] - adapt_rc->l2h_ini_hist[3];
342
343 if (adapt_rc->low_rate_tx_fail_hist[0] < tx_fail_low_th &&
344 adapt_rc->low_rate_tx_fail_hist[1] > tx_fail_high_th2 &&
345 adapt_rc->low_rate_tx_fail_hist[2] < tx_fail_low_th &&
346 adapt_rc->low_rate_tx_fail_hist[3] < tx_fail_low_th) {
347 /*@Check each fa element*/
348 tx_fail_pattern_match = 1;
349 }
350 break;
351 default:
352 break;
353 }
354
355 if (diff1 >= 2 && diff2 >= 2 && tx_fail_pattern_match) {
356 for (i = 0; i < L2H_INI_RECORD_NUM; i++) {
357 if (min_l2h_ini > adapt_rc->l2h_ini_hist[i])
358 min_l2h_ini = adapt_rc->l2h_ini_hist[i];
359 }
360
361 adapt_rc->damping_limit_en = 1;
362 adapt_rc->damping_limit_val = min_l2h_ini;
363 adapt_rc->limit_time = dm->phydm_sys_up_time;
364 adapt_rc->limit_low_rate_tx_fail = dm->low_rate_tx_fail_cnt;
365
366 PHYDM_DBG(dm, DBG_ADPTVTY,
367 "[Start damping_limit!] l2h_ini_min=0x%x, limit_time=%d, limit_low_rate_tx_fail=%d\n",
368 adapt_rc->damping_limit_val,
369 adapt_rc->limit_time, adapt_rc->limit_low_rate_tx_fail);
370 }
371
372 PHYDM_DBG(dm, DBG_ADPTVTY, "damping_limit=%d\n", adapt_rc->damping_limit_en);
373 }
374
phydm_low_rate_tx_fail_threshold_check(void * dm_void)375 void phydm_low_rate_tx_fail_threshold_check(void *dm_void)
376 {
377 struct dm_struct *dm = (struct dm_struct *)dm_void;
378 struct phydm_adaptivity_struct *adapt = &dm->adaptivity;
379
380 if (adapt->is_dbg_low_rate_tx_fail_th) {
381 PHYDM_DBG(dm, DBG_ADPTVTY, "Manual Fix low_rate_tx_fail_th\n");
382 } else {
383 adapt->low_rate_tx_fail_th[0] = 2;
384 adapt->low_rate_tx_fail_th[1] = 2;
385 adapt->low_rate_tx_fail_th[2] = 5;
386 }
387
388 PHYDM_DBG(dm, DBG_ADPTVTY, "low_rate_tx_fail_th={%d,%d,%d}\n", adapt->low_rate_tx_fail_th[0],
389 adapt->low_rate_tx_fail_th[1], adapt->low_rate_tx_fail_th[2]);
390 }
391
phydm_new_l2h_ini_by_low_rate_tx_fail(void * dm_void,s8 l2h_ini,u8 * step_size)392 s8 phydm_new_l2h_ini_by_low_rate_tx_fail(void *dm_void, s8 l2h_ini,
393 u8 *step_size)
394 {
395 struct dm_struct *dm = (struct dm_struct *)dm_void;
396 struct phydm_adaptivity_struct *adapt = &dm->adaptivity;
397 u32 low_rate_tx_fail_cnt = dm->low_rate_tx_fail_cnt;
398
399 if (low_rate_tx_fail_cnt > adapt->low_rate_tx_fail_th[2])
400 l2h_ini = l2h_ini - step_size[2];
401 else if (low_rate_tx_fail_cnt > adapt->low_rate_tx_fail_th[1])
402 l2h_ini = l2h_ini - step_size[1];
403 else if (low_rate_tx_fail_cnt < adapt->low_rate_tx_fail_th[0])
404 l2h_ini = l2h_ini + step_size[0];
405
406 return l2h_ini;
407 }
408
409
phydm_get_new_l2h_ini(void * dm_void)410 void phydm_get_new_l2h_ini(void *dm_void)
411 {
412 struct dm_struct *dm = (struct dm_struct *)dm_void;
413 struct phydm_adaptivity_struct *adapt = &dm->adaptivity;
414 struct phydm_l2h_ini_recorder_strcut *adapt_rc = &adapt->l2h_ini_recorder_t;
415 u8 step[3] = {1, 2, 5};
416 u32 low_rate_tx_fail_cnt = dm->low_rate_tx_fail_cnt;
417 u32 low_rate_tx_ok_cnt = dm->low_rate_tx_ok_cnt;
418 s8 l2h_ini = dm->th_l2h_ini;
419
420 if (!dm->is_linked || adapt->is_adapt_by_dig || adapt->rts_drop_en)
421 return;
422
423 if (adapt_rc->damping_limit_en) {
424 dm->th_l2h_ini = adapt_rc->damping_limit_val;
425 PHYDM_DBG(dm, DBG_ADPTVTY, "[Limit by Damping] l2h_ini: 0x%x -> 0x%x\n",
426 l2h_ini, dm->th_l2h_ini);
427 return;
428 }
429
430 l2h_ini = phydm_new_l2h_ini_by_low_rate_tx_fail(dm, l2h_ini, step);
431
432 PHYDM_DBG(dm, DBG_ADPTVTY, "step = {-%d, -%d, +%d}\n", step[2], step[1],
433 step[0]);
434
435 /*@Check th_l2h_ini by dyn-upper/lower bound */
436 if (l2h_ini < adapt->l2h_ini_range_min)
437 l2h_ini = adapt->l2h_ini_range_min;
438
439 if (l2h_ini > adapt->l2h_ini_range_max)
440 l2h_ini = adapt->l2h_ini_range_max;
441
442 PHYDM_DBG(dm, DBG_ADPTVTY, "low_rate_tx_fail_cnt = %d, low_rate_tx_ok_cnt = %d, l2h_ini: 0x%x -> 0x%x\n",
443 low_rate_tx_fail_cnt, low_rate_tx_ok_cnt, dm->th_l2h_ini,
444 l2h_ini);
445
446 dm->th_l2h_ini = l2h_ini;
447 }
448
phydm_dyn_l2h_ini(void * dm_void)449 void phydm_dyn_l2h_ini(void *dm_void)
450 {
451 struct dm_struct *dm = (struct dm_struct *)dm_void;
452 struct phydm_adaptivity_struct *adapt = &dm->adaptivity;
453
454 if (dm->rssi_min <= 20 || !dm->is_linked) {
455 phydm_set_l2h_th_ini_win(dm);
456 PHYDM_DBG(dm, DBG_ADPTVTY, "th_l2h_ini = %d\n", dm->th_l2h_ini);
457 return;
458 }
459
460 /*Check rts drop*/
461 phydm_rts_drop_chk(dm);
462
463 /*Record l2h_ini History*/
464 phydm_l2h_ini_recorder(dm);
465
466 /*@l2h_ini Damping Check*/
467 phydm_l2h_ini_damping_chk(dm);
468
469 /*@low_rate_tx_fail threshold decision */
470 phydm_low_rate_tx_fail_threshold_check(dm);
471
472 /*Select new l2h_ini by tx_fail */
473 phydm_get_new_l2h_ini(dm);
474 PHYDM_DBG(dm, DBG_ADPTVTY, "Adjust l2h init @ linked, th_l2h_ini = %d\n",
475 dm->th_l2h_ini);
476 }
477
478 #endif
479
phydm_dig_up_bound_lmt_en(void * dm_void)480 void phydm_dig_up_bound_lmt_en(void *dm_void)
481 {
482 struct dm_struct *dm = (struct dm_struct *)dm_void;
483 struct phydm_adaptivity_struct *adapt = &dm->adaptivity;
484
485 if (*dm->edcca_mode != PHYDM_EDCCA_ADAPT_MODE ||
486 !dm->is_linked) {
487 adapt->igi_up_bound_lmt_cnt = 0;
488 adapt->igi_lmt_en = false;
489 return;
490 }
491
492 if (dm->total_tp > 1) {
493 adapt->igi_lmt_en = true;
494 adapt->igi_up_bound_lmt_cnt = adapt->igi_up_bound_lmt_val;
495 PHYDM_DBG(dm, DBG_ADPTVTY,
496 "TP >1, Start limit IGI upper bound\n");
497 } else {
498 if (adapt->igi_up_bound_lmt_cnt == 0)
499 adapt->igi_lmt_en = false;
500 else
501 adapt->igi_up_bound_lmt_cnt--;
502 }
503
504 PHYDM_DBG(dm, DBG_ADPTVTY, "IGI_lmt_cnt = %d\n",
505 adapt->igi_up_bound_lmt_cnt);
506 }
507
phydm_set_edcca_threshold(void * dm_void,s8 H2L,s8 L2H)508 void phydm_set_edcca_threshold(void *dm_void, s8 H2L, s8 L2H)
509 {
510 struct dm_struct *dm = (struct dm_struct *)dm_void;
511
512 if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
513 odm_set_bb_reg(dm, R_0x84c, MASKBYTE2, (u8)L2H + 0x80);
514 odm_set_bb_reg(dm, R_0x84c, MASKBYTE3, (u8)H2L + 0x80);
515 } else if (dm->support_ic_type & ODM_IC_11N_SERIES) {
516 odm_set_bb_reg(dm, R_0xc4c, MASKBYTE0, (u8)L2H);
517 odm_set_bb_reg(dm, R_0xc4c, MASKBYTE2, (u8)H2L);
518 } else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
519 odm_set_bb_reg(dm, R_0x8a4, MASKBYTE0, (u8)L2H);
520 odm_set_bb_reg(dm, R_0x8a4, MASKBYTE1, (u8)H2L);
521 }
522 }
523
phydm_mac_edcca_state(void * dm_void,enum phydm_mac_edcca_type state)524 void phydm_mac_edcca_state(void *dm_void, enum phydm_mac_edcca_type state)
525 {
526 struct dm_struct *dm = (struct dm_struct *)dm_void;
527
528 if (state == PHYDM_IGNORE_EDCCA) {
529 /*@ignore EDCCA*/
530 odm_set_mac_reg(dm, R_0x520, BIT(15), 1);
531 /*@enable EDCCA count down*/
532 odm_set_mac_reg(dm, R_0x524, BIT(11), 0);
533 } else { /*@don't set MAC ignore EDCCA signal*/
534 /*@don't ignore EDCCA*/
535 odm_set_mac_reg(dm, R_0x520, BIT(15), 0);
536 /*@disable EDCCA count down*/
537 odm_set_mac_reg(dm, R_0x524, BIT(11), 1);
538 }
539 PHYDM_DBG(dm, DBG_ADPTVTY, "EDCCA enable state = %d\n", state);
540 }
541
phydm_search_pwdb_lower_bound(void * dm_void)542 void phydm_search_pwdb_lower_bound(void *dm_void)
543 {
544 struct dm_struct *dm = (struct dm_struct *)dm_void;
545 struct phydm_adaptivity_struct *adapt = &dm->adaptivity;
546 u32 value32 = 0, reg_value32 = 0;
547 u8 cnt = 0, try_count = 0;
548 u8 tx_edcca1 = 0;
549 boolean is_adjust = true;
550 s8 th_l2h, th_h2l, igi_target_dc = 0x32;
551 s8 diff = 0;
552 s8 IGI = adapt->igi_base + 30 + dm->th_l2h_ini - dm->th_edcca_hl_diff;
553
554 halrf_rf_lna_setting(dm, HALRF_LNA_DISABLE);
555 diff = igi_target_dc - IGI;
556 th_l2h = dm->th_l2h_ini + diff;
557 if (th_l2h > 10)
558 th_l2h = 10;
559
560 th_h2l = th_l2h - dm->th_edcca_hl_diff;
561 phydm_set_edcca_threshold(dm, th_h2l, th_l2h);
562 ODM_delay_ms(30);
563
564 while (is_adjust) {
565 /*@check CCA status*/
566 /*set debug port to 0x0*/
567 if (phydm_set_bb_dbg_port(dm, DBGPORT_PRI_1, 0x0)) {
568 reg_value32 = phydm_get_bb_dbg_port_val(dm);
569
570 while (reg_value32 & BIT(3) && try_count < 3) {
571 ODM_delay_ms(3);
572 try_count = try_count + 1;
573 reg_value32 = phydm_get_bb_dbg_port_val(dm);
574 }
575 phydm_release_bb_dbg_port(dm);
576 try_count = 0;
577 }
578
579 /*@count EDCCA signal = 1 times*/
580 for (cnt = 0; cnt < 20; cnt++) {
581 if (phydm_set_bb_dbg_port(dm, DBGPORT_PRI_1,
582 adapt->adaptivity_dbg_port)) {
583 value32 = phydm_get_bb_dbg_port_val(dm);
584 phydm_release_bb_dbg_port(dm);
585 }
586
587 if (value32 & BIT(30) && dm->support_ic_type &
588 (ODM_RTL8723B | ODM_RTL8188E))
589 tx_edcca1 = tx_edcca1 + 1;
590 else if (value32 & BIT(29))
591 tx_edcca1 = tx_edcca1 + 1;
592 }
593
594 if (tx_edcca1 > 1) {
595 IGI = IGI - 1;
596 th_l2h = th_l2h + 1;
597 if (th_l2h > 10)
598 th_l2h = 10;
599
600 th_h2l = th_l2h - dm->th_edcca_hl_diff;
601 phydm_set_edcca_threshold(dm, th_h2l, th_l2h);
602 tx_edcca1 = 0;
603 if (th_l2h == 10)
604 is_adjust = false;
605
606 } else {
607 is_adjust = false;
608 }
609 }
610
611 adapt->adapt_igi_up = IGI - ADAPT_DC_BACKOFF;
612 adapt->h2l_lb = th_h2l + ADAPT_DC_BACKOFF;
613 adapt->l2h_lb = th_l2h + ADAPT_DC_BACKOFF;
614
615 halrf_rf_lna_setting(dm, HALRF_LNA_ENABLE);
616 phydm_set_edcca_threshold(dm, 0x7f, 0x7f); /*resume to no link state*/
617 }
618
phydm_re_search_condition(void * dm_void)619 boolean phydm_re_search_condition(void *dm_void)
620 {
621 struct dm_struct *dm = (struct dm_struct *)dm_void;
622 struct phydm_adaptivity_struct *adaptivity = &dm->adaptivity;
623 u8 adaptivity_igi_upper = adaptivity->adapt_igi_up + ADAPT_DC_BACKOFF;
624
625 if (adaptivity_igi_upper <= 0x26)
626 return true;
627 else
628 return false;
629 }
630
phydm_set_l2h_th_ini(void * dm_void)631 void phydm_set_l2h_th_ini(void *dm_void)
632 {
633 struct dm_struct *dm = (struct dm_struct *)dm_void;
634
635 /*@ [New Format: JGR3]IGI-idx:45 = RSSI:35 = -65dBm*/
636 if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
637 if (dm->support_ic_type & (ODM_RTL8822C | ODM_RTL8723F))
638 dm->th_l2h_ini = 45;
639 else if (dm->support_ic_type & (ODM_RTL8814B | ODM_RTL8814C))
640 dm->th_l2h_ini = 49;
641 } else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
642 /*@ [Old Format] -11+base(50) = IGI_idx:39 = RSSI:29 = -71dBm*/
643 if (dm->support_ic_type & (ODM_RTL8821 | ODM_RTL8812))
644 dm->th_l2h_ini = -17;
645 else
646 dm->th_l2h_ini = -14;
647 } else { /*ODM_IC_11N_SERIES*/
648 if (dm->support_ic_type & ODM_RTL8721D)
649 dm->th_l2h_ini = -14;
650 else
651 dm->th_l2h_ini = -11;
652 }
653 }
654
phydm_set_l2h_th_ini_carrier_sense(void * dm_void)655 void phydm_set_l2h_th_ini_carrier_sense(void *dm_void)
656 {
657 struct dm_struct *dm = (struct dm_struct *)dm_void;
658
659 if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
660 dm->th_l2h_ini = 60; /*@ -50dBm*/
661 else
662 dm->th_l2h_ini = 10; /*@ -50dBm*/
663 }
664
phydm_set_forgetting_factor(void * dm_void)665 void phydm_set_forgetting_factor(void *dm_void)
666 {
667 struct dm_struct *dm = (struct dm_struct *)dm_void;
668
669 if (*dm->edcca_mode != PHYDM_EDCCA_ADAPT_MODE)
670 return;
671
672 if (dm->support_ic_type & (ODM_RTL8821C | ODM_RTL8822B | ODM_RTL8814A |
673 ODM_RTL8195B))
674 odm_set_bb_reg(dm, R_0x8a0, BIT(1) | BIT(0), 0);
675 }
676
phydm_edcca_decision_opt(void * dm_void)677 void phydm_edcca_decision_opt(void *dm_void)
678 {
679 struct dm_struct *dm = (struct dm_struct *)dm_void;
680
681 if (*dm->edcca_mode != PHYDM_EDCCA_ADAPT_MODE)
682 return;
683
684 if (dm->support_ic_type & ODM_RTL8822B)
685 odm_set_bb_reg(dm, R_0x8dc, BIT(5), 0x1);
686 else if (dm->support_ic_type & (ODM_RTL8197F | ODM_RTL8192F))
687 odm_set_bb_reg(dm, R_0xce8, BIT(13), 0x1);
688 else if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
689 odm_set_bb_reg(dm, R_0x844, BIT(30) | BIT(29), 0x0);
690 }
691
phydm_adaptivity_debug(void * dm_void,char input[][16],u32 * _used,char * output,u32 * _out_len)692 void phydm_adaptivity_debug(void *dm_void, char input[][16], u32 *_used,
693 char *output, u32 *_out_len)
694 {
695 struct dm_struct *dm = (struct dm_struct *)dm_void;
696 struct phydm_adaptivity_struct *adaptivity = &dm->adaptivity;
697 struct phydm_l2h_ini_recorder_strcut *adapt_rc = &adaptivity->l2h_ini_recorder_t;
698 u32 used = *_used;
699 u32 out_len = *_out_len;
700 char help[] = "-h";
701 u32 dm_value[10] = {0};
702 u8 i = 0, input_idx = 0;
703 u32 reg_value32 = 0;
704 s8 h2l_diff = 0;
705
706 for (i = 0; i < 6; i++) {
707 PHYDM_SSCANF(input[i + 1], DCMD_HEX, &dm_value[i]);
708 input_idx++;
709 }
710 if (strcmp(input[1], help) == 0) {
711 PDM_SNPF(out_len, used, output + used, out_len - used,
712 "Show adaptivity message: {0}\n");
713 PDM_SNPF(out_len, used, output + used, out_len - used,
714 "Enter debug mode: {1} {th_l2h_ini} {th_edcca_hl_diff}\n");
715 PDM_SNPF(out_len, used, output + used, out_len - used,
716 "Leave debug mode: {2}\n");
717 PDM_SNPF(out_len, used, output + used, out_len - used,
718 "RTS drop debug mode: {3} {en} {low_rate_tx_fail_th[0]} {low_rate_tx_fail_th[1]} {low_rate_tx_fail_th[2]}\n");
719 goto out;
720 }
721
722 if (input_idx == 0)
723 return;
724
725 if (dm_value[0] == PHYDM_ADAPT_DEBUG) {
726 adaptivity->debug_mode = true;
727 if (dm_value[1] != 0)
728 dm->th_l2h_ini = (s8)dm_value[1];
729 if (dm_value[2] != 0)
730 dm->th_edcca_hl_diff = (s8)dm_value[2];
731 PDM_SNPF(out_len, used, output + used, out_len - used,
732 "th_l2h_ini = %d, th_edcca_hl_diff = %d\n",
733 dm->th_l2h_ini, dm->th_edcca_hl_diff);
734 } else if (dm_value[0] == PHYDM_ADAPT_RESUME) {
735 adaptivity->debug_mode = false;
736 dm->th_l2h_ini = adaptivity->th_l2h_ini_backup;
737 dm->th_edcca_hl_diff = adaptivity->th_edcca_hl_diff_backup;
738 } else if (dm_value[0] == PHYDM_ADAPT_MSG) {
739 PDM_SNPF(out_len, used, output + used, out_len - used,
740 "debug_mode = %s, th_l2h_ini = %d\n",
741 (adaptivity->debug_mode ? "TRUE" : "FALSE"),
742 dm->th_l2h_ini);
743 if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
744 reg_value32 = odm_get_bb_reg(dm, R_0x84c, MASKDWORD);
745 h2l_diff = (s8)((0x00ff0000 & reg_value32) >> 16) -
746 (s8)((0xff000000 & reg_value32) >> 24);
747 } else if (dm->support_ic_type & ODM_IC_11N_SERIES) {
748 reg_value32 = odm_get_bb_reg(dm, R_0xc4c, MASKDWORD);
749 h2l_diff = (s8)(0x000000ff & reg_value32) -
750 (s8)((0x00ff0000 & reg_value32) >> 16);
751 } else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
752 reg_value32 = odm_get_bb_reg(dm, R_0x8a4, MASKDWORD);
753 h2l_diff = (s8)(0x000000ff & reg_value32) -
754 (s8)((0x0000ff00 & reg_value32) >> 8);
755 }
756
757 if (h2l_diff == 7)
758 PDM_SNPF(out_len, used, output + used, out_len - used,
759 "adaptivity enable\n");
760 else
761 PDM_SNPF(out_len, used, output + used, out_len - used,
762 "adaptivity disable\n");
763 } else if (dm_value[0] == PHYDM_L2H_INI_DEBUG) {
764 if (dm_value[1] == 1) {
765 adaptivity->is_dbg_low_rate_tx_fail_th = true;
766 adaptivity->low_rate_tx_fail_th[0] = (u32)dm_value[2];
767 adaptivity->low_rate_tx_fail_th[1] = (u32)dm_value[3];
768 adaptivity->low_rate_tx_fail_th[2] = (u32)dm_value[4];
769
770 PDM_SNPF(out_len, used, output + used, out_len - used,
771 "Set low_rate_tx_fail_th={%d,%d,%d}\n",
772 adaptivity->low_rate_tx_fail_th[0],
773 adaptivity->low_rate_tx_fail_th[1],
774 adaptivity->low_rate_tx_fail_th[2]);
775 } else {
776 adaptivity->is_dbg_low_rate_tx_fail_th = false;
777 }
778 }
779
780 out:
781 *_used = used;
782 *_out_len = out_len;
783 }
784
phydm_set_edcca_val(void * dm_void,u32 * val_buf,u8 val_len)785 void phydm_set_edcca_val(void *dm_void, u32 *val_buf, u8 val_len)
786 {
787 struct dm_struct *dm = (struct dm_struct *)dm_void;
788
789 if (val_len != 2) {
790 PHYDM_DBG(dm, ODM_COMP_API,
791 "[Error][adaptivity]Need val_len = 2\n");
792 return;
793 }
794 phydm_set_edcca_threshold(dm, (s8)val_buf[1], (s8)val_buf[0]);
795 }
796
phydm_edcca_abort(void * dm_void)797 boolean phydm_edcca_abort(void *dm_void)
798 {
799 struct dm_struct *dm = (struct dm_struct *)dm_void;
800 struct phydm_adaptivity_struct *adapt = &dm->adaptivity;
801 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
802 void *adapter = dm->adapter;
803 u32 is_fw_in_psmode = false;
804 #endif
805
806 if (!(dm->support_ability & ODM_BB_ADAPTIVITY)) {
807 PHYDM_DBG(dm, DBG_ADPTVTY, "adaptivity disable\n");
808 return true;
809 }
810
811 if (dm->pause_ability & ODM_BB_ADAPTIVITY) {
812 PHYDM_DBG(dm, DBG_ADPTVTY, "Return: Pause ADPTVTY in LV=%d\n",
813 dm->pause_lv_table.lv_adapt);
814 return true;
815 }
816
817 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
818 ((PADAPTER)adapter)->HalFunc.GetHwRegHandler(adapter,
819 HW_VAR_FW_PSMODE_STATUS,
820 (u8 *)(&is_fw_in_psmode));
821
822 /*@Disable EDCCA while under LPS mode, added by Roger, 2012.09.14.*/
823 if (is_fw_in_psmode)
824 return true;
825 #endif
826
827 return false;
828 }
829
phydm_edcca_thre_calc_jgr3(void * dm_void)830 void phydm_edcca_thre_calc_jgr3(void *dm_void)
831 {
832 struct dm_struct *dm = (struct dm_struct *)dm_void;
833 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
834 struct phydm_adaptivity_struct *adapt = &dm->adaptivity;
835 u8 igi = dig_t->cur_ig_value;
836 s8 th_l2h = 0, th_h2l = 0;
837
838 if (*dm->edcca_mode == PHYDM_EDCCA_ADAPT_MODE) {
839 /*prevent pwdB clipping and result in Miss Detection*/
840 adapt->l2h_dyn_min = (u8)(dm->th_l2h_ini - ADC_BACKOFF);
841
842 if (igi < adapt->l2h_dyn_min)
843 th_l2h = igi + ADC_BACKOFF;
844 else
845 th_l2h = dm->th_l2h_ini;
846
847 th_h2l = th_l2h - dm->th_edcca_hl_diff;
848 } else {
849 th_l2h = MAX_2(igi + TH_L2H_DIFF_IGI, EDCCA_TH_L2H_LB);
850 th_h2l = th_l2h - EDCCA_HL_DIFF_NORMAL;
851 }
852 adapt->th_l2h = th_l2h;
853 adapt->th_h2l = th_h2l;
854
855 phydm_set_edcca_threshold(dm, adapt->th_h2l, adapt->th_l2h);
856 }
857
phydm_edcca_thre_calc(void * dm_void)858 void phydm_edcca_thre_calc(void *dm_void)
859 {
860 struct dm_struct *dm = (struct dm_struct *)dm_void;
861 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
862 struct phydm_adaptivity_struct *adapt = &dm->adaptivity;
863 u8 igi = dig_t->cur_ig_value;
864 s8 th_l2h = 0, th_h2l = 0;
865 s8 diff = 0, igi_target = adapt->igi_base;
866
867 if (dm->support_ic_type & ODM_IC_PWDB_EDCCA) {
868 /*@fix EDCCA hang issue*/
869 if (dm->support_ic_type & ODM_RTL8812) {
870 /*@ADC_mask disable*/
871 odm_set_bb_reg(dm, R_0x800, BIT(10), 1);
872 /*@ADC_mask enable*/
873 odm_set_bb_reg(dm, R_0x800, BIT(10), 0);
874 }
875
876 if (*dm->edcca_mode == PHYDM_EDCCA_ADAPT_MODE) {
877 /*@Limit IGI upper bound for adaptivity*/
878 phydm_dig_up_bound_lmt_en(dm);
879 diff = igi_target - (s8)igi;
880 th_l2h = dm->th_l2h_ini + diff;
881 if (th_l2h > 10)
882 th_l2h = 10;
883
884 th_h2l = th_l2h - dm->th_edcca_hl_diff;
885 } else {
886 th_l2h = 70 - igi;
887 th_h2l = th_l2h - EDCCA_HL_DIFF_NORMAL;
888 }
889 /*replace lower bound to prevent EDCCA always equal 1*/
890 if (th_h2l < adapt->h2l_lb)
891 th_h2l = adapt->h2l_lb;
892 if (th_l2h < adapt->l2h_lb)
893 th_l2h = adapt->l2h_lb;
894 PHYDM_DBG(dm, DBG_ADPTVTY,
895 "adapt_igi_up=0x%x, l2h_lb = %d dBm, h2l_lb = %d dBm\n",
896 adapt->adapt_igi_up,
897 IGI_2_DBM(adapt->l2h_lb + adapt->adapt_igi_up),
898 IGI_2_DBM(adapt->h2l_lb + adapt->adapt_igi_up));
899 } else { /* < JGR2 & N*/
900 if (*dm->edcca_mode == PHYDM_EDCCA_ADAPT_MODE) {
901 /*need to consider PwdB upper bound for 8814 later IC*/
902 adapt->l2h_dyn_min = (u8)(dm->th_l2h_ini + igi_target);
903
904 if (igi < adapt->l2h_dyn_min)
905 th_l2h = igi;
906 else
907 th_l2h = adapt->l2h_dyn_min;
908
909 th_h2l = th_l2h - dm->th_edcca_hl_diff;
910 } else {
911 th_l2h = MAX_2(igi + TH_L2H_DIFF_IGI, EDCCA_TH_L2H_LB);
912 th_h2l = th_l2h - EDCCA_HL_DIFF_NORMAL;
913 }
914 }
915
916 adapt->th_l2h = th_l2h;
917 adapt->th_h2l = th_h2l;
918
919 phydm_set_edcca_threshold(dm, adapt->th_h2l, adapt->th_l2h);
920 }
921 #endif
922
phydm_set_edcca_threshold_api(void * dm_void)923 void phydm_set_edcca_threshold_api(void *dm_void)
924 {
925 #ifdef PHYDM_SUPPORT_ADAPTIVITY
926 struct dm_struct *dm = (struct dm_struct *)dm_void;
927 struct phydm_adaptivity_struct *adapt = &dm->adaptivity;
928
929 if (*dm->edcca_mode != PHYDM_EDCCA_ADAPT_MODE)
930 return;
931
932 if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
933 phydm_edcca_thre_calc_jgr3(dm);
934 else
935 phydm_edcca_thre_calc(dm);
936
937 PHYDM_DBG(dm, DBG_ADPTVTY,
938 "API :IGI = 0x%x, th_l2h = %d, th_h2l = %d\n",
939 dm->dm_dig_table.cur_ig_value, adapt->th_l2h, adapt->th_h2l);
940 #endif
941 }
942
phydm_adaptivity_info_init(void * dm_void,enum phydm_adapinfo cmn_info,u32 value)943 void phydm_adaptivity_info_init(void *dm_void, enum phydm_adapinfo cmn_info,
944 u32 value)
945 {
946 struct dm_struct *dm = (struct dm_struct *)dm_void;
947 struct phydm_adaptivity_struct *adaptivity = &dm->adaptivity;
948
949 switch (cmn_info) {
950 case PHYDM_ADAPINFO_CARRIER_SENSE_ENABLE:
951 dm->carrier_sense_enable = (boolean)value;
952 break;
953 case PHYDM_ADAPINFO_TH_L2H_INI:
954 dm->th_l2h_ini = (s8)value;
955 break;
956 case PHYDM_ADAPINFO_TH_EDCCA_HL_DIFF:
957 dm->th_edcca_hl_diff = (s8)value;
958 break;
959 case PHYDM_ADAPINFO_AP_NUM_TH:
960 adaptivity->ap_num_th = (u8)value;
961 break;
962 case PHYDM_ADAPINFO_SWITCH_TH_L2H_INI_IN_BAND:
963 adaptivity->switch_th_l2h_ini_in_band = (u8)value;
964 break;
965 default:
966 break;
967 }
968 }
969
phydm_adaptivity_info_update(void * dm_void,enum phydm_adapinfo cmn_info,u32 value)970 void phydm_adaptivity_info_update(void *dm_void, enum phydm_adapinfo cmn_info,
971 u32 value)
972 {
973 struct dm_struct *dm = (struct dm_struct *)dm_void;
974 struct phydm_adaptivity_struct *adapt = &dm->adaptivity;
975
976 /*This init variable may be changed in run time.*/
977 switch (cmn_info) {
978 case PHYDM_ADAPINFO_DOMAIN_CODE_2G:
979 adapt->regulation_2g = (u8)value;
980 break;
981 case PHYDM_ADAPINFO_DOMAIN_CODE_5G:
982 adapt->regulation_5g = (u8)value;
983 break;
984 default:
985 break;
986 }
987 }
988
phydm_adaptivity_init(void * dm_void)989 void phydm_adaptivity_init(void *dm_void)
990 {
991 #ifdef PHYDM_SUPPORT_ADAPTIVITY
992 struct dm_struct *dm = (struct dm_struct *)dm_void;
993 struct phydm_adaptivity_struct *adaptivity = &dm->adaptivity;
994
995 /* @[Config Adaptivity]*/
996 if (!dm->edcca_mode) {
997 pr_debug("[%s] warning!\n", __func__);
998 dm->edcca_mode = &dm->u8_dummy;
999 dm->support_ability &= ~ODM_BB_ADAPTIVITY;
1000 return;
1001 }
1002
1003 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
1004 if (!dm->carrier_sense_enable) {
1005 if (dm->th_l2h_ini == 0 &&
1006 !adaptivity->switch_th_l2h_ini_in_band)
1007 phydm_set_l2h_th_ini(dm);
1008 } else {
1009 phydm_set_l2h_th_ini_carrier_sense(dm);
1010 }
1011
1012 if (dm->th_edcca_hl_diff == 0)
1013 dm->th_edcca_hl_diff = 7;
1014
1015 if (dm->wifi_test & RT_WIFI_LOGO)
1016 dm->support_ability &= ~ODM_BB_ADAPTIVITY;
1017
1018 if (*dm->edcca_mode == PHYDM_EDCCA_ADAPT_MODE)
1019 adaptivity->mode_cvrt_en = true;
1020 else
1021 adaptivity->mode_cvrt_en = false;
1022
1023 if (dm->support_ic_type & ODM_RTL8822C) {
1024 adaptivity->l2h_ini_range_max = 45;
1025 adaptivity->l2h_ini_range_min = 35;
1026 } else {
1027 adaptivity->l2h_ini_range_max = dm->th_l2h_ini;
1028 adaptivity->l2h_ini_range_min = dm->th_l2h_ini;
1029 }
1030 adaptivity->low_rate_tx_fail_th[0] = 2;
1031 adaptivity->low_rate_tx_fail_th[1] = 2;
1032 adaptivity->low_rate_tx_fail_th[2] = 5;
1033 adaptivity->is_dbg_low_rate_tx_fail_th = false;
1034 adaptivity->rts_drop_en = false;
1035 phydm_l2h_ini_recorder_reset(dm);
1036 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
1037 if (!dm->carrier_sense_enable) {
1038 if (dm->th_l2h_ini == 0)
1039 phydm_set_l2h_th_ini(dm);
1040 } else {
1041 phydm_set_l2h_th_ini_carrier_sense(dm);
1042 }
1043
1044 if (dm->th_edcca_hl_diff == 0)
1045 dm->th_edcca_hl_diff = 7;
1046
1047 if (dm->wifi_test || *dm->mp_mode)
1048 dm->support_ability &= ~ODM_BB_ADAPTIVITY;
1049 #elif (DM_ODM_SUPPORT_TYPE & ODM_AP)
1050 if (dm->carrier_sense_enable) {
1051 phydm_set_l2h_th_ini_carrier_sense(dm);
1052 dm->th_edcca_hl_diff = 7;
1053 } else {
1054 dm->th_l2h_ini = dm->TH_L2H_default; /*set by mib*/
1055 dm->th_edcca_hl_diff = dm->th_edcca_hl_diff_default;
1056 }
1057 #elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
1058 if (!dm->carrier_sense_enable) {
1059 if (dm->th_l2h_ini == 0)
1060 phydm_set_l2h_th_ini(dm);
1061 } else {
1062 phydm_set_l2h_th_ini_carrier_sense(dm);
1063 }
1064
1065 if (dm->th_edcca_hl_diff == 0)
1066 dm->th_edcca_hl_diff = 7;
1067 #endif
1068
1069 adaptivity->debug_mode = false;
1070 adaptivity->th_l2h_ini_backup = dm->th_l2h_ini;
1071 adaptivity->th_edcca_hl_diff_backup = dm->th_edcca_hl_diff;
1072 adaptivity->igi_base = 0x32;
1073 adaptivity->adapt_igi_up = 0;
1074 adaptivity->h2l_lb = 0;
1075 adaptivity->l2h_lb = 0;
1076 adaptivity->l2h_dyn_min = 0;
1077 adaptivity->th_l2h = 0x7f;
1078 adaptivity->th_h2l = 0x7f;
1079
1080 if (dm->support_ic_type & ODM_IC_11N_SERIES)
1081 adaptivity->adaptivity_dbg_port = 0x208;
1082 else if (dm->support_ic_type & ODM_IC_11AC_SERIES)
1083 adaptivity->adaptivity_dbg_port = 0x209;
1084
1085 if (dm->support_ic_type & ODM_IC_11N_SERIES &&
1086 !(dm->support_ic_type & ODM_IC_PWDB_EDCCA)) {
1087 if (dm->support_ic_type & (ODM_RTL8197F | ODM_RTL8192F)) {
1088 /*set to page B1*/
1089 odm_set_bb_reg(dm, R_0xe28, BIT(30), 0x1);
1090 /*@0:rx_dfir, 1: dcnf_out, 2 :rx_iq, 3: rx_nbi_nf_out*/
1091 odm_set_bb_reg(dm, R_0xbc0, BIT(27) | BIT(26), 0x1);
1092 odm_set_bb_reg(dm, R_0xe28, BIT(30), 0x0);
1093 } else {
1094 /*@0:rx_dfir, 1: dcnf_out, 2 :rx_iq, 3: rx_nbi_nf_out*/
1095 odm_set_bb_reg(dm, R_0xe24, BIT(21) | BIT(20), 0x1);
1096 }
1097 } else if (dm->support_ic_type & ODM_IC_11AC_SERIES &&
1098 !(dm->support_ic_type & ODM_IC_PWDB_EDCCA)) {
1099 /*@0:rx_dfir, 1: dcnf_out, 2 :rx_iq, 3: rx_nbi_nf_out*/
1100 odm_set_bb_reg(dm, R_0x944, BIT(29) | BIT(28), 0x1);
1101 }
1102
1103 if (dm->support_ic_type & ODM_IC_PWDB_EDCCA) {
1104 phydm_search_pwdb_lower_bound(dm);
1105 if (phydm_re_search_condition(dm))
1106 phydm_search_pwdb_lower_bound(dm);
1107 } else {
1108 /*resume to no link state*/
1109 phydm_set_edcca_threshold(dm, 0x7f, 0x7f);
1110 }
1111
1112 /*@whether to ignore EDCCA*/
1113 phydm_mac_edcca_state(dm, PHYDM_DONT_IGNORE_EDCCA);
1114
1115 /*@forgetting factor setting*/
1116 phydm_set_forgetting_factor(dm);
1117
1118 /*@EDCCA behavior based on maximum or mean power*/
1119 phydm_edcca_decision_opt(dm);
1120
1121 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
1122 adaptivity->igi_up_bound_lmt_val = 180;
1123 #else
1124 adaptivity->igi_up_bound_lmt_val = 90;
1125 #endif
1126 adaptivity->igi_up_bound_lmt_cnt = 0;
1127 adaptivity->igi_lmt_en = false;
1128 #endif
1129 }
1130
phydm_adaptivity(void * dm_void)1131 void phydm_adaptivity(void *dm_void)
1132 {
1133 #ifdef PHYDM_SUPPORT_ADAPTIVITY
1134 struct dm_struct *dm = (struct dm_struct *)dm_void;
1135 struct phydm_adaptivity_struct *adapt = &dm->adaptivity;
1136 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
1137
1138 if (phydm_edcca_abort(dm))
1139 return;
1140
1141 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
1142 phydm_check_adaptivity(dm); /*@Check adaptivity enable*/
1143
1144 if (!dm->carrier_sense_enable &&
1145 !adapt->debug_mode &&
1146 adapt->switch_th_l2h_ini_in_band)
1147 phydm_set_l2h_th_ini_win(dm);
1148
1149 if (dm->support_ic_type & ODM_RTL8822C)
1150 phydm_dyn_l2h_ini(dm);
1151 #endif
1152 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
1153 if (!adapt->debug_mode) {
1154 if (*dm->edcca_mode == PHYDM_EDCCA_ADAPT_MODE &&
1155 dm->carrier_sense_enable)
1156 phydm_set_l2h_th_ini_carrier_sense(dm);
1157 else if (*dm->edcca_mode == PHYDM_EDCCA_ADAPT_MODE)
1158 phydm_set_l2h_th_ini(dm);
1159 }
1160 #endif
1161 PHYDM_DBG(dm, DBG_ADPTVTY, "%s ====>\n", __func__);
1162 PHYDM_DBG(dm, DBG_ADPTVTY, "mode = %s, debug_mode = %d\n",
1163 (*dm->edcca_mode ?
1164 (dm->carrier_sense_enable ?
1165 "CARRIER SENSE" :
1166 "ADAPTIVITY") :
1167 "NORMAL"),
1168 adapt->debug_mode);
1169
1170 if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
1171 phydm_edcca_thre_calc_jgr3(dm);
1172 else
1173 phydm_edcca_thre_calc(dm);
1174
1175 if (*dm->edcca_mode == PHYDM_EDCCA_ADAPT_MODE)
1176 PHYDM_DBG(dm, DBG_ADPTVTY,
1177 "th_l2h_ini = %d, th_edcca_hl_diff = %d\n",
1178 dm->th_l2h_ini, dm->th_edcca_hl_diff);
1179 if (dm->support_ic_type & ODM_IC_PWDB_EDCCA)
1180 PHYDM_DBG(dm, DBG_ADPTVTY,
1181 "IGI = 0x%x, th_l2h = %d dBm, th_h2l = %d dBm\n",
1182 dig_t->cur_ig_value,
1183 IGI_2_DBM(adapt->th_l2h + dig_t->cur_ig_value),
1184 IGI_2_DBM(adapt->th_h2l + dig_t->cur_ig_value));
1185 else
1186 PHYDM_DBG(dm, DBG_ADPTVTY,
1187 "IGI = 0x%x, th_l2h = %d dBm, th_h2l = %d dBm\n",
1188 dig_t->cur_ig_value,
1189 IGI_2_DBM(adapt->th_l2h),
1190 IGI_2_DBM(adapt->th_h2l));
1191 #endif
1192 }
1193
1194