1 /******************************************************************************
2 *
3 * Copyright(c) 2007 - 2017 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26 /*@
27 * ============================================================
28 * include files
29 * ============================================================
30 */
31
32 #include "mp_precomp.h"
33 #include "phydm_precomp.h"
34
35 #if defined(CONFIG_PHYDM_DFS_MASTER)
36
phydm_dfs_is_meteorology_channel(void * dm_void)37 boolean phydm_dfs_is_meteorology_channel(void *dm_void)
38 {
39 struct dm_struct *dm = (struct dm_struct *)dm_void;
40
41 u8 ch = *dm->channel;
42 u8 bw = *dm->band_width;
43
44 return ((bw == CHANNEL_WIDTH_80 && (ch) >= 116 && (ch) <= 128) ||
45 (bw == CHANNEL_WIDTH_40 && (ch) >= 116 && (ch) <= 128) ||
46 (bw == CHANNEL_WIDTH_20 && (ch) >= 120 && (ch) <= 128));
47 }
48
phydm_dfs_segment_distinguish(void * dm_void,enum rf_syn syn_path)49 void phydm_dfs_segment_distinguish(void *dm_void, enum rf_syn syn_path)
50 {
51 struct dm_struct *dm = (struct dm_struct *)dm_void;
52
53 if (!(dm->support_ic_type & (ODM_RTL8814B | ODM_RTL8814C)))
54 return;
55 if (syn_path == RF_SYN1)
56 dm->seg1_dfs_flag = 1;
57 else
58 dm->seg1_dfs_flag = 0;
59 }
60
phydm_dfs_segment_flag_reset(void * dm_void)61 void phydm_dfs_segment_flag_reset(void *dm_void)
62 {
63 struct dm_struct *dm = (struct dm_struct *)dm_void;
64
65 if (!(dm->support_ic_type & (ODM_RTL8814B | ODM_RTL8814C)))
66 return;
67 if (dm->seg1_dfs_flag)
68 dm->seg1_dfs_flag = 0;
69 }
70
phydm_radar_detect_reset(void * dm_void)71 void phydm_radar_detect_reset(void *dm_void)
72 {
73 struct dm_struct *dm = (struct dm_struct *)dm_void;
74
75 if (dm->support_ic_type & (ODM_RTL8198F | ODM_RTL8822C | ODM_RTL8812F |
76 ODM_RTL8197G | ODM_RTL8723F)) {
77 odm_set_bb_reg(dm, R_0xa40, BIT(15), 0);
78 odm_set_bb_reg(dm, R_0xa40, BIT(15), 1);
79 #if (RTL8721D_SUPPORT)
80 } else if (dm->support_ic_type & (ODM_RTL8721D)) {
81 odm_set_bb_reg(dm, R_0xf58, BIT(29), 0);
82 odm_set_bb_reg(dm, R_0xf58, BIT(29), 1);
83 #endif
84 } else if (dm->support_ic_type & (ODM_RTL8814B | ODM_RTL8814C)) {
85 if (dm->seg1_dfs_flag == 1) {
86 odm_set_bb_reg(dm, R_0xa6c, BIT(0), 0);
87 odm_set_bb_reg(dm, R_0xa6c, BIT(0), 1);
88 return;
89 }
90 odm_set_bb_reg(dm, R_0xa40, BIT(15), 0);
91 odm_set_bb_reg(dm, R_0xa40, BIT(15), 1);
92 } else {
93 odm_set_bb_reg(dm, R_0x924, BIT(15), 0);
94 odm_set_bb_reg(dm, R_0x924, BIT(15), 1);
95 }
96 }
97
phydm_radar_detect_disable(void * dm_void)98 void phydm_radar_detect_disable(void *dm_void)
99 {
100 struct dm_struct *dm = (struct dm_struct *)dm_void;
101
102 if (dm->support_ic_type & (ODM_RTL8198F | ODM_RTL8822C | ODM_RTL8812F |
103 ODM_RTL8197G | ODM_RTL8723F))
104 odm_set_bb_reg(dm, R_0xa40, BIT(15), 0);
105 else if (dm->support_ic_type & (ODM_RTL8814B | ODM_RTL8814C)) {
106 if (dm->seg1_dfs_flag == 1) {
107 odm_set_bb_reg(dm, R_0xa6c, BIT(0), 0);
108 dm->seg1_dfs_flag = 0;
109 return;
110 }
111 odm_set_bb_reg(dm, R_0xa40, BIT(15), 0);
112 }
113 #if (RTL8721D_SUPPORT)
114 else if (dm->support_ic_type & (ODM_RTL8721D))
115 odm_set_bb_reg(dm, R_0xf58, BIT(29), 0);
116 #endif
117 else
118 odm_set_bb_reg(dm, R_0x924, BIT(15), 0);
119
120 PHYDM_DBG(dm, DBG_DFS, "\n");
121 }
122
phydm_radar_detect_with_dbg_parm(void * dm_void)123 static void phydm_radar_detect_with_dbg_parm(void *dm_void)
124 {
125 struct dm_struct *dm = (struct dm_struct *)dm_void;
126
127 if (dm->support_ic_type & ODM_RTL8721D) {
128 odm_set_bb_reg(dm, R_0xf54, MASKDWORD,
129 dm->radar_detect_reg_f54);
130 odm_set_bb_reg(dm, R_0xf58, MASKDWORD,
131 dm->radar_detect_reg_f58);
132 odm_set_bb_reg(dm, R_0xf5c, MASKDWORD,
133 dm->radar_detect_reg_f5c);
134 odm_set_bb_reg(dm, R_0xf70, MASKDWORD,
135 dm->radar_detect_reg_f70);
136 odm_set_bb_reg(dm, R_0xf74, MASKDWORD,
137 dm->radar_detect_reg_f74);
138 } else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
139 odm_set_bb_reg(dm, R_0xa40, MASKDWORD,
140 dm->radar_detect_reg_a40);
141 odm_set_bb_reg(dm, R_0xa44, MASKDWORD,
142 dm->radar_detect_reg_a44);
143 odm_set_bb_reg(dm, R_0xa48, MASKDWORD,
144 dm->radar_detect_reg_a48);
145 odm_set_bb_reg(dm, R_0xa4c, MASKDWORD,
146 dm->radar_detect_reg_a4c);
147 odm_set_bb_reg(dm, R_0xa50, MASKDWORD,
148 dm->radar_detect_reg_a50);
149 odm_set_bb_reg(dm, R_0xa54, MASKDWORD,
150 dm->radar_detect_reg_a54);
151 } else {
152 odm_set_bb_reg(dm, R_0x918, MASKDWORD,
153 dm->radar_detect_reg_918);
154 odm_set_bb_reg(dm, R_0x91c, MASKDWORD,
155 dm->radar_detect_reg_91c);
156 odm_set_bb_reg(dm, R_0x920, MASKDWORD,
157 dm->radar_detect_reg_920);
158 odm_set_bb_reg(dm, R_0x924, MASKDWORD,
159 dm->radar_detect_reg_924);
160 }
161 }
162
163 /* @Init radar detection parameters, called after ch, bw is set */
164
phydm_radar_detect_enable(void * dm_void)165 void phydm_radar_detect_enable(void *dm_void)
166 {
167 struct dm_struct *dm = (struct dm_struct *)dm_void;
168 struct _DFS_STATISTICS *dfs = &dm->dfs;
169 u8 region_domain = dm->dfs_region_domain;
170 u8 c_channel = *dm->channel;
171 u8 band_width = *dm->band_width;
172 u8 enable = 0, i;
173 u8 short_pw_upperbound = 0;
174
175 PHYDM_DBG(dm, DBG_DFS, "test, region_domain = %d\n", region_domain);
176 if (region_domain == PHYDM_DFS_DOMAIN_UNKNOWN) {
177 PHYDM_DBG(dm, DBG_DFS, "PHYDM_DFS_DOMAIN_UNKNOWN\n");
178 goto exit;
179 }
180
181 if (dm->support_ic_type & (ODM_RTL8821 | ODM_RTL8812 | ODM_RTL8881A)) {
182 odm_set_bb_reg(dm, R_0x814, 0x3fffffff, 0x04cc4d10);
183 odm_set_bb_reg(dm, R_0x834, MASKBYTE0, 0x06);
184
185 if (dm->radar_detect_dbg_parm_en) {
186 phydm_radar_detect_with_dbg_parm(dm);
187 enable = 1;
188 goto exit;
189 }
190
191 if (region_domain == PHYDM_DFS_DOMAIN_ETSI) {
192 odm_set_bb_reg(dm, R_0x918, MASKDWORD, 0x1c17ecdf);
193 odm_set_bb_reg(dm, R_0x924, MASKDWORD, 0x01528500);
194 odm_set_bb_reg(dm, R_0x91c, MASKDWORD, 0x0fa21a20);
195 odm_set_bb_reg(dm, R_0x920, MASKDWORD, 0xe0f69204);
196
197 } else if (region_domain == PHYDM_DFS_DOMAIN_MKK) {
198 odm_set_bb_reg(dm, R_0x924, MASKDWORD, 0x01528500);
199 odm_set_bb_reg(dm, R_0x920, MASKDWORD, 0xe0d67234);
200
201 if (c_channel >= 52 && c_channel <= 64) {
202 odm_set_bb_reg(dm, R_0x918, MASKDWORD,
203 0x1c16ecdf);
204 odm_set_bb_reg(dm, R_0x91c, MASKDWORD,
205 0x0f141a20);
206 } else {
207 odm_set_bb_reg(dm, R_0x918, MASKDWORD,
208 0x1c16acdf);
209 if (band_width == CHANNEL_WIDTH_20)
210 odm_set_bb_reg(dm, R_0x91c, MASKDWORD,
211 0x64721a20);
212 else
213 odm_set_bb_reg(dm, R_0x91c, MASKDWORD,
214 0x68721a20);
215 }
216
217 } else if (region_domain == PHYDM_DFS_DOMAIN_FCC) {
218 odm_set_bb_reg(dm, R_0x918, MASKDWORD, 0x1c16acdf);
219 odm_set_bb_reg(dm, R_0x924, MASKDWORD, 0x01528500);
220 odm_set_bb_reg(dm, R_0x920, MASKDWORD, 0xe0d67231);
221 if (band_width == CHANNEL_WIDTH_20)
222 odm_set_bb_reg(dm, R_0x91c, MASKDWORD,
223 0x64741a20);
224 else
225 odm_set_bb_reg(dm, R_0x91c, MASKDWORD,
226 0x68741a20);
227
228 } else {
229 /* not supported */
230 PHYDM_DBG(dm, DBG_DFS,
231 "Unsupported dfs_region_domain:%d\n",
232 region_domain);
233 goto exit;
234 }
235
236 } else if (dm->support_ic_type &
237 (ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8821C)) {
238
239 odm_set_bb_reg(dm, R_0x814, 0x3fffffff, 0x04cc4d10);
240 odm_set_bb_reg(dm, R_0x834, MASKBYTE0, 0x06);
241
242 /* @8822B only, when BW = 20M, DFIR output is 40Mhz,
243 * but DFS input is 80MMHz, so it need to upgrade to 80MHz
244 */
245 if (dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8821C)) {
246 if (band_width == CHANNEL_WIDTH_20)
247 odm_set_bb_reg(dm, R_0x1984, BIT(26), 1);
248 else
249 odm_set_bb_reg(dm, R_0x1984, BIT(26), 0);
250 }
251
252 if (dm->radar_detect_dbg_parm_en) {
253 phydm_radar_detect_with_dbg_parm(dm);
254 enable = 1;
255 goto exit;
256 }
257
258 if (region_domain == PHYDM_DFS_DOMAIN_ETSI) {
259 odm_set_bb_reg(dm, R_0x918, MASKDWORD, 0x1c16acdf);
260 odm_set_bb_reg(dm, R_0x924, MASKDWORD, 0x095a8500);
261 odm_set_bb_reg(dm, R_0x91c, MASKDWORD, 0x0fc01a1f);
262 odm_set_bb_reg(dm, R_0x920, MASKDWORD, 0xe0f57204);
263
264 } else if (region_domain == PHYDM_DFS_DOMAIN_MKK) {
265 odm_set_bb_reg(dm, R_0x924, MASKDWORD, 0x095a8500);
266 odm_set_bb_reg(dm, R_0x920, MASKDWORD, 0xe0d67234);
267
268 if (c_channel >= 52 && c_channel <= 64) {
269 odm_set_bb_reg(dm, R_0x918, MASKDWORD,
270 0x1c16ecdf);
271 odm_set_bb_reg(dm, R_0x91c, MASKDWORD,
272 0x0f141a1f);
273 } else {
274 odm_set_bb_reg(dm, R_0x918, MASKDWORD,
275 0x1c166cdf);
276 if (band_width == CHANNEL_WIDTH_20)
277 odm_set_bb_reg(dm, R_0x91c, MASKDWORD,
278 0x64721a1f);
279 else
280 odm_set_bb_reg(dm, R_0x91c, MASKDWORD,
281 0x68721a1f);
282 }
283
284 } else if (region_domain == PHYDM_DFS_DOMAIN_FCC) {
285 odm_set_bb_reg(dm, R_0x918, MASKDWORD, 0x1c176cdf);
286 odm_set_bb_reg(dm, R_0x924, MASKDWORD, 0x095a8400);
287 odm_set_bb_reg(dm, R_0x920, MASKDWORD, 0xe076d231);
288 if (band_width == CHANNEL_WIDTH_20)
289 odm_set_bb_reg(dm, R_0x91c, MASKDWORD,
290 0x64901a1f);
291 else
292 odm_set_bb_reg(dm, R_0x91c, MASKDWORD,
293 0x62901a1f);
294
295 } else {
296 /* not supported */
297 PHYDM_DBG(dm, DBG_DFS,
298 "Unsupported dfs_region_domain:%d\n",
299 region_domain);
300 goto exit;
301 }
302 /*RXHP low corner will extend the pulse width,
303 *so we need to increase the upper bound.
304 */
305 if (dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8821C)) {
306 if (odm_get_bb_reg(dm, 0x8d8,
307 BIT28 | BIT27 | BIT26) == 0) {
308 short_pw_upperbound =
309 (u8)odm_get_bb_reg(dm, 0x91c,
310 BIT23 | BIT22 |
311 BIT21 | BIT20);
312 if ((short_pw_upperbound + 4) > 15)
313 odm_set_bb_reg(dm, 0x91c,
314 BIT23 | BIT22 |
315 BIT21 | BIT20, 15);
316 else
317 odm_set_bb_reg(dm, 0x91c,
318 BIT23 | BIT22 |
319 BIT21 | BIT20,
320 short_pw_upperbound + 4);
321 }
322 /*@if peak index -1~+1, use original NB method*/
323 odm_set_bb_reg(dm, 0x19e4, 0x003C0000, 13);
324 odm_set_bb_reg(dm, 0x924, 0x70000, 0);
325 }
326
327 if (dm->support_ic_type & (ODM_RTL8881A))
328 odm_set_bb_reg(dm, 0xb00, 0xc0000000, 3);
329
330 /*@for 8814 new dfs mechanism setting*/
331 if (dm->support_ic_type &
332 (ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8821C)) {
333 /*Turn off dfs scaling factor*/
334 odm_set_bb_reg(dm, 0x19e4, 0x1fff, 0x0c00);
335 /*NonDC peak_th = 2times DC peak_th*/
336 odm_set_bb_reg(dm, 0x19e4, 0x30000, 1);
337 /*power for debug and auto test flow latch after ST*/
338 odm_set_bb_reg(dm, 0x9f8, 0xc0000000, 3);
339
340 /*@low pulse width radar pattern will cause wrong drop*/
341 /*@disable peak index should the same
342 *during the same short pulse (new mechan)
343 */
344 odm_set_bb_reg(dm, 0x9f4, 0x80000000, 0);
345
346 /*@disable peak index should the same
347 *during the same short pulse (old mechan)
348 */
349 odm_set_bb_reg(dm, 0x924, 0x20000000, 0);
350
351 /*@if peak index diff >=2, then drop the result*/
352 odm_set_bb_reg(dm, 0x19e4, 0xe000, 2);
353 if (region_domain == 2) {
354 if ((c_channel >= 52) && (c_channel <= 64)) {
355 /*pulse width hist th setting*/
356 /*th1=2*04us*/
357 odm_set_bb_reg(dm, 0x19e4,
358 0xff000000, 2);
359 /*th2 = 3*0.4us, th3 = 4*0.4us
360 *th4 = 7*0.4, th5 = 34*0.4
361 */
362 odm_set_bb_reg(dm, 0x19e8,
363 MASKDWORD, 0x22070403);
364
365 /*PRI hist th setting*/
366 /*th1=42*32us*/
367 odm_set_bb_reg(dm, 0x19b8,
368 0x00007f80, 42);
369 /*th2=47*32us, th3=115*32us,
370 *th4=123*32us, th5=130*32us
371 */
372 odm_set_bb_reg(dm, 0x19ec,
373 MASKDWORD, 0x827b732f);
374 } else {
375 /*pulse width hist th setting*/
376 /*th1=2*04us*/
377 odm_set_bb_reg(dm, 0x19e4,
378 0xff000000, 1);
379 /*th2 = 13*0.4us, th3 = 26*0.4us
380 *th4 = 75*0.4us, th5 = 255*0.4us
381 */
382 odm_set_bb_reg(dm, 0x19e8,
383 MASKDWORD, 0xff4b1a0d);
384 /*PRI hist th setting*/
385 /*th1=4*32us*/
386
387 odm_set_bb_reg(dm, 0x19b8,
388 0x00007f80, 4);
389 /*th2=8*32us, th3=16*32us,
390 *th4=32*32us, th5=128*32=4096us
391 */
392 odm_set_bb_reg(dm, 0x19ec,
393 MASKDWORD, 0x80201008);
394 }
395 }
396 /*@ETSI*/
397 else if (region_domain == 3) {
398 /*pulse width hist th setting*/
399 /*th1=2*04us*/
400 odm_set_bb_reg(dm, 0x19e4, 0xff000000, 1);
401 odm_set_bb_reg(dm, 0x19e8,
402 MASKDWORD, 0x68260d06);
403 /*PRI hist th setting*/
404 /*th1=7*32us*/
405 odm_set_bb_reg(dm, 0x19b8, 0x00007f80, 7);
406 /*th2=40*32us, th3=80*32us,
407 *th4=110*32us, th5=157*32=5024
408 */
409 odm_set_bb_reg(dm, 0x19ec,
410 MASKDWORD, 0xc06e2010);
411 }
412 /*@FCC*/
413 else if (region_domain == 1) {
414 /*pulse width hist th setting*/
415 /*th1=2*04us*/
416 odm_set_bb_reg(dm, 0x19e4, 0xff000000, 2);
417 /*th2 = 13*0.4us, th3 = 26*0.4us,
418 *th4 = 75*0.4us, th5 = 255*0.4us
419 */
420 odm_set_bb_reg(dm, 0x19e8,
421 MASKDWORD, 0xff4b1a0d);
422
423 /*PRI hist th setting*/
424 /*th1=4*32us*/
425 odm_set_bb_reg(dm, 0x19b8, 0x00007f80, 4);
426 /*th2=8*32us, th3=21*32us,
427 *th4=32*32us, th5=96*32=3072
428 */
429 if (band_width == CHANNEL_WIDTH_20)
430 odm_set_bb_reg(dm, 0x19ec,
431 MASKDWORD, 0x60282010);
432 else
433 odm_set_bb_reg(dm, 0x19ec,
434 MASKDWORD, 0x60282420);
435 } else {
436 }
437 }
438 } else if (dm->support_ic_type &
439 ODM_IC_JGR3_SERIES) {
440 if (dm->radar_detect_dbg_parm_en) {
441 phydm_radar_detect_with_dbg_parm(dm);
442 enable = 1;
443 goto exit;
444 }
445 if (region_domain == PHYDM_DFS_DOMAIN_ETSI) {
446 odm_set_bb_reg(dm, R_0xa40, MASKDWORD, 0xb25dc0bd);
447 if (dm->support_ic_type &
448 (ODM_RTL8814B | ODM_RTL8814C)) {
449 if (dm->seg1_dfs_flag == 1)
450 odm_set_bb_reg(dm, R_0xa6c, BIT(0), 1);
451 }
452 odm_set_bb_reg(dm, R_0xa44, MASKDWORD, 0x3030bea0);
453 odm_set_bb_reg(dm, R_0xa48, MASKDWORD, 0x2a521254);
454 odm_set_bb_reg(dm, R_0xa4c, MASKDWORD, 0x42533345);
455 odm_set_bb_reg(dm, R_0xa50, MASKDWORD, 0x605be0c3);
456 odm_set_bb_reg(dm, R_0xa54, MASKDWORD, 0x500009e8);
457 odm_set_bb_reg(dm, R_0x180c, 0xe0000, 0x0);
458 } else if (region_domain == PHYDM_DFS_DOMAIN_MKK) {
459 odm_set_bb_reg(dm, R_0xa40, MASKDWORD, 0xb25dc0bd);
460 if (dm->support_ic_type &
461 (ODM_RTL8814B | ODM_RTL8814C)) {
462 if (dm->seg1_dfs_flag == 1)
463 odm_set_bb_reg(dm, R_0xa6c, BIT(0), 1);
464 }
465 odm_set_bb_reg(dm, R_0xa44, MASKDWORD, 0x3030bea0);
466 odm_set_bb_reg(dm, R_0xa48, MASKDWORD, 0x2a521254);
467 odm_set_bb_reg(dm, R_0xa4c, MASKDWORD, 0x42533345);
468 odm_set_bb_reg(dm, R_0xa50, MASKDWORD, 0x605be0c3);
469 odm_set_bb_reg(dm, R_0xa54, MASKDWORD, 0x500009e8);
470 odm_set_bb_reg(dm, R_0x180c, 0xe0000, 0x0);
471 } else if (region_domain == PHYDM_DFS_DOMAIN_FCC) {
472 odm_set_bb_reg(dm, R_0xa40, MASKDWORD, 0xb25dc0bd);
473 if (dm->support_ic_type &
474 (ODM_RTL8814B | ODM_RTL8814C)) {
475 if (dm->seg1_dfs_flag == 1)
476 odm_set_bb_reg(dm, R_0xa6c, BIT(0), 1);
477 }
478 odm_set_bb_reg(dm, R_0xa44, MASKDWORD, 0x3030bea0);
479 odm_set_bb_reg(dm, R_0xa48, MASKDWORD, 0x2a521254);
480 odm_set_bb_reg(dm, R_0xa4c, MASKDWORD, 0x42533345);
481 odm_set_bb_reg(dm, R_0xa50, MASKDWORD, 0x605be0c3);
482 odm_set_bb_reg(dm, R_0xa54, MASKDWORD, 0x500009e8);
483 odm_set_bb_reg(dm, R_0x180c, 0xe0000, 0x0);
484 } else {
485 /* not supported */
486 PHYDM_DBG(dm, DBG_DFS,
487 "Unsupported dfs_region_domain:%d\n",
488 region_domain);
489 goto exit;
490 }
491 #if (RTL8721D_SUPPORT)
492 } else if (dm->support_ic_type & ODM_RTL8721D) {
493 odm_set_bb_reg(dm, R_0x814, 0x3fffffff, 0x04cc4d10);
494 /*CCA MASK*/
495 odm_set_bb_reg(dm, R_0xc38, 0x07c00000, 0x06);
496 /*CCA Threshold*/
497 odm_set_bb_reg(dm, R_0xc3c, 0x00000007, 0x0);
498
499 if (dm->radar_detect_dbg_parm_en) {
500 phydm_radar_detect_with_dbg_parm(dm);
501 enable = 1;
502 goto exit;
503 }
504
505 if (region_domain == PHYDM_DFS_DOMAIN_ETSI) {
506 odm_set_bb_reg(dm, R_0xf54, MASKDWORD, 0x230006a8);
507 odm_set_bb_reg(dm, R_0xf58, MASKDWORD, 0x354cd7dd);
508 odm_set_bb_reg(dm, R_0xf5c, MASKDWORD, 0x9984ab25);
509 odm_set_bb_reg(dm, R_0xf70, MASKDWORD, 0xbd9fab98);
510 odm_set_bb_reg(dm, R_0xf74, MASKDWORD, 0xcc45029f);
511
512 } else if (region_domain == PHYDM_DFS_DOMAIN_MKK) {
513 odm_set_bb_reg(dm, R_0xf54, MASKDWORD, 0x230006a8);
514 odm_set_bb_reg(dm, R_0xf5c, MASKDWORD, 0x9984ab25);
515 odm_set_bb_reg(dm, R_0xf70, MASKDWORD, 0xbd9fb398);
516 odm_set_bb_reg(dm, R_0xf74, MASKDWORD, 0xcc450e9d);
517
518 if (c_channel >= 52 && c_channel <= 64) {
519 odm_set_bb_reg(dm, R_0xf58, MASKDWORD,
520 0x354cd7fd);
521 } else {
522 odm_set_bb_reg(dm, R_0xf58, MASKDWORD,
523 0x354cd7bd);
524 }
525 } else if (region_domain == PHYDM_DFS_DOMAIN_FCC) {
526 odm_set_bb_reg(dm, R_0xf54, MASKDWORD, 0x230006a8);
527 odm_set_bb_reg(dm, R_0xf58, MASKDWORD, 0x3558d7bd);
528 odm_set_bb_reg(dm, R_0xf5c, MASKDWORD, 0x9984ab35);
529 odm_set_bb_reg(dm, R_0xf70, MASKDWORD, 0xbd9fb398);
530 odm_set_bb_reg(dm, R_0xf74, MASKDWORD, 0xcc444e9d);
531 } else {
532 /* not supported */
533 PHYDM_DBG(dm, DBG_DFS,
534 "Unsupported dfs_region_domain:%d\n",
535 region_domain);
536 goto exit;
537 }
538
539 /*if peak index -1~+1, use original NB method*/
540 odm_set_bb_reg(dm, R_0xf70, 0x00070000, 0x7);
541 odm_set_bb_reg(dm, R_0xf74, 0x000c0000, 0);
542
543 /*Turn off dfs scaling factor*/
544 odm_set_bb_reg(dm, R_0xf70, 0x00080000, 0x0);
545 /*NonDC peak_th = 2times DC peak_th*/
546 odm_set_bb_reg(dm, R_0xf58, 0x00007800, 1);
547
548 /*low pulse width radar pattern will cause wrong drop*/
549 /*disable peak index should the same*/
550 /*during the same short pulse (new mechan)*/
551 odm_set_bb_reg(dm, R_0xf70, 0x00100000, 0x0);
552 /*if peak index diff >=2, then drop the result*/
553 odm_set_bb_reg(dm, R_0xf70, 0x30000000, 0x2);
554 #endif
555 } else {
556 /*not supported IC type*/
557 PHYDM_DBG(dm, DBG_DFS, "Unsupported IC type:%d\n",
558 dm->support_ic_type);
559 goto exit;
560 }
561
562 enable = 1;
563
564 if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
565 dfs->st_l2h_cur = (u8)odm_get_bb_reg(dm, R_0xa40, 0x00007f00);
566 dfs->pwdb_th_cur = (u8)odm_get_bb_reg(dm, R_0xa50, 0x000000f0);
567 dfs->peak_th = (u8)odm_get_bb_reg(dm, R_0xa48, 0x00c00000);
568 dfs->short_pulse_cnt_th = (u8)odm_get_bb_reg(dm, R_0xa50,
569 0x00f00000);
570 dfs->long_pulse_cnt_th = (u8)odm_get_bb_reg(dm, R_0xa4c,
571 0xf0000000);
572 dfs->peak_window = (u8)odm_get_bb_reg(dm, R_0xa40, 0x00030000);
573 dfs->three_peak_opt = (u8)odm_get_bb_reg(dm, R_0xa40,
574 0x30000000);
575 dfs->three_peak_th2 = (u8)odm_get_bb_reg(dm, R_0xa44,
576 0x00000007);
577 #if (RTL8721D_SUPPORT)
578 } else if (dm->support_ic_type & (ODM_RTL8721D)) {
579 dfs->st_l2h_cur = (u8)odm_get_bb_reg(dm, R_0xf54,
580 0x0000001f) << 2);
581 dfs->st_l2h_cur += (u8)odm_get_bb_reg(dm, R_0xf58, 0xc0000000);
582 dfs->pwdb_th_cur = (u8)odm_get_bb_reg(dm, R_0xf70, 0x03c00000);
583 dfs->peak_th = (u8)odm_get_bb_reg(dm, R_0xf5c, 0x00000030);
584 dfs->short_pulse_cnt_th = (u8)odm_get_bb_reg(dm, R_0xf70,
585 0x00007800);
586 dfs->long_pulse_cnt_th = (u8)odm_get_bb_reg(dm, R_0xf74,
587 0x0000000f);
588 dfs->peak_window = (u8)odm_get_bb_reg(dm, R_0xf58, 0x18000000);
589 dfs->three_peak_opt = (u8)odm_get_bb_reg(dm, R_0xf58,
590 0x00030000);
591 dfs->three_peak_th2 = (u8)odm_get_bb_reg(dm,
592 R_0xf58, 0x00007c00);
593 #endif
594 } else {
595 dfs->st_l2h_cur = (u8)odm_get_bb_reg(dm, R_0x91c, 0x000000ff);
596 dfs->pwdb_th_cur = (u8)odm_get_bb_reg(dm, R_0x918, 0x00001f00);
597 dfs->peak_th = (u8)odm_get_bb_reg(dm, R_0x918, 0x00030000);
598 dfs->short_pulse_cnt_th = (u8)odm_get_bb_reg(dm, R_0x920,
599 0x000f0000);
600 dfs->long_pulse_cnt_th = (u8)odm_get_bb_reg(dm, R_0x920,
601 0x00f00000);
602 dfs->peak_window = (u8)odm_get_bb_reg(dm, R_0x920, 0x00000300);
603 dfs->three_peak_opt = (u8)odm_get_bb_reg(dm, 0x924, 0x00000180);
604 dfs->three_peak_th2 = (u8)odm_get_bb_reg(dm, 0x924, 0x00007000);
605 }
606
607 phydm_dfs_parameter_init(dm);
608
609 exit:
610 if (enable) {
611 phydm_radar_detect_reset(dm);
612 PHYDM_DBG(dm, DBG_DFS, "on cch:%u, bw:%u\n", c_channel,
613 band_width);
614 } else
615 phydm_radar_detect_disable(dm);
616 }
617
phydm_dfs_parameter_init(void * dm_void)618 void phydm_dfs_parameter_init(void *dm_void)
619 {
620 struct dm_struct *dm = (struct dm_struct *)dm_void;
621 struct _DFS_STATISTICS *dfs = &dm->dfs;
622
623 u8 i;
624 for (i = 0; i < 5; i++) {
625 dfs->pulse_flag_hist[i] = 0;
626 dfs->pulse_type_hist[i] = 0;
627 dfs->radar_det_mask_hist[i] = 0;
628 dfs->fa_inc_hist[i] = 0;
629 }
630
631 /*@for dfs mode*/
632 dfs->force_TP_mode = 0;
633 dfs->sw_trigger_mode = 0;
634 dfs->det_print = 0;
635 dfs->det_print2 = 0;
636 dfs->print_hist_rpt = 0;
637 if (dm->support_ic_type & (ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8821C))
638 dfs->hist_cond_on = 1;
639 else
640 dfs->hist_cond_on = 0;
641 if (dm->support_ic_type & (ODM_RTL8723F | ODM_RTL8822C)) {
642 dfs->det_print_jar3 = 1;
643 dfs->nhm_dfs_en = true;
644 dfs->det_jar3_en = true;
645 } else {
646 dfs->det_print_jar3 = 0;
647 dfs->nhm_dfs_en = false;
648 dfs->det_jar3_en = false;
649 }
650
651 /*@for flag en*/
652 dfs->pw_flag_en = true;
653 dfs->pri_flag_en = true;
654 dfs->loct_flag_en = true;
655 dfs->nhm_cnt_th = 4;
656 dfs->nhm_dty_th = 40;
657
658 /*@for jgar3*/
659 dfs->pri_var_offset = 2;
660 dfs->pri_var_tp_offset = 10;
661 dfs->pri_cnt_th = 2;
662 dfs->loct_diff_th = 15;
663 dfs->dc_cnt_th = 3;
664
665 /*@for dynamic dfs*/
666 dfs->pwdb_th = 8;
667 dfs->fa_mask_th = 120 * dfs->dfs_polling_time / 100;
668 dfs->st_l2h_min = 0x20;
669 dfs->st_l2h_max = 0x4e;
670 dfs->pwdb_scalar_factor = 12;
671
672 /*@for dfs histogram*/
673 dfs->pri_hist_th = 5;
674 dfs->pri_sum_g1_th = 9;
675 dfs->pri_sum_g5_th = 5;
676 dfs->pri_sum_g1_fcc_th = 4; /*@FCC Type6*/
677 dfs->pri_sum_g3_fcc_th = 6;
678 dfs->pri_sum_safe_th = 50;
679 dfs->pri_sum_safe_fcc_th = 110; /*@30 for AP*/
680 dfs->pri_sum_type4_th = 16;
681 dfs->pri_sum_type6_th = 12;
682 dfs->pri_sum_g5_under_g1_th = 4;
683 dfs->pri_pw_diff_th = 4;
684 dfs->pri_pw_diff_fcc_th = 8;
685 dfs->pri_pw_diff_fcc_idle_th = 2;
686 dfs->pri_pw_diff_w53_th = 10;
687 dfs->pw_std_th = 7; /*@FCC Type4*/
688 dfs->pw_std_idle_th = 10;
689 dfs->pri_std_th = 6; /*@FCC Type3,4,6*/
690 dfs->pri_std_idle_th = 10;
691 dfs->pri_type1_upp_fcc_th = 110;
692 dfs->pri_type1_low_fcc_th = 50;
693 dfs->pri_type1_cen_fcc_th = 70;
694 dfs->pw_g0_th = 8;
695 dfs->pw_long_lower_th = 6; /*@7->6*/
696 dfs->pri_long_upper_th = 30;
697 dfs->pw_long_lower_20m_th = 7; /*@7 for AP*/
698 dfs->pw_long_sum_upper_th = 60;
699 dfs->type4_pw_max_cnt = 7;
700 dfs->type4_safe_pri_sum_th = 5;
701 }
702
phydm_dfs_dynamic_setting(void * dm_void)703 void phydm_dfs_dynamic_setting(
704 void *dm_void)
705 {
706 struct dm_struct *dm = (struct dm_struct *)dm_void;
707 struct _DFS_STATISTICS *dfs = &dm->dfs;
708
709 u8 peak_th_cur = 0, short_pulse_cnt_th_cur = 0;
710 u8 long_pulse_cnt_th_cur = 0, three_peak_opt_cur = 0;
711 u8 three_peak_th2_cur = 0;
712 u8 peak_window_cur = 0;
713 u8 region_domain = dm->dfs_region_domain;
714 u8 c_channel = *dm->channel;
715
716 if (dm->rx_tp + dm->tx_tp <= 2) {
717 dfs->idle_mode = 1;
718 if (dfs->force_TP_mode)
719 dfs->idle_mode = 0;
720 } else {
721 dfs->idle_mode = 0;
722 }
723
724 if (dfs->idle_mode == 1) { /*@idle (no traffic)*/
725 peak_th_cur = 3;
726 short_pulse_cnt_th_cur = 6;
727 long_pulse_cnt_th_cur = 9;
728 peak_window_cur = 2;
729 three_peak_opt_cur = 0;
730 three_peak_th2_cur = 2;
731 if (region_domain == PHYDM_DFS_DOMAIN_MKK) {
732 if (c_channel >= 52 && c_channel <= 64) {
733 short_pulse_cnt_th_cur = 14;
734 long_pulse_cnt_th_cur = 15;
735 three_peak_th2_cur = 0;
736 } else {
737 short_pulse_cnt_th_cur = 6;
738 three_peak_th2_cur = 0;
739 long_pulse_cnt_th_cur = 10;
740 }
741 } else if (region_domain == PHYDM_DFS_DOMAIN_FCC) {
742 three_peak_th2_cur = 0;
743 } else if (region_domain == PHYDM_DFS_DOMAIN_ETSI) {
744 long_pulse_cnt_th_cur = 15;
745 if (phydm_dfs_is_meteorology_channel(dm)) {
746 /*need to add check cac end condition*/
747 peak_th_cur = 2;
748 three_peak_opt_cur = 0;
749 three_peak_th2_cur = 0;
750 short_pulse_cnt_th_cur = 7;
751 } else {
752 three_peak_opt_cur = 0;
753 three_peak_th2_cur = 0;
754 short_pulse_cnt_th_cur = 7;
755 }
756 } else /*@default: FCC*/
757 three_peak_th2_cur = 0;
758
759 } else { /*@in service (with TP)*/
760 peak_th_cur = 2;
761 short_pulse_cnt_th_cur = 6;
762 long_pulse_cnt_th_cur = 7;
763 peak_window_cur = 2;
764 three_peak_opt_cur = 0;
765 three_peak_th2_cur = 2;
766 if (region_domain == PHYDM_DFS_DOMAIN_MKK) {
767 if (c_channel >= 52 && c_channel <= 64) {
768 long_pulse_cnt_th_cur = 15;
769 /*@for high duty cycle*/
770 short_pulse_cnt_th_cur = 5;
771 three_peak_th2_cur = 0;
772 } else {
773 three_peak_opt_cur = 0;
774 three_peak_th2_cur = 0;
775 long_pulse_cnt_th_cur = 8;
776 }
777 } else if (region_domain == PHYDM_DFS_DOMAIN_FCC) {
778 long_pulse_cnt_th_cur = 5; /*for 80M FCC*/
779 short_pulse_cnt_th_cur = 5; /*for 80M FCC*/
780 } else if (region_domain == PHYDM_DFS_DOMAIN_ETSI) {
781 long_pulse_cnt_th_cur = 15;
782 short_pulse_cnt_th_cur = 5;
783 three_peak_opt_cur = 0;
784 }
785 }
786
787 if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
788 /*
789 if (dfs->peak_th != peak_th_cur)
790 odm_set_bb_reg(dm, R_0xa48, 0x00c00000, peak_th_cur);
791 if (dfs->short_pulse_cnt_th != short_pulse_cnt_th_cur)
792 odm_set_bb_reg(dm, R_0xa50, 0x00f00000,
793 short_pulse_cnt_th_cur);
794 if (dfs->long_pulse_cnt_th != long_pulse_cnt_th_cur)
795 odm_set_bb_reg(dm, R_0xa4c, 0xf0000000,
796 long_pulse_cnt_th_cur);
797 if (dfs->peak_window != peak_window_cur)
798 odm_set_bb_reg(dm, R_0xa40, 0x00030000,
799 peak_window_cur);
800 if (dfs->three_peak_opt != three_peak_opt_cur)
801 odm_set_bb_reg(dm, R_0xa40, 0x30000000,
802 three_peak_opt_cur);
803 if (dfs->three_peak_th2 != three_peak_th2_cur)
804 odm_set_bb_reg(dm, R_0xa44, 0x00000007,
805 three_peak_th2_cur);
806 */
807 #if (RTL8721D_SUPPORT)
808 } else if (dm->support_ic_type & (ODM_RTL8721D)) {
809 if (dfs->peak_th != peak_th_cur)
810 odm_set_bb_reg(dm, R_0xf5c, 0x00000030, peak_th_cur);
811 if (dfs->short_pulse_cnt_th != short_pulse_cnt_th_cur)
812 odm_set_bb_reg(dm, R_0xf70, 0x00007800,
813 short_pulse_cnt_th_cur);
814 if (dfs->long_pulse_cnt_th != long_pulse_cnt_th_cur)
815 odm_set_bb_reg(dm, R_0xf74, 0x0000000f,
816 long_pulse_cnt_th_cur);
817 if (dfs->peak_window != peak_window_cur)
818 odm_set_bb_reg(dm, R_0xf58, 0x18000000,
819 peak_window_cur);
820 if (dfs->three_peak_opt != three_peak_opt_cur)
821 odm_set_bb_reg(dm, R_0xf58, 0x00030000,
822 three_peak_opt_cur);
823 if (dfs->three_peak_th2 != three_peak_th2_cur)
824 odm_set_bb_reg(dm, R_0xf58, 0x00007c00,
825 three_peak_th2_cur);
826 #endif
827 } else {
828 if (dfs->peak_th != peak_th_cur)
829 odm_set_bb_reg(dm, R_0x918, 0x00030000, peak_th_cur);
830 if (dfs->short_pulse_cnt_th != short_pulse_cnt_th_cur)
831 odm_set_bb_reg(dm, R_0x920, 0x000f0000,
832 short_pulse_cnt_th_cur);
833 if (dfs->long_pulse_cnt_th != long_pulse_cnt_th_cur)
834 odm_set_bb_reg(dm, R_0x920, 0x00f00000,
835 long_pulse_cnt_th_cur);
836 if (dfs->peak_window != peak_window_cur)
837 odm_set_bb_reg(dm, R_0x920, 0x00000300,
838 peak_window_cur);
839 if (dfs->three_peak_opt != three_peak_opt_cur)
840 odm_set_bb_reg(dm, R_0x924, 0x00000180,
841 three_peak_opt_cur);
842 if (dfs->three_peak_th2 != three_peak_th2_cur)
843 odm_set_bb_reg(dm, R_0x924, 0x00007000,
844 three_peak_th2_cur);
845 }
846
847 dfs->peak_th = peak_th_cur;
848 dfs->short_pulse_cnt_th = short_pulse_cnt_th_cur;
849 dfs->long_pulse_cnt_th = long_pulse_cnt_th_cur;
850 dfs->peak_window = peak_window_cur;
851 dfs->three_peak_opt = three_peak_opt_cur;
852 dfs->three_peak_th2 = three_peak_th2_cur;
853 }
854
855 boolean
phydm_radar_detect_dm_check(void * dm_void)856 phydm_radar_detect_dm_check(
857 void *dm_void)
858 {
859 struct dm_struct *dm = (struct dm_struct *)dm_void;
860 struct _DFS_STATISTICS *dfs = &dm->dfs;
861 struct phydm_fa_struct *fa_t = &dm->false_alm_cnt;
862 u8 region_domain = dm->dfs_region_domain, index = 0;
863
864 u16 i = 0, j = 0, fa_count_cur = 0, fa_count_inc = 0;
865 u16 total_fa_in_hist = 0, total_pulse_count_inc = 0;
866 u16 short_pulse_cnt_inc = 0, short_pulse_cnt_cur = 0;
867 u16 long_pulse_cnt_inc = 0, long_pulse_cnt_cur = 0;
868 u32 regf98_value = 0, reg918_value = 0, reg91c_value = 0;
869 u32 reg920_value = 0, reg924_value = 0, radar_rpt_reg_value = 0;
870 u32 regf54_value = 0, regf58_value = 0, regf5c_value = 0;
871 u32 regdf4_value = 0, regf70_value = 0, regf74_value = 0;
872 #if (RTL8812F_SUPPORT || RTL8822C_SUPPORT || RTL8814B_SUPPORT || RTL8723F_SUPPORT)
873 u32 rega40_value = 0, rega44_value = 0, rega48_value = 0;
874 u32 rega4c_value = 0, rega50_value = 0, rega54_value = 0;
875 u32 reg_2e08 = 0, reg_2e24 = 0, reg_2e28 = 0;
876 u32 reg_2e2c = 0, reg_2e30 = 0, reg_2e34 = 0;
877 u32 reg_2e0c = 0, reg_2e10 = 0, reg_2e20 = 0;
878 #endif
879 #if (RTL8721D_SUPPORT)
880 u32 reg908_value = 0, regdf4_value = 0;
881 u32 regf54_value = 0, regf58_value = 0, regf5c_value = 0;
882 u32 regf70_value = 0, regf74_value = 0;
883 #endif
884 boolean tri_short_pulse = 0, tri_long_pulse = 0, radar_type = 0;
885 boolean fault_flag_det = 0, fault_flag_psd = 0, fa_flag = 0;
886 boolean radar_detected = 0;
887 u8 st_l2h_new = 0, fa_mask_th = 0, k = 0, sum = 0;
888 u8 c_channel = *dm->channel;
889
890 /*@Get FA count during past 100ms, R_0xf48 for AC series*/
891 if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
892 /*fa_count_cur = (u16)odm_get_bb_reg(dm, R_0x2d00, MASKLWORD);*/
893 /*1-sec period*/
894 fa_count_cur = fa_t->cnt_all * dfs->dfs_polling_time / 1000;
895 #if (RTL8721D_SUPPORT)
896 else if (dm->support_ic_type & (ODM_RTL8721D)) {
897 fa_count_cur = (u16)odm_get_bb_reg(dm,
898 ODM_REG_OFDM_FA_TYPE2_11N,
899 MASKHWORD);
900 fa_count_cur += (u16)odm_get_bb_reg(dm,
901 ODM_REG_OFDM_FA_TYPE3_11N,
902 MASKLWORD);
903 fa_count_cur += (u16)odm_get_bb_reg(dm,
904 ODM_REG_OFDM_FA_TYPE3_11N,
905 MASKHWORD);
906 fa_count_cur += (u16)odm_get_bb_reg(dm,
907 ODM_REG_OFDM_FA_TYPE4_11N,
908 MASKLWORD);
909 fa_count_cur += (u16)odm_get_bb_reg(dm,
910 ODM_REG_OFDM_FA_TYPE1_11N,
911 MASKLWORD);
912 fa_count_cur += (u16)odm_get_bb_reg(dm,
913 ODM_REG_OFDM_FA_TYPE1_11N,
914 MASKHWORD);
915 }
916 #endif
917 else
918 fa_count_cur = (u16)odm_get_bb_reg(dm, R_0xf48, 0x0000ffff);
919
920 if (!(dm->support_ic_type & ODM_IC_JGR3_SERIES)) {
921 if (dfs->fa_count_pre == 0)
922 fa_count_inc = 0;
923 else if (fa_count_cur >= dfs->fa_count_pre)
924 fa_count_inc = fa_count_cur - dfs->fa_count_pre;
925 else
926 fa_count_inc = fa_count_cur;
927 dfs->fa_count_pre = fa_count_cur;
928 } else {
929 fa_count_inc = fa_count_cur;
930 }
931
932 for (i = 0; i < 5; i++)
933 total_fa_in_hist = total_fa_in_hist + dfs->fa_inc_hist[i];
934
935 if (dfs->mask_idx >= 2)
936 index = dfs->mask_idx - 2;
937 else
938 index = 5 + dfs->mask_idx - 2;
939
940 if (dm->support_ic_type & (ODM_RTL8198F | ODM_RTL8822C | ODM_RTL8812F |
941 ODM_RTL8197G| ODM_RTL8723F)) {
942 radar_rpt_reg_value = odm_get_bb_reg(dm, R_0x2e00, 0xffffffff);
943 short_pulse_cnt_cur = (u16)((radar_rpt_reg_value & 0x000ff800)
944 >> 11);
945 long_pulse_cnt_cur = (u16)((radar_rpt_reg_value & 0x0fc00000)
946 >> 22);
947 #if (RTL8721D_SUPPORT)
948 } else if (dm->support_ic_type & (ODM_RTL8721D)) {
949 reg908_value = (u32)odm_get_bb_reg(dm, R_0x908, MASKDWORD);
950 odm_set_bb_reg(dm, R_0x908, MASKDWORD, 0x254);
951 regdf4_value = odm_get_bb_reg(dm, R_0xdf4, MASKDWORD);
952 short_pulse_cnt_cur = (u16)((regdf4_value & 0x000ff000) >> 12);
953 long_pulse_cnt_cur = (u16)((regdf4_value & 0x0fc00000) >> 22);
954
955 tri_short_pulse = (regdf4_value & BIT(20)) ? 1 : 0;
956 tri_long_pulse = (regdf4_value & BIT(28)) ? 1 : 0;
957 if (tri_short_pulse || tri_long_pulse) {
958 odm_set_bb_reg(dm, R_0xf58, BIT(29), 0);
959 odm_set_bb_reg(dm, R_0xf58, BIT(29), 1);
960 }
961 #endif
962 } else if (dm->support_ic_type & (ODM_RTL8814B | ODM_RTL8814C)) {
963 if (dm->seg1_dfs_flag == 1)
964 radar_rpt_reg_value = odm_get_bb_reg(dm, R_0x2e20,
965 0xffffffff);
966 else
967 radar_rpt_reg_value = odm_get_bb_reg(dm, R_0x2e00,
968 0xffffffff);
969 short_pulse_cnt_cur = (u16)((radar_rpt_reg_value & 0x000ff800)
970 >> 11);
971 long_pulse_cnt_cur = (u16)((radar_rpt_reg_value & 0x0fc00000)
972 >> 22);
973 } else {
974 regf98_value = odm_get_bb_reg(dm, R_0xf98, 0xffffffff);
975 short_pulse_cnt_cur = (u16)(regf98_value & 0x000000ff);
976 long_pulse_cnt_cur = (u16)((regf98_value & 0x0000ff00) >> 8);
977 }
978
979 /*@Get short pulse count, need carefully handle the counter overflow*/
980 if (short_pulse_cnt_cur >= dfs->short_pulse_cnt_pre) {
981 short_pulse_cnt_inc = short_pulse_cnt_cur -
982 dfs->short_pulse_cnt_pre;
983 } else {
984 short_pulse_cnt_inc = short_pulse_cnt_cur;
985 }
986 dfs->short_pulse_cnt_pre = short_pulse_cnt_cur;
987
988 /*@Get long pulse count, need carefully handle the counter overflow*/
989 if (long_pulse_cnt_cur >= dfs->long_pulse_cnt_pre) {
990 long_pulse_cnt_inc = long_pulse_cnt_cur -
991 dfs->long_pulse_cnt_pre;
992 } else {
993 long_pulse_cnt_inc = long_pulse_cnt_cur;
994 }
995 dfs->long_pulse_cnt_pre = long_pulse_cnt_cur;
996
997 total_pulse_count_inc = short_pulse_cnt_inc + long_pulse_cnt_inc;
998
999 if (dfs->det_print) {
1000 PHYDM_DBG(dm, DBG_DFS,
1001 "===============================================\n");
1002 PHYDM_DBG(dm, DBG_DFS, "FA_count_inc[%d]\n", fa_count_inc);
1003 if (dm->support_ic_type & (ODM_RTL8721D)) {
1004 PHYDM_DBG(dm, DBG_DFS,
1005 "Init_Gain[%x] st_l2h_cur[%x] 0xdf4[%08x] short_pulse_cnt_inc[%d] long_pulse_cnt_inc[%d]\n",
1006 dfs->igi_cur, dfs->st_l2h_cur, regdf4_value,
1007 short_pulse_cnt_inc, long_pulse_cnt_inc);
1008 regf54_value = odm_get_bb_reg(dm, R_0xf54, MASKDWORD);
1009 regf58_value = odm_get_bb_reg(dm, R_0xf58, MASKDWORD);
1010 regf5c_value = odm_get_bb_reg(dm, R_0xf5c, MASKDWORD);
1011 regf70_value = odm_get_bb_reg(dm, R_0xf70, MASKDWORD);
1012 regf74_value = odm_get_bb_reg(dm, R_0xf74, MASKDWORD);
1013 PHYDM_DBG(dm, DBG_DFS,
1014 "0xf54[%08x] 0xf58[%08x] 0xf5c[%08x] 0xf70[%08x] 0xf74[%08x]\n",
1015 regf54_value, regf58_value, regf5c_value,
1016 regf70_value, regf74_value);
1017 } else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
1018 PHYDM_DBG(dm, DBG_DFS,
1019 "Init_Gain[%x] st_l2h_cur[%x] 0x2dbc[%08x] short_pulse_cnt_inc[%d] long_pulse_cnt_inc[%d]\n",
1020 dfs->igi_cur, dfs->st_l2h_cur,
1021 radar_rpt_reg_value, short_pulse_cnt_inc,
1022 long_pulse_cnt_inc);
1023 #if (RTL8812F_SUPPORT || RTL8822C_SUPPORT || RTL8814B_SUPPORT)
1024 rega40_value = odm_get_bb_reg(dm, R_0xa40, MASKDWORD);
1025 rega44_value = odm_get_bb_reg(dm, R_0xa44, MASKDWORD);
1026 rega48_value = odm_get_bb_reg(dm, R_0xa48, MASKDWORD);
1027 rega4c_value = odm_get_bb_reg(dm, R_0xa4c, MASKDWORD);
1028 rega50_value = odm_get_bb_reg(dm, R_0xa50, MASKDWORD);
1029 rega54_value = odm_get_bb_reg(dm, R_0xa54, MASKDWORD);
1030 PHYDM_DBG(dm, DBG_DFS,
1031 "0xa40[%08x] 0xa44[%08x] 0xa48[%08x] 0xa4c[%08x] 0xa50[%08x] 0xa54[%08x]\n",
1032 rega40_value, rega44_value, rega48_value,
1033 rega4c_value, rega50_value, rega54_value);
1034 #endif
1035 } else {
1036 PHYDM_DBG(dm, DBG_DFS,
1037 "Init_Gain[%x] 0x91c[%x] 0xf98[%08x] short_pulse_cnt_inc[%d] long_pulse_cnt_inc[%d]\n",
1038 dfs->igi_cur, dfs->st_l2h_cur, regf98_value,
1039 short_pulse_cnt_inc, long_pulse_cnt_inc);
1040 reg918_value = odm_get_bb_reg(dm, R_0x918,
1041 0xffffffff);
1042 reg91c_value = odm_get_bb_reg(dm, R_0x91c,
1043 0xffffffff);
1044 reg920_value = odm_get_bb_reg(dm, R_0x920,
1045 0xffffffff);
1046 reg924_value = odm_get_bb_reg(dm, R_0x924,
1047 0xffffffff);
1048 PHYDM_DBG(dm, DBG_DFS,
1049 "0x918[%08x] 0x91c[%08x] 0x920[%08x] 0x924[%08x]\n",
1050 reg918_value, reg91c_value,
1051 reg920_value, reg924_value);
1052 }
1053 PHYDM_DBG(dm, DBG_DFS, "Throughput: %dMbps\n",
1054 (dm->rx_tp + dm->tx_tp));
1055
1056 PHYDM_DBG(dm, DBG_DFS,
1057 "dfs_regdomain = %d, dbg_mode = %d, idle_mode = %d, print_hist_rpt = %d, hist_cond_on = %d\n",
1058 region_domain, dfs->dbg_mode,
1059 dfs->idle_mode, dfs->print_hist_rpt,
1060 dfs->hist_cond_on);
1061 }
1062 if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
1063 tri_short_pulse = (radar_rpt_reg_value & BIT(20)) ? 1 : 0;
1064 tri_long_pulse = (radar_rpt_reg_value & BIT(28)) ? 1 : 0;
1065 } else {
1066 tri_short_pulse = (regf98_value & BIT(17)) ? 1 : 0;
1067 tri_long_pulse = (regf98_value & BIT(19)) ? 1 : 0;
1068 }
1069
1070 if (tri_long_pulse){
1071 PHYDM_DBG(dm, DBG_DFS, "\n");
1072 PHYDM_DBG(dm, DBG_DFS, "tri_long_pulse = %d\n", tri_long_pulse);
1073 dfs->pulse_flag_hist[dfs->mask_idx] = 1;
1074 dfs->pulse_type_hist[dfs->mask_idx] = 1;
1075 }
1076
1077 else if (tri_short_pulse){
1078 PHYDM_DBG(dm, DBG_DFS, "\n");
1079 PHYDM_DBG(dm, DBG_DFS, "tri_short_pulse = %d\n", tri_short_pulse);
1080 dfs->pulse_flag_hist[dfs->mask_idx] = 1;
1081 dfs->pulse_type_hist[dfs->mask_idx] = 0;
1082 }
1083
1084 else{
1085 dfs->pulse_flag_hist[dfs->mask_idx] = 0;
1086 dfs->pulse_type_hist[dfs->mask_idx] = 0;
1087 }
1088
1089
1090
1091 if (tri_short_pulse) {
1092 if (!(dm->support_ic_type & ODM_IC_JGR3_SERIES))
1093 phydm_radar_detect_reset(dm);
1094 }
1095 if (tri_long_pulse) {
1096 /*
1097 if (!(dm->support_ic_type & ODM_IC_JGR3_SERIES))
1098 phydm_radar_detect_reset(dm);
1099 */
1100 if (region_domain == PHYDM_DFS_DOMAIN_MKK) {
1101 if (c_channel >= 52 && c_channel <= 64) {
1102 tri_long_pulse = 0;
1103 }
1104 }
1105 if (region_domain == PHYDM_DFS_DOMAIN_ETSI) {
1106 tri_long_pulse = 0;
1107 }
1108 }
1109
1110 st_l2h_new = dfs->st_l2h_cur;
1111 #if (RTL8723F_SUPPORT||RTL8822C_SUPPORT)
1112 if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
1113 if (dfs->pulse_type_hist[dfs->mask_idx])
1114 dfs->radar_type = 1;
1115 else
1116 dfs->radar_type = 0;
1117
1118 if (dfs->pulse_flag_hist[dfs->mask_idx]) {
1119 if (dfs->det_jar3_en)
1120 phydm_dfs_rpt_distinguish(dm);
1121 phydm_radar_detect_reset(dm);
1122 }
1123 }
1124 #endif
1125
1126 /* PSD(not ready) */
1127
1128 fault_flag_det = 0;
1129 fault_flag_psd = 0;
1130 fa_flag = 0;
1131 if (region_domain == PHYDM_DFS_DOMAIN_ETSI) {
1132 fa_mask_th = dfs->fa_mask_th + 20;
1133 } else {
1134 fa_mask_th = dfs->fa_mask_th;
1135 }
1136 if (total_fa_in_hist >= fa_mask_th || dfs->igi_cur >= 0x30) {
1137 /* st_l2h_new = dfs->st_l2h_max; */
1138 dfs->radar_det_mask_hist[index] = 1;
1139 if (dfs->pulse_flag_hist[index] == 1) {
1140 dfs->pulse_flag_hist[index] = 0;
1141 if (dfs->det_print2) {
1142 PHYDM_DBG(dm, DBG_DFS,
1143 "Radar is masked : FA mask\n");
1144 }
1145 }
1146 fa_flag = 1;
1147 } else {
1148 dfs->radar_det_mask_hist[index] = 0;
1149 }
1150
1151 if (dfs->det_print) {
1152 PHYDM_DBG(dm, DBG_DFS, "mask_idx: %d\n", dfs->mask_idx);
1153 PHYDM_DBG(dm, DBG_DFS, "radar_det_mask_hist: ");
1154 for (i = 0; i < 5; i++)
1155 PHYDM_DBG(dm, DBG_DFS, "%d ",
1156 dfs->radar_det_mask_hist[i]);
1157 PHYDM_DBG(dm, DBG_DFS, "pulse_flag_hist: ");
1158 for (i = 0; i < 5; i++)
1159 PHYDM_DBG(dm, DBG_DFS, "%d ", dfs->pulse_flag_hist[i]);
1160 PHYDM_DBG(dm, DBG_DFS, "fa_inc_hist: ");
1161 for (i = 0; i < 5; i++)
1162 PHYDM_DBG(dm, DBG_DFS, "%d ", dfs->fa_inc_hist[i]);
1163 PHYDM_DBG(dm, DBG_DFS,
1164 "\nfa_mask_th: %d, total_fa_in_hist: %d ",
1165 fa_mask_th, total_fa_in_hist);
1166 }
1167
1168 sum = 0;
1169 for (k = 0; k < 5; k++) {
1170 if (dfs->radar_det_mask_hist[k] == 1)
1171 sum++;
1172 }
1173
1174 if (dfs->mask_hist_checked <= 5)
1175 dfs->mask_hist_checked++;
1176
1177 if (dfs->mask_hist_checked >= 5 && dfs->pulse_flag_hist[dfs->mask_idx]) {
1178 if (sum <= 2) {
1179 if (dfs->hist_cond_on) {
1180 /*return the value from hist_radar_detected*/
1181 radar_detected = phydm_dfs_hist_log(dm, index);
1182 } else if (dfs->det_jar3_en) {
1183 if (dfs->nhm_dfs_flag || dfs->b_flag) {
1184 radar_detected = false;
1185 } else if (dfs->pw_flag && dfs->pri_flag &&
1186 dfs->loct_flag) {
1187 PHYDM_DBG(dm, DBG_DFS, "Detected type %d radar signal!\n",
1188 dfs->radar_type);
1189 radar_detected = true;
1190 }
1191 } else {
1192 if (dfs->pulse_type_hist[dfs->mask_idx] == 0)
1193 dfs->radar_type = 0;
1194 else if (dfs->pulse_type_hist[dfs->mask_idx] == 1)
1195 dfs->radar_type = 1;
1196 radar_detected = true;
1197 PHYDM_DBG(dm, DBG_DFS,
1198 "Detected type %d radar signal!\n",
1199 dfs->radar_type);
1200 }
1201 } else {
1202 fault_flag_det = 1;
1203 if (dfs->det_print2) {
1204 PHYDM_DBG(dm, DBG_DFS,
1205 "Radar is masked : mask_hist large than thd\n");
1206 }
1207 }
1208 }
1209
1210 dfs->mask_idx++;
1211 if (dfs->mask_idx == 5)
1212 dfs->mask_idx = 0;
1213
1214 if (fault_flag_det == 0 && fault_flag_psd == 0 && fa_flag == 0) {
1215 if (dfs->igi_cur < 0x30) {
1216 st_l2h_new = dfs->st_l2h_min;
1217 }
1218 }
1219
1220 if (st_l2h_new != dfs->st_l2h_cur) {
1221 if (st_l2h_new < dfs->st_l2h_min) {
1222 dfs->st_l2h_cur = dfs->st_l2h_min;
1223 } else if (st_l2h_new > dfs->st_l2h_max)
1224 dfs->st_l2h_cur = dfs->st_l2h_max;
1225 else
1226 dfs->st_l2h_cur = st_l2h_new;
1227 /*odm_set_bb_reg(dm, R_0x91c, 0xff, dfs->st_l2h_cur);*/
1228
1229 dfs->pwdb_th_cur = ((int)dfs->st_l2h_cur - (int)dfs->igi_cur)
1230 / 2 + dfs->pwdb_scalar_factor;
1231
1232 /*@limit the pwdb value to absolute lower bound 8*/
1233 dfs->pwdb_th_cur = MAX_2(dfs->pwdb_th_cur, (int)dfs->pwdb_th);
1234
1235 /*@limit the pwdb value to absolute upper bound 0x1f*/
1236 dfs->pwdb_th_cur = MIN_2(dfs->pwdb_th_cur, 0x1f);
1237
1238 if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
1239 odm_set_bb_reg(dm, R_0xa50, 0x000000f0,
1240 dfs->pwdb_th_cur);
1241 #if (RTL8721D_SUPPORT)
1242 else if (dm->support_ic_type & ODM_RTL8721D) {
1243 odm_set_bb_reg(dm, R_0xf54, 0x0000001f,
1244 ((dfs->st_l2h_cur & 0x0000007c) >> 2));
1245 odm_set_bb_reg(dm, R_0xf58, 0xc0000000,
1246 (dfs->st_l2h_cur & 0x00000003));
1247 odm_set_bb_reg(dm, R_0xf70, 0x03c00000,
1248 dfs->pwdb_th_cur);
1249 }
1250 #endif
1251 else
1252 odm_set_bb_reg(dm, R_0x918, 0x00001f00,
1253 dfs->pwdb_th_cur);
1254 }
1255
1256 if (dfs->det_print) {
1257 PHYDM_DBG(dm, DBG_DFS,
1258 "fault_flag_det[%d], fault_flag_psd[%d], DFS_detected [%d]\n",
1259 fault_flag_det, fault_flag_psd, radar_detected);
1260 }
1261 #if (RTL8721D_SUPPORT)
1262 if (dm->support_ic_type & (ODM_RTL8721D))
1263 odm_set_bb_reg(dm, R_0x908, MASKDWORD, reg908_value);
1264 #endif
1265
1266 return radar_detected;
1267 }
1268 #if (RTL8723F_SUPPORT || RTL8822C_SUPPORT)
phydm_dfs_rpt_distinguish(void * dm_void)1269 void phydm_dfs_rpt_distinguish(void *dm_void)
1270 {
1271 struct dm_struct *dm = (struct dm_struct *)dm_void;
1272 struct _DFS_STATISTICS *dfs = &dm->dfs;
1273 struct ccx_info *ccx = &dm->dm_ccx_info;
1274
1275 u8 region_domain = dm->dfs_region_domain;
1276 u8 c_channel = *dm->channel;
1277 u8 band_width = *dm->band_width;
1278
1279 u32 reg_2e08, reg_2e24, reg_2e28, reg_2e2c, reg_2e30, reg_2e34;
1280 u32 reg_2e0c, reg_2e10, reg_2e20;
1281 u16 pw_rpt_set[12] = {0}, pri_rpt_set[12] = {0};
1282 s8 loct_rpt_set[12] = {0};
1283 u8 pw_lth[10] = {255,255,255,255,255,255,255,255,255,255};
1284 u16 pw_uth[10] = {255,255,255,255,255,255,255,255,255,255};
1285 u8 pri_lth[10] = {255,255,255,255,255,255,255,255,255,255};
1286 u8 pri_uth[10] = {255,255,255,255,255,255,255,255,255,255};
1287 u8 pri_vd_max = 0, pri_vd_min = 255, rdr_tmp = 0;
1288 u8 i, j, dc_cnt = 0, rdr_num = 0, rdr_cnt[10] = {0};
1289 u8 short_cnt_th, long_cnt_th, loop_cnt, cnt_th, loct_diff = 0;
1290 u8 pri_var_up, pri_var_low, pri_cnt_tmp, pri_cnt_fnl = 0;
1291 u8 pri_cnt_th = dfs->pri_cnt_th;
1292
1293 /* PW : Wordlength : U(8,0) , unit: 400ns */
1294 reg_2e08 = odm_get_bb_reg(dm, 0x2e08, 0xffffffff);
1295 pw_rpt_set[0]=(unsigned int)(reg_2e08 & 0x000000ff);
1296 pw_rpt_set[1]=(unsigned int)((reg_2e08 & 0x0000ff00)>>8);
1297 pw_rpt_set[2]=(unsigned int)((reg_2e08 & 0x00ff0000)>>16);
1298 pw_rpt_set[3]=(unsigned int)((reg_2e08 & 0xff000000)>>24);
1299 reg_2e24 = odm_get_bb_reg(dm, 0x2e24, 0xffffffff);
1300 pw_rpt_set[4]=(unsigned int)(reg_2e24 & 0x000000ff);
1301 pw_rpt_set[5]=(unsigned int)((reg_2e24 & 0x0000ff00)>>8);
1302 pw_rpt_set[6]=(unsigned int)((reg_2e24 & 0x00ff0000)>>16);
1303 pw_rpt_set[7]=(unsigned int)((reg_2e24 & 0xff000000)>>24);
1304 reg_2e28 = odm_get_bb_reg(dm, 0x2e28, 0xffffffff);
1305 pw_rpt_set[8]=(unsigned int)(reg_2e28 & 0x000000ff);
1306 pw_rpt_set[9]=(unsigned int)((reg_2e28 & 0x0000ff00)>>8);
1307 pw_rpt_set[10]=(unsigned int)((reg_2e28 & 0x00ff0000)>>16);
1308 pw_rpt_set[11]=(unsigned int)((reg_2e28 & 0xff000000)>>24);
1309
1310 /* PRI : Wordlength : U(8,0) , unit: 25.6us */
1311 reg_2e2c = odm_get_bb_reg(dm, 0x2e2c, 0xffffffff);
1312 pri_rpt_set[0]=(unsigned int)(reg_2e2c & 0x000000ff);
1313 pri_rpt_set[1]=(unsigned int)((reg_2e2c & 0x0000ff00)>>8);
1314 pri_rpt_set[2]=(unsigned int)((reg_2e2c & 0x00ff0000)>>16);
1315 pri_rpt_set[3]=(unsigned int)((reg_2e2c & 0xff000000)>>24);
1316 reg_2e30 = odm_get_bb_reg(dm, 0x2e30, 0xffffffff);
1317 pri_rpt_set[4]=(unsigned int)(reg_2e30 & 0x000000ff);
1318 pri_rpt_set[5]=(unsigned int)((reg_2e30 & 0x0000ff00)>>8);
1319 pri_rpt_set[6]=(unsigned int)((reg_2e30 & 0x00ff0000)>>16);
1320 pri_rpt_set[7]=(unsigned int)((reg_2e30 & 0xff000000)>>24);
1321 reg_2e34 = odm_get_bb_reg(dm, 0x2e34, 0xffffffff);
1322 pri_rpt_set[8]=(unsigned int)(reg_2e34 & 0x000000ff);
1323 pri_rpt_set[9]=(unsigned int)((reg_2e34 & 0x0000ff00)>>8);
1324 pri_rpt_set[10]=(unsigned int)((reg_2e34 & 0x00ff0000)>>16);
1325 pri_rpt_set[11]=(unsigned int)((reg_2e34 & 0xff000000)>>24);
1326
1327 /* Location : Wordlength : S(8,0) , unit: MHz */
1328 reg_2e0c = odm_get_bb_reg(dm, 0x2e0c, 0xffffffff);
1329 loct_rpt_set[0]=(signed char)(reg_2e0c & 0x000000ff);
1330 loct_rpt_set[1]=(signed char)((reg_2e0c & 0x0000ff00)>>8);
1331 loct_rpt_set[2]=(signed char)((reg_2e0c & 0x00ff0000)>>16);
1332 loct_rpt_set[3]=(signed char)((reg_2e0c & 0xff000000)>>24);
1333 reg_2e10 = odm_get_bb_reg(dm, 0x2e10, 0xffffffff);
1334 loct_rpt_set[4]=(signed char)(reg_2e10 & 0x000000ff);
1335 loct_rpt_set[5]=(signed char)((reg_2e10 & 0x0000ff00)>>8);
1336 loct_rpt_set[6]=(signed char)((reg_2e10 & 0x00ff0000)>>16);
1337 loct_rpt_set[7]=(signed char)((reg_2e10 & 0xff000000)>>24);
1338 reg_2e20 = odm_get_bb_reg(dm, 0x2e20, 0xffffffff);
1339 loct_rpt_set[8]=(signed char)(reg_2e20 & 0x000000ff);
1340 loct_rpt_set[9]=(signed char)((reg_2e20 & 0x0000ff00)>>8);
1341 loct_rpt_set[10]=(signed char)((reg_2e20 & 0x00ff0000)>>16);
1342 loct_rpt_set[11]=(signed char)((reg_2e20 & 0xff000000)>>24);
1343
1344 dfs->pw_flag = false;
1345 dfs->loct_flag = false;
1346 dfs->pri_flag = false;
1347 for (i = 0; i < 12; i++) {
1348 dfs->pw_rslt[i] = 0;
1349 dfs->loct_rslt[i] = 0;
1350 dfs->pri_rslt[i] = 0;
1351 }
1352
1353 // for NHMxDFS //
1354 dfs->nhm_dfs_cnt = 0;
1355 dfs->nhm_dfs_flag = false;
1356 dfs->b_flag = false;
1357
1358 short_cnt_th = odm_get_bb_reg(dm, 0xa50, 0x00f00000);
1359 long_cnt_th = odm_get_bb_reg(dm, 0xa4c, 0xf0000000);
1360
1361 if (dfs->radar_type)
1362 loop_cnt = long_cnt_th + 2;
1363 else
1364 loop_cnt = short_cnt_th + 2;
1365
1366 if (region_domain == PHYDM_DFS_DOMAIN_ETSI)
1367 loop_cnt = short_cnt_th + 2;
1368
1369 if (loop_cnt > 12)
1370 loop_cnt = 12;
1371
1372 cnt_th = loop_cnt / 2;
1373
1374 /* Calculate the difference between each element (1st Not calculated) */
1375 for(i = 0; i < loop_cnt; i++)
1376 dfs->loct_rslt[i] = loct_rpt_set[i];
1377 for(i = 1; i < loop_cnt; i++)
1378 loct_diff = loct_diff + abs(dfs->loct_rslt[i] - dfs->loct_rslt[i-1]);
1379
1380 for (i = 0; i < loop_cnt; i++) {
1381 if ((-2 < loct_rpt_set[i]) && (loct_rpt_set[i] < 2))
1382 dc_cnt++;
1383 }
1384
1385 if (region_domain == PHYDM_DFS_DOMAIN_FCC){
1386 rdr_num = 7;
1387
1388 pw_lth[0]=2;
1389 pw_lth[1]=2;
1390 pw_lth[2]=2;
1391 pw_lth[3]=12;
1392 pw_lth[4]=22;
1393 pw_lth[5]=120;
1394 pw_lth[6]=2;
1395
1396 pw_uth[0]=3;
1397 pw_uth[1]=3;
1398 pw_uth[2]=15;
1399 pw_uth[3]=30;
1400 pw_uth[4]=60;
1401 pw_uth[5]=253;
1402 pw_uth[6]=3;
1403
1404 pri_lth[0]=50;
1405 pri_lth[1]=18;
1406 pri_lth[2]=5;
1407 pri_lth[3]=7;
1408 pri_lth[4]=7;
1409 pri_lth[5]=38;
1410 pri_lth[6]=11;
1411
1412 pri_uth[0]=62;
1413 pri_uth[1]=130;
1414 pri_uth[2]=10;
1415 pri_uth[3]=21;
1416 pri_uth[4]=21;
1417 pri_uth[5]=80;
1418 pri_uth[6]=15;
1419 if (dc_cnt > dfs->dc_cnt_th){
1420 pw_lth[0] = 0;
1421 pw_lth[1] = 0;
1422 pw_lth[2] = 0;
1423 pw_lth[3] = 0;
1424 pw_lth[4] = 0;
1425 pw_lth[5] = 80;
1426 pw_lth[6] = 0;
1427 }
1428 }
1429 else if (region_domain == PHYDM_DFS_DOMAIN_MKK){
1430 rdr_num = 8;
1431 if (c_channel >= 52 && c_channel <= 64){
1432 dfs->loct_diff_th = dfs->loct_diff_th + 15;
1433 pw_lth[0]=1;
1434 pw_lth[1]=1;
1435 pw_lth[2]=1;
1436 pw_lth[3]=1;
1437 pw_lth[4]=1;
1438 pw_lth[5]=1;
1439 pw_lth[6]=1;
1440 pw_lth[7]=1;
1441
1442 pw_uth[0]=14;
1443 pw_uth[1]=40;
1444 pw_uth[2]=14;
1445 pw_uth[3]=40;
1446 pw_uth[4]=5;
1447 pw_uth[5]=5;
1448 pw_uth[6]=5;
1449 pw_uth[7]=5;
1450
1451 pri_lth[0]=35;
1452 pri_lth[1]=20;
1453 pri_lth[2]=35;
1454 pri_lth[3]=18;
1455 pri_lth[4]=32;
1456 pri_lth[5]=38;
1457 pri_lth[6]=40;
1458 pri_lth[7]=48;
1459
1460 pri_uth[0]=200;
1461 pri_uth[1]=200;
1462 pri_uth[2]=200;
1463 pri_uth[3]=200;
1464 pri_uth[4]=38;
1465 pri_uth[5]=44;
1466 pri_uth[6]=48;
1467 pri_uth[7]=55;
1468 if (dc_cnt > dfs->dc_cnt_th){
1469 pw_lth[0] = 0;
1470 pw_lth[1] = 0;
1471 pw_lth[2] = 0;
1472 pw_lth[3] = 0;
1473 pw_lth[4] = 0;
1474 pw_lth[5] = 0;
1475 pw_lth[6] = 0;
1476 pw_lth[7] = 0;
1477 cnt_th--;
1478 }
1479 }
1480 else{
1481 pw_lth[0]=1;
1482 pw_lth[1]=2;
1483 pw_lth[2]=4;
1484 pw_lth[3]=2;
1485 pw_lth[4]=12;
1486 pw_lth[5]=22;
1487 pw_lth[6]=100;
1488 pw_lth[7]=2;
1489
1490 pw_uth[0]=2;
1491 pw_uth[1]=3;
1492 pw_uth[2]=6;
1493 pw_uth[3]=15;
1494 pw_uth[4]=30;
1495 pw_uth[5]=60;
1496 pw_uth[6]=300;
1497 pw_uth[7]=3;
1498
1499 pri_lth[0]=33;
1500 pri_lth[1]=35;
1501 pri_lth[2]=130;
1502 pri_lth[3]=5;
1503 pri_lth[4]=7;
1504 pri_lth[5]=7;
1505 pri_lth[6]=35;
1506 pri_lth[7]=11;
1507
1508 pri_uth[0]=73;
1509 pri_uth[1]=75;
1510 pri_uth[2]=170;
1511 pri_uth[3]=10;
1512 pri_uth[4]=22;
1513 pri_uth[5]=22;
1514 pri_uth[6]=86;
1515 pri_uth[7]=15;
1516 if (dc_cnt > dfs->dc_cnt_th){
1517 pw_lth[0] = 0;
1518 pw_lth[1] = 0;
1519 pw_lth[2] = 0;
1520 pw_lth[3] = 0;
1521 pw_lth[4] = 0;
1522 pw_lth[5] = 0;
1523 pw_lth[6] = 80;
1524 pw_lth[7] = 0;
1525 }
1526 }
1527 }
1528 else if (region_domain == PHYDM_DFS_DOMAIN_ETSI){
1529 rdr_num = 6;
1530 pw_lth[0]=1;
1531 pw_lth[1]=1;
1532 pw_lth[2]=1;
1533 pw_lth[3]=40;
1534 pw_lth[4]=1;
1535 pw_lth[5]=1;
1536
1537 pw_uth[0]=15;
1538 pw_uth[1]=45;
1539 pw_uth[2]=45;
1540 pw_uth[3]=90;
1541 pw_uth[4]=6;
1542 pw_uth[5]=6;
1543
1544 pri_lth[0]=35;
1545 pri_lth[1]=21;
1546 pri_lth[2]=8;
1547 pri_lth[3]=8;
1548 pri_lth[4]=87;
1549 pri_lth[5]=29;
1550
1551 pri_uth[0]=215;
1552 pri_uth[1]=215;
1553 pri_uth[2]=19;
1554 pri_uth[3]=22;
1555 pri_uth[4]=144;
1556 pri_uth[5]=108;
1557 if (dc_cnt > dfs->dc_cnt_th){
1558 pw_lth[0] = 0;
1559 pw_lth[1] = 0;
1560 pw_lth[2] = 0;
1561 pw_lth[3] = 0;
1562 pw_lth[4] = 0;
1563 pw_lth[5] = 0;
1564 }
1565 }
1566
1567 for (i = 0; i < loop_cnt; i++) {
1568 dfs->pw_rslt[i] = pw_rpt_set[i];
1569 dfs->pri_rslt[i] = pri_rpt_set[i];
1570 for (j = 0; j < rdr_num; j++) {
1571 if (dfs->radar_type) {
1572 if ((pw_lth[j] <= dfs->pw_rslt[i]) && (dfs->pw_rslt[i] <= pw_uth[j]))
1573 rdr_cnt[j]++;
1574 } else {
1575 if ((pw_lth[j] <= dfs->pw_rslt[i]) && (dfs->pw_rslt[i] <= pw_uth[j]) &&
1576 (pri_lth[j] <= dfs->pri_rslt[i]) && (dfs->pri_rslt[i] <= pri_uth[j])) {
1577 rdr_cnt[j]++;
1578 if (dfs->pri_rslt[i] > pri_vd_max)
1579 pri_vd_max = dfs->pri_rslt[i];
1580 if (dfs->pri_rslt[i] < pri_vd_min)
1581 pri_vd_min = dfs->pri_rslt[i];
1582 }
1583 }
1584 }
1585 }
1586
1587 /* Pattern Judgement */
1588 for (i = 0; i < rdr_num; i++){
1589 if (rdr_cnt[i] >= cnt_th){
1590 dfs->pw_flag = true;
1591 rdr_tmp = i;
1592 }
1593 }
1594
1595 /* Add NHM to decide the validity of the three flags */
1596 /* Use for chaotic open space */
1597 if (dfs->nhm_dfs_en) {
1598 for (i = 0; i <= (NHM_RPT_NUM - 1); i++) {
1599 if (ccx->nhm_result[i] > 0)
1600 break;
1601 }
1602 for (j = (i + 1); j <= (NHM_RPT_NUM - 1); j++) {
1603 if (ccx->nhm_result[j] > 0)
1604 dfs->nhm_dfs_cnt++;
1605 }
1606 if (dfs->nhm_dfs_cnt > dfs->nhm_cnt_th) {
1607 dfs->nhm_dfs_flag = true;
1608 cnt_th = loop_cnt;
1609 }
1610 }
1611 if (dm->support_ability & ODM_BB_ENV_MONITOR) {
1612 if ((100-((ccx->nhm_rpt_sum * 100) >> 8)) >= dfs->nhm_dty_th) {
1613 dfs->b_flag = true;
1614 cnt_th = loop_cnt;
1615 }
1616 }
1617
1618 /* Relax */
1619 if (!(dfs->idle_mode)) {
1620 pri_cnt_th--;
1621 if (!(region_domain == PHYDM_DFS_DOMAIN_ETSI)){
1622 dfs->pri_var_offset = 15;
1623 if (region_domain == PHYDM_DFS_DOMAIN_MKK)
1624 dfs->pri_var_offset = 5 + 10*pri_vd_min/20;
1625 }
1626 else
1627 dfs->pri_var_offset = dfs->pri_var_tp_offset;
1628 }
1629
1630 // Mode approximation for PRI
1631 for (i = 0; i < (loop_cnt - 1); i++) {
1632 pri_cnt_tmp = 0;
1633 for (j = 0; j < (loop_cnt - 1); j++) {
1634 if ((i == j) || (dfs->pri_rslt[i] <= 4))
1635 continue;
1636 if (dfs->pri_rslt[j] > (255 - dfs->pri_var_offset))
1637 pri_var_up = 255;
1638 else
1639 pri_var_up = dfs->pri_rslt[j] + dfs->pri_var_offset;
1640 if (dfs->pri_var_offset >= dfs->pri_rslt[j])
1641 pri_var_low = 0;
1642 else
1643 pri_var_low = dfs->pri_rslt[j] - dfs->pri_var_offset;
1644 if ((dfs->pri_rslt[i] <= pri_var_up) && (dfs->pri_rslt[i] >= pri_var_low) &&
1645 (dfs->pri_rslt[i] <= pri_vd_max) && (dfs->pri_rslt[i] >= pri_vd_min))
1646 pri_cnt_tmp++;
1647 }
1648 if (pri_cnt_tmp > pri_cnt_fnl)
1649 pri_cnt_fnl = pri_cnt_tmp;
1650 }
1651
1652 // Advanced PRI Judgement (Bypass for long pulse flag)
1653 if (pri_cnt_fnl != 0)
1654 pri_cnt_fnl++;
1655
1656 /* PRI */
1657 if (dfs->radar_type)
1658 dfs->pri_flag= true;
1659 else if (pri_cnt_fnl >= pri_cnt_th)
1660 dfs->pri_flag= true;
1661 /* For the case of SRTC */
1662 else if ((dfs->pri_rslt[0] == 0) && (dfs->pri_rslt[1] > 0) &&
1663 (dfs->pri_rslt[2] == 0) && (dfs->pri_rslt[3] > 0))
1664 dfs->pri_flag= true;
1665 else if ((dfs->pri_rslt[0] > 0) && (dfs->pri_rslt[1] == 0) &&
1666 (dfs->pri_rslt[2] > 0) && (dfs->pri_rslt[3] == 0))
1667 dfs->pri_flag= true;
1668 else if (!(dfs->pri_flag_en))
1669 dfs->pri_flag= true;
1670
1671 if (region_domain == PHYDM_DFS_DOMAIN_MKK){
1672 if (c_channel >= 52 && c_channel <= 64){
1673 if (!(dfs->idle_mode))
1674 dfs->pri_flag= true; // MKK, 52<=ch<=64 , TP mode
1675 }
1676 }
1677
1678 /* PW */
1679 if (!(dfs->pw_flag_en))
1680 dfs->pw_flag = true;
1681
1682 /* LOCT */
1683 if (!(dfs->idle_mode))
1684 dfs->loct_diff_th = dfs->loct_diff_th + 15;
1685 if (loct_diff <= dfs->loct_diff_th)
1686 dfs->loct_flag = true;
1687 else if (dfs->radar_type)
1688 dfs->loct_flag = true;
1689 else if (!(dfs->loct_flag_en))
1690 dfs->loct_flag = true;
1691
1692 if (dfs->det_print_jar3) {
1693 if (dfs->nhm_dfs_flag || dfs->b_flag)
1694 PHYDM_DBG(dm, DBG_DFS, "Anti-FRD Rdr Drop\n");
1695 if (!(dfs->pw_flag_en) || !(dfs->loct_flag_en) || !(dfs->pri_flag_en))
1696 PHYDM_DBG(dm, DBG_DFS, "Byps flag scenario\n");
1697 if (dc_cnt > dfs->dc_cnt_th)
1698 PHYDM_DBG(dm, DBG_DFS, "Radar is near DC\n");
1699 if (!(dfs->pw_flag))
1700 PHYDM_DBG(dm, DBG_DFS, "- PW/PRI-J Failure\n");
1701 if (!(dfs->loct_flag))
1702 PHYDM_DBG(dm, DBG_DFS, "- Loct-J Failure\n");
1703 if (!(dfs->pri_flag))
1704 PHYDM_DBG(dm, DBG_DFS, "- Adv-PRI-J Failure\n");
1705 if (!(dfs->pw_flag) || !(dfs->pri_flag) || !(dfs->loct_flag))
1706 PHYDM_DBG(dm, DBG_DFS, "Suspected radar result is dropped by SW mechanism !!\n");
1707
1708 PHYDM_DBG(dm, DBG_DFS, "\n");
1709 PHYDM_DBG(dm, DBG_DFS, "The current information: ([Lower bound / Upper bound])\n");
1710 PHYDM_DBG(dm, DBG_DFS, "pw_th1 : [%d, %d], pw_th2 : [%d, %d], pw_th3 : [%d, %d]\n",
1711 pw_lth[0], pw_uth[0], pw_lth[1], pw_uth[1],
1712 pw_lth[2], pw_uth[2]);
1713 PHYDM_DBG(dm, DBG_DFS, "pw_th4 : [%d, %d], pw_th5 : [%d, %d], pw_th6 : [%d, %d] \n",
1714 pw_lth[3], pw_uth[3], pw_lth[4],
1715 pw_uth[4], pw_lth[5], pw_uth[5]);
1716 PHYDM_DBG(dm, DBG_DFS, "pw_th7 : [%d, %d], pw_th8 : [%d, %d]\n",
1717 pw_lth[6], pw_uth[6], pw_lth[7], pw_uth[7]);
1718 PHYDM_DBG(dm, DBG_DFS, "pri_th1 : [%d, %d], pri_th2 : [%d, %d], pri_th3 : [%d, %d]\n",
1719 pri_lth[0], pri_uth[0], pri_lth[1], pri_uth[1],
1720 pri_lth[2], pri_uth[2]);
1721 PHYDM_DBG(dm, DBG_DFS, "pri_th4 : [%d, %d], pri_th5 : [%d, %d], pri_th6 : [%d, %d]\n",
1722 pri_lth[3], pri_uth[3], pri_lth[4], pri_uth[4],
1723 pri_lth[5], pri_uth[5]);
1724 PHYDM_DBG(dm, DBG_DFS, "pri_th7 : [%d, %d], pri_th8 : [%d, %d]\n",
1725 pri_lth[6], pri_uth[6], pri_lth[7], pri_uth[7]);
1726
1727 if (!(dfs->idle_mode))
1728 PHYDM_DBG(dm, DBG_DFS, "loct_diff_th = [%d](Relax for TP mode)\n",
1729 dfs->loct_diff_th);
1730 else
1731 PHYDM_DBG(dm, DBG_DFS, "loct_diff_th = [%d](Idle mode)\n",
1732 dfs->loct_diff_th);
1733
1734 if (!(dfs->idle_mode)) {
1735 PHYDM_DBG(dm, DBG_DFS, "pri_var_offset = [%d] (Relax for TP mode)\n",
1736 dfs->pri_var_offset);
1737 PHYDM_DBG(dm, DBG_DFS, "pri_cnt_th = [%d] (Relax for TP mode)\n",
1738 pri_cnt_th);
1739 } else {
1740 PHYDM_DBG(dm, DBG_DFS, "pri_var_offset = [%d] (Idle mode)\n",
1741 dfs->pri_var_offset);
1742 PHYDM_DBG(dm, DBG_DFS, "pri_cnt_th = [%d] (Idle mode)\n",
1743 pri_cnt_th);
1744 }
1745
1746 PHYDM_DBG(dm, DBG_DFS, "\n");
1747 PHYDM_DBG(dm, DBG_DFS, "loop_cnt = [%d]\n", loop_cnt);
1748 if (dfs->nhm_dfs_flag) {
1749 PHYDM_DBG(dm, DBG_DFS, "Nmode cnt = %d!\n",
1750 dfs->nhm_dfs_cnt);
1751 }
1752 else if (dfs->b_flag) {
1753 PHYDM_DBG(dm, DBG_DFS, "Bmode DTY = %d\n",
1754 (100-((ccx->nhm_rpt_sum * 100) >> 8)));
1755 }
1756 else {
1757 PHYDM_DBG(dm, DBG_DFS, "cnt_th = [%d] (Default : Half of loop cnt)\n",
1758 cnt_th);
1759 PHYDM_DBG(dm, DBG_DFS, "Bmode DTY = %d\n",
1760 (100-((ccx->nhm_rpt_sum * 100) >> 8)));
1761 }
1762
1763 PHYDM_DBG(dm, DBG_DFS, "\n");
1764 PHYDM_DBG(dm, DBG_DFS, "The current report:\n");
1765 PHYDM_DBG(dm, DBG_DFS, "pw_rpt(1-12) = [%d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d]\n",
1766 pw_rpt_set[0], pw_rpt_set[1], pw_rpt_set[2],
1767 pw_rpt_set[3], pw_rpt_set[4], pw_rpt_set[5],
1768 pw_rpt_set[6], pw_rpt_set[7], pw_rpt_set[8],
1769 pw_rpt_set[9], pw_rpt_set[10], pw_rpt_set[11]);
1770 PHYDM_DBG(dm, DBG_DFS, "loct_rpt(1-12) = [%d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d]\n",
1771 loct_rpt_set[0], loct_rpt_set[1],
1772 loct_rpt_set[2], loct_rpt_set[3],
1773 loct_rpt_set[4], loct_rpt_set[5],
1774 loct_rpt_set[6], loct_rpt_set[7],
1775 loct_rpt_set[8], loct_rpt_set[9],
1776 loct_rpt_set[10], loct_rpt_set[11]);
1777 PHYDM_DBG(dm, DBG_DFS, "pri_rpt(1-12) = [%d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d]\n",
1778 pri_rpt_set[0], pri_rpt_set[1],
1779 pri_rpt_set[2], pri_rpt_set[3],
1780 pri_rpt_set[4], pri_rpt_set[5],
1781 pri_rpt_set[6], pri_rpt_set[7],
1782 pri_rpt_set[8], pri_rpt_set[9],
1783 pri_rpt_set[10], pri_rpt_set[11]);
1784
1785 PHYDM_DBG(dm, DBG_DFS, "\n");
1786 PHYDM_DBG(dm, DBG_DFS, "dc_cnt = [%d]\n", dc_cnt);
1787 PHYDM_DBG(dm, DBG_DFS, "loct_diff = [%d]\n", loct_diff);
1788
1789 if (pri_vd_max == 0 && pri_vd_min == 255)
1790 PHYDM_DBG(dm, DBG_DFS, "No vaild pri_max and pri_min");
1791 else
1792 PHYDM_DBG(dm, DBG_DFS, "pri_vaild_max = %d, pri_vaild_min = %d\n",
1793 pri_vd_max, pri_vd_min);
1794 PHYDM_DBG(dm, DBG_DFS, "advanced_pri_cnt = %d\n",
1795 pri_cnt_fnl);
1796
1797 PHYDM_DBG(dm, DBG_DFS, "radar_class_cnt[1-8] = [%d, %d, %d, %d, %d, %d, %d, %d]\n",
1798 rdr_cnt[0], rdr_cnt[1], rdr_cnt[2], rdr_cnt[3],
1799 rdr_cnt[4], rdr_cnt[5], rdr_cnt[6], rdr_cnt[7]);
1800 }
1801 }
1802 #endif
1803
1804 #if (RTL8814A_SUPPORT || RTL8822B_SUPPORT || RTL8821C_SUPPORT)
phydm_dfs_histogram_radar_distinguish(void * dm_void)1805 void phydm_dfs_histogram_radar_distinguish(
1806 void *dm_void)
1807 {
1808 struct dm_struct *dm = (struct dm_struct *)dm_void;
1809 struct _DFS_STATISTICS *dfs = &dm->dfs;
1810 u8 region_domain = dm->dfs_region_domain;
1811 u8 c_channel = *dm->channel;
1812 u8 band_width = *dm->band_width;
1813
1814 u8 dfs_pw_thd1 = 0, dfs_pw_thd2 = 0, dfs_pw_thd3 = 0;
1815 u8 dfs_pw_thd4 = 0, dfs_pw_thd5 = 0;
1816 u8 dfs_pri_thd1 = 0, dfs_pri_thd2 = 0, dfs_pri_thd3 = 0;
1817 u8 dfs_pri_thd4 = 0, dfs_pri_thd5 = 0;
1818 u8 pri_th = 0, i = 0;
1819 u8 max_pri_idx = 0, max_pw_idx = 0, max_pri_cnt_th = 0;
1820 u8 max_pri_cnt_fcc_g1_th = 0, max_pri_cnt_fcc_g3_th = 0;
1821 u8 safe_pri_pw_diff_th = 0, safe_pri_pw_diff_fcc_th = 0;
1822 u8 safe_pri_pw_diff_w53_th = 0, safe_pri_pw_diff_fcc_idle_th = 0;
1823 u8 j = 0;
1824 u32 dfs_hist1_pw = 0, dfs_hist2_pw = 0, g_pw[6] = {0};
1825 u32 dfs_hist1_pri = 0, dfs_hist2_pri = 0, g_pri[6] = {0};
1826 u8 pw_sum_g0g5 = 0, pw_sum_g1g2g3g4 = 0;
1827 u8 pri_sum_g0g5 = 0, pri_sum_g1g2g3g4 = 0;
1828 u16 pw_sum_ss_g1g2g3g4 = 0, pri_sum_ss_g1g2g3g4 = 0;
1829 u8 max_pri_cnt = 0, max_pw_cnt = 0;
1830 #if (RTL8721D_SUPPORT)
1831 if (dm->support_ic_type & (ODM_RTL8721D))
1832 return;
1833 #endif
1834
1835 /*read pulse width hist report*/
1836 odm_set_bb_reg(dm, 0x19e4, BIT(22) | BIT(23), 0x1);
1837 dfs_hist1_pw = odm_get_bb_reg(dm, 0xf5c, 0xffffffff);
1838 dfs_hist2_pw = odm_get_bb_reg(dm, 0xf74, 0xffffffff);
1839
1840 g_pw[0] = (unsigned int)((dfs_hist2_pw & 0xff000000) >> 24);
1841 g_pw[1] = (unsigned int)((dfs_hist2_pw & 0x00ff0000) >> 16);
1842 g_pw[2] = (unsigned int)((dfs_hist2_pw & 0x0000ff00) >> 8);
1843 g_pw[3] = (unsigned int)dfs_hist2_pw & 0x000000ff;
1844 g_pw[4] = (unsigned int)((dfs_hist1_pw & 0xff000000) >> 24);
1845 g_pw[5] = (unsigned int)((dfs_hist1_pw & 0x00ff0000) >> 16);
1846
1847 /*read pulse repetition interval hist report*/
1848 odm_set_bb_reg(dm, 0x19e4, BIT(22) | BIT(23), 0x3);
1849 dfs_hist1_pri = odm_get_bb_reg(dm, 0xf5c, 0xffffffff);
1850 dfs_hist2_pri = odm_get_bb_reg(dm, 0xf74, 0xffffffff);
1851 odm_set_bb_reg(dm, 0x19b4, 0x10000000, 1); /*reset histo report*/
1852 odm_set_bb_reg(dm, 0x19b4, 0x10000000, 0); /*@continue histo report*/
1853
1854 g_pri[0] = (unsigned int)((dfs_hist2_pri & 0xff000000) >> 24);
1855 g_pri[1] = (unsigned int)((dfs_hist2_pri & 0x00ff0000) >> 16);
1856 g_pri[2] = (unsigned int)((dfs_hist2_pri & 0x0000ff00) >> 8);
1857 g_pri[3] = (unsigned int)dfs_hist2_pri & 0x000000ff;
1858 g_pri[4] = (unsigned int)((dfs_hist1_pri & 0xff000000) >> 24);
1859 g_pri[5] = (unsigned int)((dfs_hist1_pri & 0x00ff0000) >> 16);
1860
1861 dfs->pri_cond1 = 0;
1862 dfs->pri_cond2 = 0;
1863 dfs->pri_cond3 = 0;
1864 dfs->pri_cond4 = 0;
1865 dfs->pri_cond5 = 0;
1866 dfs->pw_cond1 = 0;
1867 dfs->pw_cond2 = 0;
1868 dfs->pw_cond3 = 0;
1869 dfs->pri_type3_4_cond1 = 0; /*@for ETSI*/
1870 dfs->pri_type3_4_cond2 = 0; /*@for ETSI*/
1871 dfs->pw_long_cond1 = 0; /*@for long radar*/
1872 dfs->pw_long_cond2 = 0; /*@for long radar*/
1873 dfs->pri_long_cond1 = 0; /*@for long radar*/
1874 dfs->pw_flag = 0;
1875 dfs->pri_flag = 0;
1876 dfs->pri_type3_4_flag = 0; /*@for ETSI*/
1877 dfs->long_radar_flag = 0;
1878 dfs->pw_std = 0; /*The std(var) of reasonable num of pw group*/
1879 dfs->pri_std = 0; /*The std(var) of reasonable num of pri group*/
1880
1881 for (i = 0; i < 6; i++) {
1882 dfs->pw_hold_sum[i] = 0;
1883 dfs->pri_hold_sum[i] = 0;
1884 }
1885
1886 if (dfs->idle_mode == 1)
1887 pri_th = dfs->pri_hist_th;
1888 else
1889 pri_th = dfs->pri_hist_th - 1;
1890
1891 for (i = 0; i < 6; i++) {
1892 dfs->pw_hold[dfs->hist_idx][i] = (u8)g_pw[i];
1893 dfs->pri_hold[dfs->hist_idx][i] = (u8)g_pri[i];
1894 /*@collect whole histogram report may take some time
1895 *so we add the counter of 2 time slots in FCC and ETSI
1896 */
1897 dfs->pw_hold_sum[i] = dfs->pw_hold_sum[i] +
1898 dfs->pw_hold[(dfs->hist_idx + 1) % 3][i] +
1899 dfs->pw_hold[(dfs->hist_idx + 2) % 3][i];
1900 dfs->pri_hold_sum[i] = dfs->pri_hold_sum[i] +
1901 dfs->pri_hold[(dfs->hist_idx + 1) % 3][i] +
1902 dfs->pri_hold[(dfs->hist_idx + 2) % 3][i];
1903 }
1904 /*@For long radar type*/
1905 for (j = 1; j < 4; j++) {
1906 dfs->pw_long_hold_sum[i] = dfs->pw_long_hold_sum[i] +
1907 dfs->pw_hold[(dfs->hist_long_idx + j) % 4][i];
1908 dfs->pri_long_hold_sum[i] = dfs->pri_long_hold_sum[i] +
1909 dfs->pri_hold[(dfs->hist_long_idx + j) % 4][i];
1910 }
1911
1912 dfs->hist_idx++;
1913 if (dfs->hist_idx == 3)
1914 dfs->hist_idx = 0;
1915 dfs->hist_long_idx++;
1916 if (dfs->hist_long_idx == 4)
1917 dfs->hist_long_idx = 0;
1918
1919 max_pri_cnt = 0;
1920 max_pri_idx = 0;
1921 max_pw_cnt = 0;
1922 max_pw_idx = 0;
1923 max_pri_cnt_th = dfs->pri_sum_g1_th;
1924 max_pri_cnt_fcc_g1_th = dfs->pri_sum_g1_fcc_th;
1925 max_pri_cnt_fcc_g3_th = dfs->pri_sum_g3_fcc_th;
1926 safe_pri_pw_diff_th = dfs->pri_pw_diff_th;
1927 safe_pri_pw_diff_fcc_th = dfs->pri_pw_diff_fcc_th;
1928 safe_pri_pw_diff_fcc_idle_th = dfs->pri_pw_diff_fcc_idle_th;
1929 safe_pri_pw_diff_w53_th = dfs->pri_pw_diff_w53_th;
1930
1931 /*@g1 to g4 is the reseasonable range of pri and pw*/
1932 for (i = 1; i <= 4; i++) {
1933 if (dfs->pri_hold_sum[i] > max_pri_cnt) {
1934 max_pri_cnt = dfs->pri_hold_sum[i];
1935 max_pri_idx = i;
1936 }
1937 if (dfs->pw_hold_sum[i] > max_pw_cnt) {
1938 max_pw_cnt = dfs->pw_hold_sum[i];
1939 max_pw_idx = i;
1940 }
1941 if (dfs->pri_hold_sum[i] >= pri_th)
1942 dfs->pri_cond1 = 1;
1943 }
1944
1945 pri_sum_g0g5 = dfs->pri_hold_sum[0];
1946 if (pri_sum_g0g5 == 0)
1947 pri_sum_g0g5 = 1;
1948 pri_sum_g1g2g3g4 = dfs->pri_hold_sum[1] + dfs->pri_hold_sum[2]
1949 + dfs->pri_hold_sum[3] + dfs->pri_hold_sum[4];
1950
1951 /*pw will reduce because of dc, so we do not treat g0 as illegal group*/
1952 pw_sum_g0g5 = dfs->pw_hold_sum[5];
1953 if (pw_sum_g0g5 == 0)
1954 pw_sum_g0g5 = 1;
1955 pw_sum_g1g2g3g4 = dfs->pw_hold_sum[1] + dfs->pw_hold_sum[2] +
1956 dfs->pw_hold_sum[3] + dfs->pw_hold_sum[4];
1957
1958 /*@Calculate the variation from g1 to g4*/
1959 for (i = 1; i < 5; i++) {
1960 /*Sum of square*/
1961 pw_sum_ss_g1g2g3g4 = pw_sum_ss_g1g2g3g4 +
1962 (dfs->pw_hold_sum[i] - (pw_sum_g1g2g3g4 / 4)) *
1963 (dfs->pw_hold_sum[i] - (pw_sum_g1g2g3g4 / 4));
1964 pri_sum_ss_g1g2g3g4 = pri_sum_ss_g1g2g3g4 +
1965 (dfs->pri_hold_sum[i] - (pri_sum_g1g2g3g4 / 4)) *
1966 (dfs->pri_hold_sum[i] - (pri_sum_g1g2g3g4 / 4));
1967 }
1968 /*The value may less than the normal variance,
1969 *since the variable type is int (not float)
1970 */
1971 dfs->pw_std = (u8)(pw_sum_ss_g1g2g3g4 / 4);
1972 dfs->pri_std = (u8)(pri_sum_ss_g1g2g3g4 / 4);
1973
1974 if (region_domain == 1) {
1975 dfs->pri_type3_4_flag = 1; /*@ETSI flag*/
1976
1977 /*(OTA) Cancel long PRI case*/
1978 dfs->pri_cond2 = 1;
1979
1980 /*reasonable group shouldn't large*/
1981 if ((pri_sum_g0g5 + pri_sum_g1g2g3g4) / pri_sum_g0g5 > 2 &&
1982 pri_sum_g1g2g3g4 <= dfs->pri_sum_safe_fcc_th)
1983 dfs->pri_cond3 = 1;
1984
1985 /*@Cancel the condition that the abs between pri and pw*/
1986 if (dfs->pri_std >= dfs->pri_std_th)
1987 dfs->pri_cond4 = 1;
1988 else if (max_pri_idx == 1 &&
1989 max_pri_cnt >= max_pri_cnt_fcc_g1_th)
1990 dfs->pri_cond4 = 1;
1991
1992 /*(OTA) Cancel the condition (type 3,4 distinction)*/
1993 dfs->pri_cond5 = 1;
1994
1995 if (dfs->pri_cond1 && dfs->pri_cond2 && dfs->pri_cond3 &&
1996 dfs->pri_cond4 && dfs->pri_cond5)
1997 dfs->pri_flag = 1;
1998
1999 /* PW judgment conditions for short radar type */
2000 /*ratio of reasonable and illegal group && g5 should be zero*/
2001 if (((pw_sum_g0g5 + pw_sum_g1g2g3g4) / pw_sum_g0g5 > 2) &&
2002 (dfs->pw_hold_sum[5] <= 1))
2003 dfs->pw_cond1 = 1;
2004 /*unreasonable group*/
2005 if (dfs->pw_hold_sum[4] == 0 && dfs->pw_hold_sum[5] == 0)
2006 dfs->pw_cond2 = 1;
2007 /*pw's std (short radar) should be large(=7)*/
2008 if (dfs->pw_std >= dfs->pw_std_th)
2009 dfs->pw_cond3 = 1;
2010 if (dfs->pw_cond1 && dfs->pw_cond2 && dfs->pw_cond3)
2011 dfs->pw_flag = 1;
2012
2013 /* @Judgment conditions of long radar type */
2014 if (band_width == CHANNEL_WIDTH_20) {
2015 if (dfs->pw_long_hold_sum[4] >=
2016 dfs->pw_long_lower_20m_th)
2017 dfs->pw_long_cond1 = 1;
2018 } else{
2019 if (dfs->pw_long_hold_sum[4] >= dfs->pw_long_lower_th)
2020 dfs->pw_long_cond1 = 1;
2021 }
2022 /* @Disable the condition that dfs->pw_long_hold_sum[1] */
2023 if (dfs->pw_long_hold_sum[2] + dfs->pw_long_hold_sum[3] +
2024 dfs->pw_long_hold_sum[4] <= dfs->pw_long_sum_upper_th &&
2025 dfs->pw_long_hold_sum[2] <= dfs->pw_long_hold_sum[4] &&
2026 dfs->pw_long_hold_sum[3] <= dfs->pw_long_hold_sum[4])
2027 dfs->pw_long_cond2 = 1;
2028 /*@g4 should be large for long radar*/
2029 if (dfs->pri_long_hold_sum[4] <= dfs->pri_long_upper_th)
2030 dfs->pri_long_cond1 = 1;
2031 if (dfs->pw_long_cond1 && dfs->pw_long_cond2 &&
2032 dfs->pri_long_cond1)
2033 dfs->long_radar_flag = 1;
2034 } else if (region_domain == 2) {
2035 dfs->pri_type3_4_flag = 1; /*@ETSI flag*/
2036
2037 /*PRI judgment conditions for short radar type*/
2038 if ((pri_sum_g0g5 + pri_sum_g1g2g3g4) / pri_sum_g0g5 > 2)
2039 dfs->pri_cond2 = 1;
2040
2041 /*reasonable group shouldn't too large*/
2042 if (pri_sum_g1g2g3g4 <= dfs->pri_sum_safe_fcc_th)
2043 dfs->pri_cond3 = 1;
2044
2045 /*Cancel the abs diff between pri and pw for idle mode (thr=2)*/
2046 dfs->pri_cond4 = 1;
2047
2048 if (dfs->idle_mode == 1) {
2049 if (dfs->pri_std >= dfs->pri_std_idle_th) {
2050 if (max_pw_idx == 3 &&
2051 pri_sum_g1g2g3g4 <= dfs->pri_sum_type4_th){
2052 /*To distinguish between type 4 radar and false detection*/
2053 dfs->pri_cond5 = 1;
2054 } else if (max_pw_idx == 1 &&
2055 pri_sum_g1g2g3g4 >=
2056 dfs->pri_sum_type6_th) {
2057 /*To distinguish between type 6 radar and false detection*/
2058 dfs->pri_cond5 = 1;
2059 } else {
2060 /*pri variation of short radar should be large (idle mode)*/
2061 dfs->pri_cond5 = 1;
2062 }
2063 }
2064 } else {
2065 /*pri variation of short radar should be large (TP mode)*/
2066 if (dfs->pri_std >= dfs->pri_std_th)
2067 dfs->pri_cond5 = 1;
2068 }
2069
2070 if (dfs->pri_cond1 && dfs->pri_cond2 && dfs->pri_cond3 &&
2071 dfs->pri_cond4 && dfs->pri_cond5)
2072 dfs->pri_flag = 1;
2073
2074 /* PW judgment conditions for short radar type */
2075 if (((pw_sum_g0g5 + pw_sum_g1g2g3g4) / pw_sum_g0g5 > 2) &&
2076 (dfs->pw_hold_sum[5] <= 1))
2077 /*ratio of reasonable and illegal group && g5 should be zero*/
2078 dfs->pw_cond1 = 1;
2079
2080 if ((c_channel >= 52) && (c_channel <= 64))
2081 dfs->pw_cond2 = 1;
2082 /*unreasonable group shouldn't too large*/
2083 else if (dfs->pw_hold_sum[0] <= dfs->pw_g0_th)
2084 dfs->pw_cond2 = 1;
2085
2086 if (dfs->idle_mode == 1) {
2087 /*pw variation of short radar should be large (idle mode)*/
2088 if (dfs->pw_std >= dfs->pw_std_idle_th)
2089 dfs->pw_cond3 = 1;
2090 } else {
2091 /*pw variation of short radar should be large (TP mode)*/
2092 if (dfs->pw_std >= dfs->pw_std_th)
2093 dfs->pw_cond3 = 1;
2094 }
2095 if (dfs->pw_cond1 && dfs->pw_cond2 && dfs->pw_cond3)
2096 dfs->pw_flag = 1;
2097
2098 /* @Judgment conditions of long radar type */
2099 if (band_width == CHANNEL_WIDTH_20) {
2100 if (dfs->pw_long_hold_sum[4] >=
2101 dfs->pw_long_lower_20m_th)
2102 dfs->pw_long_cond1 = 1;
2103 } else{
2104 if (dfs->pw_long_hold_sum[4] >= dfs->pw_long_lower_th)
2105 dfs->pw_long_cond1 = 1;
2106 }
2107 if (dfs->pw_long_hold_sum[1] + dfs->pw_long_hold_sum[2] +
2108 dfs->pw_long_hold_sum[3] + dfs->pw_long_hold_sum[4]
2109 <= dfs->pw_long_sum_upper_th)
2110 dfs->pw_long_cond2 = 1;
2111 /*@g4 should be large for long radar*/
2112 if (dfs->pri_long_hold_sum[4] <= dfs->pri_long_upper_th)
2113 dfs->pri_long_cond1 = 1;
2114 if (dfs->pw_long_cond1 &&
2115 dfs->pw_long_cond2 && dfs->pri_long_cond1)
2116 dfs->long_radar_flag = 1;
2117 } else if (region_domain == 3) {
2118 /*ratio of reasonable group and illegal group */
2119 if ((pri_sum_g0g5 + pri_sum_g1g2g3g4) / pri_sum_g0g5 > 2)
2120 dfs->pri_cond2 = 1;
2121
2122 if (pri_sum_g1g2g3g4 <= dfs->pri_sum_safe_th)
2123 dfs->pri_cond3 = 1;
2124
2125 /*@Cancel the condition that the abs between pri and pw*/
2126 dfs->pri_cond4 = 1;
2127
2128 if (dfs->pri_hold_sum[5] <= dfs->pri_sum_g5_th)
2129 dfs->pri_cond5 = 1;
2130
2131 if (band_width == CHANNEL_WIDTH_40) {
2132 if (max_pw_idx == 4) {
2133 if (max_pw_cnt >= dfs->type4_pw_max_cnt &&
2134 pri_sum_g1g2g3g4 >=
2135 dfs->type4_safe_pri_sum_th) {
2136 dfs->pri_cond1 = 1;
2137 dfs->pri_cond4 = 1;
2138 dfs->pri_type3_4_cond1 = 1;
2139 }
2140 }
2141 }
2142
2143 if (dfs->pri_cond1 && dfs->pri_cond2 &&
2144 dfs->pri_cond3 && dfs->pri_cond4 && dfs->pri_cond5)
2145 dfs->pri_flag = 1;
2146
2147 if (((pw_sum_g0g5 + pw_sum_g1g2g3g4) / pw_sum_g0g5 > 2))
2148 dfs->pw_flag = 1;
2149
2150 /*@max num pri group is g1 means radar type3 or type4*/
2151 if (max_pri_idx == 1) {
2152 if (max_pri_cnt >= max_pri_cnt_th)
2153 dfs->pri_type3_4_cond1 = 1;
2154 if (dfs->pri_hold_sum[4] <=
2155 dfs->pri_sum_g5_under_g1_th &&
2156 dfs->pri_hold_sum[5] <= dfs->pri_sum_g5_under_g1_th)
2157 dfs->pri_type3_4_cond2 = 1;
2158 } else {
2159 dfs->pri_type3_4_cond1 = 1;
2160 dfs->pri_type3_4_cond2 = 1;
2161 }
2162 if (dfs->pri_type3_4_cond1 && dfs->pri_type3_4_cond2)
2163 dfs->pri_type3_4_flag = 1;
2164 } else {
2165 }
2166
2167 if (dfs->print_hist_rpt) {
2168 dfs_pw_thd1 = (u8)odm_get_bb_reg(dm, 0x19e4, 0xff000000);
2169 dfs_pw_thd2 = (u8)odm_get_bb_reg(dm, 0x19e8, 0x000000ff);
2170 dfs_pw_thd3 = (u8)odm_get_bb_reg(dm, 0x19e8, 0x0000ff00);
2171 dfs_pw_thd4 = (u8)odm_get_bb_reg(dm, 0x19e8, 0x00ff0000);
2172 dfs_pw_thd5 = (u8)odm_get_bb_reg(dm, 0x19e8, 0xff000000);
2173
2174 dfs_pri_thd1 = (u8)odm_get_bb_reg(dm, 0x19b8, 0x7F80);
2175 dfs_pri_thd2 = (u8)odm_get_bb_reg(dm, 0x19ec, 0x000000ff);
2176 dfs_pri_thd3 = (u8)odm_get_bb_reg(dm, 0x19ec, 0x0000ff00);
2177 dfs_pri_thd4 = (u8)odm_get_bb_reg(dm, 0x19ec, 0x00ff0000);
2178 dfs_pri_thd5 = (u8)odm_get_bb_reg(dm, 0x19ec, 0xff000000);
2179
2180 PHYDM_DBG(dm, DBG_DFS, "\ndfs_pw_thd=%d %d %d %d %d\n",
2181 dfs_pw_thd1, dfs_pw_thd2, dfs_pw_thd3,
2182 dfs_pw_thd4, dfs_pw_thd5);
2183 PHYDM_DBG(dm, DBG_DFS, "-----pulse width hist-----\n");
2184 PHYDM_DBG(dm, DBG_DFS, "dfs_hist_pw=%x %x\n",
2185 dfs_hist1_pw, dfs_hist2_pw);
2186 PHYDM_DBG(dm, DBG_DFS, "g_pw_hist = %x %x %x %x %x %x\n",
2187 g_pw[0], g_pw[1], g_pw[2], g_pw[3],
2188 g_pw[4], g_pw[5]);
2189 PHYDM_DBG(dm, DBG_DFS, "dfs_pri_thd=%d %d %d %d %d\n",
2190 dfs_pri_thd1, dfs_pri_thd2, dfs_pri_thd3,
2191 dfs_pri_thd4, dfs_pri_thd5);
2192 PHYDM_DBG(dm, DBG_DFS, "-----pulse interval hist-----\n");
2193 PHYDM_DBG(dm, DBG_DFS, "dfs_hist_pri=%x %x\n",
2194 dfs_hist1_pri, dfs_hist2_pri);
2195 PHYDM_DBG(dm, DBG_DFS,
2196 "g_pri_hist = %x %x %x %x %x %x, pw_flag = %d, pri_flag = %d\n",
2197 g_pri[0], g_pri[1], g_pri[2], g_pri[3], g_pri[4],
2198 g_pri[5], dfs->pw_flag, dfs->pri_flag);
2199 if (region_domain == 1 || region_domain == 3) {
2200 PHYDM_DBG(dm, DBG_DFS, "hist_idx= %d\n",
2201 (dfs->hist_idx + 2) % 3);
2202 } else {
2203 PHYDM_DBG(dm, DBG_DFS, "hist_idx= %d\n",
2204 (dfs->hist_idx + 3) % 4);
2205 }
2206 PHYDM_DBG(dm, DBG_DFS, "hist_long_idx= %d\n",
2207 (dfs->hist_long_idx + 299) % 300);
2208 PHYDM_DBG(dm, DBG_DFS,
2209 "pw_sum_g0g5 = %d, pw_sum_g1g2g3g4 = %d\n",
2210 pw_sum_g0g5, pw_sum_g1g2g3g4);
2211 PHYDM_DBG(dm, DBG_DFS,
2212 "pri_sum_g0g5 = %d, pri_sum_g1g2g3g4 = %d\n",
2213 pri_sum_g0g5, pri_sum_g1g2g3g4);
2214 PHYDM_DBG(dm, DBG_DFS, "pw_hold_sum = %d %d %d %d %d %d\n",
2215 dfs->pw_hold_sum[0], dfs->pw_hold_sum[1],
2216 dfs->pw_hold_sum[2], dfs->pw_hold_sum[3],
2217 dfs->pw_hold_sum[4], dfs->pw_hold_sum[5]);
2218 PHYDM_DBG(dm, DBG_DFS, "pri_hold_sum = %d %d %d %d %d %d\n",
2219 dfs->pri_hold_sum[0], dfs->pri_hold_sum[1],
2220 dfs->pri_hold_sum[2], dfs->pri_hold_sum[3],
2221 dfs->pri_hold_sum[4], dfs->pri_hold_sum[5]);
2222 PHYDM_DBG(dm, DBG_DFS, "pw_long_hold_sum = %d %d %d %d %d %d\n",
2223 dfs->pw_long_hold_sum[0], dfs->pw_long_hold_sum[1],
2224 dfs->pw_long_hold_sum[2], dfs->pw_long_hold_sum[3],
2225 dfs->pw_long_hold_sum[4], dfs->pw_long_hold_sum[5]);
2226 PHYDM_DBG(dm, DBG_DFS,
2227 "pri_long_hold_sum = %d %d %d %d %d %d\n",
2228 dfs->pri_long_hold_sum[0], dfs->pri_long_hold_sum[1],
2229 dfs->pri_long_hold_sum[2], dfs->pri_long_hold_sum[3],
2230 dfs->pri_long_hold_sum[4], dfs->pri_long_hold_sum[5]);
2231 PHYDM_DBG(dm, DBG_DFS, "idle_mode = %d\n", dfs->idle_mode);
2232 PHYDM_DBG(dm, DBG_DFS, "pw_standard = %d\n", dfs->pw_std);
2233 PHYDM_DBG(dm, DBG_DFS, "pri_standard = %d\n", dfs->pri_std);
2234 PHYDM_DBG(dm, DBG_DFS, "\n");
2235 PHYDM_DBG(dm, DBG_DFS,
2236 "pri_cond1 = %d, pri_cond2 = %d, pri_cond3 = %d, pri_cond4 = %d, pri_cond5 = %d\n",
2237 dfs->pri_cond1, dfs->pri_cond2, dfs->pri_cond3,
2238 dfs->pri_cond4, dfs->pri_cond5);
2239 PHYDM_DBG(dm, DBG_DFS,
2240 "bandwidth = %d, pri_th = %d, max_pri_cnt_th = %d, safe_pri_pw_diff_th = %d\n",
2241 band_width, pri_th, max_pri_cnt_th,
2242 safe_pri_pw_diff_th);
2243 }
2244 }
2245 #endif
phydm_dfs_hist_log(void * dm_void,u8 index)2246 boolean phydm_dfs_hist_log(void *dm_void, u8 index)
2247 {
2248 struct dm_struct *dm = (struct dm_struct *)dm_void;
2249 struct _DFS_STATISTICS *dfs = &dm->dfs;
2250 u8 i = 0, j = 0;
2251 boolean hist_radar_detected = 0;
2252
2253 if (dfs->pulse_type_hist[index] == 0) {
2254 dfs->radar_type = 0;
2255 if (dfs->pw_flag && dfs->pri_flag &&
2256 dfs->pri_type3_4_flag) {
2257 hist_radar_detected = 1;
2258 PHYDM_DBG(dm, DBG_DFS,
2259 "Detected type %d radar signal!\n",
2260 dfs->radar_type);
2261 if (dfs->det_print2) {
2262 PHYDM_DBG(dm, DBG_DFS,
2263 "hist_idx= %d\n",
2264 (dfs->hist_idx + 3) % 4);
2265 for (j = 0; j < 4; j++) {
2266 for (i = 0; i < 6; i++) {
2267 PHYDM_DBG(dm, DBG_DFS,
2268 "pri_hold = %d ",
2269 dfs->pri_hold[j][i]);
2270 }
2271 PHYDM_DBG(dm, DBG_DFS, "\n");
2272 }
2273 PHYDM_DBG(dm, DBG_DFS, "\n");
2274 for (j = 0; j < 4; j++) {
2275 for (i = 0; i < 6; i++) {
2276 PHYDM_DBG(dm, DBG_DFS, "pw_hold = %d ",
2277 dfs->pw_hold[j][i]);
2278 }
2279 PHYDM_DBG(dm, DBG_DFS, "\n");
2280 }
2281 PHYDM_DBG(dm, DBG_DFS, "\n");
2282 PHYDM_DBG(dm, DBG_DFS, "idle_mode = %d\n",
2283 dfs->idle_mode);
2284 PHYDM_DBG(dm, DBG_DFS,
2285 "pw_hold_sum = %d %d %d %d %d %d\n",
2286 dfs->pw_hold_sum[0],
2287 dfs->pw_hold_sum[1],
2288 dfs->pw_hold_sum[2],
2289 dfs->pw_hold_sum[3],
2290 dfs->pw_hold_sum[4],
2291 dfs->pw_hold_sum[5]);
2292 PHYDM_DBG(dm, DBG_DFS,
2293 "pri_hold_sum = %d %d %d %d %d %d\n",
2294 dfs->pri_hold_sum[0],
2295 dfs->pri_hold_sum[1],
2296 dfs->pri_hold_sum[2],
2297 dfs->pri_hold_sum[3],
2298 dfs->pri_hold_sum[4],
2299 dfs->pri_hold_sum[5]);
2300 }
2301 } else {
2302 if (dfs->det_print2) {
2303 if (dfs->pulse_flag_hist[index] &&
2304 dfs->pri_flag == 0) {
2305 PHYDM_DBG(dm, DBG_DFS, "pri_variation = %d\n",
2306 dfs->pri_std);
2307 PHYDM_DBG(dm, DBG_DFS,
2308 "PRI criterion is not satisfied!\n");
2309 if (dfs->pri_cond1 == 0)
2310 PHYDM_DBG(dm, DBG_DFS,
2311 "pri_cond1 is not satisfied!\n");
2312 if (dfs->pri_cond2 == 0)
2313 PHYDM_DBG(dm, DBG_DFS,
2314 "pri_cond2 is not satisfied!\n");
2315 if (dfs->pri_cond3 == 0)
2316 PHYDM_DBG(dm, DBG_DFS,
2317 "pri_cond3 is not satisfied!\n");
2318 if (dfs->pri_cond4 == 0)
2319 PHYDM_DBG(dm, DBG_DFS,
2320 "pri_cond4 is not satisfied!\n");
2321 if (dfs->pri_cond5 == 0)
2322 PHYDM_DBG(dm, DBG_DFS,
2323 "pri_cond5 is not satisfied!\n");
2324 }
2325 if (dfs->pulse_flag_hist[index] &&
2326 dfs->pw_flag == 0) {
2327 PHYDM_DBG(dm, DBG_DFS, "pw_variation = %d\n",
2328 dfs->pw_std);
2329 PHYDM_DBG(dm, DBG_DFS,
2330 "PW criterion is not satisfied!\n");
2331 if (dfs->pw_cond1 == 0)
2332 PHYDM_DBG(dm, DBG_DFS,
2333 "pw_cond1 is not satisfied!\n");
2334 if (dfs->pw_cond2 == 0)
2335 PHYDM_DBG(dm, DBG_DFS,
2336 "pw_cond2 is not satisfied!\n");
2337 if (dfs->pw_cond3 == 0)
2338 PHYDM_DBG(dm, DBG_DFS,
2339 "pw_cond3 is not satisfied!\n");
2340 }
2341 if (dfs->pulse_flag_hist[index] &&
2342 (dfs->pri_type3_4_flag == 0)) {
2343 PHYDM_DBG(dm, DBG_DFS,
2344 "pri_type3_4 criterion is not satisfied!\n");
2345 if (dfs->pri_type3_4_cond1 == 0)
2346 PHYDM_DBG(dm, DBG_DFS,
2347 "pri_type3_4_cond1 is not satisfied!\n");
2348 if (dfs->pri_type3_4_cond2 == 0)
2349 PHYDM_DBG(dm, DBG_DFS,
2350 "pri_type3_4_cond2 is not satisfied!\n");
2351 }
2352 PHYDM_DBG(dm, DBG_DFS, "hist_idx= %d\n",
2353 (dfs->hist_idx + 3) % 4);
2354 for (j = 0; j < 4; j++) {
2355 for (i = 0; i < 6; i++) {
2356 PHYDM_DBG(dm, DBG_DFS,
2357 "pri_hold = %d ",
2358 dfs->pri_hold[j][i]);
2359 }
2360 PHYDM_DBG(dm, DBG_DFS, "\n");
2361 }
2362 PHYDM_DBG(dm, DBG_DFS, "\n");
2363 for (j = 0; j < 4; j++) {
2364 for (i = 0; i < 6; i++)
2365 PHYDM_DBG(dm, DBG_DFS,
2366 "pw_hold = %d ",
2367 dfs->pw_hold[j][i]);
2368 PHYDM_DBG(dm, DBG_DFS, "\n");
2369 }
2370 PHYDM_DBG(dm, DBG_DFS, "\n");
2371 PHYDM_DBG(dm, DBG_DFS, "idle_mode = %d\n",
2372 dfs->idle_mode);
2373 PHYDM_DBG(dm, DBG_DFS,
2374 "pw_hold_sum = %d %d %d %d %d %d\n",
2375 dfs->pw_hold_sum[0], dfs->pw_hold_sum[1],
2376 dfs->pw_hold_sum[2], dfs->pw_hold_sum[3],
2377 dfs->pw_hold_sum[4], dfs->pw_hold_sum[5]);
2378 PHYDM_DBG(dm, DBG_DFS,
2379 "pri_hold_sum = %d %d %d %d %d %d\n",
2380 dfs->pri_hold_sum[0], dfs->pri_hold_sum[1],
2381 dfs->pri_hold_sum[2], dfs->pri_hold_sum[3],
2382 dfs->pri_hold_sum[4], dfs->pri_hold_sum[5]);
2383 }
2384 }
2385 } else {
2386 dfs->radar_type = 1;
2387 if (dfs->det_print2) {
2388 PHYDM_DBG(dm, DBG_DFS, "\n");
2389 PHYDM_DBG(dm, DBG_DFS, "idle_mode = %d\n",
2390 dfs->idle_mode);
2391 }
2392 /* @Long radar should satisfy three conditions */
2393 if (dfs->long_radar_flag == 1) {
2394 hist_radar_detected = 1;
2395 PHYDM_DBG(dm, DBG_DFS,
2396 "Detected type %d radar signal!\n",
2397 dfs->radar_type);
2398 } else {
2399 if (dfs->det_print2) {
2400 if (dfs->pw_long_cond1 == 0)
2401 PHYDM_DBG(dm, DBG_DFS,
2402 "--pw_long_cond1 is not satisfied!--\n");
2403 if (dfs->pw_long_cond2 == 0)
2404 PHYDM_DBG(dm, DBG_DFS,
2405 "--pw_long_cond2 is not satisfied!--\n");
2406 if (dfs->pri_long_cond1 == 0)
2407 PHYDM_DBG(dm, DBG_DFS,
2408 "--pri_long_cond1 is not satisfied!--\n");
2409 }
2410 }
2411 }
2412 return hist_radar_detected;
2413 }
2414
phydm_radar_detect(void * dm_void)2415 boolean phydm_radar_detect(void *dm_void)
2416 {
2417 struct dm_struct *dm = (struct dm_struct *)dm_void;
2418 struct _DFS_STATISTICS *dfs = &dm->dfs;
2419 boolean radar_detected = false;
2420
2421 if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
2422 dfs->igi_cur = (u8)odm_get_bb_reg(dm, R_0x1d70, 0x0000007f);
2423 dfs->st_l2h_cur = (u8)odm_get_bb_reg(dm, R_0xa40, 0x00007f00);
2424 #if (RTL8721D_SUPPORT)
2425 } else if (dm->support_ic_type & (ODM_RTL8721D)) {
2426 dfs->st_l2h_cur = (u8)(odm_get_bb_reg(dm, R_0xf54,
2427 0x0000001f) << 2);
2428 dfs->st_l2h_cur += (u8)odm_get_bb_reg(dm, R_0xf58, 0xc0000000);
2429 #endif
2430 } else {
2431 dfs->igi_cur = (u8)odm_get_bb_reg(dm, R_0xc50, 0x0000007f);
2432 dfs->st_l2h_cur = (u8)odm_get_bb_reg(dm, R_0x91c, 0x000000ff);
2433 }
2434
2435 /* @dynamic pwdb calibration */
2436 if (dfs->igi_pre != dfs->igi_cur) {
2437 dfs->pwdb_th_cur = ((int)dfs->st_l2h_cur - (int)dfs->igi_cur)
2438 / 2 + dfs->pwdb_scalar_factor;
2439
2440 /* @limit the pwdb value to absolute lower bound 0xa */
2441 dfs->pwdb_th_cur = MAX_2(dfs->pwdb_th_cur, (int)dfs->pwdb_th);
2442 /* @limit the pwdb value to absolute upper bound 0x1f */
2443 dfs->pwdb_th_cur = MIN_2(dfs->pwdb_th_cur, 0x1f);
2444
2445 if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
2446 odm_set_bb_reg(dm, R_0xa50, 0x000000f0,
2447 dfs->pwdb_th_cur);
2448 #if (RTL8721D_SUPPORT)
2449 else if (dm->support_ic_type & (ODM_RTL8721D))
2450 odm_set_bb_reg(dm, R_0xf70, 0x03c00000,
2451 dfs->pwdb_th_cur);
2452 #endif
2453 else
2454 odm_set_bb_reg(dm, R_0x918, 0x00001f00,
2455 dfs->pwdb_th_cur);
2456 }
2457 dfs->igi_pre = dfs->igi_cur;
2458
2459 phydm_dfs_dynamic_setting(dm);
2460 #if (RTL8814A_SUPPORT || RTL8822B_SUPPORT || RTL8821C_SUPPORT)
2461 if (dm->support_ic_type & (ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8821C))
2462 phydm_dfs_histogram_radar_distinguish(dm);
2463 #endif
2464 radar_detected = phydm_radar_detect_dm_check(dm);
2465
2466 if (radar_detected) {
2467 /*
2468 PHYDM_DBG(dm, DBG_DFS,
2469 "Radar detect: %d\n", radar_detected);
2470 */
2471 phydm_radar_detect_reset(dm);
2472 if (dfs->dbg_mode == 1) {
2473 PHYDM_DBG(dm, DBG_DFS,
2474 "Radar is detected in DFS dbg mode!!!!!!!!!!!\n");
2475 radar_detected = 0;
2476 }
2477 }
2478
2479 if (dfs->sw_trigger_mode) {
2480 radar_detected = 1;
2481 PHYDM_DBG(dm, DBG_DFS,
2482 "Radar is detected in DFS SW trigger mode.\n");
2483 }
2484
2485 return radar_detected;
2486 }
2487
phydm_dfs_hist_dbg(void * dm_void,char input[][16],u32 * _used,char * output,u32 * _out_len)2488 void phydm_dfs_hist_dbg(void *dm_void, char input[][16], u32 *_used,
2489 char *output, u32 *_out_len)
2490 {
2491 struct dm_struct *dm = (struct dm_struct *)dm_void;
2492 struct _DFS_STATISTICS *dfs = &dm->dfs;
2493 char help[] = "-h";
2494 u32 argv[5] = {0};
2495 u32 used = *_used;
2496 u32 out_len = *_out_len;
2497 u8 i;
2498
2499 if ((strcmp(input[1], help) == 0)) {
2500 PDM_SNPF(out_len, used, output + used, out_len - used,
2501 "{0} pri_hist_th = %d\n", dfs->pri_hist_th);
2502 PDM_SNPF(out_len, used, output + used, out_len - used,
2503 "{1} pri_sum_g1_th = %d\n", dfs->pri_sum_g1_th);
2504 PDM_SNPF(out_len, used, output + used, out_len - used,
2505 "{2} pri_sum_g5_th = %d\n", dfs->pri_sum_g5_th);
2506 PDM_SNPF(out_len, used, output + used, out_len - used,
2507 "{3} pri_sum_g1_fcc_th = %d\n",
2508 dfs->pri_sum_g1_fcc_th);
2509 PDM_SNPF(out_len, used, output + used, out_len - used,
2510 "{4} pri_sum_g3_fcc_th = %d\n",
2511 dfs->pri_sum_g3_fcc_th);
2512 PDM_SNPF(out_len, used, output + used, out_len - used,
2513 "{5} pri_sum_safe_fcc_th = %d\n",
2514 dfs->pri_sum_safe_fcc_th);
2515 PDM_SNPF(out_len, used, output + used, out_len - used,
2516 "{6} pri_sum_type4_th = %d\n", dfs->pri_sum_type4_th);
2517 PDM_SNPF(out_len, used, output + used, out_len - used,
2518 "{7} pri_sum_type6_th = %d\n", dfs->pri_sum_type6_th);
2519 PDM_SNPF(out_len, used, output + used, out_len - used,
2520 "{8} pri_sum_safe_th = %d\n", dfs->pri_sum_safe_th);
2521 PDM_SNPF(out_len, used, output + used, out_len - used,
2522 "{9} pri_sum_g5_under_g1_th = %d\n",
2523 dfs->pri_sum_g5_under_g1_th);
2524 PDM_SNPF(out_len, used, output + used, out_len - used,
2525 "{10} pri_pw_diff_th = %d\n", dfs->pri_pw_diff_th);
2526 PDM_SNPF(out_len, used, output + used, out_len - used,
2527 "{11} pri_pw_diff_fcc_th = %d\n",
2528 dfs->pri_pw_diff_fcc_th);
2529 PDM_SNPF(out_len, used, output + used, out_len - used,
2530 "{12} pri_pw_diff_fcc_idle_th = %d\n",
2531 dfs->pri_pw_diff_fcc_idle_th);
2532 PDM_SNPF(out_len, used, output + used, out_len - used,
2533 "{13} pri_pw_diff_w53_th = %d\n",
2534 dfs->pri_pw_diff_w53_th);
2535 PDM_SNPF(out_len, used, output + used, out_len - used,
2536 "{14} pri_type1_low_fcc_th = %d\n",
2537 dfs->pri_type1_low_fcc_th);
2538 PDM_SNPF(out_len, used, output + used, out_len - used,
2539 "{15} pri_type1_upp_fcc_th = %d\n",
2540 dfs->pri_type1_upp_fcc_th);
2541 PDM_SNPF(out_len, used, output + used, out_len - used,
2542 "{16} pri_type1_cen_fcc_th = %d\n",
2543 dfs->pri_type1_cen_fcc_th);
2544 PDM_SNPF(out_len, used, output + used, out_len - used,
2545 "{17} pw_g0_th = %d\n", dfs->pw_g0_th);
2546 PDM_SNPF(out_len, used, output + used, out_len - used,
2547 "{18} pw_long_lower_20m_th = %d\n",
2548 dfs->pw_long_lower_20m_th);
2549 PDM_SNPF(out_len, used, output + used, out_len - used,
2550 "{19} pw_long_lower_th = %d\n",
2551 dfs->pw_long_lower_th);
2552 PDM_SNPF(out_len, used, output + used, out_len - used,
2553 "{20} pri_long_upper_th = %d\n",
2554 dfs->pri_long_upper_th);
2555 PDM_SNPF(out_len, used, output + used, out_len - used,
2556 "{21} pw_long_sum_upper_th = %d\n",
2557 dfs->pw_long_sum_upper_th);
2558 PDM_SNPF(out_len, used, output + used, out_len - used,
2559 "{22} pw_std_th = %d\n", dfs->pw_std_th);
2560 PDM_SNPF(out_len, used, output + used, out_len - used,
2561 "{23} pw_std_idle_th = %d\n", dfs->pw_std_idle_th);
2562 PDM_SNPF(out_len, used, output + used, out_len - used,
2563 "{24} pri_std_th = %d\n", dfs->pri_std_th);
2564 PDM_SNPF(out_len, used, output + used, out_len - used,
2565 "{25} pri_std_idle_th = %d\n", dfs->pri_std_idle_th);
2566 PDM_SNPF(out_len, used, output + used, out_len - used,
2567 "{26} type4_pw_max_cnt = %d\n", dfs->type4_pw_max_cnt);
2568 PDM_SNPF(out_len, used, output + used, out_len - used,
2569 "{27} type4_safe_pri_sum_th = %d\n",
2570 dfs->type4_safe_pri_sum_th);
2571 PDM_SNPF(out_len, used, output + used, out_len - used,
2572 "{28} fa_mask_th = %d\n",
2573 dfs->fa_mask_th);
2574 PDM_SNPF(out_len, used, output + used, out_len - used,
2575 "{29} nhm_cnt_th = %d\n",
2576 dfs->nhm_cnt_th);
2577 PDM_SNPF(out_len, used, output + used, out_len - used,
2578 "{30} nhm_dty_th = %d\n",
2579 dfs->nhm_dty_th);
2580 PDM_SNPF(out_len, used, output + used, out_len - used,
2581 "{31} pw_flag_en = %d\n",
2582 dfs->pw_flag_en);
2583 PDM_SNPF(out_len, used, output + used, out_len - used,
2584 "{32} loct_flag_en = %d\n",
2585 dfs->loct_flag_en);
2586 PDM_SNPF(out_len, used, output + used, out_len - used,
2587 "{33} pri_flag_en = %d\n",
2588 dfs->pri_flag_en);
2589 PDM_SNPF(out_len, used, output + used, out_len - used,
2590 "{34} pri_var_offset = %d\n",
2591 dfs->pri_var_offset);
2592 PDM_SNPF(out_len, used, output + used, out_len - used,
2593 "{35} pri_var_tp_offset = %d\n",
2594 dfs->pri_var_tp_offset);
2595 PDM_SNPF(out_len, used, output + used, out_len - used,
2596 "{36} pri_cnt_th = %d\n",
2597 dfs->pri_cnt_th);
2598 PDM_SNPF(out_len, used, output + used, out_len - used,
2599 "{37} loct_diff_th = %d\n",
2600 dfs->loct_diff_th);
2601 PDM_SNPF(out_len, used, output + used, out_len - used,
2602 "{38} dc_cnt_th = %d\n",
2603 dfs->dc_cnt_th);
2604 } else {
2605 PHYDM_SSCANF(input[1], DCMD_DECIMAL, &argv[0]);
2606
2607 for (i = 1; i < 5; i++) {
2608 PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL,
2609 &argv[i]);
2610 }
2611 if (argv[0] == 0) {
2612 dfs->pri_hist_th = (u8)argv[1];
2613 PDM_SNPF(out_len, used, output + used, out_len - used,
2614 "pri_hist_th = %d\n",
2615 dfs->pri_hist_th);
2616 } else if (argv[0] == 1) {
2617 dfs->pri_sum_g1_th = (u8)argv[1];
2618 PDM_SNPF(out_len, used, output + used, out_len - used,
2619 "pri_sum_g1_th = %d\n",
2620 dfs->pri_sum_g1_th);
2621 } else if (argv[0] == 2) {
2622 dfs->pri_sum_g5_th = (u8)argv[1];
2623 PDM_SNPF(out_len, used, output + used, out_len - used,
2624 "pri_sum_g5_th = %d\n",
2625 dfs->pri_sum_g5_th);
2626 } else if (argv[0] == 3) {
2627 dfs->pri_sum_g1_fcc_th = (u8)argv[1];
2628 PDM_SNPF(out_len, used, output + used, out_len - used,
2629 "pri_sum_g1_fcc_th = %d\n",
2630 dfs->pri_sum_g1_fcc_th);
2631 } else if (argv[0] == 4) {
2632 dfs->pri_sum_g3_fcc_th = (u8)argv[1];
2633 PDM_SNPF(out_len, used, output + used, out_len - used,
2634 "pri_sum_g3_fcc_th = %d\n",
2635 dfs->pri_sum_g3_fcc_th);
2636 } else if (argv[0] == 5) {
2637 dfs->pri_sum_safe_fcc_th = (u8)argv[1];
2638 PDM_SNPF(out_len, used, output + used, out_len - used,
2639 "pri_sum_safe_fcc_th = %d\n",
2640 dfs->pri_sum_safe_fcc_th);
2641 } else if (argv[0] == 6) {
2642 dfs->pri_sum_type4_th = (u8)argv[1];
2643 PDM_SNPF(out_len, used, output + used, out_len - used,
2644 "pri_sum_type4_th = %d\n",
2645 dfs->pri_sum_type4_th);
2646 } else if (argv[0] == 7) {
2647 dfs->pri_sum_type6_th = (u8)argv[1];
2648 PDM_SNPF(out_len, used, output + used, out_len - used,
2649 "pri_sum_type6_th = %d\n",
2650 dfs->pri_sum_type6_th);
2651 } else if (argv[0] == 8) {
2652 dfs->pri_sum_safe_th = (u8)argv[1];
2653 PDM_SNPF(out_len, used, output + used, out_len - used,
2654 "pri_sum_safe_th = %d\n",
2655 dfs->pri_sum_safe_th);
2656 } else if (argv[0] == 9) {
2657 dfs->pri_sum_g5_under_g1_th = (u8)argv[1];
2658 PDM_SNPF(out_len, used, output + used, out_len - used,
2659 "pri_sum_g5_under_g1_th = %d\n",
2660 dfs->pri_sum_g5_under_g1_th);
2661 } else if (argv[0] == 10) {
2662 dfs->pri_pw_diff_th = (u8)argv[1];
2663 PDM_SNPF(out_len, used, output + used, out_len - used,
2664 "pri_pw_diff_th = %d\n",
2665 dfs->pri_pw_diff_th);
2666 } else if (argv[0] == 11) {
2667 dfs->pri_pw_diff_fcc_th = (u8)argv[1];
2668 PDM_SNPF(out_len, used, output + used, out_len - used,
2669 "pri_pw_diff_fcc_th = %d\n",
2670 dfs->pri_pw_diff_fcc_th);
2671 } else if (argv[0] == 12) {
2672 dfs->pri_pw_diff_fcc_idle_th = (u8)argv[1];
2673 PDM_SNPF(out_len, used, output + used, out_len - used,
2674 "pri_pw_diff_fcc_idle_th = %d\n",
2675 dfs->pri_pw_diff_fcc_idle_th);
2676 } else if (argv[0] == 13) {
2677 dfs->pri_pw_diff_w53_th = (u8)argv[1];
2678 PDM_SNPF(out_len, used, output + used, out_len - used,
2679 "pri_pw_diff_w53_th = %d\n",
2680 dfs->pri_pw_diff_w53_th);
2681 } else if (argv[0] == 14) {
2682 dfs->pri_type1_low_fcc_th = (u8)argv[1];
2683 PDM_SNPF(out_len, used, output + used, out_len - used,
2684 "pri_type1_low_fcc_th = %d\n",
2685 dfs->pri_type1_low_fcc_th);
2686 } else if (argv[0] == 15) {
2687 dfs->pri_type1_upp_fcc_th = (u8)argv[1];
2688 PDM_SNPF(out_len, used, output + used, out_len - used,
2689 "pri_type1_upp_fcc_th = %d\n",
2690 dfs->pri_type1_upp_fcc_th);
2691 } else if (argv[0] == 16) {
2692 dfs->pri_type1_cen_fcc_th = (u8)argv[1];
2693 PDM_SNPF(out_len, used, output + used, out_len - used,
2694 "pri_type1_cen_fcc_th = %d\n",
2695 dfs->pri_type1_cen_fcc_th);
2696 } else if (argv[0] == 17) {
2697 dfs->pw_g0_th = (u8)argv[1];
2698 PDM_SNPF(out_len, used, output + used, out_len - used,
2699 "pw_g0_th = %d\n",
2700 dfs->pw_g0_th);
2701 } else if (argv[0] == 18) {
2702 dfs->pw_long_lower_20m_th = (u8)argv[1];
2703 PDM_SNPF(out_len, used, output + used, out_len - used,
2704 "pw_long_lower_20m_th = %d\n",
2705 dfs->pw_long_lower_20m_th);
2706 } else if (argv[0] == 19) {
2707 dfs->pw_long_lower_th = (u8)argv[1];
2708 PDM_SNPF(out_len, used, output + used, out_len - used,
2709 "pw_long_lower_th = %d\n",
2710 dfs->pw_long_lower_th);
2711 } else if (argv[0] == 20) {
2712 dfs->pri_long_upper_th = (u8)argv[1];
2713 PDM_SNPF(out_len, used, output + used, out_len - used,
2714 "pri_long_upper_th = %d\n",
2715 dfs->pri_long_upper_th);
2716 } else if (argv[0] == 21) {
2717 dfs->pw_long_sum_upper_th = (u8)argv[1];
2718 PDM_SNPF(out_len, used, output + used, out_len - used,
2719 "pw_long_sum_upper_th = %d\n",
2720 dfs->pw_long_sum_upper_th);
2721 } else if (argv[0] == 22) {
2722 dfs->pw_std_th = (u8)argv[1];
2723 PDM_SNPF(out_len, used, output + used, out_len - used,
2724 "pw_std_th = %d\n",
2725 dfs->pw_std_th);
2726 } else if (argv[0] == 23) {
2727 dfs->pw_std_idle_th = (u8)argv[1];
2728 PDM_SNPF(out_len, used, output + used, out_len - used,
2729 "pw_std_idle_th = %d\n",
2730 dfs->pw_std_idle_th);
2731 } else if (argv[0] == 24) {
2732 dfs->pri_std_th = (u8)argv[1];
2733 PDM_SNPF(out_len, used, output + used, out_len - used,
2734 "pri_std_th = %d\n",
2735 dfs->pri_std_th);
2736 } else if (argv[0] == 25) {
2737 dfs->pri_std_idle_th = (u8)argv[1];
2738 PDM_SNPF(out_len, used, output + used, out_len - used,
2739 "pri_std_idle_th = %d\n",
2740 dfs->pri_std_idle_th);
2741 } else if (argv[0] == 26) {
2742 dfs->type4_pw_max_cnt = (u8)argv[1];
2743 PDM_SNPF(out_len, used, output + used, out_len - used,
2744 "type4_pw_max_cnt = %d\n",
2745 dfs->type4_pw_max_cnt);
2746 } else if (argv[0] == 27) {
2747 dfs->type4_safe_pri_sum_th = (u8)argv[1];
2748 PDM_SNPF(out_len, used, output + used, out_len - used,
2749 "type4_safe_pri_sum_th = %d\n",
2750 dfs->type4_safe_pri_sum_th);
2751 } else if (argv[0] == 28) {
2752 dfs->fa_mask_th = (u8)argv[1];
2753 PDM_SNPF(out_len, used, output + used, out_len - used,
2754 "fa_mask_th = %d\n",
2755 dfs->fa_mask_th);
2756 } else if (argv[0] == 29) {
2757 dfs->nhm_cnt_th = (u8)argv[1];
2758 PDM_SNPF(out_len, used, output + used, out_len - used,
2759 "nhm_cnt_th = %d\n",
2760 dfs->nhm_cnt_th);
2761 } else if (argv[0] == 30) {
2762 dfs->nhm_dty_th = (u8)argv[1];
2763 PDM_SNPF(out_len, used, output + used, out_len - used,
2764 "nhm_dty_th = %d\n",
2765 dfs->nhm_dty_th);
2766 } else if (argv[0] == 31) {
2767 dfs->pw_flag_en = (u8)argv[1];
2768 PDM_SNPF(out_len, used, output + used, out_len - used,
2769 "pw_flag_en = %d\n",
2770 dfs->pw_flag_en);
2771 } else if (argv[0] == 32) {
2772 dfs->loct_flag_en = (u8)argv[1];
2773 PDM_SNPF(out_len, used, output + used, out_len - used,
2774 "loct_flag_en = %d\n",
2775 dfs->loct_flag_en);
2776 } else if (argv[0] == 33) {
2777 dfs->pri_flag_en = (u8)argv[1];
2778 PDM_SNPF(out_len, used, output + used, out_len - used,
2779 "pri_flag_en = %d\n",
2780 dfs->pri_flag_en);
2781 } else if (argv[0] == 34) {
2782 dfs->pri_var_offset = (u8)argv[1];
2783 PDM_SNPF(out_len, used, output + used, out_len - used,
2784 "pri_var_offset = %d\n",
2785 dfs->pri_var_offset);
2786 } else if (argv[0] == 35) {
2787 dfs->pri_var_tp_offset = (u8)argv[1];
2788 PDM_SNPF(out_len, used, output + used, out_len - used,
2789 "pri_var_tp_offset = %d\n",
2790 dfs->pri_var_tp_offset);
2791 } else if (argv[0] == 36) {
2792 dfs->pri_cnt_th = (u8)argv[1];
2793 PDM_SNPF(out_len, used, output + used, out_len - used,
2794 "pri_cnt_th = %d\n",
2795 dfs->pri_cnt_th);
2796 } else if (argv[0] == 37) {
2797 dfs->loct_diff_th = (u8)argv[1];
2798 PDM_SNPF(out_len, used, output + used, out_len - used,
2799 "loct_diff_th = %d\n",
2800 dfs->loct_diff_th);
2801 } else if (argv[0] == 38) {
2802 dfs->dc_cnt_th = (u8)argv[1];
2803 PDM_SNPF(out_len, used, output + used, out_len - used,
2804 "dc_cnt_th = %d\n",
2805 dfs->dc_cnt_th);
2806 }
2807 }
2808 *_used = used;
2809 *_out_len = out_len;
2810 }
2811
phydm_dfs_debug(void * dm_void,char input[][16],u32 * _used,char * output,u32 * _out_len)2812 void phydm_dfs_debug(void *dm_void, char input[][16], u32 *_used,
2813 char *output, u32 *_out_len)
2814 {
2815 struct dm_struct *dm = (struct dm_struct *)dm_void;
2816 struct _DFS_STATISTICS *dfs = &dm->dfs;
2817 u32 used = *_used;
2818 u32 out_len = *_out_len;
2819 u32 argv[10] = {0};
2820 u8 i, input_idx = 0;
2821
2822 for (i = 0; i < 10; i++) {
2823 PHYDM_SSCANF(input[i + 1], DCMD_HEX, &argv[i]);
2824 input_idx++;
2825 }
2826
2827 if (input_idx == 0)
2828 return;
2829
2830 dfs->dbg_mode = (boolean)argv[0];
2831 dfs->sw_trigger_mode = (boolean)argv[1];
2832 dfs->force_TP_mode = (boolean)argv[2];
2833 dfs->det_print = (boolean)argv[3];
2834 dfs->det_print2 = (boolean)argv[4];
2835 dfs->print_hist_rpt = (boolean)argv[5];
2836 dfs->hist_cond_on = (boolean)argv[6];
2837 dfs->det_print_jar3 = (boolean)argv[7];
2838 dfs->nhm_dfs_en = (boolean)argv[8];
2839 dfs->det_jar3_en = (boolean)argv[9];
2840
2841 PDM_SNPF(out_len, used, output + used, out_len - used,
2842 "dbg_mode: %d, sw_trigger_mode: %d, force_TP_mode: %d, det_print: %d, det_print2: %d, print_hist_rpt: %d, hist_cond_on: %d\n, det_print_jar3: %d, nhm_dfs_en: %d, dfs->det_jar3_en: %d\n",
2843 dfs->dbg_mode, dfs->sw_trigger_mode, dfs->force_TP_mode,
2844 dfs->det_print, dfs->det_print2, dfs->print_hist_rpt,
2845 dfs->hist_cond_on, dfs->det_print_jar3, dfs->nhm_dfs_en,
2846 dfs->det_jar3_en);
2847 }
2848
phydm_dfs_polling_time(void * dm_void)2849 u8 phydm_dfs_polling_time(void *dm_void)
2850 {
2851 struct dm_struct *dm = (struct dm_struct *)dm_void;
2852 struct _DFS_STATISTICS *dfs = &dm->dfs;
2853
2854 if (dm->support_ic_type & (ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8821C | ODM_RTL8822C | ODM_RTL8723F))
2855 dfs->dfs_polling_time = 40;
2856 else
2857 dfs->dfs_polling_time = 100;
2858
2859 return dfs->dfs_polling_time;
2860 }
2861
2862 #endif /* @defined(CONFIG_PHYDM_DFS_MASTER) */
2863
2864 boolean
phydm_is_dfs_band(void * dm_void)2865 phydm_is_dfs_band(void *dm_void)
2866 {
2867 struct dm_struct *dm = (struct dm_struct *)dm_void;
2868
2869 if (((*dm->channel >= 52) && (*dm->channel <= 64)) ||
2870 ((*dm->channel >= 100) && (*dm->channel <= 144)))
2871 return true;
2872 else
2873 return false;
2874 }
2875
2876 boolean
phydm_dfs_master_enabled(void * dm_void)2877 phydm_dfs_master_enabled(void *dm_void)
2878 {
2879 #ifdef CONFIG_PHYDM_DFS_MASTER
2880 struct dm_struct *dm = (struct dm_struct *)dm_void;
2881 boolean ret_val = false;
2882
2883 if (dm->dfs_master_enabled) /*pointer protection*/
2884 ret_val = *dm->dfs_master_enabled ? true : false;
2885
2886 return ret_val;
2887 #else
2888 return false;
2889 #endif
2890 }
2891
2892 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
2893 #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
phydm_dfs_ap_reset_radar_detect_counter_and_flag(void * dm_void)2894 void phydm_dfs_ap_reset_radar_detect_counter_and_flag(void *dm_void)
2895 {
2896 struct dm_struct *dm = (struct dm_struct *)dm_void;
2897
2898 /* @Clear Radar Counter and Radar flag */
2899 odm_set_bb_reg(dm, R_0xa40, BIT(15), 0);
2900 odm_set_bb_reg(dm, R_0xa40, BIT(15), 1);
2901
2902 /* RT_TRACE(COMP_DFS, DBG_LOUD, ("[DFS], After reset radar counter, 0xcf8 = 0x%x, 0xcf4 = 0x%x\n", */
2903 /* PHY_QueryBBReg(Adapter, 0xcf8, bMaskDWord), */
2904 /* PHY_QueryBBReg(Adapter, 0xcf4, bMaskDWord))); */
2905 }
2906 #endif
2907 #endif
2908