1 /******************************************************************************
2 *
3 * Copyright(c) 2007 - 2017 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26 /*@************************************************************
27 * include files
28 * ************************************************************
29 */
30 #include "mp_precomp.h"
31 #include "phydm_precomp.h"
32
33 #ifdef CFG_DIG_DAMPING_CHK
phydm_dig_recorder_reset(void * dm_void)34 void phydm_dig_recorder_reset(void *dm_void)
35 {
36 struct dm_struct *dm = (struct dm_struct *)dm_void;
37 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
38 struct phydm_dig_recorder_strcut *dig_rc = &dig_t->dig_recorder_t;
39
40 PHYDM_DBG(dm, DBG_DIG, "%s ======>\n", __func__);
41
42 odm_memory_set(dm, &dig_rc->igi_bitmap, 0,
43 sizeof(struct phydm_dig_recorder_strcut));
44 }
45
phydm_dig_recorder(void * dm_void,u8 igi_curr,u32 fa_metrics)46 void phydm_dig_recorder(void *dm_void, u8 igi_curr,
47 u32 fa_metrics)
48 {
49 struct dm_struct *dm = (struct dm_struct *)dm_void;
50 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
51 struct phydm_dig_recorder_strcut *dig_rc = &dig_t->dig_recorder_t;
52 u8 igi_pre = dig_rc->igi_history[0];
53 u8 igi_up = 0;
54
55 if (!dm->is_linked)
56 return;
57
58 PHYDM_DBG(dm, DBG_DIG, "%s ======>\n", __func__);
59
60 if (dm->first_connect) {
61 phydm_dig_recorder_reset(dm);
62 dig_rc->igi_history[0] = igi_curr;
63 dig_rc->fa_history[0] = fa_metrics;
64 return;
65 }
66
67 if (igi_curr % 2)
68 igi_curr--;
69
70 igi_pre = dig_rc->igi_history[0];
71 igi_up = (igi_curr > igi_pre) ? 1 : 0;
72 dig_rc->igi_bitmap = ((dig_rc->igi_bitmap << 1) & 0xfe) | igi_up;
73
74 dig_rc->igi_history[3] = dig_rc->igi_history[2];
75 dig_rc->igi_history[2] = dig_rc->igi_history[1];
76 dig_rc->igi_history[1] = dig_rc->igi_history[0];
77 dig_rc->igi_history[0] = igi_curr;
78
79 dig_rc->fa_history[3] = dig_rc->fa_history[2];
80 dig_rc->fa_history[2] = dig_rc->fa_history[1];
81 dig_rc->fa_history[1] = dig_rc->fa_history[0];
82 dig_rc->fa_history[0] = fa_metrics;
83
84 PHYDM_DBG(dm, DBG_DIG, "igi_history[3:0] = {0x%x, 0x%x, 0x%x, 0x%x}\n",
85 dig_rc->igi_history[3], dig_rc->igi_history[2],
86 dig_rc->igi_history[1], dig_rc->igi_history[0]);
87 PHYDM_DBG(dm, DBG_DIG, "fa_history[3:0] = {%d, %d, %d, %d}\n",
88 dig_rc->fa_history[3], dig_rc->fa_history[2],
89 dig_rc->fa_history[1], dig_rc->fa_history[0]);
90 PHYDM_DBG(dm, DBG_DIG, "igi_bitmap = {%d, %d, %d, %d} = 0x%x\n",
91 (u8)((dig_rc->igi_bitmap & BIT(3)) >> 3),
92 (u8)((dig_rc->igi_bitmap & BIT(2)) >> 2),
93 (u8)((dig_rc->igi_bitmap & BIT(1)) >> 1),
94 (u8)(dig_rc->igi_bitmap & BIT(0)),
95 dig_rc->igi_bitmap);
96 }
97
phydm_dig_damping_chk(void * dm_void)98 void phydm_dig_damping_chk(void *dm_void)
99 {
100 struct dm_struct *dm = (struct dm_struct *)dm_void;
101 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
102 struct phydm_dig_recorder_strcut *dig_rc = &dig_t->dig_recorder_t;
103 u8 igi_bitmap_4bit = dig_rc->igi_bitmap & 0xf;
104 u8 diff1 = 0, diff2 = 0;
105 u32 fa_low_th = dig_t->fa_th[0];
106 u32 fa_high_th = dig_t->fa_th[1];
107 u32 fa_high_th2 = dig_t->fa_th[2];
108 u8 fa_pattern_match = 0;
109 u32 time_tmp = 0;
110
111 if (!dm->is_linked)
112 return;
113
114 PHYDM_DBG(dm, DBG_DIG, "%s ======>\n", __func__);
115
116 /*@== Release Damping ================================================*/
117 if (dig_rc->damping_limit_en) {
118 PHYDM_DBG(dm, DBG_DIG,
119 "[Damping Limit!] limit_time=%d, phydm_sys_up_time=%d\n",
120 dig_rc->limit_time, dm->phydm_sys_up_time);
121
122 time_tmp = dig_rc->limit_time + DIG_LIMIT_PERIOD;
123
124 if (DIFF_2(dm->rssi_min, dig_rc->limit_rssi) > 3 ||
125 time_tmp < dm->phydm_sys_up_time) {
126 dig_rc->damping_limit_en = 0;
127 PHYDM_DBG(dm, DBG_DIG, "rssi_min=%d, limit_rssi=%d\n",
128 dm->rssi_min, dig_rc->limit_rssi);
129 }
130 return;
131 }
132
133 /*@== Damping Pattern Check===========================================*/
134 PHYDM_DBG(dm, DBG_DIG, "fa_th{H, L}= {%d,%d}\n", fa_high_th, fa_low_th);
135
136 switch (igi_bitmap_4bit) {
137 case 0x5:
138 /*@ 4b'0101
139 * IGI:[3]down(0x24)->[2]up(0x26)->[1]down(0x24)->[0]up(0x26)->[new](Lock @ 0x26)
140 * FA: [3] >high1 ->[2] <low ->[1] >high1 ->[0] <low ->[new] <low
141 *
142 * IGI:[3]down(0x24)->[2]up(0x28)->[1]down(0x24)->[0]up(0x28)->[new](Lock @ 0x28)
143 * FA: [3] >high2 ->[2] <low ->[1] >high2 ->[0] <low ->[new] <low
144 */
145 if (dig_rc->igi_history[0] > dig_rc->igi_history[1])
146 diff1 = dig_rc->igi_history[0] - dig_rc->igi_history[1];
147
148 if (dig_rc->igi_history[2] > dig_rc->igi_history[3])
149 diff2 = dig_rc->igi_history[2] - dig_rc->igi_history[3];
150
151 if (dig_rc->fa_history[0] < fa_low_th &&
152 dig_rc->fa_history[1] > fa_high_th &&
153 dig_rc->fa_history[2] < fa_low_th &&
154 dig_rc->fa_history[3] > fa_high_th) {
155 /*@Check each fa element*/
156 fa_pattern_match = 1;
157 }
158 break;
159 case 0x9:
160 /*@ 4b'1001
161 * IGI:[3]up(0x28)->[2]down(0x26)->[1]down(0x24)->[0]up(0x28)->[new](Lock @ 0x28)
162 * FA: [3] <low ->[2] <low ->[1] >high2 ->[0] <low ->[new] <low
163 */
164 if (dig_rc->igi_history[0] > dig_rc->igi_history[1])
165 diff1 = dig_rc->igi_history[0] - dig_rc->igi_history[1];
166
167 if (dig_rc->igi_history[2] < dig_rc->igi_history[3])
168 diff2 = dig_rc->igi_history[3] - dig_rc->igi_history[2];
169
170 if (dig_rc->fa_history[0] < fa_low_th &&
171 dig_rc->fa_history[1] > fa_high_th2 &&
172 dig_rc->fa_history[2] < fa_low_th &&
173 dig_rc->fa_history[3] < fa_low_th) {
174 /*@Check each fa element*/
175 fa_pattern_match = 1;
176 }
177 break;
178 default:
179 break;
180 }
181
182 if (diff1 >= 2 && diff2 >= 2 && fa_pattern_match) {
183 dig_rc->damping_limit_en = 1;
184 dig_rc->damping_limit_val = dig_rc->igi_history[0];
185 dig_rc->limit_time = dm->phydm_sys_up_time;
186 dig_rc->limit_rssi = dm->rssi_min;
187
188 PHYDM_DBG(dm, DBG_DIG,
189 "[Start damping_limit!] IGI_dyn_min=0x%x, limit_time=%d, limit_rssi=%d\n",
190 dig_rc->damping_limit_val,
191 dig_rc->limit_time, dig_rc->limit_rssi);
192 }
193
194 PHYDM_DBG(dm, DBG_DIG, "damping_limit=%d\n", dig_rc->damping_limit_en);
195 }
196 #endif
197
phydm_fa_threshold_check(void * dm_void,boolean is_dfs_band)198 void phydm_fa_threshold_check(void *dm_void, boolean is_dfs_band)
199 {
200 struct dm_struct *dm = (struct dm_struct *)dm_void;
201 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
202 u8 i = 0;
203
204 dig_t->dm_dig_fa_th1 = DM_DIG_FA_TH1;
205
206 if (dig_t->is_dbg_fa_th) {
207 PHYDM_DBG(dm, DBG_DIG, "Manual Fix FA_th\n");
208 } else if (dm->is_linked) {
209 if (dm->rssi_min < 20) { /*@[PHYDM-252]*/
210 dig_t->fa_th[0] = 500;
211 dig_t->fa_th[1] = 750;
212 dig_t->fa_th[2] = 1000;
213 } else if (((dm->rx_tp >> 2) > dm->tx_tp) && /*Test RX TP*/
214 (dm->rx_tp < 10) && (dm->rx_tp > 1)) { /*TP=1~10Mb*/
215 dig_t->fa_th[0] = 125;
216 dig_t->fa_th[1] = 250;
217 dig_t->fa_th[2] = 500;
218 } else {
219 dig_t->fa_th[0] = 250;
220 dig_t->fa_th[1] = 500;
221 dig_t->fa_th[2] = 750;
222 }
223 } else {
224 if (is_dfs_band) { /* @For DFS band and no link */
225
226 dig_t->fa_th[0] = 250;
227 dig_t->fa_th[1] = 1000;
228 dig_t->fa_th[2] = 2000;
229 } else {
230 dig_t->fa_th[0] = 2000;
231 dig_t->fa_th[1] = 4000;
232 dig_t->fa_th[2] = 5000;
233 }
234 }
235
236 if ((dig_t->fa_source >= 1) && (dig_t->fa_source <= 3)) {
237 for (i = 0; i < 3; i++)
238 dig_t->fa_th[i] *= OFDM_FA_EXP_DURATION;
239
240 dig_t->dm_dig_fa_th1 *= OFDM_FA_EXP_DURATION;
241 }
242
243 PHYDM_DBG(dm, DBG_DIG, "FA_th={%d,%d,%d}\n", dig_t->fa_th[0],
244 dig_t->fa_th[1], dig_t->fa_th[2]);
245 }
246
phydm_set_big_jump_step(void * dm_void,u8 curr_igi)247 void phydm_set_big_jump_step(void *dm_void, u8 curr_igi)
248 {
249 #if (RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8192F_SUPPORT)
250 struct dm_struct *dm = (struct dm_struct *)dm_void;
251 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
252 u8 step1[8] = {24, 30, 40, 50, 60, 70, 80, 90};
253 u8 big_jump_lmt = dig_t->big_jump_lmt[dig_t->agc_table_idx];
254 u8 i;
255
256 if (dig_t->enable_adjust_big_jump == 0)
257 return;
258
259 for (i = 0; i <= dig_t->big_jump_step1; i++) {
260 if ((curr_igi + step1[i]) > big_jump_lmt) {
261 if (i != 0)
262 i = i - 1;
263 break;
264 } else if (i == dig_t->big_jump_step1) {
265 break;
266 }
267 }
268 if (dm->support_ic_type & ODM_RTL8822B)
269 odm_set_bb_reg(dm, R_0x8c8, 0xe, i);
270 else if (dm->support_ic_type & (ODM_RTL8197F | ODM_RTL8192F))
271 odm_set_bb_reg(dm, ODM_REG_BB_AGC_SET_2_11N, 0xe, i);
272
273 PHYDM_DBG(dm, DBG_DIG, "Bigjump = %d (ori = 0x%x), LMT=0x%x\n", i,
274 dig_t->big_jump_step1, big_jump_lmt);
275 #endif
276 }
277
278 #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
phydm_write_dig_reg_jgr3(void * dm_void,u8 igi)279 void phydm_write_dig_reg_jgr3(void *dm_void, u8 igi)
280 {
281 struct dm_struct *dm = (struct dm_struct *)dm_void;
282 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
283
284 PHYDM_DBG(dm, DBG_DIG, "%s===>\n", __func__);
285
286 /* Set IGI value */
287 if (!(dm->support_ic_type & ODM_IC_JGR3_SERIES))
288 return;
289
290 odm_set_bb_reg(dm, R_0x1d70, ODM_BIT_IGI_11AC, igi);
291
292 #if (defined(PHYDM_COMPILE_ABOVE_2SS))
293 if (dm->support_ic_type & PHYDM_IC_ABOVE_2SS)
294 odm_set_bb_reg(dm, R_0x1d70, ODM_BIT_IGI_B_11AC3, igi);
295 #endif
296
297 #if (defined(PHYDM_COMPILE_ABOVE_4SS))
298 if (dm->support_ic_type & PHYDM_IC_ABOVE_4SS) {
299 odm_set_bb_reg(dm, R_0x1d70, ODM_BIT_IGI_C_11AC3, igi);
300 odm_set_bb_reg(dm, R_0x1d70, ODM_BIT_IGI_D_11AC3, igi);
301 }
302 #endif
303 }
304
phydm_get_igi_reg_val_jgr3(void * dm_void,enum bb_path path)305 u8 phydm_get_igi_reg_val_jgr3(void *dm_void, enum bb_path path)
306 {
307 struct dm_struct *dm = (struct dm_struct *)dm_void;
308 u32 val = 0;
309
310 PHYDM_DBG(dm, DBG_DIG, "%s===>\n", __func__);
311
312 /* Set IGI value */
313 if (!(dm->support_ic_type & ODM_IC_JGR3_SERIES))
314 return (u8)val;
315
316 if (path == BB_PATH_A)
317 val = odm_get_bb_reg(dm, R_0x1d70, ODM_BIT_IGI_11AC);
318 #if (defined(PHYDM_COMPILE_ABOVE_2SS))
319 else if (path == BB_PATH_B)
320 val = odm_get_bb_reg(dm, R_0x1d70, ODM_BIT_IGI_B_11AC3);
321 #endif
322
323 #if (defined(PHYDM_COMPILE_ABOVE_3SS))
324 else if (path == BB_PATH_C)
325 val = odm_get_bb_reg(dm, R_0x1d70, ODM_BIT_IGI_C_11AC3);
326 #endif
327
328 #if (defined(PHYDM_COMPILE_ABOVE_4SS))
329 else if (path == BB_PATH_D)
330 val = odm_get_bb_reg(dm, R_0x1d70, ODM_BIT_IGI_D_11AC3);
331 #endif
332 return (u8)val;
333 }
334
phydm_fa_cnt_statistics_jgr3(void * dm_void)335 void phydm_fa_cnt_statistics_jgr3(void *dm_void)
336 {
337 struct dm_struct *dm = (struct dm_struct *)dm_void;
338 struct phydm_fa_struct *fa_t = &dm->false_alm_cnt;
339 u32 ret_value = 0;
340 u32 cck_enable = 0;
341
342 if (!(dm->support_ic_type & ODM_IC_JGR3_SERIES))
343 return;
344
345 ret_value = odm_get_bb_reg(dm, R_0x2de4, MASKDWORD);
346 fa_t->cnt_cck_txen = (ret_value & 0xffff);
347 fa_t->cnt_cck_txon = ((ret_value & 0xffff0000) >> 16);
348 ret_value = odm_get_bb_reg(dm, R_0x2de0, MASKDWORD);
349 fa_t->cnt_ofdm_txen = (ret_value & 0xffff);
350 fa_t->cnt_ofdm_txon = ((ret_value & 0xffff0000) >> 16);
351
352 ret_value = odm_get_bb_reg(dm, R_0x2d20, MASKDWORD);
353 fa_t->cnt_fast_fsync = ret_value & 0xffff;
354 fa_t->cnt_sb_search_fail = (ret_value & 0xffff0000) >> 16;
355
356 ret_value = odm_get_bb_reg(dm, R_0x2d04, MASKDWORD);
357 fa_t->cnt_parity_fail = (ret_value & 0xffff0000) >> 16;
358
359 ret_value = odm_get_bb_reg(dm, R_0x2d08, MASKDWORD);
360 fa_t->cnt_rate_illegal = ret_value & 0xffff;
361 fa_t->cnt_crc8_fail = (ret_value & 0xffff0000) >> 16;
362
363 ret_value = odm_get_bb_reg(dm, R_0x2d10, MASKDWORD);
364 fa_t->cnt_mcs_fail = ret_value & 0xffff;
365
366 /* read CCK CRC32 counter */
367 if (dm->support_ic_type & ODM_RTL8723F)
368 ret_value = odm_get_bb_reg(dm, R_0x2aac, MASKDWORD);
369 else
370 ret_value = odm_get_bb_reg(dm, R_0x2c04, MASKDWORD);
371 fa_t->cnt_cck_crc32_ok = ret_value & 0xffff;
372 fa_t->cnt_cck_crc32_error = (ret_value & 0xffff0000) >> 16;
373
374 /* read OFDM CRC32 counter */
375 ret_value = odm_get_bb_reg(dm, R_0x2c14, MASKDWORD);
376 fa_t->cnt_ofdm_crc32_ok = ret_value & 0xffff;
377 fa_t->cnt_ofdm_crc32_error = (ret_value & 0xffff0000) >> 16;
378
379 /* read OFDM2 CRC32 counter */
380 ret_value = odm_get_bb_reg(dm, R_0x2c1c, MASKDWORD);
381 fa_t->cnt_ofdm2_crc32_ok = ret_value & 0xffff;
382 fa_t->cnt_ofdm2_crc32_error = (ret_value & 0xffff0000) >> 16;
383
384 /* read HT CRC32 counter */
385 ret_value = odm_get_bb_reg(dm, R_0x2c10, MASKDWORD);
386 fa_t->cnt_ht_crc32_ok = ret_value & 0xffff;
387 fa_t->cnt_ht_crc32_error = (ret_value & 0xffff0000) >> 16;
388
389 /* read HT2 CRC32 counter */
390 ret_value = odm_get_bb_reg(dm, R_0x2c18, MASKDWORD);
391 fa_t->cnt_ht2_crc32_ok = ret_value & 0xffff;
392 fa_t->cnt_ht2_crc32_error = (ret_value & 0xffff0000) >> 16;
393
394 /*for VHT part */
395 if (dm->support_ic_type & (ODM_RTL8822C | ODM_RTL8812F |
396 ODM_RTL8814B | ODM_RTL8814C)) {
397 /*read VHT CRC32 counter */
398 ret_value = odm_get_bb_reg(dm, R_0x2c0c, MASKDWORD);
399 fa_t->cnt_vht_crc32_ok = ret_value & 0xffff;
400 fa_t->cnt_vht_crc32_error = (ret_value & 0xffff0000) >> 16;
401
402 /*read VHT2 CRC32 counter */
403 ret_value = odm_get_bb_reg(dm, R_0x2c54, MASKDWORD);
404 fa_t->cnt_vht2_crc32_ok = ret_value & 0xffff;
405 fa_t->cnt_vht2_crc32_error = (ret_value & 0xffff0000) >> 16;
406
407 ret_value = odm_get_bb_reg(dm, R_0x2d10, MASKDWORD);
408 fa_t->cnt_mcs_fail_vht = (ret_value & 0xffff0000) >> 16;
409
410 ret_value = odm_get_bb_reg(dm, R_0x2d0c, MASKDWORD);
411 fa_t->cnt_crc8_fail_vhta = ret_value & 0xffff;
412 fa_t->cnt_crc8_fail_vhtb = (ret_value & 0xffff0000) >> 16;
413 } else {
414 fa_t->cnt_vht_crc32_error = 0;
415 fa_t->cnt_vht_crc32_ok = 0;
416 fa_t->cnt_vht2_crc32_error = 0;
417 fa_t->cnt_vht2_crc32_ok = 0;
418 fa_t->cnt_mcs_fail_vht = 0;
419 fa_t->cnt_crc8_fail_vhta = 0;
420 fa_t->cnt_crc8_fail_vhtb = 0;
421 }
422
423 /* @calculate OFDM FA counter instead of reading brk_cnt*/
424 fa_t->cnt_ofdm_fail = fa_t->cnt_parity_fail + fa_t->cnt_rate_illegal +
425 fa_t->cnt_crc8_fail + fa_t->cnt_mcs_fail +
426 fa_t->cnt_fast_fsync + fa_t->cnt_sb_search_fail +
427 fa_t->cnt_mcs_fail_vht + fa_t->cnt_crc8_fail_vhta;
428
429 /* Read CCK FA counter */
430 if (dm->support_ic_type & ODM_RTL8723F){
431 ret_value= odm_get_bb_reg(dm, R_0x2aa8, MASKLWORD);
432 fa_t->cnt_cck_fail=(ret_value&0xffff)+((ret_value&0xffff0000)>>16);
433 }
434 else
435 fa_t->cnt_cck_fail = odm_get_bb_reg(dm, R_0x1a5c, MASKLWORD);
436
437 /* read CCK/OFDM CCA counter */
438 ret_value = odm_get_bb_reg(dm, R_0x2c08, MASKDWORD);
439 fa_t->cnt_ofdm_cca = ((ret_value & 0xffff0000) >> 16);
440 if (dm->support_ic_type & ODM_RTL8723F)
441 ret_value = odm_get_bb_reg(dm, R_0x2aa0, MASKDWORD);
442 fa_t->cnt_cck_cca = ret_value & 0xffff;
443
444 /* @CCK RxIQ weighting = 1 => 0x1a14[9:8]=0x0 */
445 if (dm->support_ic_type & ODM_RTL8723F)
446 cck_enable = odm_get_bb_reg(dm, R_0x2a24, BIT(13));
447 else
448 cck_enable = odm_get_bb_reg(dm, R_0x1a14, 0x300);
449
450 if (cck_enable == 0x0) { /* @if(*dm->band_type == ODM_BAND_2_4G) */
451 fa_t->cnt_all = fa_t->cnt_ofdm_fail + fa_t->cnt_cck_fail;
452 fa_t->cnt_cca_all = fa_t->cnt_cck_cca + fa_t->cnt_ofdm_cca;
453 } else {
454 fa_t->cnt_all = fa_t->cnt_ofdm_fail;
455 fa_t->cnt_cca_all = fa_t->cnt_ofdm_cca;
456 }
457 }
458
459 #endif
460
phydm_write_dig_reg_c50(void * dm_void,u8 igi)461 void phydm_write_dig_reg_c50(void *dm_void, u8 igi)
462 {
463 struct dm_struct *dm = (struct dm_struct *)dm_void;
464
465 PHYDM_DBG(dm, DBG_DIG, "%s===>\n", __func__);
466
467 odm_set_bb_reg(dm, ODM_REG(IGI_A, dm), ODM_BIT(IGI, dm), igi);
468
469 #if (defined(PHYDM_COMPILE_ABOVE_2SS))
470 if (dm->support_ic_type & PHYDM_IC_ABOVE_2SS)
471 odm_set_bb_reg(dm, ODM_REG(IGI_B, dm), ODM_BIT(IGI, dm), igi);
472 #endif
473
474 #if (defined(PHYDM_COMPILE_ABOVE_4SS))
475 if (dm->support_ic_type & PHYDM_IC_ABOVE_4SS) {
476 odm_set_bb_reg(dm, ODM_REG(IGI_C, dm), ODM_BIT(IGI, dm), igi);
477 odm_set_bb_reg(dm, ODM_REG(IGI_D, dm), ODM_BIT(IGI, dm), igi);
478 }
479 #endif
480 }
481
phydm_write_dig_reg(void * dm_void,u8 igi)482 void phydm_write_dig_reg(void *dm_void, u8 igi)
483 {
484 struct dm_struct *dm = (struct dm_struct *)dm_void;
485 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
486 u8 rf_gain = 0;
487
488 PHYDM_DBG(dm, DBG_DIG, "%s===>\n", __func__);
489
490 #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
491 if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
492 phydm_write_dig_reg_jgr3(dm, igi);
493 else
494 #endif
495 phydm_write_dig_reg_c50(dm, igi);
496
497 #if (RTL8721D_SUPPORT)
498 if (dm->invalid_mode) {
499 if (igi <= 0x10)
500 rf_gain = 0xfa;
501 else if (igi <= 0x40)
502 rf_gain = 0xe3 + 0x20 - (igi >> 1);
503 else if (igi <= 0x50)
504 rf_gain = 0xcb - (igi >> 1);
505 else if (igi <= 0x5e)
506 rf_gain = 0x92 - (igi >> 1);
507 else if (igi <= 0x64)
508 rf_gain = 0x74 - (igi >> 1);
509 else
510 rf_gain = (0x3d > (igi >> 1)) ? (0x3d - (igi >> 1)) : 0;
511 odm_set_bb_reg(dm, R_0x850, 0x1fe0, rf_gain);
512 }
513 #endif
514
515 if (igi == dig_t->cur_ig_value)
516 dig_t->igi_trend = DIG_STABLE;
517 else if (igi > dig_t->cur_ig_value)
518 dig_t->igi_trend = DIG_INCREASING;
519 else
520 dig_t->igi_trend = DIG_DECREASING;
521
522 PHYDM_DBG(dm, DBG_DIG, "Update IGI:0x%x -> 0x%x\n",
523 dig_t->cur_ig_value, igi);
524
525 dig_t->cur_ig_value = igi;
526 }
527
odm_write_dig(void * dm_void,u8 new_igi)528 void odm_write_dig(void *dm_void, u8 new_igi)
529 {
530 struct dm_struct *dm = (struct dm_struct *)dm_void;
531 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
532 struct phydm_adaptivity_struct *adaptivity = &dm->adaptivity;
533
534 PHYDM_DBG(dm, DBG_DIG, "%s===>\n", __func__);
535
536 /* @1 Check IGI by upper bound */
537 if (adaptivity->igi_lmt_en &&
538 new_igi > adaptivity->adapt_igi_up && dm->is_linked) {
539 new_igi = adaptivity->adapt_igi_up;
540
541 PHYDM_DBG(dm, DBG_DIG, "Force Adaptivity Up-bound=((0x%x))\n",
542 new_igi);
543 }
544
545 #if (RTL8192F_SUPPORT)
546 if ((dm->support_ic_type & ODM_RTL8192F) &&
547 dm->cut_version == ODM_CUT_A &&
548 new_igi > 0x38) {
549 new_igi = 0x38;
550 PHYDM_DBG(dm, DBG_DIG,
551 "Force 92F Adaptivity Up-bound=((0x%x))\n", new_igi);
552 }
553 #endif
554
555 if (dig_t->cur_ig_value != new_igi) {
556 #if (RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8192F_SUPPORT)
557 /* @Modify big jump step for 8822B and 8197F */
558 if (dm->support_ic_type &
559 (ODM_RTL8822B | ODM_RTL8197F | ODM_RTL8192F))
560 phydm_set_big_jump_step(dm, new_igi);
561 #endif
562
563 #if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT)
564 /* Set IGI value of CCK for new CCK AGC */
565 if (dm->cck_new_agc &&
566 (dm->support_ic_type & PHYSTS_2ND_TYPE_IC))
567 odm_set_bb_reg(dm, R_0xa0c, 0x3f00, (new_igi >> 1));
568 #endif
569
570 /*@Add by YuChen for USB IO too slow issue*/
571 if (*dm->edcca_mode == PHYDM_EDCCA_ADAPT_MODE) {
572 if (!(dm->support_ic_type & ODM_IC_PWDB_EDCCA)) {
573 if (new_igi < dig_t->cur_ig_value ||
574 dm->is_pause_dig) {
575 dig_t->cur_ig_value = new_igi;
576 adaptivity->is_adapt_by_dig = true;
577 phydm_adaptivity(dm);
578 }
579 } else {
580 if (new_igi > dig_t->cur_ig_value) {
581 dig_t->cur_ig_value = new_igi;
582 adaptivity->is_adapt_by_dig = true;
583 phydm_adaptivity(dm);
584 }
585 }
586 }
587 adaptivity->is_adapt_by_dig = false;
588 phydm_write_dig_reg(dm, new_igi);
589 } else {
590 dig_t->igi_trend = DIG_STABLE;
591 }
592
593 PHYDM_DBG(dm, DBG_DIG, "[%s]New_igi=((0x%x))\n\n",
594 ((dig_t->igi_trend == DIG_STABLE) ? "=" :
595 ((dig_t->igi_trend == DIG_INCREASING) ? "+" : "-")),
596 new_igi);
597 }
598
phydm_get_igi_reg_val(void * dm_void,enum bb_path path)599 u8 phydm_get_igi_reg_val(void *dm_void, enum bb_path path)
600 {
601 struct dm_struct *dm = (struct dm_struct *)dm_void;
602 u32 val = 0;
603 u32 bit_map = ODM_BIT(IGI, dm);
604
605 switch (path) {
606 case BB_PATH_A:
607 val = odm_get_bb_reg(dm, ODM_REG(IGI_A, dm), bit_map);
608 break;
609 #if (defined(PHYDM_COMPILE_ABOVE_2SS))
610 case BB_PATH_B:
611 val = odm_get_bb_reg(dm, ODM_REG(IGI_B, dm), bit_map);
612 break;
613 #endif
614
615 #if (defined(PHYDM_COMPILE_ABOVE_3SS))
616 case BB_PATH_C:
617 val = odm_get_bb_reg(dm, ODM_REG(IGI_C, dm), bit_map);
618 break;
619 #endif
620
621 #if (defined(PHYDM_COMPILE_ABOVE_4SS))
622 case BB_PATH_D:
623 val = odm_get_bb_reg(dm, ODM_REG(IGI_D, dm), bit_map);
624 break;
625 #endif
626
627 default:
628 break;
629 }
630
631 return (u8)val;
632 }
633
phydm_get_igi(void * dm_void,enum bb_path path)634 u8 phydm_get_igi(void *dm_void, enum bb_path path)
635 {
636 struct dm_struct *dm = (struct dm_struct *)dm_void;
637 u8 val = 0;
638
639 #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
640 if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
641 val = phydm_get_igi_reg_val_jgr3(dm, path);
642 else
643 #endif
644 val = phydm_get_igi_reg_val(dm, path);
645
646 return val;
647 }
648
phydm_set_dig_val(void * dm_void,u32 * val_buf,u8 val_len)649 void phydm_set_dig_val(void *dm_void, u32 *val_buf, u8 val_len)
650 {
651 struct dm_struct *dm = (struct dm_struct *)dm_void;
652
653 if (val_len != 1) {
654 PHYDM_DBG(dm, ODM_COMP_API, "[Error][DIG]Need val_len=1\n");
655 return;
656 }
657
658 odm_write_dig(dm, (u8)(*val_buf));
659 }
660
odm_pause_dig(void * dm_void,enum phydm_pause_type type,enum phydm_pause_level lv,u8 igi_input)661 void odm_pause_dig(void *dm_void, enum phydm_pause_type type,
662 enum phydm_pause_level lv, u8 igi_input)
663 {
664 struct dm_struct *dm = (struct dm_struct *)dm_void;
665 u8 rpt = false;
666 u32 igi = (u32)igi_input;
667
668 PHYDM_DBG(dm, DBG_DIG, "[%s]type=%d, LV=%d, igi=0x%x\n", __func__, type,
669 lv, igi);
670
671 switch (type) {
672 case PHYDM_PAUSE:
673 case PHYDM_PAUSE_NO_SET: {
674 dm->is_pause_dig = true;
675 rpt = phydm_pause_func(dm, F00_DIG, PHYDM_PAUSE, lv, 1, &igi);
676 break;
677 }
678
679 case PHYDM_RESUME: {
680 rpt = phydm_pause_func(dm, F00_DIG, PHYDM_RESUME, lv, 1, &igi);
681 dm->is_pause_dig = false;
682 break;
683 }
684 default:
685 PHYDM_DBG(dm, DBG_DIG, "Wrong type\n");
686 break;
687 }
688
689 PHYDM_DBG(dm, DBG_DIG, "DIG pause_result=%d\n", rpt);
690 }
691
692 boolean
phydm_dig_abort(void * dm_void)693 phydm_dig_abort(void *dm_void)
694 {
695 struct dm_struct *dm = (struct dm_struct *)dm_void;
696 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
697 void *adapter = dm->adapter;
698 #endif
699
700 /* support_ability */
701 if ((!(dm->support_ability & ODM_BB_FA_CNT)) ||
702 (!(dm->support_ability & ODM_BB_DIG))) {
703 PHYDM_DBG(dm, DBG_DIG, "[DIG] Not Support\n");
704 return true;
705 }
706
707 if (dm->pause_ability & ODM_BB_DIG) {
708 PHYDM_DBG(dm, DBG_DIG, "Return: Pause DIG in LV=%d\n",
709 dm->pause_lv_table.lv_dig);
710 return true;
711 }
712
713 if (*dm->is_scan_in_process) {
714 PHYDM_DBG(dm, DBG_DIG, "Return: Scan in process\n");
715 return true;
716 }
717
718 if (dm->dm_dig_table.fw_dig_enable) {
719 PHYDM_DBG(dm, DBG_DIG, "Return: FW DIG enable\n");
720 return true;
721 }
722
723 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
724 #if OS_WIN_FROM_WIN7(OS_VERSION)
725 if (IsAPModeExist(adapter) && ((PADAPTER)(adapter))->bInHctTest) {
726 PHYDM_DBG(dm, DBG_DIG, " Return: Is AP mode or In HCT Test\n");
727 return true;
728 }
729 #endif
730 #endif
731
732 return false;
733 }
734
735 #ifdef PHYDM_HW_IGI
736 #ifdef BB_RAM_SUPPORT
phydm_rd_hwigi_pre_setting(void * dm_void,u32 * _used,char * output,u32 * _out_len)737 void phydm_rd_hwigi_pre_setting(void *dm_void, u32 *_used, char *output,
738 u32 *_out_len)
739 {
740 struct dm_struct *dm = (struct dm_struct *)dm_void;
741 u32 used = *_used;
742 u32 out_len = *_out_len;
743 u8 igi_ofst = 0x0;
744 u32 t1, t2, t3 = 0x0;
745
746 igi_ofst = (u8)odm_get_bb_reg(dm, R_0x1e80, MASKBYTE0);
747 t1 = odm_get_bb_reg(dm, R_0x1e80, MASKBYTE1) * 400;
748 t2 = odm_get_bb_reg(dm, R_0x1e80, MASKBYTE2) * 400;
749 t3 = odm_get_bb_reg(dm, R_0x1e80, MASKBYTE3) * 400;
750
751 PDM_SNPF(out_len, used, output + used, out_len - used,
752 "igi_offset:0x%x, t1:%d(ns), t2:%d(ns), t3:%d(ns)\n",
753 igi_ofst, t1, t2, t3);
754 }
755
phydm_set_hwigi_pre_setting(void * dm_void,u8 igi_ofst,u8 t1,u8 t2,u8 t3)756 void phydm_set_hwigi_pre_setting(void *dm_void, u8 igi_ofst, u8 t1, u8 t2,
757 u8 t3)
758 {
759 struct dm_struct *dm = (struct dm_struct *)dm_void;
760 u32 reg_0x1e80 = 0;
761
762 reg_0x1e80 = igi_ofst + (t1 << 8) + (t2 << 16) + (t3 << 24);
763 odm_set_bb_reg(dm, R_0x1e80, MASKDWORD, reg_0x1e80);
764 }
765
phydm_rd_hwigi_table(void * dm_void,u8 macid,u32 * _used,char * output,u32 * _out_len)766 void phydm_rd_hwigi_table(void *dm_void, u8 macid, u32 *_used, char *output,
767 u32 *_out_len)
768 {
769 struct dm_struct *dm = (struct dm_struct *)dm_void;
770 u32 used = *_used;
771 u32 out_len = *_out_len;
772 boolean hwigi_en = false;
773 u8 hwigi = 0x0;
774 u8 hwigi_rx_offset = 0x0;
775 u32 reg_0x1e84 = 0x0;
776
777 reg_0x1e84 |= (macid & 0x3f) << 24; /*macid*/
778 reg_0x1e84 |= BIT(31); /*read_en*/
779 odm_set_bb_reg(dm, R_0x1e84, MASKDWORD, reg_0x1e84);
780
781 hwigi_en = (boolean)odm_get_bb_reg(dm, R_0x2de8, BIT(15));
782 hwigi = (u8)odm_get_bb_reg(dm, R_0x2de8, 0x7f00);
783 odm_set_bb_reg(dm, R_0x1e84, MASKDWORD, 0x0); /* disable rd/wt*/
784
785 PDM_SNPF(out_len, used, output + used, out_len - used,
786 "(macid:%d) hwigi_en:%d, hwigi:0x%x\n", macid, hwigi_en,
787 hwigi);
788
789 *_used = used;
790 *_out_len = out_len;
791 }
792
phydm_wt_hwigi_table(void * dm_void,u8 macid,boolean hwigi_en,u8 hwigi)793 void phydm_wt_hwigi_table(void *dm_void, u8 macid, boolean hwigi_en, u8 hwigi)
794 {
795 struct dm_struct *dm = (struct dm_struct *)dm_void;
796 struct phydm_bb_ram_per_sta *dm_ram_per_sta = NULL;
797 u32 reg_0x1e84 = 0;
798
799 if (macid > 63)
800 macid = 63;
801
802 dm_ram_per_sta = &dm->p_bb_ram_ctrl.pram_sta_ctrl[macid];
803 dm_ram_per_sta->hw_igi_en = hwigi_en;
804 dm_ram_per_sta->hw_igi = hwigi;
805
806 reg_0x1e84 = (dm_ram_per_sta->tx_pwr_offset0_en << 15) +
807 ((dm_ram_per_sta->tx_pwr_offset0 & 0x7f) << 8) +
808 (dm_ram_per_sta->tx_pwr_offset1_en << 23) +
809 ((dm_ram_per_sta->tx_pwr_offset1 & 0x7f) << 16);
810
811 reg_0x1e84 |= (hwigi_en << 7) + (hwigi & 0x7f);
812 reg_0x1e84 |= (macid & 0x3f) << 24;/*macid*/
813 reg_0x1e84 |= BIT(30); /*write_en*/
814 odm_set_bb_reg(dm, R_0x1e84, MASKDWORD, reg_0x1e84);
815 odm_set_bb_reg(dm, R_0x1e84, MASKDWORD, 0x80000000); /*read_en*/
816 odm_set_bb_reg(dm, R_0x1e84, MASKDWORD, 0x0); /*disable rd/wt*/
817 }
818
phydm_rst_hwigi(void * dm_void)819 void phydm_rst_hwigi(void *dm_void)
820 {
821 struct dm_struct *dm = (struct dm_struct *)dm_void;
822 struct phydm_bb_ram_per_sta *dm_ram_per_sta = NULL;
823 u32 reg_0x1e84 = 0;
824 u8 i = 0;
825
826 PHYDM_DBG(dm, DBG_DIG, "reset hwigi!\n");
827
828 for (i = 0; i < 64; i++) {
829 dm_ram_per_sta = &dm->p_bb_ram_ctrl.pram_sta_ctrl[i];
830 dm_ram_per_sta->hw_igi_en = false;
831 dm_ram_per_sta->hw_igi = 0x0;
832
833 reg_0x1e84 = (dm_ram_per_sta->tx_pwr_offset0_en << 15) +
834 ((dm_ram_per_sta->tx_pwr_offset0 & 0x7f) << 8) +
835 (dm_ram_per_sta->tx_pwr_offset1_en << 23) +
836 ((dm_ram_per_sta->tx_pwr_offset1 & 0x7f) << 16);
837
838 reg_0x1e84 |= (i & 0x3f) << 24;
839 reg_0x1e84 |= BIT(30);
840 odm_set_bb_reg(dm, R_0x1e84, MASKDWORD, reg_0x1e84);
841 }
842
843 odm_set_bb_reg(dm, R_0x1e84, MASKDWORD, 0x80000000);
844 odm_set_bb_reg(dm, R_0x1e84, MASKDWORD, 0x0);
845 }
846
phydm_hwigi_init(void * dm_void)847 void phydm_hwigi_init(void *dm_void)
848 {
849 struct dm_struct *dm = (struct dm_struct *)dm_void;
850 struct phydm_bb_ram_ctrl *bb_ctrl = &dm->p_bb_ram_ctrl;
851 u8 igi_ofst = 0x0;
852 u8 t1 = 0x0;
853 u8 t2 = 0x0;
854 u8 t3 = 0x0;
855
856 t1 = 0x55; /*34 us*/
857 t3 = 0x55; /*34 us*/
858
859 bb_ctrl->hwigi_watchdog_en = false;
860
861 if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
862 phydm_set_hwigi_pre_setting(dm, igi_ofst, t1, t2, t3);
863 }
864
phydm_hwigi(void * dm_void)865 void phydm_hwigi(void *dm_void)
866 {
867 struct dm_struct *dm = (struct dm_struct *)dm_void;
868 struct cmn_sta_info *sta = NULL;
869 struct phydm_bb_ram_per_sta *dm_ram_per_sta = NULL;
870 struct rssi_info *rssi = NULL;
871 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
872 struct phydm_bb_ram_ctrl *bb_ctrl = &dm->p_bb_ram_ctrl;
873 u8 sta_cnt = 0;
874 u8 i = 0;
875 u8 hwigi = 0x0;
876 u8 macid = 0;
877 u8 macid_cnt = 0;
878 u64 macid_cur = 0;
879 u64 macid_diff = 0;
880 u64 macid_mask = 0;
881
882 if (!(dm->support_ic_type & ODM_IC_JGR3_SERIES))
883 return;
884
885 if (!(bb_ctrl->hwigi_watchdog_en)) {
886 return;
887 }
888
889 for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
890 sta = dm->phydm_sta_info[i];
891 if (is_sta_active(sta)) {
892 sta_cnt++;
893
894 if (sta->mac_id > 63)
895 macid = 63;
896 else
897 macid = sta->mac_id;
898
899 dm_ram_per_sta = &bb_ctrl->pram_sta_ctrl[macid];
900 rssi = &sta->rssi_stat;
901 macid_mask = (u64)BIT(sta->mac_id);
902 bb_ctrl->hwigi_macid_is_linked |= macid_mask;
903 macid_cur |= macid_mask;
904 PHYDM_DBG(dm, DBG_DIG,
905 "STA_id=%d, MACID=%d, RSSI=%d, hwigi_en=%d, hwigi=0x%x\n",
906 i, sta->mac_id, rssi->rssi,
907 dm_ram_per_sta->hw_igi_en,
908 dm_ram_per_sta->hw_igi);
909
910 hwigi = MAX_2((u8)(rssi->rssi + 10),
911 dig_t->cur_ig_value);
912
913 if (hwigi > DIG_MAX_PERFORMANCE_MODE)
914 hwigi = DIG_MAX_PERFORMANCE_MODE;
915 else if (hwigi < DIG_MIN_PERFORMANCE)
916 hwigi = DIG_MIN_PERFORMANCE;
917
918 if (dm_ram_per_sta->hw_igi == hwigi) {
919 PHYDM_DBG(dm, DBG_DIG,
920 "hwigi not change!\n");
921 } else {
922
923 PHYDM_DBG(dm, DBG_DIG,
924 "hwigi update: ((0x%x)) -> ((0x%x))\n",
925 dm_ram_per_sta->hw_igi, hwigi);
926
927 phydm_wt_hwigi_table(dm, sta->mac_id, true, hwigi);
928 }
929
930 if (sta_cnt == dm->number_linked_client)
931 break;
932 }
933 }
934 macid_diff = bb_ctrl->hwigi_macid_is_linked ^ macid_cur;
935 if (macid_diff)
936 bb_ctrl->hwigi_macid_is_linked &= ~macid_diff;
937 while (macid_diff) {
938 if (macid_diff & 0x1)
939 phydm_wt_hwigi_table(dm, macid_cnt, false, 0x0);
940 macid_cnt++;
941 macid_diff >>= 1;
942 }
943 }
944
phydm_hwigi_dbg(void * dm_void,char input[][16],u32 * _used,char * output,u32 * _out_len)945 void phydm_hwigi_dbg(void *dm_void, char input[][16], u32 *_used,
946 char *output, u32 *_out_len)
947 {
948 struct dm_struct *dm = (struct dm_struct *)dm_void;
949 struct phydm_bb_ram_ctrl *bb_ctrl = &dm->p_bb_ram_ctrl;
950 char help[] = "-h";
951 u32 used = *_used;
952 u32 out_len = *_out_len;
953 u32 var1[7] = {0};
954 u8 i = 0;
955
956 if (!(dm->support_ic_type & ODM_IC_JGR3_SERIES))
957 return;
958
959 if ((strcmp(input[1], help) == 0)) {
960 PDM_SNPF(out_len, used, output + used, out_len - used,
961 "Disable/Enable watchdog : {0/1}\n");
962 PDM_SNPF(out_len, used, output + used, out_len - used,
963 "Set hwigi pre-setting: {2} {IGI offset} {T1(after data tx)} {T2(after Rx)} {T3(after rsp tx)}\n");
964 PDM_SNPF(out_len, used, output + used, out_len - used,
965 "Set hwigi table: {3} {en} {value} {macid}\n");
966 PDM_SNPF(out_len, used, output + used, out_len - used,
967 "Read hwigi : {4} {macid(0~63), 255:all}\n");
968 PDM_SNPF(out_len, used, output + used, out_len - used,
969 "Reset all hwigi : {5}\n");
970 } else {
971 for (i = 0; i < 7; i++) {
972 if (input[i + 1])
973 PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL,
974 &var1[i]);
975 }
976 switch (var1[0]) {
977 case 0:
978 case 1:
979 bb_ctrl->hwigi_watchdog_en = (var1[0]) ? true : false;
980 break;
981 case 2:
982 phydm_set_hwigi_pre_setting(dm, (u8)var1[1],
983 (u8)var1[2], (u8)var1[3],
984 (u8)var1[4]);
985 break;
986 case 3:
987 phydm_wt_hwigi_table(dm, (u8)var1[3], (boolean)var1[1],
988 (boolean)var1[2]);
989 break;
990 case 4:
991 phydm_rd_hwigi_pre_setting(dm, &used, output, &out_len);
992 if ((u8)var1[1] == 0xff)
993 for (i = 0; i < 64; i++)
994 phydm_rd_hwigi_table(dm, i, &used,
995 output, &out_len);
996 else
997 phydm_rd_hwigi_table(dm, (u8)var1[1], &used,
998 output, &out_len);
999 break;
1000 case 5:
1001 phydm_rst_hwigi(dm);
1002 break;
1003 }
1004 }
1005 *_used = used;
1006 *_out_len = out_len;
1007 }
1008 #endif
1009 #endif
1010
phydm_dig_init(void * dm_void)1011 void phydm_dig_init(void *dm_void)
1012 {
1013 struct dm_struct *dm = (struct dm_struct *)dm_void;
1014 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
1015 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
1016 struct phydm_fa_struct *false_alm_cnt = &dm->false_alm_cnt;
1017 #endif
1018 u32 ret_value = 0;
1019 u8 i;
1020
1021 dig_t->dm_dig_max = DIG_MAX_BALANCE_MODE;
1022 dig_t->dm_dig_min = DIG_MIN_PERFORMANCE;
1023 dig_t->dig_max_of_min = DIG_MAX_OF_MIN_BALANCE_MODE;
1024
1025 dig_t->cur_ig_value = phydm_get_igi(dm, BB_PATH_A);
1026
1027 dig_t->fa_th[0] = 250;
1028 dig_t->fa_th[1] = 500;
1029 dig_t->fa_th[2] = 750;
1030 dig_t->dm_dig_fa_th1 = DM_DIG_FA_TH1;
1031 dig_t->is_dbg_fa_th = false;
1032 dig_t->igi_dyn_up_hit = false;
1033 dig_t->fw_dig_enable = false;
1034 dig_t->fa_source = 0;
1035
1036 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
1037 /* @For RTL8881A */
1038 false_alm_cnt->cnt_ofdm_fail_pre = 0;
1039 #endif
1040
1041 dig_t->rx_gain_range_max = DIG_MAX_BALANCE_MODE;
1042 dig_t->rx_gain_range_min = dig_t->cur_ig_value;
1043
1044 #if (RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8192F_SUPPORT)
1045 if (dm->support_ic_type &
1046 (ODM_RTL8822B | ODM_RTL8197F | ODM_RTL8192F)) {
1047 dig_t->enable_adjust_big_jump = 1;
1048
1049 if (dm->support_ic_type & ODM_RTL8822B)
1050 ret_value = odm_get_bb_reg(dm, R_0x8c8, MASKLWORD);
1051 else if (dm->support_ic_type & (ODM_RTL8197F | ODM_RTL8192F))
1052 ret_value = odm_get_bb_reg(dm, R_0xc74, MASKLWORD);
1053
1054 dig_t->big_jump_step1 = (u8)(ret_value & 0xe) >> 1;
1055 dig_t->big_jump_step2 = (u8)(ret_value & 0x30) >> 4;
1056 dig_t->big_jump_step3 = (u8)(ret_value & 0xc0) >> 6;
1057
1058 for (i = 0; i < sizeof(dig_t->big_jump_lmt); i++) {
1059 if (dig_t->big_jump_lmt[i] == 0)
1060 dig_t->big_jump_lmt[i] = 0x64;
1061 /* Set -10dBm as default value */
1062 }
1063 }
1064 #endif
1065
1066 #ifdef PHYDM_TDMA_DIG_SUPPORT
1067 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
1068 dm->original_dig_restore = true;
1069 dm->tdma_dig_state_number = DIG_NUM_OF_TDMA_STATES;
1070 dm->tdma_dig_timer_ms = DIG_TIMER_MS;
1071 #endif
1072 dig_t->tdma_force_l_igi = 0xff;
1073 dig_t->tdma_force_h_igi = 0xff;
1074 #endif
1075 #ifdef CFG_DIG_DAMPING_CHK
1076 phydm_dig_recorder_reset(dm);
1077 dig_t->dig_dl_en = 1;
1078 #endif
1079
1080 #ifdef PHYDM_HW_IGI
1081 phydm_hwigi_init(dm);
1082 #endif
1083 }
phydm_dig_abs_boundary_decision(struct dm_struct * dm,boolean is_dfs_band)1084 void phydm_dig_abs_boundary_decision(struct dm_struct *dm, boolean is_dfs_band)
1085 {
1086 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
1087 struct phydm_adaptivity_struct *adapt = &dm->adaptivity;
1088
1089 if (is_dfs_band) {
1090 if (*dm->band_width == CHANNEL_WIDTH_20){
1091 if (dm->support_ic_type &
1092 (ODM_RTL8814A | ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8822B)){
1093 if (odm_get_bb_reg(dm, R_0x8d8, BIT(27)) == 1)
1094 dig_t->dm_dig_min = DIG_MIN_DFS + 2;
1095 else
1096 dig_t->dm_dig_min = DIG_MIN_DFS;
1097 }
1098 else
1099 dig_t->dm_dig_min = DIG_MIN_DFS;
1100 }
1101 else
1102 dig_t->dm_dig_min = DIG_MIN_DFS;
1103
1104 dig_t->dig_max_of_min = DIG_MIN_DFS;
1105 dig_t->dm_dig_max = DIG_MAX_BALANCE_MODE;
1106 } else if (!dm->is_linked) {
1107 dig_t->dm_dig_max = DIG_MAX_COVERAGR;
1108 dig_t->dm_dig_min = DIG_MIN_COVERAGE;
1109 } else {
1110 if (*dm->bb_op_mode == PHYDM_BALANCE_MODE) {
1111 /*service > 2 devices*/
1112 dig_t->dm_dig_max = DIG_MAX_BALANCE_MODE;
1113 #if (DIG_HW == 1)
1114 dig_t->dig_max_of_min = DIG_MIN_COVERAGE;
1115 #else
1116 dig_t->dig_max_of_min = DIG_MAX_OF_MIN_BALANCE_MODE;
1117 #endif
1118 } else if (*dm->bb_op_mode == PHYDM_PERFORMANCE_MODE) {
1119 /*service 1 devices*/
1120 if (*dm->edcca_mode == PHYDM_EDCCA_ADAPT_MODE &&
1121 dm->support_ic_type & (ODM_RTL8197F | ODM_RTL8192F))
1122 /*dig_max shouldn't be too high because of adaptivity*/
1123 dig_t->dm_dig_max =
1124 MIN_2((adapt->th_l2h + 30),
1125 DIG_MAX_PERFORMANCE_MODE);
1126 else
1127 dig_t->dm_dig_max = DIG_MAX_PERFORMANCE_MODE;
1128
1129 #if (RTL8822B_SUPPORT == 1)
1130 if (dm->is_dig_low_bond)
1131 dig_t->dig_max_of_min = DIG_MAX_OF_MIN_PERFORMANCE_MODE_22B;
1132 else
1133 dig_t->dig_max_of_min = DIG_MAX_OF_MIN_PERFORMANCE_MODE;
1134 #else
1135 dig_t->dig_max_of_min = DIG_MAX_OF_MIN_PERFORMANCE_MODE;
1136 #endif
1137 }
1138
1139 if (dm->support_ic_type &
1140 (ODM_RTL8814A | ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8822B))
1141 dig_t->dm_dig_min = 0x1c;
1142 else if (dm->support_ic_type & ODM_RTL8197F)
1143 dig_t->dm_dig_min = 0x1e; /*@For HW setting*/
1144 else
1145 dig_t->dm_dig_min = DIG_MIN_PERFORMANCE;
1146 }
1147
1148 PHYDM_DBG(dm, DBG_DIG, "Abs{Max, Min}={0x%x, 0x%x}, Max_of_min=0x%x\n",
1149 dig_t->dm_dig_max, dig_t->dm_dig_min, dig_t->dig_max_of_min);
1150 }
1151
phydm_dig_dym_boundary_decision(struct dm_struct * dm,boolean is_dfs_band)1152 void phydm_dig_dym_boundary_decision(struct dm_struct *dm, boolean is_dfs_band)
1153 {
1154 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
1155 #ifdef CFG_DIG_DAMPING_CHK
1156 struct phydm_dig_recorder_strcut *dig_rc = &dig_t->dig_recorder_t;
1157 #endif
1158 u8 offset = 15, tmp_max = 0;
1159 u8 max_of_rssi_min = 0;
1160
1161 PHYDM_DBG(dm, DBG_DIG, "%s ======>\n", __func__);
1162 #if (RTL8822B_SUPPORT == 1)
1163 if (dm->is_dig_low_bond)
1164 offset = 5;
1165 else
1166 offset = 15;
1167 #else
1168 offset = 15;
1169 #endif
1170
1171 if (!dm->is_linked) {
1172 /*@if no link, always stay at lower bound*/
1173 dig_t->rx_gain_range_max = dig_t->dig_max_of_min;
1174 dig_t->rx_gain_range_min = dig_t->dm_dig_min;
1175
1176 PHYDM_DBG(dm, DBG_DIG, "No-Link, Dyn{Max, Min}={0x%x, 0x%x}\n",
1177 dig_t->rx_gain_range_max, dig_t->rx_gain_range_min);
1178 return;
1179 }
1180
1181 PHYDM_DBG(dm, DBG_DIG, "rssi_min=%d, ofst=%d\n", dm->rssi_min, offset);
1182
1183 /* @DIG lower bound */
1184 if (is_dfs_band)
1185 dig_t->rx_gain_range_min = dig_t->dm_dig_min;
1186 else if (dm->rssi_min > dig_t->dig_max_of_min)
1187 dig_t->rx_gain_range_min = dig_t->dig_max_of_min;
1188 else if (dm->rssi_min < dig_t->dm_dig_min)
1189 dig_t->rx_gain_range_min = dig_t->dm_dig_min;
1190 else
1191 dig_t->rx_gain_range_min = dm->rssi_min;
1192
1193 #ifdef CFG_DIG_DAMPING_CHK
1194 /*@Limit Dyn min by damping*/
1195 if (dig_t->dig_dl_en &&
1196 dig_rc->damping_limit_en &&
1197 dig_t->rx_gain_range_min < dig_rc->damping_limit_val) {
1198 PHYDM_DBG(dm, DBG_DIG,
1199 "[Limit by Damping] Dig_dyn_min=0x%x -> 0x%x\n",
1200 dig_t->rx_gain_range_min, dig_rc->damping_limit_val);
1201
1202 dig_t->rx_gain_range_min = dig_rc->damping_limit_val;
1203 }
1204 #endif
1205
1206 /* @DIG upper bound */
1207 tmp_max = dig_t->rx_gain_range_min + offset;
1208 if (dig_t->rx_gain_range_min != dm->rssi_min) {
1209 max_of_rssi_min = dm->rssi_min + offset;
1210 if (tmp_max > max_of_rssi_min)
1211 tmp_max = max_of_rssi_min;
1212 }
1213
1214 if (tmp_max > dig_t->dm_dig_max)
1215 dig_t->rx_gain_range_max = dig_t->dm_dig_max;
1216 else if (tmp_max < dig_t->dm_dig_min)
1217 dig_t->rx_gain_range_max = dig_t->dm_dig_min;
1218 else
1219 dig_t->rx_gain_range_max = tmp_max;
1220
1221 #ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
1222 /* @1 Force Lower Bound for AntDiv */
1223 if (!dm->is_one_entry_only &&
1224 (dm->support_ability & ODM_BB_ANT_DIV) &&
1225 (dm->ant_div_type == CG_TRX_HW_ANTDIV ||
1226 dm->ant_div_type == CG_TRX_SMART_ANTDIV)) {
1227 if (dig_t->ant_div_rssi_max > dig_t->dig_max_of_min)
1228 dig_t->rx_gain_range_min = dig_t->dig_max_of_min;
1229 else
1230 dig_t->rx_gain_range_min = (u8)dig_t->ant_div_rssi_max;
1231
1232 PHYDM_DBG(dm, DBG_DIG, "Force Dyn-Min=0x%x, RSSI_max=0x%x\n",
1233 dig_t->rx_gain_range_min, dig_t->ant_div_rssi_max);
1234 }
1235 #endif
1236
1237 PHYDM_DBG(dm, DBG_DIG, "Dyn{Max, Min}={0x%x, 0x%x}\n",
1238 dig_t->rx_gain_range_max, dig_t->rx_gain_range_min);
1239 }
1240
phydm_dig_abnormal_case(struct dm_struct * dm)1241 void phydm_dig_abnormal_case(struct dm_struct *dm)
1242 {
1243 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
1244
1245 /* @Abnormal lower bound case */
1246 if (dig_t->rx_gain_range_min > dig_t->rx_gain_range_max)
1247 dig_t->rx_gain_range_min = dig_t->rx_gain_range_max;
1248
1249 PHYDM_DBG(dm, DBG_DIG, "Abnoraml checked {Max, Min}={0x%x, 0x%x}\n",
1250 dig_t->rx_gain_range_max, dig_t->rx_gain_range_min);
1251 }
1252
phydm_new_igi_by_fa(struct dm_struct * dm,u8 igi,u32 fa_metrics,u8 * step_size)1253 u8 phydm_new_igi_by_fa(struct dm_struct *dm, u8 igi, u32 fa_metrics,
1254 u8 *step_size)
1255 {
1256 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
1257
1258 if (fa_metrics > dig_t->fa_th[2])
1259 igi = igi + step_size[0];
1260 else if (fa_metrics > dig_t->fa_th[1])
1261 igi = igi + step_size[1];
1262 else if (fa_metrics < dig_t->fa_th[0])
1263 igi = igi - step_size[2];
1264
1265 return igi;
1266 }
1267
phydm_get_new_igi(struct dm_struct * dm,u8 igi,u32 fa_metrics,boolean is_dfs_band)1268 u8 phydm_get_new_igi(struct dm_struct *dm, u8 igi, u32 fa_metrics,
1269 boolean is_dfs_band)
1270 {
1271 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
1272 u8 step[3] = {0};
1273
1274 if (dm->is_linked) {
1275 if (dm->pre_rssi_min <= dm->rssi_min) {
1276 PHYDM_DBG(dm, DBG_DIG, "pre_rssi_min <= rssi_min\n");
1277 step[0] = 2;
1278 step[1] = 1;
1279 step[2] = 2;
1280 } else {
1281 step[0] = 4;
1282 step[1] = 2;
1283 step[2] = 2;
1284 }
1285 } else {
1286 step[0] = 2;
1287 step[1] = 1;
1288 step[2] = 2;
1289 }
1290
1291 PHYDM_DBG(dm, DBG_DIG, "step = {-%d, +%d, +%d}\n", step[2], step[1],
1292 step[0]);
1293
1294 if (dm->first_connect) {
1295 if (is_dfs_band) {
1296 if (dm->rssi_min > DIG_MAX_DFS)
1297 igi = DIG_MAX_DFS;
1298 else
1299 igi = dm->rssi_min;
1300 PHYDM_DBG(dm, DBG_DIG, "DFS band:IgiMax=0x%x\n",
1301 dig_t->rx_gain_range_max);
1302 } else {
1303 igi = dig_t->rx_gain_range_min;
1304 }
1305
1306 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
1307 #if (RTL8812A_SUPPORT)
1308 if (dm->support_ic_type == ODM_RTL8812)
1309 odm_config_bb_with_header_file(dm,
1310 CONFIG_BB_AGC_TAB_DIFF);
1311 #endif
1312 #endif
1313 PHYDM_DBG(dm, DBG_DIG, "First connect: foce IGI=0x%x\n", igi);
1314 } else if (dm->is_linked) {
1315 PHYDM_DBG(dm, DBG_DIG, "Adjust IGI @ linked\n");
1316 /* @4 Abnormal # beacon case */
1317 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
1318 if (dm->phy_dbg_info.num_qry_beacon_pkt < 5 &&
1319 fa_metrics < dig_t->dm_dig_fa_th1 && dm->bsta_state &&
1320 dm->support_ic_type != ODM_RTL8723D &&
1321 dm->support_ic_type != ODM_RTL8822B &&
1322 dm->support_ic_type != ODM_RTL8822C) {
1323 dig_t->rx_gain_range_min = 0x1c;
1324 igi = dig_t->rx_gain_range_min;
1325 PHYDM_DBG(dm, DBG_DIG, "Beacon_num=%d,force igi=0x%x\n",
1326 dm->phy_dbg_info.num_qry_beacon_pkt, igi);
1327 } else {
1328 igi = phydm_new_igi_by_fa(dm, igi, fa_metrics, step);
1329 }
1330 #else
1331 igi = phydm_new_igi_by_fa(dm, igi, fa_metrics, step);
1332 #endif
1333 } else {
1334 /* @2 Before link */
1335 PHYDM_DBG(dm, DBG_DIG, "Adjust IGI before link\n");
1336
1337 if (dm->first_disconnect) {
1338 igi = dig_t->dm_dig_min;
1339 PHYDM_DBG(dm, DBG_DIG,
1340 "First disconnect:foce IGI to lower bound\n");
1341 } else {
1342 PHYDM_DBG(dm, DBG_DIG, "Pre_IGI=((0x%x)), FA=((%d))\n",
1343 igi, fa_metrics);
1344
1345 igi = phydm_new_igi_by_fa(dm, igi, fa_metrics, step);
1346 }
1347 }
1348
1349 /*@Check IGI by dyn-upper/lower bound */
1350 if (igi < dig_t->rx_gain_range_min)
1351 igi = dig_t->rx_gain_range_min;
1352
1353 if (igi >= dig_t->rx_gain_range_max) {
1354 igi = dig_t->rx_gain_range_max;
1355 dig_t->igi_dyn_up_hit = true;
1356 } else {
1357 dig_t->igi_dyn_up_hit = false;
1358 }
1359 PHYDM_DBG(dm, DBG_DIG, "igi_dyn_up_hit=%d\n",
1360 dig_t->igi_dyn_up_hit);
1361
1362 PHYDM_DBG(dm, DBG_DIG, "fa_metrics = %d, IGI: 0x%x -> 0x%x\n",
1363 fa_metrics, dig_t->cur_ig_value, igi);
1364
1365 return igi;
1366 }
1367
phydm_dig_dfs_mode_en(void * dm_void)1368 boolean phydm_dig_dfs_mode_en(void *dm_void)
1369 {
1370 struct dm_struct *dm = (struct dm_struct *)dm_void;
1371 boolean dfs_mode_en = false;
1372
1373 /* @Modify lower bound for DFS band */
1374 if (dm->is_dfs_band) {
1375 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
1376 dfs_mode_en = true;
1377 #else
1378 if (phydm_dfs_master_enabled(dm))
1379 dfs_mode_en = true;
1380 #endif
1381 PHYDM_DBG(dm, DBG_DIG, "In DFS band\n");
1382 }
1383 return dfs_mode_en;
1384 }
1385
phydm_dig_fa_source(void * dm_void,u8 fa_source,u32 * fa_metrics)1386 void phydm_dig_fa_source(void *dm_void, u8 fa_source, u32 *fa_metrics)
1387 {
1388 struct dm_struct *dm = (struct dm_struct *)dm_void;
1389 struct phydm_fa_struct *fa = &dm->false_alm_cnt;
1390
1391 switch (fa_source) {
1392 case 1:
1393 *fa_metrics = fa->time_fa_exp;
1394 break;
1395 #ifdef IFS_CLM_SUPPORT
1396 case 2:
1397 if (fa->time_fa_ifs_clm) {
1398 *fa_metrics = fa->time_fa_ifs_clm;
1399 } else {
1400 fa_source = 1;
1401 *fa_metrics = fa->time_fa_exp;
1402 }
1403 break;
1404 #endif
1405 #ifdef FAHM_SUPPORT
1406 case 3:
1407 if (fa->time_fa_fahm) {
1408 *fa_metrics = fa->time_fa_fahm;
1409 } else {
1410 fa_source = 1;
1411 *fa_metrics = fa->time_fa_exp;
1412 }
1413 break;
1414 #endif
1415 default:
1416 break;
1417 }
1418
1419 PHYDM_DBG(dm, DBG_DIG,
1420 "fa_source:%d, fa_cnt=%d ,time_fa_exp=%d, fa_metrics=%d\n",
1421 fa_source, fa->cnt_all, fa->time_fa_exp, *fa_metrics);
1422 }
1423
phydm_dig(void * dm_void)1424 void phydm_dig(void *dm_void)
1425 {
1426 struct dm_struct *dm = (struct dm_struct *)dm_void;
1427 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
1428 struct phydm_fa_struct *fa = &dm->false_alm_cnt;
1429 #ifdef PHYDM_TDMA_DIG_SUPPORT
1430 struct phydm_fa_acc_struct *falm_cnt_acc = &dm->false_alm_cnt_acc;
1431 #endif
1432 u8 igi = dig_t->cur_ig_value;
1433 u8 new_igi = 0x20;
1434 u32 fa_metrics = fa->cnt_all;
1435 boolean dfs_mode_en = false;
1436
1437 PHYDM_DBG(dm, DBG_DIG, "%s Start===>\n", __func__);
1438
1439 #ifdef PHYDM_DCC_ENHANCE
1440 if (dm->dm_dcc_info.dcc_en) {
1441 fa_metrics = fa->cnt_ofdm_fail; /*OFDM FA only*/
1442 dig_t->fa_source = 0;
1443 }
1444 #endif
1445
1446 #ifdef PHYDM_TDMA_DIG_SUPPORT
1447 if (!(dm->original_dig_restore)) {
1448 if (dig_t->cur_ig_value_tdma == 0)
1449 dig_t->cur_ig_value_tdma = dig_t->cur_ig_value;
1450
1451 igi = dig_t->cur_ig_value_tdma;
1452 fa_metrics = falm_cnt_acc->cnt_all_1sec;
1453 dig_t->fa_source = 0;
1454 }
1455 #endif
1456
1457 if (phydm_dig_abort(dm)) {
1458 dig_t->cur_ig_value = phydm_get_igi(dm, BB_PATH_A);
1459 return;
1460 }
1461
1462 if (dig_t->fa_source)
1463 phydm_dig_fa_source(dm, dig_t->fa_source, &fa_metrics);
1464
1465 PHYDM_DBG(dm, DBG_DIG,
1466 "is_linked=%d, RSSI=%d, 1stConnect=%d, 1stDisconnect=%d\n",
1467 dm->is_linked, dm->rssi_min,
1468 dm->first_connect, dm->first_disconnect);
1469
1470 PHYDM_DBG(dm, DBG_DIG, "DIG ((%s)) mode\n",
1471 (*dm->bb_op_mode ? "Balance" : "Performance"));
1472
1473 /*@DFS mode enable check*/
1474 dfs_mode_en = phydm_dig_dfs_mode_en(dm);
1475
1476 #ifdef CFG_DIG_DAMPING_CHK
1477 /*Record IGI History*/
1478 phydm_dig_recorder(dm, igi, fa_metrics);
1479
1480 /*@DIG Damping Check*/
1481 phydm_dig_damping_chk(dm);
1482 #endif
1483
1484 /*@Absolute Boundary Decision */
1485 phydm_dig_abs_boundary_decision(dm, dfs_mode_en);
1486
1487 /*@Dynamic Boundary Decision*/
1488 phydm_dig_dym_boundary_decision(dm, dfs_mode_en);
1489
1490 /*@Abnormal case check*/
1491 phydm_dig_abnormal_case(dm);
1492
1493 /*@FA threshold decision */
1494 phydm_fa_threshold_check(dm, dfs_mode_en);
1495
1496 /*Select new IGI by FA */
1497 new_igi = phydm_get_new_igi(dm, igi, fa_metrics, dfs_mode_en);
1498
1499 /* @1 Update status */
1500 #ifdef PHYDM_TDMA_DIG_SUPPORT
1501 if (!(dm->original_dig_restore)) {
1502 dig_t->cur_ig_value_tdma = new_igi;
1503 /*@It is possible fa_acc_1sec_tsf >= */
1504 /*@1sec while tdma_dig_state == 0*/
1505 if (dig_t->tdma_dig_state != 0)
1506 odm_write_dig(dm, dig_t->cur_ig_value_tdma);
1507 } else
1508 #endif
1509 odm_write_dig(dm, new_igi);
1510 }
1511
phydm_dig_lps_32k(void * dm_void)1512 void phydm_dig_lps_32k(void *dm_void)
1513 {
1514 struct dm_struct *dm = (struct dm_struct *)dm_void;
1515 u8 current_igi = dm->rssi_min;
1516
1517 odm_write_dig(dm, current_igi);
1518 }
1519
phydm_dig_by_rssi_lps(void * dm_void)1520 void phydm_dig_by_rssi_lps(void *dm_void)
1521 {
1522 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE | ODM_IOT))
1523 struct dm_struct *dm = (struct dm_struct *)dm_void;
1524 struct phydm_fa_struct *falm_cnt;
1525
1526 u8 rssi_lower = DIG_MIN_LPS; /* @0x1E or 0x1C */
1527 u8 current_igi = dm->rssi_min;
1528
1529 falm_cnt = &dm->false_alm_cnt;
1530 if (phydm_dig_abort(dm))
1531 return;
1532
1533 current_igi = current_igi + RSSI_OFFSET_DIG_LPS;
1534 PHYDM_DBG(dm, DBG_DIG, "%s==>\n", __func__);
1535
1536 /* Using FW PS mode to make IGI */
1537 /* @Adjust by FA in LPS MODE */
1538 if (falm_cnt->cnt_all > DM_DIG_FA_TH2_LPS)
1539 current_igi = current_igi + 4;
1540 else if (falm_cnt->cnt_all > DM_DIG_FA_TH1_LPS)
1541 current_igi = current_igi + 2;
1542 else if (falm_cnt->cnt_all < DM_DIG_FA_TH0_LPS)
1543 current_igi = current_igi - 2;
1544
1545 /* @Lower bound checking */
1546
1547 /* RSSI Lower bound check */
1548 if ((dm->rssi_min - 10) > DIG_MIN_LPS)
1549 rssi_lower = (dm->rssi_min - 10);
1550 else
1551 rssi_lower = DIG_MIN_LPS;
1552
1553 /* Upper and Lower Bound checking */
1554 if (current_igi > DIG_MAX_LPS)
1555 current_igi = DIG_MAX_LPS;
1556 else if (current_igi < rssi_lower)
1557 current_igi = rssi_lower;
1558
1559 PHYDM_DBG(dm, DBG_DIG, "fa_cnt_all=%d, rssi_min=%d, curr_igi=0x%x\n",
1560 falm_cnt->cnt_all, dm->rssi_min, current_igi);
1561 odm_write_dig(dm, current_igi);
1562 #endif
1563 }
1564
phydm_get_dig_coverage(void * dm_void,u8 * max,u8 * min)1565 void phydm_get_dig_coverage(void *dm_void, u8 *max, u8 *min)
1566 {
1567 *min = DIG_MIN_COVERAGE;
1568 *max = DIG_MAX_PERFORMANCE_MODE;
1569 }
1570
phydm_get_igi_for_target_pin_scan(void * dm_void,u8 rssi)1571 u8 phydm_get_igi_for_target_pin_scan(void *dm_void, u8 rssi)
1572 {
1573 struct dm_struct *dm = (struct dm_struct *)dm_void;
1574 u8 igi = 0;
1575 u8 max = 0;
1576 u8 min = 0;
1577
1578 igi = rssi + 10;
1579
1580 phydm_get_dig_coverage(dm, &max, &min);
1581
1582 if (igi > max)
1583 igi = max;
1584 else if (igi < min)
1585 igi = min;
1586
1587 return igi;
1588 }
1589
1590 /* @3============================================================
1591 * 3 FASLE ALARM CHECK
1592 * 3============================================================
1593 */
phydm_false_alarm_counter_reg_reset(void * dm_void)1594 void phydm_false_alarm_counter_reg_reset(void *dm_void)
1595 {
1596 struct dm_struct *dm = (struct dm_struct *)dm_void;
1597 struct phydm_fa_struct *falm_cnt = &dm->false_alm_cnt;
1598 #ifdef PHYDM_TDMA_DIG_SUPPORT
1599 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
1600 struct phydm_fa_acc_struct *falm_cnt_acc = &dm->false_alm_cnt_acc;
1601 #endif
1602 u32 false_alm_cnt = 0;
1603
1604 #ifdef PHYDM_TDMA_DIG_SUPPORT
1605 if (!(dm->original_dig_restore)) {
1606 if (dig_t->cur_ig_value_tdma == 0)
1607 dig_t->cur_ig_value_tdma = dig_t->cur_ig_value;
1608
1609 false_alm_cnt = falm_cnt_acc->cnt_all_1sec;
1610 } else
1611 #endif
1612 {
1613 false_alm_cnt = falm_cnt->cnt_all;
1614 }
1615
1616 #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
1617 if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
1618 if (dm->support_ic_type & ODM_RTL8723F) {
1619 /* @reset CCK FA and CCA counter */
1620 odm_set_bb_reg(dm, R_0x2a44, BIT(21), 0);
1621 odm_set_bb_reg(dm, R_0x2a44, BIT(21), 1);
1622 } else {
1623 /* @reset CCK FA counter */
1624 odm_set_bb_reg(dm, R_0x1a2c, BIT(15) | BIT(14), 0);
1625 odm_set_bb_reg(dm, R_0x1a2c, BIT(15) | BIT(14), 2);
1626
1627 /* @reset CCK CCA counter */
1628 odm_set_bb_reg(dm, R_0x1a2c, BIT(13) | BIT(12), 0);
1629 odm_set_bb_reg(dm, R_0x1a2c, BIT(13) | BIT(12), 2);
1630 }
1631 /* @Disable common rx clk gating => WLANBB-1106*/
1632 odm_set_bb_reg(dm, R_0x1d2c, BIT(31), 0);
1633 /* @reset OFDM CCA counter, OFDM FA counter*/
1634 phydm_reset_bb_hw_cnt(dm);
1635 /* @Enable common rx clk gating => WLANBB-1106*/
1636 odm_set_bb_reg(dm, R_0x1d2c, BIT(31), 1);
1637 }
1638 #endif
1639 #if (ODM_IC_11N_SERIES_SUPPORT)
1640 if (dm->support_ic_type & ODM_IC_11N_SERIES) {
1641 /* @reset false alarm counter registers*/
1642 odm_set_bb_reg(dm, R_0xc0c, BIT(31), 1);
1643 odm_set_bb_reg(dm, R_0xc0c, BIT(31), 0);
1644 odm_set_bb_reg(dm, R_0xd00, BIT(27), 1);
1645 odm_set_bb_reg(dm, R_0xd00, BIT(27), 0);
1646
1647 /* @update ofdm counter*/
1648 /* @update page C counter*/
1649 odm_set_bb_reg(dm, R_0xc00, BIT(31), 0);
1650 /* @update page D counter*/
1651 odm_set_bb_reg(dm, R_0xd00, BIT(31), 0);
1652
1653 /* @reset CCK CCA counter*/
1654 odm_set_bb_reg(dm, R_0xa2c, BIT(13) | BIT(12), 0);
1655 odm_set_bb_reg(dm, R_0xa2c, BIT(13) | BIT(12), 2);
1656
1657 /* @reset CCK FA counter*/
1658 odm_set_bb_reg(dm, R_0xa2c, BIT(15) | BIT(14), 0);
1659 odm_set_bb_reg(dm, R_0xa2c, BIT(15) | BIT(14), 2);
1660
1661 /* @reset CRC32 counter*/
1662 odm_set_bb_reg(dm, R_0xf14, BIT(16), 1);
1663 odm_set_bb_reg(dm, R_0xf14, BIT(16), 0);
1664 }
1665 #endif /* @#if (ODM_IC_11N_SERIES_SUPPORT) */
1666
1667 #if (ODM_IC_11AC_SERIES_SUPPORT)
1668 if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
1669 #if (RTL8881A_SUPPORT)
1670 /* @Reset FA counter by enable/disable OFDM */
1671 if ((dm->support_ic_type == ODM_RTL8881A) &&
1672 false_alm_cnt->cnt_ofdm_fail_pre >= 0x7fff) {
1673 /* reset OFDM */
1674 odm_set_bb_reg(dm, R_0x808, BIT(29), 0);
1675 odm_set_bb_reg(dm, R_0x808, BIT(29), 1);
1676 false_alm_cnt->cnt_ofdm_fail_pre = 0;
1677 PHYDM_DBG(dm, DBG_FA_CNT, "Reset FA_cnt\n");
1678 }
1679 #endif /* @#if (RTL8881A_SUPPORT) */
1680
1681 /* @reset OFDM FA countner */
1682 odm_set_bb_reg(dm, R_0x9a4, BIT(17), 1);
1683 odm_set_bb_reg(dm, R_0x9a4, BIT(17), 0);
1684
1685 /* @reset CCK FA counter */
1686 odm_set_bb_reg(dm, R_0xa2c, BIT(15), 0);
1687 odm_set_bb_reg(dm, R_0xa2c, BIT(15), 1);
1688
1689 /* @reset CCA counter */
1690 phydm_reset_bb_hw_cnt(dm);
1691 }
1692 #endif /* @#if (ODM_IC_11AC_SERIES_SUPPORT) */
1693 }
1694
phydm_false_alarm_counter_reg_hold(void * dm_void)1695 void phydm_false_alarm_counter_reg_hold(void *dm_void)
1696 {
1697 struct dm_struct *dm = (struct dm_struct *)dm_void;
1698
1699 if (dm->support_ic_type & ODM_RTL8723F)
1700 return;
1701
1702 if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
1703 /* @hold cck counter */
1704 odm_set_bb_reg(dm, R_0x1a2c, BIT(12), 1);
1705 odm_set_bb_reg(dm, R_0x1a2c, BIT(14), 1);
1706 } else if (dm->support_ic_type & ODM_IC_11N_SERIES) {
1707 /*@hold ofdm counter*/
1708 /*@hold page C counter*/
1709 odm_set_bb_reg(dm, R_0xc00, BIT(31), 1);
1710 /*@hold page D counter*/
1711 odm_set_bb_reg(dm, R_0xd00, BIT(31), 1);
1712
1713 /*@hold cck counter*/
1714 odm_set_bb_reg(dm, R_0xa2c, BIT(12), 1);
1715 odm_set_bb_reg(dm, R_0xa2c, BIT(14), 1);
1716 }
1717 }
1718
1719 #if (ODM_IC_11N_SERIES_SUPPORT)
phydm_fa_cnt_statistics_n(void * dm_void)1720 void phydm_fa_cnt_statistics_n(void *dm_void)
1721 {
1722 struct dm_struct *dm = (struct dm_struct *)dm_void;
1723 struct phydm_fa_struct *fa_t = &dm->false_alm_cnt;
1724 u32 reg = 0;
1725
1726 if (!(dm->support_ic_type & ODM_IC_11N_SERIES))
1727 return;
1728
1729 /* @hold ofdm & cck counter */
1730 phydm_false_alarm_counter_reg_hold(dm);
1731
1732 reg = odm_get_bb_reg(dm, R_0x9d0, MASKDWORD);
1733 fa_t->cnt_cck_txon = (reg & 0xffff);
1734 fa_t->cnt_cck_txen = ((reg & 0xffff0000) >> 16);
1735 reg = odm_get_bb_reg(dm, R_0x9cc, MASKDWORD);
1736 fa_t->cnt_ofdm_txon = (reg & 0xffff);
1737 fa_t->cnt_ofdm_txen = ((reg & 0xffff0000) >> 16);
1738
1739 reg = odm_get_bb_reg(dm, ODM_REG_OFDM_FA_TYPE1_11N, MASKDWORD);
1740 fa_t->cnt_fast_fsync = (reg & 0xffff);
1741 fa_t->cnt_sb_search_fail = ((reg & 0xffff0000) >> 16);
1742
1743 reg = odm_get_bb_reg(dm, ODM_REG_OFDM_FA_TYPE2_11N, MASKDWORD);
1744 fa_t->cnt_ofdm_cca = (reg & 0xffff);
1745 fa_t->cnt_parity_fail = ((reg & 0xffff0000) >> 16);
1746
1747 reg = odm_get_bb_reg(dm, ODM_REG_OFDM_FA_TYPE3_11N, MASKDWORD);
1748 fa_t->cnt_rate_illegal = (reg & 0xffff);
1749 fa_t->cnt_crc8_fail = ((reg & 0xffff0000) >> 16);
1750
1751 reg = odm_get_bb_reg(dm, ODM_REG_OFDM_FA_TYPE4_11N, MASKDWORD);
1752 fa_t->cnt_mcs_fail = (reg & 0xffff);
1753
1754 fa_t->cnt_ofdm_fail =
1755 fa_t->cnt_parity_fail + fa_t->cnt_rate_illegal +
1756 fa_t->cnt_crc8_fail + fa_t->cnt_mcs_fail +
1757 fa_t->cnt_fast_fsync + fa_t->cnt_sb_search_fail;
1758
1759 /* read CCK CRC32 counter */
1760 fa_t->cnt_cck_crc32_error = odm_get_bb_reg(dm, R_0xf84, MASKDWORD);
1761 fa_t->cnt_cck_crc32_ok = odm_get_bb_reg(dm, R_0xf88, MASKDWORD);
1762
1763 /* read OFDM CRC32 counter */
1764 reg = odm_get_bb_reg(dm, ODM_REG_OFDM_CRC32_CNT_11N, MASKDWORD);
1765 fa_t->cnt_ofdm_crc32_error = (reg & 0xffff0000) >> 16;
1766 fa_t->cnt_ofdm_crc32_ok = reg & 0xffff;
1767
1768 /* read OFDM2 CRC32 counter */
1769 reg = odm_get_bb_reg(dm, R_0xf9c, MASKDWORD);
1770 fa_t->cnt_ofdm_crc32_error = (reg & 0xffff0000) >> 16;
1771 fa_t->cnt_ofdm2_crc32_ok = reg & 0xffff;
1772
1773 /* read HT CRC32 counter */
1774 reg = odm_get_bb_reg(dm, ODM_REG_HT_CRC32_CNT_11N, MASKDWORD);
1775 fa_t->cnt_ht_crc32_error = (reg & 0xffff0000) >> 16;
1776 fa_t->cnt_ht_crc32_ok = reg & 0xffff;
1777
1778 /* read HT2 CRC32 counter */
1779 reg = odm_get_bb_reg(dm, R_0xf98, MASKDWORD);
1780 fa_t->cnt_ht_crc32_error = (reg & 0xffff0000) >> 16;
1781 fa_t->cnt_ht2_crc32_ok = reg & 0xffff;
1782
1783 /* read VHT CRC32 counter */
1784 fa_t->cnt_vht_crc32_error = 0;
1785 fa_t->cnt_vht_crc32_ok = 0;
1786
1787 #if (RTL8723D_SUPPORT)
1788 if (dm->support_ic_type == ODM_RTL8723D) {
1789 /* read HT CRC32 agg counter */
1790 reg = odm_get_bb_reg(dm, R_0xfb8, MASKDWORD);
1791 fa_t->cnt_ht_crc32_error_agg = (reg & 0xffff0000) >> 16;
1792 fa_t->cnt_ht_crc32_ok_agg = reg & 0xffff;
1793 }
1794 #endif
1795
1796 #if (RTL8188E_SUPPORT)
1797 if (dm->support_ic_type == ODM_RTL8188E) {
1798 reg = odm_get_bb_reg(dm, ODM_REG_SC_CNT_11N, MASKDWORD);
1799 fa_t->cnt_bw_lsc = (reg & 0xffff);
1800 fa_t->cnt_bw_usc = ((reg & 0xffff0000) >> 16);
1801 }
1802 #endif
1803
1804 reg = odm_get_bb_reg(dm, ODM_REG_CCK_FA_LSB_11N, MASKBYTE0);
1805 fa_t->cnt_cck_fail = reg;
1806
1807 reg = odm_get_bb_reg(dm, ODM_REG_CCK_FA_MSB_11N, MASKBYTE3);
1808 fa_t->cnt_cck_fail += (reg & 0xff) << 8;
1809
1810 reg = odm_get_bb_reg(dm, ODM_REG_CCK_CCA_CNT_11N, MASKDWORD);
1811 fa_t->cnt_cck_cca = ((reg & 0xFF) << 8) | ((reg & 0xFF00) >> 8);
1812
1813 fa_t->cnt_all_pre = fa_t->cnt_all;
1814
1815 fa_t->cnt_all = fa_t->cnt_fast_fsync +
1816 fa_t->cnt_sb_search_fail +
1817 fa_t->cnt_parity_fail +
1818 fa_t->cnt_rate_illegal +
1819 fa_t->cnt_crc8_fail +
1820 fa_t->cnt_mcs_fail +
1821 fa_t->cnt_cck_fail;
1822
1823 fa_t->cnt_cca_all = fa_t->cnt_ofdm_cca + fa_t->cnt_cck_cca;
1824 }
1825 #endif
1826
1827 #if (ODM_IC_11AC_SERIES_SUPPORT)
phydm_fa_cnt_statistics_ac(void * dm_void)1828 void phydm_fa_cnt_statistics_ac(void *dm_void)
1829 {
1830 struct dm_struct *dm = (struct dm_struct *)dm_void;
1831 struct phydm_fa_struct *fa_t = &dm->false_alm_cnt;
1832 u32 ret_value = 0;
1833 u32 cck_enable = 0;
1834
1835 if (!(dm->support_ic_type & ODM_IC_11AC_SERIES))
1836 return;
1837
1838 ret_value = odm_get_bb_reg(dm, R_0xf50, MASKDWORD);
1839 fa_t->cnt_cck_txen = (ret_value & 0xffff);
1840 fa_t->cnt_ofdm_txen = ((ret_value & 0xffff0000) >> 16);
1841 fa_t->cnt_cck_txon = (u16)odm_get_bb_reg(dm, R_0xfcc, MASKLWORD);
1842 fa_t->cnt_ofdm_txon = (u16)odm_get_bb_reg(dm, R_0xfc8, MASKHWORD);
1843
1844 ret_value = odm_get_bb_reg(dm, ODM_REG_OFDM_FA_TYPE1_11AC, MASKDWORD);
1845 fa_t->cnt_fast_fsync = (ret_value & 0xffff0000) >> 16;
1846
1847 ret_value = odm_get_bb_reg(dm, ODM_REG_OFDM_FA_TYPE2_11AC, MASKDWORD);
1848 fa_t->cnt_sb_search_fail = ret_value & 0xffff;
1849
1850 ret_value = odm_get_bb_reg(dm, ODM_REG_OFDM_FA_TYPE3_11AC, MASKDWORD);
1851 fa_t->cnt_parity_fail = ret_value & 0xffff;
1852 fa_t->cnt_rate_illegal = (ret_value & 0xffff0000) >> 16;
1853
1854 ret_value = odm_get_bb_reg(dm, ODM_REG_OFDM_FA_TYPE4_11AC, MASKDWORD);
1855 fa_t->cnt_crc8_fail = ret_value & 0xffff;
1856 fa_t->cnt_mcs_fail = (ret_value & 0xffff0000) >> 16;
1857
1858 ret_value = odm_get_bb_reg(dm, ODM_REG_OFDM_FA_TYPE5_11AC, MASKDWORD);
1859 fa_t->cnt_crc8_fail_vhta = ret_value & 0xffff;
1860 fa_t->cnt_crc8_fail_vhtb = ret_value & 0xffff0000 >> 16;
1861
1862 ret_value = odm_get_bb_reg(dm, ODM_REG_OFDM_FA_TYPE6_11AC, MASKDWORD);
1863 fa_t->cnt_mcs_fail_vht = ret_value & 0xffff;
1864
1865 /* read OFDM FA counter */
1866 fa_t->cnt_ofdm_fail = odm_get_bb_reg(dm, R_0xf48, MASKLWORD);
1867
1868 /* Read CCK FA counter */
1869 fa_t->cnt_cck_fail = odm_get_bb_reg(dm, ODM_REG_CCK_FA_11AC, MASKLWORD);
1870
1871 /* read CCK/OFDM CCA counter */
1872 ret_value = odm_get_bb_reg(dm, ODM_REG_CCK_CCA_CNT_11AC, MASKDWORD);
1873 fa_t->cnt_ofdm_cca = (ret_value & 0xffff0000) >> 16;
1874 fa_t->cnt_cck_cca = ret_value & 0xffff;
1875
1876 /* read CCK CRC32 counter */
1877 ret_value = odm_get_bb_reg(dm, ODM_REG_CCK_CRC32_CNT_11AC, MASKDWORD);
1878 fa_t->cnt_cck_crc32_error = (ret_value & 0xffff0000) >> 16;
1879 fa_t->cnt_cck_crc32_ok = ret_value & 0xffff;
1880
1881 /* read OFDM CRC32 counter */
1882 ret_value = odm_get_bb_reg(dm, ODM_REG_OFDM_CRC32_CNT_11AC, MASKDWORD);
1883 fa_t->cnt_ofdm_crc32_error = (ret_value & 0xffff0000) >> 16;
1884 fa_t->cnt_ofdm_crc32_ok = ret_value & 0xffff;
1885
1886 /* read OFDM2 CRC32 counter */
1887 ret_value = odm_get_bb_reg(dm, R_0xf1c, MASKDWORD);
1888 fa_t->cnt_ofdm2_crc32_ok = ret_value & 0xffff;
1889 fa_t->cnt_ofdm2_crc32_error = (ret_value & 0xffff0000) >> 16;
1890
1891 /* read HT CRC32 counter */
1892 ret_value = odm_get_bb_reg(dm, ODM_REG_HT_CRC32_CNT_11AC, MASKDWORD);
1893 fa_t->cnt_ht_crc32_error = (ret_value & 0xffff0000) >> 16;
1894 fa_t->cnt_ht_crc32_ok = ret_value & 0xffff;
1895
1896 /* read HT2 CRC32 counter */
1897 ret_value = odm_get_bb_reg(dm, R_0xf18, MASKDWORD);
1898 fa_t->cnt_ht2_crc32_ok = ret_value & 0xffff;
1899 fa_t->cnt_ht2_crc32_error = (ret_value & 0xffff0000) >> 16;
1900
1901 /* read VHT CRC32 counter */
1902 ret_value = odm_get_bb_reg(dm, ODM_REG_VHT_CRC32_CNT_11AC, MASKDWORD);
1903 fa_t->cnt_vht_crc32_error = (ret_value & 0xffff0000) >> 16;
1904 fa_t->cnt_vht_crc32_ok = ret_value & 0xffff;
1905
1906 /*read VHT2 CRC32 counter */
1907 ret_value = odm_get_bb_reg(dm, R_0xf54, MASKDWORD);
1908 fa_t->cnt_vht2_crc32_ok = ret_value & 0xffff;
1909 fa_t->cnt_vht2_crc32_error = (ret_value & 0xffff0000) >> 16;
1910
1911 #if (RTL8881A_SUPPORT)
1912 if (dm->support_ic_type == ODM_RTL8881A) {
1913 u32 tmp = 0;
1914
1915 if (fa_t->cnt_ofdm_fail >= fa_t->cnt_ofdm_fail_pre) {
1916 tmp = fa_t->cnt_ofdm_fail_pre;
1917 fa_t->cnt_ofdm_fail_pre = fa_t->cnt_ofdm_fail;
1918 fa_t->cnt_ofdm_fail = fa_t->cnt_ofdm_fail - tmp;
1919 } else {
1920 fa_t->cnt_ofdm_fail_pre = fa_t->cnt_ofdm_fail;
1921 }
1922
1923 PHYDM_DBG(dm, DBG_FA_CNT,
1924 "[8881]cnt_ofdm_fail{curr,pre}={%d,%d}\n",
1925 fa_t->cnt_ofdm_fail_pre, tmp);
1926 }
1927 #endif
1928
1929 cck_enable = odm_get_bb_reg(dm, ODM_REG_BB_RX_PATH_11AC, BIT(28));
1930
1931 if (cck_enable) { /* @if(*dm->band_type == ODM_BAND_2_4G) */
1932 fa_t->cnt_all = fa_t->cnt_ofdm_fail + fa_t->cnt_cck_fail;
1933 fa_t->cnt_cca_all = fa_t->cnt_cck_cca + fa_t->cnt_ofdm_cca;
1934 } else {
1935 fa_t->cnt_all = fa_t->cnt_ofdm_fail;
1936 fa_t->cnt_cca_all = fa_t->cnt_ofdm_cca;
1937 }
1938 }
1939 #endif
1940
phydm_get_edcca_report(void * dm_void)1941 u32 phydm_get_edcca_report(void *dm_void)
1942 {
1943 struct dm_struct *dm = (struct dm_struct *)dm_void;
1944 struct phydm_fa_struct *fa_t = &dm->false_alm_cnt;
1945 u32 dbg_port = dm->adaptivity.adaptivity_dbg_port;
1946 u32 val = 0;
1947
1948 if (dm->support_ic_type & ODM_RTL8723D) {
1949 val = odm_get_bb_reg(dm, R_0x9a0, BIT(29));
1950 } else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
1951 val = odm_get_bb_reg(dm, R_0x2d38, BIT(24));
1952 } else if (phydm_set_bb_dbg_port(dm, DBGPORT_PRI_1, dbg_port)) {
1953 if (dm->support_ic_type & (ODM_RTL8723B | ODM_RTL8188E))
1954 val = (phydm_get_bb_dbg_port_val(dm) & BIT(30)) >> 30;
1955 else
1956 val = (phydm_get_bb_dbg_port_val(dm) & BIT(29)) >> 29;
1957 phydm_release_bb_dbg_port(dm);
1958 }
1959
1960 return val;
1961 }
1962
phydm_get_dbg_port_info(void * dm_void)1963 void phydm_get_dbg_port_info(void *dm_void)
1964 {
1965 struct dm_struct *dm = (struct dm_struct *)dm_void;
1966 struct phydm_fa_struct *fa_t = &dm->false_alm_cnt;
1967
1968 if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
1969 fa_t->dbg_port0 = odm_get_bb_reg(dm, R_0x2db4, MASKDWORD);
1970 } else {
1971 /*set debug port to 0x0*/
1972 if (phydm_set_bb_dbg_port(dm, DBGPORT_PRI_1, 0x0)) {
1973 fa_t->dbg_port0 = phydm_get_bb_dbg_port_val(dm);
1974 phydm_release_bb_dbg_port(dm);
1975 }
1976 }
1977
1978 fa_t->edcca_flag = (boolean)phydm_get_edcca_report(dm);
1979
1980 PHYDM_DBG(dm, DBG_FA_CNT, "FA_Cnt: Dbg port 0x0 = 0x%x, EDCCA = %d\n",
1981 fa_t->dbg_port0, fa_t->edcca_flag);
1982 }
1983
phydm_set_crc32_cnt2_rate(void * dm_void,u8 rate_idx)1984 void phydm_set_crc32_cnt2_rate(void *dm_void, u8 rate_idx)
1985 {
1986 struct dm_struct *dm = (struct dm_struct *)dm_void;
1987 struct phydm_fa_struct *fa_t = &dm->false_alm_cnt;
1988 boolean is_ofdm_rate = phydm_is_ofdm_rate(dm, rate_idx);
1989 boolean is_ht_rate = phydm_is_ht_rate(dm, rate_idx);
1990 boolean is_vht_rate = phydm_is_vht_rate(dm, rate_idx);
1991 u32 reg_addr = 0x0;
1992 u32 ofdm_rate_bitmask = 0x0;
1993 u32 ht_mcs_bitmask = 0x0;
1994 u32 vht_mcs_bitmask = 0x0;
1995 u32 vht_ss_bitmask = 0x0;
1996 u8 rate = 0x0;
1997 u8 ss = 0x0;
1998
1999 if (!is_ofdm_rate && !is_ht_rate && !is_vht_rate)
2000 PHYDM_DBG(dm, DBG_FA_CNT,
2001 "[FA CNT] rate_idx = (0x%x) is not supported !\n",
2002 rate_idx);
2003
2004 switch (dm->ic_ip_series) {
2005 case PHYDM_IC_N:
2006 reg_addr = R_0xf04;
2007 ofdm_rate_bitmask = 0x0000f000;
2008 ht_mcs_bitmask = 0x007f0000;
2009 break;
2010 case PHYDM_IC_AC:
2011 reg_addr = R_0xb04;
2012 ofdm_rate_bitmask = 0x0000f000;
2013 ht_mcs_bitmask = 0x007f0000;
2014 vht_mcs_bitmask = 0x0f000000;
2015 vht_ss_bitmask = 0x30000000;
2016 break;
2017 case PHYDM_IC_JGR3:
2018 reg_addr = R_0x1eb8;
2019 ofdm_rate_bitmask = 0x00000f00;
2020 ht_mcs_bitmask = 0x007f0000;
2021 vht_mcs_bitmask = 0x0000f000;
2022 vht_ss_bitmask = 0x000000c0;
2023 break;
2024 default:
2025 break;
2026 }
2027
2028 if (is_ofdm_rate) {
2029 rate = phydm_legacy_rate_2_spec_rate(dm, rate_idx);
2030
2031 odm_set_bb_reg(dm, reg_addr, ofdm_rate_bitmask, rate);
2032 fa_t->ofdm2_rate_idx = rate_idx;
2033 } else if (is_ht_rate) {
2034 rate = phydm_rate_2_rate_digit(dm, rate_idx);
2035
2036 odm_set_bb_reg(dm, reg_addr, ht_mcs_bitmask, rate);
2037 fa_t->ht2_rate_idx = rate_idx;
2038 } else if (is_vht_rate) {
2039 rate = phydm_rate_2_rate_digit(dm, rate_idx);
2040 ss = phydm_rate_to_num_ss(dm, rate_idx);
2041
2042 odm_set_bb_reg(dm, reg_addr, vht_mcs_bitmask, rate);
2043 odm_set_bb_reg(dm, reg_addr, vht_ss_bitmask, ss - 1);
2044 fa_t->vht2_rate_idx = rate_idx;
2045 }
2046 }
2047
phydm_fa_cnt_cal_fa_duration(void * dm_void)2048 void phydm_fa_cnt_cal_fa_duration(void *dm_void)
2049 {
2050 struct dm_struct *dm = (struct dm_struct *)dm_void;
2051 struct ccx_info *ccx = &dm->dm_ccx_info;
2052 struct phydm_fa_struct *fa_t = &dm->false_alm_cnt;
2053 u8 norm = 0; /*normalization*/
2054 boolean fahm_chk = false;
2055
2056 fa_t->time_fa_all = fa_t->cnt_fast_fsync * 12 +
2057 fa_t->cnt_sb_search_fail * 12 +
2058 fa_t->cnt_parity_fail * 28 +
2059 fa_t->cnt_rate_illegal * 28 +
2060 fa_t->cnt_crc8_fail * 20 +
2061 fa_t->cnt_crc8_fail_vhta * 28 +
2062 fa_t->cnt_mcs_fail_vht * 36 +
2063 fa_t->cnt_mcs_fail * 32 +
2064 fa_t->cnt_cck_fail * 80;
2065
2066 fa_t->time_fa_exp = fa_t->cnt_ofdm_fail * OFDM_FA_EXP_DURATION +
2067 fa_t->cnt_cck_fail * CCK_FA_EXP_DURATION;
2068
2069 fa_t->time_fa_ifs_clm = 0;
2070 fa_t->time_fa_fahm = 0;
2071
2072 #ifdef IFS_CLM_SUPPORT
2073 if (ccx->ccx_watchdog_result & IFS_CLM_SUCCESS) {
2074 norm = (u8)PHYDM_DIV(PHYDM_WATCH_DOG_PERIOD * S_TO_US,
2075 ccx->ifs_clm_period);
2076 fa_t->time_fa_ifs_clm = (ccx->ifs_clm_cckfa +
2077 ccx->ifs_clm_ofdmfa) * norm;
2078 }
2079 #endif
2080
2081 #ifdef FAHM_SUPPORT
2082 if (ccx->ccx_watchdog_result & FAHM_SUCCESS) {
2083 if (fa_t->cnt_cck_fail) {
2084 if (ccx->fahm_inclu_cck)
2085 fahm_chk = true;
2086 } else {
2087 fahm_chk = true;
2088 }
2089 }
2090
2091 if (fahm_chk) {
2092 norm = (u8)PHYDM_DIV(PHYDM_WATCH_DOG_PERIOD * S_TO_US,
2093 ccx->fahm_period);
2094 fa_t->time_fa_fahm = ccx->fahm_result_sum * norm;
2095 }
2096 #endif
2097 }
2098
phydm_false_alarm_counter_statistics(void * dm_void)2099 void phydm_false_alarm_counter_statistics(void *dm_void)
2100 {
2101 struct dm_struct *dm = (struct dm_struct *)dm_void;
2102 struct phydm_fa_struct *fa_t = &dm->false_alm_cnt;
2103 char dbg_buf[PHYDM_SNPRINT_SIZE] = {0};
2104 u32 tmp = 0;
2105
2106 if (!(dm->support_ability & ODM_BB_FA_CNT))
2107 return;
2108
2109 PHYDM_DBG(dm, DBG_FA_CNT, "%s======>\n", __func__);
2110
2111 if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
2112 #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
2113 phydm_fa_cnt_statistics_jgr3(dm);
2114 #endif
2115 } else if (dm->support_ic_type & ODM_IC_11N_SERIES) {
2116 #if (ODM_IC_11N_SERIES_SUPPORT)
2117 phydm_fa_cnt_statistics_n(dm);
2118 #endif
2119 } else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
2120 #if (ODM_IC_11AC_SERIES_SUPPORT)
2121 phydm_fa_cnt_statistics_ac(dm);
2122 #endif
2123 }
2124
2125 phydm_get_dbg_port_info(dm);
2126 phydm_false_alarm_counter_reg_reset(dm_void);
2127
2128 phydm_fa_cnt_cal_fa_duration(dm);
2129
2130 fa_t->cnt_crc32_error_all = fa_t->cnt_vht_crc32_error +
2131 fa_t->cnt_ht_crc32_error +
2132 fa_t->cnt_ofdm_crc32_error +
2133 fa_t->cnt_cck_crc32_error;
2134
2135 fa_t->cnt_crc32_ok_all = fa_t->cnt_vht_crc32_ok +
2136 fa_t->cnt_ht_crc32_ok +
2137 fa_t->cnt_ofdm_crc32_ok +
2138 fa_t->cnt_cck_crc32_ok;
2139
2140 PHYDM_DBG(dm, DBG_FA_CNT,
2141 "[Tx cnt] {CCK_TxEN, CCK_TxON, OFDM_TxEN, OFDM_TxON} = {%d, %d, %d, %d}\n",
2142 fa_t->cnt_cck_txen, fa_t->cnt_cck_txon, fa_t->cnt_ofdm_txen,
2143 fa_t->cnt_ofdm_txon);
2144 PHYDM_DBG(dm, DBG_FA_CNT,
2145 "[CCA Cnt] {CCK, OFDM, Total} = {%d, %d, %d}\n",
2146 fa_t->cnt_cck_cca, fa_t->cnt_ofdm_cca, fa_t->cnt_cca_all);
2147 PHYDM_DBG(dm, DBG_FA_CNT,
2148 "[FA Cnt] {CCK, OFDM, Total} = {%d, %d, %d}\n",
2149 fa_t->cnt_cck_fail, fa_t->cnt_ofdm_fail, fa_t->cnt_all);
2150 PHYDM_DBG(dm, DBG_FA_CNT,
2151 "[FA duration(us)] {exp, ifs_clm, fahm} = {%d, %d, %d}\n",
2152 fa_t->time_fa_exp, fa_t->time_fa_ifs_clm,
2153 fa_t->time_fa_fahm);
2154 PHYDM_DBG(dm, DBG_FA_CNT,
2155 "[OFDM FA] Parity=%d, Rate=%d, Fast_Fsync=%d, SBD=%d\n",
2156 fa_t->cnt_parity_fail, fa_t->cnt_rate_illegal,
2157 fa_t->cnt_fast_fsync, fa_t->cnt_sb_search_fail);
2158 PHYDM_DBG(dm, DBG_FA_CNT, "[HT FA] CRC8=%d, MCS=%d\n",
2159 fa_t->cnt_crc8_fail, fa_t->cnt_mcs_fail);
2160 #if (ODM_IC_11AC_SERIES_SUPPORT || defined(PHYDM_IC_JGR3_SERIES_SUPPORT))
2161 if (dm->support_ic_type & (ODM_IC_11AC_SERIES | ODM_IC_JGR3_SERIES)) {
2162 PHYDM_DBG(dm, DBG_FA_CNT,
2163 "[VHT FA] SIGA_CRC8=%d, SIGB_CRC8=%d, MCS=%d\n",
2164 fa_t->cnt_crc8_fail_vhta, fa_t->cnt_crc8_fail_vhtb,
2165 fa_t->cnt_mcs_fail_vht);
2166 }
2167 #endif
2168
2169 PHYDM_DBG(dm, DBG_FA_CNT,
2170 "[CRC32 OK Cnt] {CCK, OFDM, HT, VHT, Total} = {%d, %d, %d, %d, %d}\n",
2171 fa_t->cnt_cck_crc32_ok, fa_t->cnt_ofdm_crc32_ok,
2172 fa_t->cnt_ht_crc32_ok, fa_t->cnt_vht_crc32_ok,
2173 fa_t->cnt_crc32_ok_all);
2174 PHYDM_DBG(dm, DBG_FA_CNT,
2175 "[CRC32 Err Cnt] {CCK, OFDM, HT, VHT, Total} = {%d, %d, %d, %d, %d}\n",
2176 fa_t->cnt_cck_crc32_error, fa_t->cnt_ofdm_crc32_error,
2177 fa_t->cnt_ht_crc32_error, fa_t->cnt_vht_crc32_error,
2178 fa_t->cnt_crc32_error_all);
2179
2180 if (fa_t->ofdm2_rate_idx) {
2181 tmp = fa_t->cnt_ofdm2_crc32_error + fa_t->cnt_ofdm2_crc32_ok;
2182 fa_t->ofdm2_pcr = (u8)PHYDM_DIV(fa_t->cnt_ofdm2_crc32_ok * 100,
2183 tmp);
2184 phydm_print_rate_2_buff(dm, fa_t->ofdm2_rate_idx, dbg_buf,
2185 PHYDM_SNPRINT_SIZE);
2186 PHYDM_DBG(dm, DBG_FA_CNT,
2187 "[OFDM:%s CRC32 Cnt] {error, ok}= {%d, %d} (%d percent)\n",
2188 dbg_buf, fa_t->cnt_ofdm2_crc32_error,
2189 fa_t->cnt_ofdm2_crc32_ok, fa_t->ofdm2_pcr);
2190 } else {
2191 phydm_set_crc32_cnt2_rate(dm, ODM_RATE6M);
2192 }
2193
2194 if (fa_t->ht2_rate_idx) {
2195 tmp = fa_t->cnt_ht2_crc32_error + fa_t->cnt_ht2_crc32_ok;
2196 fa_t->ht2_pcr = (u8)PHYDM_DIV(fa_t->cnt_ht2_crc32_ok * 100,
2197 tmp);
2198 phydm_print_rate_2_buff(dm, fa_t->ht2_rate_idx, dbg_buf,
2199 PHYDM_SNPRINT_SIZE);
2200 PHYDM_DBG(dm, DBG_FA_CNT,
2201 "[HT:%s CRC32 Cnt] {error, ok}= {%d, %d} (%d percent)\n",
2202 dbg_buf, fa_t->cnt_ht2_crc32_error,
2203 fa_t->cnt_ht2_crc32_ok, fa_t->ht2_pcr);
2204 } else {
2205 phydm_set_crc32_cnt2_rate(dm, ODM_RATEMCS0);
2206 }
2207
2208 #if (ODM_IC_11AC_SERIES_SUPPORT || defined(PHYDM_IC_JGR3_SERIES_SUPPORT))
2209 if (dm->support_ic_type & (ODM_IC_11AC_SERIES | ODM_IC_JGR3_SERIES)) {
2210 if (fa_t->vht2_rate_idx) {
2211 tmp = fa_t->cnt_vht2_crc32_error +
2212 fa_t->cnt_vht2_crc32_ok;
2213 fa_t->vht2_pcr = (u8)PHYDM_DIV(fa_t->cnt_vht2_crc32_ok *
2214 100, tmp);
2215 phydm_print_rate_2_buff(dm, fa_t->vht2_rate_idx,
2216 dbg_buf, PHYDM_SNPRINT_SIZE);
2217 PHYDM_DBG(dm, DBG_FA_CNT,
2218 "[VHT:%s CRC32 Cnt] {error, ok}= {%d, %d} (%d percent)\n",
2219 dbg_buf, fa_t->cnt_vht2_crc32_error,
2220 fa_t->cnt_vht2_crc32_ok, fa_t->vht2_pcr);
2221 } else {
2222 phydm_set_crc32_cnt2_rate(dm, ODM_RATEVHTSS1MCS0);
2223 }
2224 }
2225 #endif
2226 }
2227
phydm_fill_fw_dig_info(void * dm_void,boolean * enable,u8 * para4,u8 * para8)2228 void phydm_fill_fw_dig_info(void *dm_void, boolean *enable,
2229 u8 *para4, u8 *para8) {
2230 struct dm_struct *dm = (struct dm_struct *)dm_void;
2231 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
2232
2233 dig_t->fw_dig_enable = *enable;
2234 para8[0] = dig_t->rx_gain_range_max;
2235 para8[1] = dig_t->rx_gain_range_min;
2236 para8[2] = dm->number_linked_client;
2237 para4[0] = (u8)DIG_LPS_MODE;
2238 }
2239
phydm_crc32_cnt_dbg(void * dm_void,char input[][16],u32 * _used,char * output,u32 * _out_len)2240 void phydm_crc32_cnt_dbg(void *dm_void, char input[][16], u32 *_used,
2241 char *output, u32 *_out_len)
2242 {
2243 struct dm_struct *dm = (struct dm_struct *)dm_void;
2244 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
2245 char help[] = "-h";
2246 u32 var1[10] = {0};
2247 u32 used = *_used;
2248 u32 out_len = *_out_len;
2249 u8 i = 0;
2250 u8 rate = 0x0;
2251
2252 if ((strcmp(input[1], help) == 0)) {
2253 PDM_SNPF(out_len, used, output + used, out_len - used,
2254 "[CRC32 Cnt] {rate_idx}\n");
2255 } else {
2256 PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]);
2257 rate = (u8)var1[0];
2258
2259 PDM_SNPF(out_len, used, output + used, out_len - used,
2260 "{rate}={0x%x}", rate);
2261
2262 phydm_set_crc32_cnt2_rate(dm, rate);
2263 }
2264 *_used = used;
2265 *_out_len = out_len;
2266 }
2267
2268 #ifdef PHYDM_TDMA_DIG_SUPPORT
phydm_set_tdma_dig_timer(void * dm_void)2269 void phydm_set_tdma_dig_timer(void *dm_void)
2270 {
2271 struct dm_struct *dm = (struct dm_struct *)dm_void;
2272 u32 delta_time_us = dm->tdma_dig_timer_ms * 1000;
2273 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
2274 u32 timeout = 0;
2275 u32 current_time_stamp, diff_time_stamp, regb0 = 0;
2276
2277 /*some IC has no FREERUN_CUNT register, like 92E*/
2278 if (dm->support_ic_type & ODM_RTL8197F)
2279 current_time_stamp = odm_get_bb_reg(dm, R_0x568, 0xffffffff);
2280 else
2281 return;
2282
2283 timeout = current_time_stamp + delta_time_us;
2284
2285 diff_time_stamp = current_time_stamp - dig_t->cur_timestamp;
2286 dig_t->pre_timestamp = dig_t->cur_timestamp;
2287 dig_t->cur_timestamp = current_time_stamp;
2288
2289 /*@HIMR0, it shows HW interrupt mask*/
2290 regb0 = odm_get_bb_reg(dm, R_0xb0, 0xffffffff);
2291
2292 PHYDM_DBG(dm, DBG_DIG, "Set next timer\n");
2293 PHYDM_DBG(dm, DBG_DIG,
2294 "curr_time_stamp=%d, delta_time_us=%d\n",
2295 current_time_stamp, delta_time_us);
2296 PHYDM_DBG(dm, DBG_DIG,
2297 "timeout=%d, diff_time_stamp=%d, Reg0xb0 = 0x%x\n",
2298 timeout, diff_time_stamp, regb0);
2299
2300 if (dm->support_ic_type & ODM_RTL8197F) /*REG_PS_TIMER2*/
2301 odm_set_bb_reg(dm, R_0x588, 0xffffffff, timeout);
2302 else {
2303 PHYDM_DBG(dm, DBG_DIG, "NOT 97F, NOT start\n");
2304 return;
2305 }
2306 }
2307
phydm_tdma_dig_timer_check(void * dm_void)2308 void phydm_tdma_dig_timer_check(void *dm_void)
2309 {
2310 struct dm_struct *dm = (struct dm_struct *)dm_void;
2311 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
2312
2313 PHYDM_DBG(dm, DBG_DIG, "tdma_dig_cnt=%d, pre_tdma_dig_cnt=%d\n",
2314 dig_t->tdma_dig_cnt, dig_t->pre_tdma_dig_cnt);
2315
2316 if (dig_t->tdma_dig_cnt == 0 ||
2317 dig_t->tdma_dig_cnt == dig_t->pre_tdma_dig_cnt) {
2318 if (dm->support_ability & ODM_BB_DIG) {
2319 #ifdef IS_USE_NEW_TDMA
2320 if (dm->support_ic_type & (ODM_RTL8198F | ODM_RTL8814B |
2321 ODM_RTL8812F | ODM_RTL8822B | ODM_RTL8192F |
2322 ODM_RTL8821C | ODM_RTL8197G | ODM_RTL8822C |
2323 ODM_RTL8723D | ODM_RTL8723F | ODM_RTL8814C)) {
2324 PHYDM_DBG(dm, DBG_DIG,
2325 "Check fail, Restart timer\n\n");
2326 phydm_false_alarm_counter_reset(dm);
2327 odm_set_timer(dm, &dm->tdma_dig_timer,
2328 dm->tdma_dig_timer_ms);
2329 } else {
2330 PHYDM_DBG(dm, DBG_DIG,
2331 "Not support TDMADIG, no SW timer\n");
2332 }
2333 #else
2334 /*@if interrupt mask info is got.*/
2335 /*Reg0xb0 is no longer needed*/
2336 #if 0
2337 /*regb0 = odm_get_bb_reg(dm, R_0xb0, bMaskDWord);*/
2338 #endif
2339 PHYDM_DBG(dm, DBG_DIG,
2340 "Check fail, Mask[0]=0x%x, restart timer\n",
2341 *dm->interrupt_mask);
2342
2343 phydm_tdma_dig_add_interrupt_mask_handler(dm);
2344 phydm_enable_rx_related_interrupt_handler(dm);
2345 phydm_set_tdma_dig_timer(dm);
2346 #endif
2347 }
2348 } else {
2349 PHYDM_DBG(dm, DBG_DIG, "Check pass, update pre_tdma_dig_cnt\n");
2350 }
2351
2352 dig_t->pre_tdma_dig_cnt = dig_t->tdma_dig_cnt;
2353 }
2354
2355 /*@different IC/team may use different timer for tdma-dig*/
phydm_tdma_dig_add_interrupt_mask_handler(void * dm_void)2356 void phydm_tdma_dig_add_interrupt_mask_handler(void *dm_void)
2357 {
2358 struct dm_struct *dm = (struct dm_struct *)dm_void;
2359
2360 #if (DM_ODM_SUPPORT_TYPE == (ODM_AP))
2361 if (dm->support_ic_type & ODM_RTL8197F) {
2362 /*@HAL_INT_TYPE_PSTIMEOUT2*/
2363 phydm_add_interrupt_mask_handler(dm, HAL_INT_TYPE_PSTIMEOUT2);
2364 }
2365 #elif (DM_ODM_SUPPORT_TYPE == (ODM_WIN))
2366 #elif (DM_ODM_SUPPORT_TYPE == (ODM_CE))
2367 #endif
2368 }
2369
2370 /* will be triggered by HW timer*/
phydm_tdma_dig(void * dm_void)2371 void phydm_tdma_dig(void *dm_void)
2372 {
2373 struct dm_struct *dm = (struct dm_struct *)dm_void;
2374 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
2375 struct phydm_fa_struct *falm_cnt = &dm->false_alm_cnt;
2376 u32 reg_c50 = 0;
2377
2378 #if (RTL8198F_SUPPORT || RTL8814B_SUPPORT || RTL8812F_SUPPORT ||\
2379 RTL8822B_SUPPORT || RTL8192F_SUPPORT || RTL8821C_SUPPORT)
2380 #ifdef IS_USE_NEW_TDMA
2381 if (dm->support_ic_type &
2382 (ODM_RTL8198F | ODM_RTL8814B | ODM_RTL8812F | ODM_RTL8822B |
2383 ODM_RTL8192F | ODM_RTL8821C | ODM_RTL8814C)) {
2384 PHYDM_DBG(dm, DBG_DIG, "98F/14B/12F/22B/92F/21C, new tdma\n");
2385 return;
2386 }
2387 #endif
2388 #endif
2389 reg_c50 = odm_get_bb_reg(dm, R_0xc50, MASKBYTE0);
2390
2391 dig_t->tdma_dig_state =
2392 dig_t->tdma_dig_cnt % dm->tdma_dig_state_number;
2393
2394 PHYDM_DBG(dm, DBG_DIG, "tdma_dig_state=%d, regc50=0x%x\n",
2395 dig_t->tdma_dig_state, reg_c50);
2396
2397 dig_t->tdma_dig_cnt++;
2398
2399 if (dig_t->tdma_dig_state == 1) {
2400 /* update IGI from tdma_dig_state == 0*/
2401 if (dig_t->cur_ig_value_tdma == 0)
2402 dig_t->cur_ig_value_tdma = dig_t->cur_ig_value;
2403
2404 odm_write_dig(dm, dig_t->cur_ig_value_tdma);
2405 phydm_tdma_false_alarm_counter_check(dm);
2406 PHYDM_DBG(dm, DBG_DIG, "tdma_dig_state=%d, reset FA counter\n",
2407 dig_t->tdma_dig_state);
2408
2409 } else if (dig_t->tdma_dig_state == 0) {
2410 /* update dig_t->CurIGValue,*/
2411 /* @it may different from dig_t->cur_ig_value_tdma */
2412 /* TDMA IGI upperbond @ L-state = */
2413 /* rf_ft_var.tdma_dig_low_upper_bond = 0x26 */
2414
2415 if (dig_t->cur_ig_value >= dm->tdma_dig_low_upper_bond)
2416 dig_t->low_ig_value = dm->tdma_dig_low_upper_bond;
2417 else
2418 dig_t->low_ig_value = dig_t->cur_ig_value;
2419
2420 odm_write_dig(dm, dig_t->low_ig_value);
2421 phydm_tdma_false_alarm_counter_check(dm);
2422 } else {
2423 phydm_tdma_false_alarm_counter_check(dm);
2424 }
2425 }
2426
2427 /*@============================================================*/
2428 /*@FASLE ALARM CHECK*/
2429 /*@============================================================*/
phydm_tdma_false_alarm_counter_check(void * dm_void)2430 void phydm_tdma_false_alarm_counter_check(void *dm_void)
2431 {
2432 struct dm_struct *dm = (struct dm_struct *)dm_void;
2433 struct phydm_fa_struct *falm_cnt = &dm->false_alm_cnt;
2434 struct phydm_fa_acc_struct *falm_cnt_acc = &dm->false_alm_cnt_acc;
2435 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
2436 boolean rssi_dump_en = 0;
2437 u32 timestamp = 0;
2438 u8 tdma_dig_state_number = 0;
2439 u32 start_th = 0;
2440
2441 if (dig_t->tdma_dig_state == 1)
2442 phydm_false_alarm_counter_reset(dm);
2443 /* Reset FalseAlarmCounterStatistics */
2444 /* @fa_acc_1sec_tsf = fa_acc_1sec_tsf, keep */
2445 /* @fa_end_tsf = fa_start_tsf = TSF */
2446 else {
2447 phydm_false_alarm_counter_statistics(dm);
2448 if (dm->support_ic_type & ODM_RTL8197F) /*REG_FREERUN_CNT*/
2449 timestamp = odm_get_bb_reg(dm, R_0x568, bMaskDWord);
2450 else {
2451 PHYDM_DBG(dm, DBG_DIG, "NOT 97F! NOT start\n");
2452 return;
2453 }
2454 dig_t->fa_end_timestamp = timestamp;
2455 dig_t->fa_acc_1sec_timestamp +=
2456 (dig_t->fa_end_timestamp - dig_t->fa_start_timestamp);
2457
2458 /*prevent dumb*/
2459 if (dm->tdma_dig_state_number == 1)
2460 dm->tdma_dig_state_number = 2;
2461
2462 tdma_dig_state_number = dm->tdma_dig_state_number;
2463 dig_t->sec_factor =
2464 tdma_dig_state_number / (tdma_dig_state_number - 1);
2465
2466 /*@1sec = 1000000us*/
2467 if (dig_t->sec_factor)
2468 start_th = (u32)(1000000 / dig_t->sec_factor);
2469
2470 if (dig_t->fa_acc_1sec_timestamp >= start_th) {
2471 rssi_dump_en = 1;
2472 phydm_false_alarm_counter_acc(dm, rssi_dump_en);
2473 PHYDM_DBG(dm, DBG_DIG,
2474 "sec_factor=%d, total FA=%d, is_linked=%d\n",
2475 dig_t->sec_factor, falm_cnt_acc->cnt_all,
2476 dm->is_linked);
2477
2478 phydm_noisy_detection(dm);
2479 #ifdef PHYDM_SUPPORT_CCKPD
2480 phydm_cck_pd_th(dm);
2481 #endif
2482 phydm_dig(dm);
2483 phydm_false_alarm_counter_acc_reset(dm);
2484
2485 /* Reset FalseAlarmCounterStatistics */
2486 /* @fa_end_tsf = fa_start_tsf = TSF, keep */
2487 /* @fa_acc_1sec_tsf = 0 */
2488 phydm_false_alarm_counter_reset(dm);
2489 } else {
2490 phydm_false_alarm_counter_acc(dm, rssi_dump_en);
2491 }
2492 }
2493 }
2494
phydm_false_alarm_counter_acc(void * dm_void,boolean rssi_dump_en)2495 void phydm_false_alarm_counter_acc(void *dm_void, boolean rssi_dump_en)
2496 {
2497 struct dm_struct *dm = (struct dm_struct *)dm_void;
2498 struct phydm_fa_struct *falm_cnt = &dm->false_alm_cnt;
2499 struct phydm_fa_acc_struct *falm_cnt_acc = &dm->false_alm_cnt_acc;
2500 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
2501
2502 falm_cnt_acc->cnt_parity_fail += falm_cnt->cnt_parity_fail;
2503 falm_cnt_acc->cnt_rate_illegal += falm_cnt->cnt_rate_illegal;
2504 falm_cnt_acc->cnt_crc8_fail += falm_cnt->cnt_crc8_fail;
2505 falm_cnt_acc->cnt_mcs_fail += falm_cnt->cnt_mcs_fail;
2506 falm_cnt_acc->cnt_ofdm_fail += falm_cnt->cnt_ofdm_fail;
2507 falm_cnt_acc->cnt_cck_fail += falm_cnt->cnt_cck_fail;
2508 falm_cnt_acc->cnt_all += falm_cnt->cnt_all;
2509 falm_cnt_acc->cnt_fast_fsync += falm_cnt->cnt_fast_fsync;
2510 falm_cnt_acc->cnt_sb_search_fail += falm_cnt->cnt_sb_search_fail;
2511 falm_cnt_acc->cnt_ofdm_cca += falm_cnt->cnt_ofdm_cca;
2512 falm_cnt_acc->cnt_cck_cca += falm_cnt->cnt_cck_cca;
2513 falm_cnt_acc->cnt_cca_all += falm_cnt->cnt_cca_all;
2514 falm_cnt_acc->cnt_cck_crc32_error += falm_cnt->cnt_cck_crc32_error;
2515 falm_cnt_acc->cnt_cck_crc32_ok += falm_cnt->cnt_cck_crc32_ok;
2516 falm_cnt_acc->cnt_ofdm_crc32_error += falm_cnt->cnt_ofdm_crc32_error;
2517 falm_cnt_acc->cnt_ofdm_crc32_ok += falm_cnt->cnt_ofdm_crc32_ok;
2518 falm_cnt_acc->cnt_ht_crc32_error += falm_cnt->cnt_ht_crc32_error;
2519 falm_cnt_acc->cnt_ht_crc32_ok += falm_cnt->cnt_ht_crc32_ok;
2520 falm_cnt_acc->cnt_vht_crc32_error += falm_cnt->cnt_vht_crc32_error;
2521 falm_cnt_acc->cnt_vht_crc32_ok += falm_cnt->cnt_vht_crc32_ok;
2522 falm_cnt_acc->cnt_crc32_error_all += falm_cnt->cnt_crc32_error_all;
2523 falm_cnt_acc->cnt_crc32_ok_all += falm_cnt->cnt_crc32_ok_all;
2524
2525 if (rssi_dump_en == 1) {
2526 falm_cnt_acc->cnt_all_1sec =
2527 falm_cnt_acc->cnt_all * dig_t->sec_factor;
2528 falm_cnt_acc->cnt_cca_all_1sec =
2529 falm_cnt_acc->cnt_cca_all * dig_t->sec_factor;
2530 falm_cnt_acc->cnt_cck_fail_1sec =
2531 falm_cnt_acc->cnt_cck_fail * dig_t->sec_factor;
2532 }
2533 }
2534
phydm_false_alarm_counter_acc_reset(void * dm_void)2535 void phydm_false_alarm_counter_acc_reset(void *dm_void)
2536 {
2537 struct dm_struct *dm = (struct dm_struct *)dm_void;
2538 struct phydm_fa_acc_struct *falm_cnt_acc = NULL;
2539
2540 #ifdef IS_USE_NEW_TDMA
2541 struct phydm_fa_acc_struct *falm_cnt_acc_low = NULL;
2542 u32 tmp_cca_1sec = 0;
2543 u32 tmp_fa_1sec = 0;
2544
2545 /*@clear L-fa_acc struct*/
2546 falm_cnt_acc_low = &dm->false_alm_cnt_acc_low;
2547 tmp_cca_1sec = falm_cnt_acc_low->cnt_cca_all_1sec;
2548 tmp_fa_1sec = falm_cnt_acc_low->cnt_all_1sec;
2549 odm_memory_set(dm, falm_cnt_acc_low, 0, sizeof(dm->false_alm_cnt_acc));
2550 falm_cnt_acc_low->cnt_cca_all_1sec = tmp_cca_1sec;
2551 falm_cnt_acc_low->cnt_all_1sec = tmp_fa_1sec;
2552
2553 /*@clear H-fa_acc struct*/
2554 falm_cnt_acc = &dm->false_alm_cnt_acc;
2555 tmp_cca_1sec = falm_cnt_acc->cnt_cca_all_1sec;
2556 tmp_fa_1sec = falm_cnt_acc->cnt_all_1sec;
2557 odm_memory_set(dm, falm_cnt_acc, 0, sizeof(dm->false_alm_cnt_acc));
2558 falm_cnt_acc->cnt_cca_all_1sec = tmp_cca_1sec;
2559 falm_cnt_acc->cnt_all_1sec = tmp_fa_1sec;
2560 #else
2561 falm_cnt_acc = &dm->false_alm_cnt_acc;
2562 /* @Cnt_all_for_rssi_dump & Cnt_CCA_all_for_rssi_dump */
2563 /* @do NOT need to be reset */
2564 odm_memory_set(dm, falm_cnt_acc, 0, sizeof(falm_cnt_acc));
2565 #endif
2566 }
2567
phydm_false_alarm_counter_reset(void * dm_void)2568 void phydm_false_alarm_counter_reset(void *dm_void)
2569 {
2570 struct dm_struct *dm = (struct dm_struct *)dm_void;
2571 struct phydm_fa_struct *falm_cnt;
2572 struct phydm_dig_struct *dig_t;
2573 u32 timestamp;
2574
2575 falm_cnt = &dm->false_alm_cnt;
2576 dig_t = &dm->dm_dig_table;
2577
2578 memset(falm_cnt, 0, sizeof(dm->false_alm_cnt));
2579 phydm_false_alarm_counter_reg_reset(dm);
2580
2581 #ifdef IS_USE_NEW_TDMA
2582 return;
2583 #endif
2584 if (dig_t->tdma_dig_state != 1)
2585 dig_t->fa_acc_1sec_timestamp = 0;
2586 else
2587 dig_t->fa_acc_1sec_timestamp = dig_t->fa_acc_1sec_timestamp;
2588
2589 /*REG_FREERUN_CNT*/
2590 timestamp = odm_get_bb_reg(dm, R_0x568, bMaskDWord);
2591 dig_t->fa_start_timestamp = timestamp;
2592 dig_t->fa_end_timestamp = timestamp;
2593 }
2594
phydm_tdma_dig_para_upd(void * dm_void,enum upd_type type,u8 input)2595 void phydm_tdma_dig_para_upd(void *dm_void, enum upd_type type, u8 input)
2596 {
2597 struct dm_struct *dm = (struct dm_struct *)dm_void;
2598
2599 switch (type) {
2600 case ENABLE_TDMA:
2601 dm->original_dig_restore = !((boolean)input);
2602 break;
2603 case MODE_DECISION:
2604 if (input == (u8)MODE_PERFORMANCE)
2605 dm->tdma_dig_state_number = DIG_NUM_OF_TDMA_STATES + 2;
2606 else if (input == (u8)MODE_COVERAGE)
2607 dm->tdma_dig_state_number = DIG_NUM_OF_TDMA_STATES;
2608 else
2609 dm->tdma_dig_state_number = DIG_NUM_OF_TDMA_STATES;
2610 break;
2611 }
2612 }
2613
2614 #ifdef IS_USE_NEW_TDMA
2615 #if defined(CONFIG_RTL_TRIBAND_SUPPORT) && defined(CONFIG_USB_HCI)
pre_phydm_tdma_dig_cbk(unsigned long task_dm)2616 static void pre_phydm_tdma_dig_cbk(unsigned long task_dm)
2617 {
2618 struct dm_struct *dm = (struct dm_struct *)task_dm;
2619 struct rtl8192cd_priv *priv = dm->priv;
2620 struct priv_shared_info *pshare = priv->pshare;
2621
2622 if (!(priv->drv_state & DRV_STATE_OPEN))
2623 return;
2624
2625 if (pshare->bDriverStopped || pshare->bSurpriseRemoved) {
2626 printk("[%s] bDriverStopped(%d) OR bSurpriseRemoved(%d)\n",
2627 __FUNCTION__, pshare->bDriverStopped,
2628 pshare->bSurpriseRemoved);
2629 return;
2630 }
2631
2632 rtw_enqueue_timer_event(priv, &pshare->tdma_dig_event,
2633 ENQUEUE_TO_TAIL);
2634 }
2635
phydm_tdma_dig_timers_usb(void * dm_void,u8 state)2636 void phydm_tdma_dig_timers_usb(void *dm_void, u8 state)
2637 {
2638 struct dm_struct *dm = (struct dm_struct *)dm_void;
2639 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
2640
2641 if (state == INIT_TDMA_DIG_TIMMER) {
2642 struct rtl8192cd_priv *priv = dm->priv;
2643
2644 init_timer(&dm->tdma_dig_timer);
2645 dm->tdma_dig_timer.data = (unsigned long)dm;
2646 dm->tdma_dig_timer.function = pre_phydm_tdma_dig_cbk;
2647 INIT_TIMER_EVENT_ENTRY(&priv->pshare->tdma_dig_event,
2648 phydm_tdma_dig_cbk,
2649 (unsigned long)dm);
2650 } else if (state == CANCEL_TDMA_DIG_TIMMER) {
2651 odm_cancel_timer(dm, &dm->tdma_dig_timer);
2652 } else if (state == RELEASE_TDMA_DIG_TIMMER) {
2653 odm_release_timer(dm, &dm->tdma_dig_timer);
2654 }
2655 }
2656 #endif /* defined(CONFIG_RTL_TRIBAND_SUPPORT) && defined(CONFIG_USB_HCI) */
2657
phydm_tdma_dig_timers(void * dm_void,u8 state)2658 void phydm_tdma_dig_timers(void *dm_void, u8 state)
2659 {
2660 struct dm_struct *dm = (struct dm_struct *)dm_void;
2661 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
2662 #if defined(CONFIG_RTL_TRIBAND_SUPPORT) && defined(CONFIG_USB_HCI)
2663 struct rtl8192cd_priv *priv = dm->priv;
2664
2665 if (priv->hci_type == RTL_HCI_USB) {
2666 phydm_tdma_dig_timers_usb(dm_void, state);
2667 return;
2668 }
2669 #endif /* defined(CONFIG_RTL_TRIBAND_SUPPORT) && defined(CONFIG_USB_HCI) */
2670
2671 if (state == INIT_TDMA_DIG_TIMMER)
2672 odm_initialize_timer(dm, &dm->tdma_dig_timer,
2673 (void *)phydm_tdma_dig_cbk,
2674 NULL, "phydm_tdma_dig_timer");
2675 else if (state == CANCEL_TDMA_DIG_TIMMER)
2676 odm_cancel_timer(dm, &dm->tdma_dig_timer);
2677 else if (state == RELEASE_TDMA_DIG_TIMMER)
2678 odm_release_timer(dm, &dm->tdma_dig_timer);
2679 }
2680
get_new_igi_bound(struct dm_struct * dm,u8 igi,u32 fa_cnt,u8 * rx_gain_max,u8 * rx_gain_min,boolean is_dfs_band)2681 u8 get_new_igi_bound(struct dm_struct *dm, u8 igi, u32 fa_cnt, u8 *rx_gain_max,
2682 u8 *rx_gain_min, boolean is_dfs_band)
2683 {
2684 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
2685 u8 step[3] = {0};
2686 u8 cur_igi = igi;
2687
2688 if (dm->is_linked) {
2689 if (dm->pre_rssi_min <= dm->rssi_min) {
2690 PHYDM_DBG(dm, DBG_DIG, "pre_rssi_min <= rssi_min\n");
2691 step[0] = 2;
2692 step[1] = 1;
2693 step[2] = 2;
2694 } else {
2695 step[0] = 4;
2696 step[1] = 2;
2697 step[2] = 2;
2698 }
2699 } else {
2700 step[0] = 2;
2701 step[1] = 1;
2702 step[2] = 2;
2703 }
2704
2705 PHYDM_DBG(dm, DBG_DIG, "step = {-%d, +%d, +%d}\n", step[2], step[1],
2706 step[0]);
2707
2708 if (dm->first_connect) {
2709 if (is_dfs_band) {
2710 if (dm->rssi_min > DIG_MAX_DFS)
2711 igi = DIG_MAX_DFS;
2712 else
2713 igi = dm->rssi_min;
2714 PHYDM_DBG(dm, DBG_DIG, "DFS band:IgiMax=0x%x\n",
2715 *rx_gain_max);
2716 } else {
2717 igi = *rx_gain_min;
2718 }
2719
2720 #if 0
2721 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
2722 #if (RTL8812A_SUPPORT)
2723 if (dm->support_ic_type == ODM_RTL8812)
2724 odm_config_bb_with_header_file(dm,
2725 CONFIG_BB_AGC_TAB_DIFF);
2726 #endif
2727 #endif
2728 #endif
2729 PHYDM_DBG(dm, DBG_DIG, "First connect: foce IGI=0x%x\n", igi);
2730 } else {
2731 /* @2 Before link */
2732 PHYDM_DBG(dm, DBG_DIG, "Adjust IGI before link\n");
2733
2734 if (dm->first_disconnect) {
2735 igi = dig_t->dm_dig_min;
2736 PHYDM_DBG(dm, DBG_DIG,
2737 "First disconnect:foce IGI to lower bound\n");
2738 } else {
2739 PHYDM_DBG(dm, DBG_DIG, "Pre_IGI=((0x%x)), FA=((%d))\n",
2740 igi, fa_cnt);
2741
2742 igi = phydm_new_igi_by_fa(dm, igi, fa_cnt, step);
2743 }
2744 }
2745 /*@Check IGI by dyn-upper/lower bound */
2746 if (igi < *rx_gain_min)
2747 igi = *rx_gain_min;
2748
2749 if (igi > *rx_gain_max)
2750 igi = *rx_gain_max;
2751
2752 PHYDM_DBG(dm, DBG_DIG, "fa_cnt = %d, IGI: 0x%x -> 0x%x\n",
2753 fa_cnt, cur_igi, igi);
2754
2755 return igi;
2756 }
2757
phydm_write_tdma_dig(void * dm_void,u8 new_igi)2758 void phydm_write_tdma_dig(void *dm_void, u8 new_igi)
2759 {
2760 struct dm_struct *dm = (struct dm_struct *)dm_void;
2761 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
2762 struct phydm_adaptivity_struct *adaptivity = &dm->adaptivity;
2763
2764 PHYDM_DBG(dm, DBG_DIG, "%s===>\n", __func__);
2765 #if 0
2766 /* @1 Check IGI by upper bound */
2767 if (adaptivity->igi_lmt_en &&
2768 new_igi > adaptivity->adapt_igi_up && dm->is_linked) {
2769 new_igi = adaptivity->adapt_igi_up;
2770
2771 PHYDM_DBG(dm, DBG_DIG, "Force Adaptivity Up-bound=((0x%x))\n",
2772 new_igi);
2773 }
2774 #endif
2775 phydm_write_dig_reg(dm, new_igi);
2776
2777 PHYDM_DBG(dm, DBG_DIG, "New %s-IGI=((0x%x))\n",
2778 (dig_t->tdma_dig_state == TDMA_DIG_LOW_STATE) ? "L" : "H",
2779 new_igi);
2780 }
2781
phydm_tdma_dig_new(void * dm_void)2782 void phydm_tdma_dig_new(void *dm_void)
2783 {
2784 struct dm_struct *dm = (struct dm_struct *)dm_void;
2785 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
2786
2787 if (phydm_dig_abort(dm) || dm->original_dig_restore)
2788 return;
2789 /*@
2790 *PHYDM_DBG(dm, DBG_DIG, "timer callback =======> tdma_dig_state=%d\n");
2791 * dig_t->tdma_dig_state);
2792 *PHYDM_DBG(dm, DBG_DIG, "tdma_h_igi=0x%x, tdma_l_igi=0x%x\n",
2793 * dig_t->cur_ig_value_tdma,
2794 * dig_t->low_ig_value);
2795 */
2796 phydm_tdma_fa_cnt_chk(dm);
2797
2798 /*@prevent dumb*/
2799 if (dm->tdma_dig_state_number < 2)
2800 dm->tdma_dig_state_number = 2;
2801
2802 /*@update state*/
2803 dig_t->tdma_dig_cnt++;
2804 dig_t->tdma_dig_state = dig_t->tdma_dig_cnt % dm->tdma_dig_state_number;
2805
2806 /*@
2807 *PHYDM_DBG(dm, DBG_DIG, "enter state %d, dig count %d\n",
2808 * dig_t->tdma_dig_state, dig_t->tdma_dig_cnt);
2809 */
2810
2811 if (dig_t->tdma_dig_state == TDMA_DIG_LOW_STATE)
2812 odm_write_dig(dm, dig_t->low_ig_value);
2813 else if (dig_t->tdma_dig_state >= TDMA_DIG_HIGH_STATE)
2814 odm_write_dig(dm, dig_t->cur_ig_value_tdma);
2815
2816 odm_set_timer(dm, &dm->tdma_dig_timer, dm->tdma_dig_timer_ms);
2817 }
2818
2819 /*@callback function triggered by SW timer*/
2820 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
phydm_tdma_dig_cbk(struct phydm_timer_list * timer)2821 void phydm_tdma_dig_cbk(struct phydm_timer_list *timer)
2822 {
2823 void *adapter = (void *)timer->Adapter;
2824 HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
2825 struct dm_struct *dm = &hal_data->DM_OutSrcs;
2826
2827 #if DEV_BUS_TYPE == RT_PCI_INTERFACE
2828 #if USE_WORKITEM
2829 odm_schedule_work_item(&dm->phydm_tdma_dig_workitem);
2830 #else
2831 phydm_tdma_dig_new(dm);
2832 #endif
2833 #else
2834 odm_schedule_work_item(&dm->phydm_tdma_dig_workitem);
2835 #endif
2836 }
2837
phydm_tdma_dig_workitem_callback(void * context)2838 void phydm_tdma_dig_workitem_callback(void *context)
2839 {
2840 void *adapter = (void *)context;
2841 HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
2842 struct dm_struct *dm = &hal_data->DM_OutSrc;
2843
2844 phydm_tdma_dig_new(dm);
2845 }
2846
2847 #elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
phydm_tdma_dig_cbk(void * dm_void)2848 void phydm_tdma_dig_cbk(void *dm_void)
2849 {
2850 struct dm_struct *dm = (struct dm_struct *)dm_void;
2851 void *padapter = dm->adapter;
2852
2853 if (dm->support_interface == ODM_ITRF_PCIE)
2854 phydm_tdma_dig_workitem_callback(dm);
2855 /* @Can't do I/O in timer callback*/
2856 else
2857 phydm_run_in_thread_cmd(dm, phydm_tdma_dig_workitem_callback,
2858 dm);
2859 }
2860
phydm_tdma_dig_workitem_callback(void * dm_void)2861 void phydm_tdma_dig_workitem_callback(void *dm_void)
2862 {
2863 struct dm_struct *dm = (struct dm_struct *)dm_void;
2864 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
2865
2866 if (phydm_dig_abort(dm) || (dm->original_dig_restore))
2867 return;
2868 /*@
2869 *PHYDM_DBG(dm, DBG_DIG, "timer callback =======> tdma_dig_state=%d\n");
2870 * dig_t->tdma_dig_state);
2871 *PHYDM_DBG(dm, DBG_DIG, "tdma_h_igi=0x%x, tdma_l_igi=0x%x\n",
2872 * dig_t->cur_ig_value_tdma,
2873 * dig_t->low_ig_value);
2874 */
2875 phydm_tdma_fa_cnt_chk(dm);
2876
2877 /*@prevent dumb*/
2878 if (dm->tdma_dig_state_number < 2)
2879 dm->tdma_dig_state_number = 2;
2880
2881 /*@update state*/
2882 dig_t->tdma_dig_cnt++;
2883 dig_t->tdma_dig_state = dig_t->tdma_dig_cnt % dm->tdma_dig_state_number;
2884
2885 /*@
2886 *PHYDM_DBG(dm, DBG_DIG, "enter state %d, dig count %d\n",
2887 * dig_t->tdma_dig_state, dig_t->tdma_dig_cnt);
2888 */
2889
2890 if (dig_t->tdma_dig_state == TDMA_DIG_LOW_STATE)
2891 odm_write_dig(dm, dig_t->low_ig_value);
2892 else if (dig_t->tdma_dig_state >= TDMA_DIG_HIGH_STATE)
2893 odm_write_dig(dm, dig_t->cur_ig_value_tdma);
2894
2895 odm_set_timer(dm, &dm->tdma_dig_timer, dm->tdma_dig_timer_ms);
2896 }
2897 #else
phydm_tdma_dig_cbk(void * dm_void)2898 void phydm_tdma_dig_cbk(void *dm_void)
2899 {
2900 struct dm_struct *dm = (struct dm_struct *)dm_void;
2901 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
2902
2903 if (phydm_dig_abort(dm) || dm->original_dig_restore)
2904 return;
2905 /*@
2906 *PHYDM_DBG(dm, DBG_DIG, "timer callback =======> tdma_dig_state=%d\n");
2907 * dig_t->tdma_dig_state);
2908 *PHYDM_DBG(dm, DBG_DIG, "tdma_h_igi=0x%x, tdma_l_igi=0x%x\n",
2909 * dig_t->cur_ig_value_tdma,
2910 * dig_t->low_ig_value);
2911 */
2912 phydm_tdma_fa_cnt_chk(dm);
2913
2914 /*@prevent dumb*/
2915 if (dm->tdma_dig_state_number < 2)
2916 dm->tdma_dig_state_number = 2;
2917
2918 /*@update state*/
2919 dig_t->tdma_dig_cnt++;
2920 dig_t->tdma_dig_state = dig_t->tdma_dig_cnt % dm->tdma_dig_state_number;
2921
2922 /*@
2923 *PHYDM_DBG(dm, DBG_DIG, "enter state %d, dig count %d\n",
2924 * dig_t->tdma_dig_state, dig_t->tdma_dig_cnt);
2925 */
2926
2927 if (dig_t->tdma_dig_state == TDMA_DIG_LOW_STATE)
2928 phydm_write_tdma_dig(dm, dig_t->low_ig_value);
2929 else if (dig_t->tdma_dig_state >= TDMA_DIG_HIGH_STATE)
2930 phydm_write_tdma_dig(dm, dig_t->cur_ig_value_tdma);
2931
2932 odm_set_timer(dm, &dm->tdma_dig_timer, dm->tdma_dig_timer_ms);
2933 }
2934 #endif
2935 /*@============================================================*/
2936 /*@FASLE ALARM CHECK*/
2937 /*@============================================================*/
phydm_tdma_fa_cnt_chk(void * dm_void)2938 void phydm_tdma_fa_cnt_chk(void *dm_void)
2939 {
2940 struct dm_struct *dm = (struct dm_struct *)dm_void;
2941 struct phydm_fa_struct *falm_cnt = &dm->false_alm_cnt;
2942 struct phydm_fa_acc_struct *fa_t_acc = &dm->false_alm_cnt_acc;
2943 struct phydm_fa_acc_struct *fa_t_acc_low = &dm->false_alm_cnt_acc_low;
2944 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
2945 boolean tdma_dig_block_1sec_flag = false;
2946 u32 timestamp = 0;
2947 u8 states_per_block = dm->tdma_dig_state_number;
2948 u8 cur_tdma_dig_state = 0;
2949 u32 start_th = 0;
2950 u8 state_diff = 0;
2951 u32 tdma_dig_block_period_ms = 0;
2952 u32 tdma_dig_block_cnt_thd = 0;
2953 u32 timestamp_diff = 0;
2954
2955 /*@calculate duration of a tdma block*/
2956 tdma_dig_block_period_ms = dm->tdma_dig_timer_ms * states_per_block;
2957
2958 /*@
2959 *caution!ONE_SEC_MS must be divisible by tdma_dig_block_period_ms,
2960 *or FA will be fewer.
2961 */
2962 tdma_dig_block_cnt_thd = ONE_SEC_MS / tdma_dig_block_period_ms;
2963
2964 /*@tdma_dig_state == 0, collect H-state FA, else, collect L-state FA*/
2965 if (dig_t->tdma_dig_state == TDMA_DIG_LOW_STATE)
2966 cur_tdma_dig_state = TDMA_DIG_LOW_STATE;
2967 else if (dig_t->tdma_dig_state >= TDMA_DIG_HIGH_STATE)
2968 cur_tdma_dig_state = TDMA_DIG_HIGH_STATE;
2969 /*@
2970 *PHYDM_DBG(dm, DBG_DIG, "in state %d, dig count %d\n",
2971 * cur_tdma_dig_state, dig_t->tdma_dig_cnt);
2972 */
2973 if (cur_tdma_dig_state == 0) {
2974 /*@L-state indicates next block*/
2975 dig_t->tdma_dig_block_cnt++;
2976
2977 /*@1sec dump check*/
2978 if (dig_t->tdma_dig_block_cnt >= tdma_dig_block_cnt_thd)
2979 tdma_dig_block_1sec_flag = true;
2980
2981 /*@
2982 *PHYDM_DBG(dm, DBG_DIG,"[L-state] tdma_dig_block_cnt=%d\n",
2983 * dig_t->tdma_dig_block_cnt);
2984 */
2985
2986 /*@collect FA till this block end*/
2987 phydm_false_alarm_counter_statistics(dm);
2988 phydm_fa_cnt_acc(dm, tdma_dig_block_1sec_flag,
2989 cur_tdma_dig_state);
2990 /*@1s L-FA collect end*/
2991
2992 /*@1sec dump reached*/
2993 if (tdma_dig_block_1sec_flag) {
2994 /*@L-DIG*/
2995 phydm_noisy_detection(dm);
2996 #ifdef PHYDM_SUPPORT_CCKPD
2997 phydm_cck_pd_th(dm);
2998 #endif
2999 PHYDM_DBG(dm, DBG_DIG, "run tdma L-state dig ====>\n");
3000 phydm_tdma_low_dig(dm);
3001 PHYDM_DBG(dm, DBG_DIG, "\n\n");
3002 }
3003 } else if (cur_tdma_dig_state == 1) {
3004 /*@1sec dump check*/
3005 if (dig_t->tdma_dig_block_cnt >= tdma_dig_block_cnt_thd)
3006 tdma_dig_block_1sec_flag = true;
3007
3008 /*@
3009 *PHYDM_DBG(dm, DBG_DIG,"[H-state] tdma_dig_block_cnt=%d\n",
3010 * dig_t->tdma_dig_block_cnt);
3011 */
3012
3013 /*@collect FA till this block end*/
3014 phydm_false_alarm_counter_statistics(dm);
3015 phydm_fa_cnt_acc(dm, tdma_dig_block_1sec_flag,
3016 cur_tdma_dig_state);
3017 /*@1s H-FA collect end*/
3018
3019 /*@1sec dump reached*/
3020 state_diff = dm->tdma_dig_state_number - dig_t->tdma_dig_state;
3021 if (tdma_dig_block_1sec_flag && state_diff == 1) {
3022 /*@H-DIG*/
3023 phydm_noisy_detection(dm);
3024 #ifdef PHYDM_SUPPORT_CCKPD
3025 phydm_cck_pd_th(dm);
3026 #endif
3027 PHYDM_DBG(dm, DBG_DIG, "run tdma H-state dig ====>\n");
3028 phydm_tdma_high_dig(dm);
3029 PHYDM_DBG(dm, DBG_DIG, "\n\n");
3030 PHYDM_DBG(dm, DBG_DIG, "1 sec reached, is_linked=%d\n",
3031 dm->is_linked);
3032 PHYDM_DBG(dm, DBG_DIG, "1 sec L-CCA=%d, L-FA=%d\n",
3033 fa_t_acc_low->cnt_cca_all_1sec,
3034 fa_t_acc_low->cnt_all_1sec);
3035 PHYDM_DBG(dm, DBG_DIG, "1 sec H-CCA=%d, H-FA=%d\n",
3036 fa_t_acc->cnt_cca_all_1sec,
3037 fa_t_acc->cnt_all_1sec);
3038 PHYDM_DBG(dm, DBG_DIG,
3039 "1 sec TOTAL-CCA=%d, TOTAL-FA=%d\n\n",
3040 fa_t_acc->cnt_cca_all +
3041 fa_t_acc_low->cnt_cca_all,
3042 fa_t_acc->cnt_all + fa_t_acc_low->cnt_all);
3043
3044 /*@Reset AccFalseAlarmCounterStatistics */
3045 phydm_false_alarm_counter_acc_reset(dm);
3046 dig_t->tdma_dig_block_cnt = 0;
3047 }
3048 }
3049 /*@Reset FalseAlarmCounterStatistics */
3050 phydm_false_alarm_counter_reset(dm);
3051 }
3052
phydm_tdma_low_dig(void * dm_void)3053 void phydm_tdma_low_dig(void *dm_void)
3054 {
3055 struct dm_struct *dm = (struct dm_struct *)dm_void;
3056 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
3057 struct phydm_fa_struct *falm_cnt = &dm->false_alm_cnt;
3058 struct phydm_fa_acc_struct *falm_cnt_acc = &dm->false_alm_cnt_acc_low;
3059 #ifdef CFG_DIG_DAMPING_CHK
3060 struct phydm_dig_recorder_strcut *dig_rc = &dig_t->dig_recorder_t;
3061 #endif
3062 u8 igi = dig_t->cur_ig_value;
3063 u8 new_igi = 0x20;
3064 u8 tdma_l_igi = dig_t->low_ig_value;
3065 u8 tdma_l_dym_min = dig_t->tdma_rx_gain_min[TDMA_DIG_LOW_STATE];
3066 u8 tdma_l_dym_max = dig_t->tdma_rx_gain_max[TDMA_DIG_LOW_STATE];
3067 u32 fa_cnt = falm_cnt->cnt_all;
3068 boolean dfs_mode_en = false, is_performance = true;
3069 u8 rssi_min = dm->rssi_min;
3070 u8 igi_upper_rssi_min = 0;
3071 u8 offset = 15;
3072
3073 if (!(dm->original_dig_restore)) {
3074 if (tdma_l_igi == 0)
3075 tdma_l_igi = igi;
3076
3077 fa_cnt = falm_cnt_acc->cnt_all_1sec;
3078 }
3079
3080 if (phydm_dig_abort(dm)) {
3081 dig_t->low_ig_value = phydm_get_igi(dm, BB_PATH_A);
3082 return;
3083 }
3084
3085 /*@Mode Decision*/
3086 dfs_mode_en = false;
3087 is_performance = true;
3088
3089 /* @Abs Boundary Decision*/
3090 dig_t->dm_dig_max = DIG_MAX_COVERAGR; //0x26
3091 dig_t->dm_dig_min = DIG_MIN_PERFORMANCE; //0x20
3092 dig_t->dig_max_of_min = DIG_MAX_OF_MIN_COVERAGE; //0x22
3093
3094 if (dm->is_dfs_band) {
3095 if (*dm->band_width == CHANNEL_WIDTH_20){
3096 if (dm->support_ic_type &
3097 (ODM_RTL8814A | ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8822B)){
3098 if (odm_get_bb_reg(dm, R_0x8d8, BIT(27)) == 1)
3099 dig_t->dm_dig_min = DIG_MIN_DFS + 2;
3100 else
3101 dig_t->dm_dig_min = DIG_MIN_DFS;
3102 }
3103 else
3104 dig_t->dm_dig_min = DIG_MIN_DFS;
3105 }
3106 else
3107 dig_t->dm_dig_min = DIG_MIN_DFS;
3108
3109 } else {
3110 #if 0
3111 if (dm->support_ic_type &
3112 (ODM_RTL8814A | ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8822B))
3113 dig_t->dm_dig_min = 0x1c;
3114 else if (dm->support_ic_type & ODM_RTL8197F)
3115 dig_t->dm_dig_min = 0x1e; /*@For HW setting*/
3116 #endif
3117 }
3118
3119 PHYDM_DBG(dm, DBG_DIG, "Abs{Max, Min}={0x%x, 0x%x}, Max_of_min=0x%x\n",
3120 dig_t->dm_dig_max, dig_t->dm_dig_min, dig_t->dig_max_of_min);
3121
3122 /* @Dyn Boundary by RSSI*/
3123 if (!dm->is_linked) {
3124 /*@if no link, always stay at lower bound*/
3125 tdma_l_dym_max = 0x26;
3126 tdma_l_dym_min = dig_t->dm_dig_min;
3127
3128 PHYDM_DBG(dm, DBG_DIG, "No-Link, Dyn{Max, Min}={0x%x, 0x%x}\n",
3129 tdma_l_dym_max, tdma_l_dym_min);
3130 } else {
3131 PHYDM_DBG(dm, DBG_DIG, "rssi_min=%d, ofst=%d\n",
3132 dm->rssi_min, offset);
3133
3134 /* @DIG lower bound in L-state*/
3135 tdma_l_dym_min = dig_t->dm_dig_min;
3136 if (dm->is_dfs_band)
3137 tdma_l_dym_min = DIG_MIN_DFS;
3138 /*@
3139 *#ifdef CFG_DIG_DAMPING_CHK
3140 *@Limit Dyn min by damping
3141 *if (dig_t->dig_dl_en &&
3142 * dig_rc->damping_limit_en &&
3143 * tdma_l_dym_min < dig_rc->damping_limit_val) {
3144 * PHYDM_DBG(dm, DBG_DIG,
3145 * "[Limit by Damping] dyn_min=0x%x -> 0x%x\n",
3146 * tdma_l_dym_min, dig_rc->damping_limit_val);
3147 *
3148 * tdma_l_dym_min = dig_rc->damping_limit_val;
3149 *}
3150 *#endif
3151 */
3152
3153 /*@DIG upper bound in L-state*/
3154 igi_upper_rssi_min = rssi_min + offset;
3155 if (igi_upper_rssi_min > dig_t->dm_dig_max)
3156 tdma_l_dym_max = dig_t->dm_dig_max;
3157 else if (igi_upper_rssi_min < dig_t->dm_dig_min)
3158 tdma_l_dym_max = dig_t->dm_dig_min;
3159 else
3160 tdma_l_dym_max = igi_upper_rssi_min;
3161
3162 /* @1 Force Lower Bound for AntDiv */
3163 /*@
3164 *if (!dm->is_one_entry_only &&
3165 *(dm->support_ability & ODM_BB_ANT_DIV) &&
3166 *(dm->ant_div_type == CG_TRX_HW_ANTDIV ||
3167 *dm->ant_div_type == CG_TRX_SMART_ANTDIV)) {
3168 *if (dig_t->ant_div_rssi_max > dig_t->dig_max_of_min)
3169 * dig_t->rx_gain_range_min = dig_t->dig_max_of_min;
3170 *else
3171 * dig_t->rx_gain_range_min = (u8)dig_t->ant_div_rssi_max;
3172 *
3173 *PHYDM_DBG(dm, DBG_DIG, "Force Dyn-Min=0x%x, RSSI_max=0x%x\n",
3174 * dig_t->rx_gain_range_min, dig_t->ant_div_rssi_max);
3175 *}
3176 */
3177
3178 PHYDM_DBG(dm, DBG_DIG, "Dyn{Max, Min}={0x%x, 0x%x}\n",
3179 tdma_l_dym_max, tdma_l_dym_min);
3180 }
3181
3182 /*@Abnormal Case Check*/
3183 /*@Abnormal lower bound case*/
3184 if (tdma_l_dym_min > tdma_l_dym_max)
3185 tdma_l_dym_min = tdma_l_dym_max;
3186
3187 PHYDM_DBG(dm, DBG_DIG,
3188 "Abnoraml chk, force {Max, Min}={0x%x, 0x%x}\n",
3189 tdma_l_dym_max, tdma_l_dym_min);
3190
3191 /*@False Alarm Threshold Decision*/
3192 phydm_fa_threshold_check(dm, dfs_mode_en);
3193
3194 /*@Adjust Initial Gain by False Alarm*/
3195 /*Select new IGI by FA */
3196 if (!(dm->original_dig_restore)) {
3197 tdma_l_igi = get_new_igi_bound(dm, tdma_l_igi, fa_cnt,
3198 &tdma_l_dym_max,
3199 &tdma_l_dym_min,
3200 dfs_mode_en);
3201 } else {
3202 new_igi = phydm_get_new_igi(dm, igi, fa_cnt, dfs_mode_en);
3203 }
3204
3205 /*Update status*/
3206 if (!(dm->original_dig_restore)) {
3207 if (dig_t->tdma_force_l_igi == 0xff)
3208 dig_t->low_ig_value = tdma_l_igi;
3209 else
3210 dig_t->low_ig_value = dig_t->tdma_force_l_igi;
3211 dig_t->tdma_rx_gain_min[TDMA_DIG_LOW_STATE] = tdma_l_dym_min;
3212 dig_t->tdma_rx_gain_max[TDMA_DIG_LOW_STATE] = tdma_l_dym_max;
3213 #if 0
3214 /*odm_write_dig(dm, tdma_l_igi);*/
3215 #endif
3216 } else {
3217 odm_write_dig(dm, new_igi);
3218 }
3219 }
3220
phydm_tdma_high_dig(void * dm_void)3221 void phydm_tdma_high_dig(void *dm_void)
3222 {
3223 struct dm_struct *dm = (struct dm_struct *)dm_void;
3224 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
3225 struct phydm_fa_struct *falm_cnt = &dm->false_alm_cnt;
3226 struct phydm_fa_acc_struct *falm_cnt_acc = &dm->false_alm_cnt_acc;
3227 struct phydm_adaptivity_struct *adapt = &dm->adaptivity;
3228 #ifdef CFG_DIG_DAMPING_CHK
3229 struct phydm_dig_recorder_strcut *dig_rc = &dig_t->dig_recorder_t;
3230 #endif
3231 u8 igi = dig_t->cur_ig_value;
3232 u8 new_igi = 0x20;
3233 u8 tdma_h_igi = dig_t->cur_ig_value_tdma;
3234 u8 tdma_h_dym_min = dig_t->tdma_rx_gain_min[TDMA_DIG_HIGH_STATE];
3235 u8 tdma_h_dym_max = dig_t->tdma_rx_gain_max[TDMA_DIG_HIGH_STATE];
3236 u32 fa_cnt = falm_cnt->cnt_all;
3237 boolean dfs_mode_en = false, is_performance = true;
3238 u8 rssi_min = dm->rssi_min;
3239 u8 igi_upper_rssi_min = 0;
3240 u8 offset = 15;
3241
3242 if (!(dm->original_dig_restore)) {
3243 if (tdma_h_igi == 0)
3244 tdma_h_igi = igi;
3245
3246 fa_cnt = falm_cnt_acc->cnt_all_1sec;
3247 }
3248
3249 if (phydm_dig_abort(dm)) {
3250 dig_t->cur_ig_value_tdma = phydm_get_igi(dm, BB_PATH_A);
3251 return;
3252 }
3253
3254 /*@Mode Decision*/
3255 dfs_mode_en = false;
3256 is_performance = true;
3257
3258 /*@Abs Boundary Decision*/
3259 dig_t->dig_max_of_min = DIG_MAX_OF_MIN_BALANCE_MODE; // 0x2a
3260
3261 if (!dm->is_linked) {
3262 dig_t->dm_dig_max = DIG_MAX_COVERAGR;
3263 dig_t->dm_dig_min = DIG_MIN_PERFORMANCE; // 0x20
3264 } else if (dm->is_dfs_band) {
3265 if (*dm->band_width == CHANNEL_WIDTH_20){
3266 if (dm->support_ic_type &
3267 (ODM_RTL8814A | ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8822B)){
3268 if (odm_get_bb_reg(dm, R_0x8d8, BIT(27)) == 1)
3269 dig_t->dm_dig_min = DIG_MIN_DFS + 2;
3270 else
3271 dig_t->dm_dig_min = DIG_MIN_DFS;
3272 }
3273 else
3274 dig_t->dm_dig_min = DIG_MIN_DFS;
3275 }
3276 else
3277 dig_t->dm_dig_min = DIG_MIN_DFS;
3278
3279 dig_t->dig_max_of_min = DIG_MAX_OF_MIN_BALANCE_MODE;
3280 dig_t->dm_dig_max = DIG_MAX_BALANCE_MODE;
3281 } else {
3282 if (*dm->bb_op_mode == PHYDM_BALANCE_MODE) {
3283 /*service > 2 devices*/
3284 dig_t->dm_dig_max = DIG_MAX_BALANCE_MODE;
3285 #if (DIG_HW == 1)
3286 dig_t->dig_max_of_min = DIG_MIN_COVERAGE;
3287 #else
3288 dig_t->dig_max_of_min = DIG_MAX_OF_MIN_BALANCE_MODE;
3289 #endif
3290 } else if (*dm->bb_op_mode == PHYDM_PERFORMANCE_MODE) {
3291 /*service 1 devices*/
3292 if (*dm->edcca_mode == PHYDM_EDCCA_ADAPT_MODE &&
3293 (dm->support_ic_type & ODM_RTL8192F)) {
3294 /*dig_max shouldn't be too high becaus of adaptivity*/
3295 dig_t->dm_dig_max = MIN_2((adapt->th_l2h + 30),
3296 DIG_MAX_PERFORMANCE_MODE);
3297 } else {
3298 dig_t->dm_dig_max = DIG_MAX_PERFORMANCE_MODE;
3299 #if (RTL8822B_SUPPORT == 1)
3300 if (dm->is_dig_low_bond)
3301 dig_t->dig_max_of_min = DIG_MAX_OF_MIN_PERFORMANCE_MODE_22B;
3302 else
3303 dig_t->dig_max_of_min = DIG_MAX_OF_MIN_PERFORMANCE_MODE;
3304 #else
3305 dig_t->dig_max_of_min = DIG_MAX_OF_MIN_PERFORMANCE_MODE;
3306 #endif
3307 }
3308 dig_t->dig_max_of_min = DIG_MAX_OF_MIN_PERFORMANCE_MODE;
3309 }
3310
3311 #if 0
3312 if (dm->support_ic_type &
3313 (ODM_RTL8814A | ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8822B))
3314 dig_t->dm_dig_min = 0x1c;
3315 else if (dm->support_ic_type & ODM_RTL8197F)
3316 dig_t->dm_dig_min = 0x1e; /*@For HW setting*/
3317 else
3318 #endif
3319 dig_t->dm_dig_min = DIG_MIN_PERFORMANCE;
3320 }
3321 PHYDM_DBG(dm, DBG_DIG, "Abs{Max, Min}={0x%x, 0x%x}, Max_of_min=0x%x\n",
3322 dig_t->dm_dig_max, dig_t->dm_dig_min, dig_t->dig_max_of_min);
3323
3324 /*@Dyn Boundary by RSSI*/
3325 if (!dm->is_linked) {
3326 /*@if no link, always stay at lower bound*/
3327 tdma_h_dym_max = dig_t->dig_max_of_min;
3328 tdma_h_dym_min = dig_t->dm_dig_min;
3329
3330 PHYDM_DBG(dm, DBG_DIG, "No-Link, Dyn{Max, Min}={0x%x, 0x%x}\n",
3331 tdma_h_dym_max, tdma_h_dym_min);
3332 } else {
3333 PHYDM_DBG(dm, DBG_DIG, "rssi_min=%d, ofst=%d\n",
3334 dm->rssi_min, offset);
3335
3336 /* @DIG lower bound in H-state*/
3337 if (dm->is_dfs_band)
3338 tdma_h_dym_min = DIG_MIN_DFS;
3339 else if (rssi_min < dig_t->dm_dig_min)
3340 tdma_h_dym_min = dig_t->dm_dig_min;
3341 else
3342 tdma_h_dym_min = rssi_min; // turbo not considered yet
3343
3344 #ifdef CFG_DIG_DAMPING_CHK
3345 /*@Limit Dyn min by damping*/
3346 if (dig_t->dig_dl_en &&
3347 dig_rc->damping_limit_en &&
3348 tdma_h_dym_min < dig_rc->damping_limit_val) {
3349 PHYDM_DBG(dm, DBG_DIG,
3350 "[Limit by Damping] dyn_min=0x%x -> 0x%x\n",
3351 tdma_h_dym_min, dig_rc->damping_limit_val);
3352
3353 tdma_h_dym_min = dig_rc->damping_limit_val;
3354 }
3355 #endif
3356
3357 /*@DIG upper bound in H-state*/
3358 igi_upper_rssi_min = rssi_min + offset;
3359 if (igi_upper_rssi_min > dig_t->dm_dig_max)
3360 tdma_h_dym_max = dig_t->dm_dig_max;
3361 else
3362 tdma_h_dym_max = igi_upper_rssi_min;
3363
3364 /* @1 Force Lower Bound for AntDiv */
3365 /*@
3366 *if (!dm->is_one_entry_only &&
3367 *(dm->support_ability & ODM_BB_ANT_DIV) &&
3368 *(dm->ant_div_type == CG_TRX_HW_ANTDIV ||
3369 *dm->ant_div_type == CG_TRX_SMART_ANTDIV)) {
3370 * if (dig_t->ant_div_rssi_max > dig_t->dig_max_of_min)
3371 * dig_t->rx_gain_range_min = dig_t->dig_max_of_min;
3372 * else
3373 * dig_t->rx_gain_range_min = (u8)dig_t->ant_div_rssi_max;
3374 */
3375 /*@
3376 *PHYDM_DBG(dm, DBG_DIG, "Force Dyn-Min=0x%x, RSSI_max=0x%x\n",
3377 * dig_t->rx_gain_range_min, dig_t->ant_div_rssi_max);
3378 *}
3379 */
3380 PHYDM_DBG(dm, DBG_DIG, "Dyn{Max, Min}={0x%x, 0x%x}\n",
3381 tdma_h_dym_max, tdma_h_dym_min);
3382 }
3383
3384 /*@Abnormal Case Check*/
3385 /*@Abnormal low higher bound case*/
3386 if (tdma_h_dym_max < dig_t->dm_dig_min)
3387 tdma_h_dym_max = dig_t->dm_dig_min;
3388 /*@Abnormal lower bound case*/
3389 if (tdma_h_dym_min > tdma_h_dym_max)
3390 tdma_h_dym_min = tdma_h_dym_max;
3391
3392 PHYDM_DBG(dm, DBG_DIG, "Abnoraml chk, force {Max, Min}={0x%x, 0x%x}\n",
3393 tdma_h_dym_max, tdma_h_dym_min);
3394
3395 /*@False Alarm Threshold Decision*/
3396 phydm_fa_threshold_check(dm, dfs_mode_en);
3397
3398 /*@Adjust Initial Gain by False Alarm*/
3399 /*Select new IGI by FA */
3400 if (!(dm->original_dig_restore)) {
3401 tdma_h_igi = get_new_igi_bound(dm, tdma_h_igi, fa_cnt,
3402 &tdma_h_dym_max,
3403 &tdma_h_dym_min,
3404 dfs_mode_en);
3405 } else {
3406 new_igi = phydm_get_new_igi(dm, igi, fa_cnt, dfs_mode_en);
3407 }
3408
3409 /*Update status*/
3410 if (!(dm->original_dig_restore)) {
3411 if (dig_t->tdma_force_h_igi == 0xff)
3412 dig_t->cur_ig_value_tdma = tdma_h_igi;
3413 else
3414 dig_t->cur_ig_value_tdma = dig_t->tdma_force_h_igi;
3415 dig_t->tdma_rx_gain_min[TDMA_DIG_HIGH_STATE] = tdma_h_dym_min;
3416 dig_t->tdma_rx_gain_max[TDMA_DIG_HIGH_STATE] = tdma_h_dym_max;
3417 #if 0
3418 /*odm_write_dig(dm, tdma_h_igi);*/
3419 #endif
3420 } else {
3421 odm_write_dig(dm, new_igi);
3422 }
3423 }
3424
phydm_fa_cnt_acc(void * dm_void,boolean tdma_dig_block_1sec_flag,u8 cur_tdma_dig_state)3425 void phydm_fa_cnt_acc(void *dm_void, boolean tdma_dig_block_1sec_flag,
3426 u8 cur_tdma_dig_state)
3427 {
3428 struct dm_struct *dm = (struct dm_struct *)dm_void;
3429 struct phydm_fa_struct *falm_cnt = &dm->false_alm_cnt;
3430 struct phydm_fa_acc_struct *falm_cnt_acc = NULL;
3431 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
3432 u8 factor_num = 0;
3433 u8 factor_denum = 1;
3434 u8 total_state_number = 0;
3435
3436 if (cur_tdma_dig_state == TDMA_DIG_LOW_STATE)
3437 falm_cnt_acc = &dm->false_alm_cnt_acc_low;
3438 else if (cur_tdma_dig_state == TDMA_DIG_HIGH_STATE)
3439
3440 falm_cnt_acc = &dm->false_alm_cnt_acc;
3441 /*@
3442 *PHYDM_DBG(dm, DBG_DIG,
3443 * "[%s] ==> dig_state=%d, one_sec=%d\n", __func__,
3444 * cur_tdma_dig_state, tdma_dig_block_1sec_flag);
3445 */
3446 falm_cnt_acc->cnt_parity_fail += falm_cnt->cnt_parity_fail;
3447 falm_cnt_acc->cnt_rate_illegal += falm_cnt->cnt_rate_illegal;
3448 falm_cnt_acc->cnt_crc8_fail += falm_cnt->cnt_crc8_fail;
3449 falm_cnt_acc->cnt_mcs_fail += falm_cnt->cnt_mcs_fail;
3450 falm_cnt_acc->cnt_ofdm_fail += falm_cnt->cnt_ofdm_fail;
3451 falm_cnt_acc->cnt_cck_fail += falm_cnt->cnt_cck_fail;
3452 falm_cnt_acc->cnt_all += falm_cnt->cnt_all;
3453 falm_cnt_acc->cnt_fast_fsync += falm_cnt->cnt_fast_fsync;
3454 falm_cnt_acc->cnt_sb_search_fail += falm_cnt->cnt_sb_search_fail;
3455 falm_cnt_acc->cnt_ofdm_cca += falm_cnt->cnt_ofdm_cca;
3456 falm_cnt_acc->cnt_cck_cca += falm_cnt->cnt_cck_cca;
3457 falm_cnt_acc->cnt_cca_all += falm_cnt->cnt_cca_all;
3458 falm_cnt_acc->cnt_cck_crc32_error += falm_cnt->cnt_cck_crc32_error;
3459 falm_cnt_acc->cnt_cck_crc32_ok += falm_cnt->cnt_cck_crc32_ok;
3460 falm_cnt_acc->cnt_ofdm_crc32_error += falm_cnt->cnt_ofdm_crc32_error;
3461 falm_cnt_acc->cnt_ofdm_crc32_ok += falm_cnt->cnt_ofdm_crc32_ok;
3462 falm_cnt_acc->cnt_ht_crc32_error += falm_cnt->cnt_ht_crc32_error;
3463 falm_cnt_acc->cnt_ht_crc32_ok += falm_cnt->cnt_ht_crc32_ok;
3464 falm_cnt_acc->cnt_vht_crc32_error += falm_cnt->cnt_vht_crc32_error;
3465 falm_cnt_acc->cnt_vht_crc32_ok += falm_cnt->cnt_vht_crc32_ok;
3466 falm_cnt_acc->cnt_crc32_error_all += falm_cnt->cnt_crc32_error_all;
3467 falm_cnt_acc->cnt_crc32_ok_all += falm_cnt->cnt_crc32_ok_all;
3468
3469 /*@
3470 *PHYDM_DBG(dm, DBG_DIG,
3471 * "[CCA Cnt] {CCK, OFDM, Total} = {%d, %d, %d}\n",
3472 * falm_cnt->cnt_cck_cca,
3473 * falm_cnt->cnt_ofdm_cca,
3474 * falm_cnt->cnt_cca_all);
3475 *PHYDM_DBG(dm, DBG_DIG,
3476 * "[FA Cnt] {CCK, OFDM, Total} = {%d, %d, %d}\n",
3477 * falm_cnt->cnt_cck_fail,
3478 * falm_cnt->cnt_ofdm_fail,
3479 * falm_cnt->cnt_all);
3480 */
3481 if (tdma_dig_block_1sec_flag) {
3482 total_state_number = dm->tdma_dig_state_number;
3483
3484 if (cur_tdma_dig_state == TDMA_DIG_HIGH_STATE) {
3485 factor_num = total_state_number;
3486 factor_denum = total_state_number - 1;
3487 } else if (cur_tdma_dig_state == TDMA_DIG_LOW_STATE) {
3488 factor_num = total_state_number;
3489 factor_denum = 1;
3490 }
3491
3492 falm_cnt_acc->cnt_all_1sec =
3493 falm_cnt_acc->cnt_all * factor_num / factor_denum;
3494 falm_cnt_acc->cnt_cca_all_1sec =
3495 falm_cnt_acc->cnt_cca_all * factor_num / factor_denum;
3496 falm_cnt_acc->cnt_cck_fail_1sec =
3497 falm_cnt_acc->cnt_cck_fail * factor_num / factor_denum;
3498
3499 PHYDM_DBG(dm, DBG_DIG,
3500 "[ACC CCA Cnt] {CCK, OFDM, Total} = {%d, %d, %d}\n",
3501 falm_cnt_acc->cnt_cck_cca,
3502 falm_cnt_acc->cnt_ofdm_cca,
3503 falm_cnt_acc->cnt_cca_all);
3504 PHYDM_DBG(dm, DBG_DIG,
3505 "[ACC FA Cnt] {CCK, OFDM, Total} = {%d, %d, %d}\n\n",
3506 falm_cnt_acc->cnt_cck_fail,
3507 falm_cnt_acc->cnt_ofdm_fail,
3508 falm_cnt_acc->cnt_all);
3509
3510 }
3511 }
3512 #endif /*@#ifdef IS_USE_NEW_TDMA*/
3513 #endif /*@#ifdef PHYDM_TDMA_DIG_SUPPORT*/
3514
phydm_dig_debug(void * dm_void,char input[][16],u32 * _used,char * output,u32 * _out_len)3515 void phydm_dig_debug(void *dm_void, char input[][16], u32 *_used, char *output,
3516 u32 *_out_len)
3517 {
3518 struct dm_struct *dm = (struct dm_struct *)dm_void;
3519 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
3520 char help[] = "-h";
3521 u32 var1[10] = {0};
3522 u32 used = *_used;
3523 u32 out_len = *_out_len;
3524 u8 i = 0;
3525
3526 if ((strcmp(input[1], help) == 0)) {
3527 PDM_SNPF(out_len, used, output + used, out_len - used,
3528 "{0} {en} fa_th[0] fa_th[1] fa_th[2]\n");
3529 PDM_SNPF(out_len, used, output + used, out_len - used,
3530 "{1} {Damping Limit en}\n");
3531 #ifdef PHYDM_TDMA_DIG_SUPPORT
3532 PDM_SNPF(out_len, used, output + used, out_len - used,
3533 "{2} {original_dig_restore = %d}\n",
3534 dm->original_dig_restore);
3535 PDM_SNPF(out_len, used, output + used, out_len - used,
3536 "{3} {tdma_dig_timer_ms = %d}\n",
3537 dm->tdma_dig_timer_ms);
3538 PDM_SNPF(out_len, used, output + used, out_len - used,
3539 "{4} {tdma_dig_state_number = %d}\n",
3540 dm->tdma_dig_state_number);
3541 PDM_SNPF(out_len, used, output + used, out_len - used,
3542 "{5} {0:L-state,1:H-state} {force IGI} (L,H)=(%2x,%2x)\n",
3543 dig_t->tdma_force_l_igi, dig_t->tdma_force_h_igi);
3544 #endif
3545 PDM_SNPF(out_len, used, output + used, out_len - used,
3546 "{6} {fw_dig_en}\n");
3547 PDM_SNPF(out_len, used, output + used, out_len - used,
3548 "{7} FA source:{0:original/1:Experimental duration/2:IFS_CLM/3:FAHM}\n");
3549 } else {
3550 PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]);
3551
3552 for (i = 1; i < 10; i++)
3553 PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var1[i]);
3554
3555 if (var1[0] == 0) {
3556 if (var1[1] == 1) {
3557 dig_t->is_dbg_fa_th = true;
3558 dig_t->fa_th[0] = (u32)var1[2];
3559 dig_t->fa_th[1] = (u32)var1[3];
3560 dig_t->fa_th[2] = (u32)var1[4];
3561
3562 PDM_SNPF(out_len, used, output + used,
3563 out_len - used,
3564 "Set DIG fa_th[0:2]= {%d, %d, %d}\n",
3565 dig_t->fa_th[0], dig_t->fa_th[1],
3566 dig_t->fa_th[2]);
3567 } else {
3568 dig_t->is_dbg_fa_th = false;
3569 }
3570 #ifdef PHYDM_TDMA_DIG_SUPPORT
3571 } else if (var1[0] == 2) {
3572 dm->original_dig_restore = (u8)var1[1];
3573 if (dm->original_dig_restore == 1) {
3574 PDM_SNPF(out_len, used, output + used,
3575 out_len - used, "Disable TDMA-DIG\n");
3576 } else {
3577 PDM_SNPF(out_len, used, output + used,
3578 out_len - used, "Enable TDMA-DIG\n");
3579 }
3580 } else if (var1[0] == 3) {
3581 dm->tdma_dig_timer_ms = (u8)var1[1];
3582 PDM_SNPF(out_len, used, output + used,
3583 out_len - used, "tdma_dig_timer_ms = %d\n",
3584 dm->tdma_dig_timer_ms);
3585 } else if (var1[0] == 4) {
3586 dm->tdma_dig_state_number = (u8)var1[1];
3587 PDM_SNPF(out_len, used, output + used,
3588 out_len - used, "tdma_dig_state_number = %d\n",
3589 dm->tdma_dig_state_number);
3590 } else if (var1[0] == 5) {
3591 PHYDM_SSCANF(input[3], DCMD_HEX, &var1[2]);
3592 if (var1[1] == 0) {
3593 dig_t->tdma_force_l_igi = (u8)var1[2];
3594 PDM_SNPF(out_len, used, output + used,
3595 out_len - used,
3596 "force L-state IGI = %2x\n",
3597 dig_t->tdma_force_l_igi);
3598 } else if (var1[1] == 1) {
3599 dig_t->tdma_force_h_igi = (u8)var1[2];
3600 PDM_SNPF(out_len, used, output + used,
3601 out_len - used,
3602 "force H-state IGI = %2x\n",
3603 dig_t->tdma_force_h_igi);
3604 }
3605 #endif
3606 }
3607
3608 #ifdef CFG_DIG_DAMPING_CHK
3609 else if (var1[0] == 1) {
3610 dig_t->dig_dl_en = (u8)var1[1];
3611 /*@*/
3612 }
3613 #endif
3614 else if (var1[0] == 6) {
3615 phydm_fw_dm_ctrl_en(dm, F00_DIG, (boolean)var1[1]);
3616 PDM_SNPF(out_len, used, output + used, out_len - used,
3617 "fw_dig_enable = %2x\n", dig_t->fw_dig_enable);
3618 } else if (var1[0] == 7) {
3619 dig_t->fa_source = (u8)var1[1];
3620 PDM_SNPF(out_len, used, output + used, out_len - used,
3621 "FA source = %d\n", dig_t->fa_source);
3622 }
3623 }
3624 *_used = used;
3625 *_out_len = out_len;
3626 }
3627
3628 #ifdef CONFIG_MCC_DM
3629 #if (RTL8822B_SUPPORT || RTL8822C_SUPPORT|| RTL8723F_SUPPORT)
phydm_mcc_igi_clr(void * dm_void,u8 clr_port)3630 void phydm_mcc_igi_clr(void *dm_void, u8 clr_port)
3631 {
3632 struct dm_struct *dm = (struct dm_struct *)dm_void;
3633 struct _phydm_mcc_dm_ *mcc_dm = &dm->mcc_dm;
3634
3635 mcc_dm->mcc_rssi[clr_port] = 0xff;
3636 mcc_dm->mcc_dm_val[0][clr_port] = 0xff; /* 0xc50 clr */
3637 mcc_dm->mcc_dm_val[1][clr_port] = 0xff; /* 0xe50 clr */
3638 }
3639
phydm_mcc_igi_chk(void * dm_void)3640 void phydm_mcc_igi_chk(void *dm_void)
3641 {
3642 struct dm_struct *dm = (struct dm_struct *)dm_void;
3643 struct _phydm_mcc_dm_ *mcc_dm = &dm->mcc_dm;
3644
3645 if (mcc_dm->mcc_dm_val[0][0] == 0xff &&
3646 mcc_dm->mcc_dm_val[0][1] == 0xff) {
3647 mcc_dm->mcc_dm_reg[0] = 0xffff;
3648 mcc_dm->mcc_reg_id[0] = 0xff;
3649 }
3650 if (mcc_dm->mcc_dm_val[1][0] == 0xff &&
3651 mcc_dm->mcc_dm_val[1][1] == 0xff) {
3652 mcc_dm->mcc_dm_reg[1] = 0xffff;
3653 mcc_dm->mcc_reg_id[1] = 0xff;
3654 }
3655 }
3656
phydm_mcc_igi_cal(void * dm_void)3657 void phydm_mcc_igi_cal(void *dm_void)
3658 {
3659 struct dm_struct *dm = (struct dm_struct *)dm_void;
3660 struct _phydm_mcc_dm_ *mcc_dm = &dm->mcc_dm;
3661 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
3662 u8 shift = 0;
3663 u8 igi_val0, igi_val1;
3664
3665 if (mcc_dm->mcc_rssi[0] == 0xff)
3666 phydm_mcc_igi_clr(dm, 0);
3667 if (mcc_dm->mcc_rssi[1] == 0xff)
3668 phydm_mcc_igi_clr(dm, 1);
3669 phydm_mcc_igi_chk(dm);
3670 igi_val0 = mcc_dm->mcc_rssi[0] - shift;
3671 igi_val1 = mcc_dm->mcc_rssi[1] - shift;
3672
3673 if (igi_val0 < DIG_MIN_PERFORMANCE)
3674 igi_val0 = DIG_MIN_PERFORMANCE;
3675
3676 if (igi_val1 < DIG_MIN_PERFORMANCE)
3677 igi_val1 = DIG_MIN_PERFORMANCE;
3678
3679 switch (dm->ic_ip_series) {
3680 #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
3681 case PHYDM_IC_JGR3:
3682 phydm_fill_mcccmd(dm, 0, R_0x1d70, igi_val0, igi_val1);
3683 phydm_fill_mcccmd(dm, 1, R_0x1d70 + 1, igi_val0, igi_val1);
3684 break;
3685 #endif
3686 default:
3687 phydm_fill_mcccmd(dm, 0, R_0xc50, igi_val0, igi_val1);
3688 phydm_fill_mcccmd(dm, 1, R_0xe50, igi_val0, igi_val1);
3689 break;
3690 }
3691
3692 PHYDM_DBG(dm, DBG_COMP_MCC, "RSSI_min: %d %d, MCC_igi: %d %d\n",
3693 mcc_dm->mcc_rssi[0], mcc_dm->mcc_rssi[1],
3694 mcc_dm->mcc_dm_val[0][0], mcc_dm->mcc_dm_val[0][1]);
3695 }
3696 #endif /*#if (RTL8822B_SUPPORT)*/
3697 #endif /*#ifdef CONFIG_MCC_DM*/
3698