1 /****************************************************************************** 2 * 3 * Copyright(c) 2007 - 2017 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * The full GNU General Public License is included in this distribution in the 15 * file called LICENSE. 16 * 17 * Contact Information: 18 * wlanfae <wlanfae@realtek.com> 19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 20 * Hsinchu 300, Taiwan. 21 * 22 * Larry Finger <Larry.Finger@lwfinger.net> 23 * 24 *****************************************************************************/ 25 26 #ifndef __PHYDMDIG_H__ 27 #define __PHYDMDIG_H__ 28 29 /* 2020.08.13 Add IFS-CLM/FAHM in dig fa source for more accurate fa info*/ 30 #define DIG_VERSION "3.9" 31 32 #define DIG_HW 0 33 #define DIG_LIMIT_PERIOD 60 /*60 sec*/ 34 35 /*@--------------------Define ---------------------------------------*/ 36 37 /*@=== [DIG Boundary] ========================================*/ 38 /*@DIG coverage mode*/ 39 #define DIG_MAX_COVERAGR 0x26 40 #define DIG_MIN_COVERAGE 0x1c 41 #define DIG_MAX_OF_MIN_COVERAGE 0x22 42 43 /*@[DIG Balance mode]*/ 44 #if (DIG_HW == 1) 45 #define DIG_MAX_BALANCE_MODE 0x32 46 #else 47 #define DIG_MAX_BALANCE_MODE 0x3e 48 #endif 49 #define DIG_MAX_OF_MIN_BALANCE_MODE 0x2a 50 51 /*@[DIG Performance mode]*/ 52 #define DIG_MAX_PERFORMANCE_MODE 0x5a 53 #define DIG_MAX_OF_MIN_PERFORMANCE_MODE 0x40 /*@[WLANBB-871]*/ 54 #define DIG_MIN_PERFORMANCE 0x20 55 #if (RTL8822B_SUPPORT == 1) 56 #define DIG_MAX_OF_MIN_PERFORMANCE_MODE_22B 0x38 57 #endif 58 59 /*@DIG DFS function*/ 60 #define DIG_MAX_DFS 0x28 61 #define DIG_MIN_DFS 0x20 62 63 /*@DIG LPS function*/ 64 #define DIG_MAX_LPS 0x3e 65 #define DIG_MIN_LPS 0x20 66 67 #ifdef PHYDM_TDMA_DIG_SUPPORT 68 #define DIG_NUM_OF_TDMA_STATES 2 /*@L, H state*/ 69 #define DIG_TIMER_MS 250 70 #define ONE_SEC_MS 1000 71 #endif 72 73 /*@=== [DIG FA Threshold] ======================================*/ 74 75 /*Normal*/ 76 #define DM_DIG_FA_TH0 500 77 #define DM_DIG_FA_TH1 750 78 79 /*@LPS*/ 80 #define DM_DIG_FA_TH0_LPS 4 /* @-> 4 lps */ 81 #define DM_DIG_FA_TH1_LPS 15 /* @-> 15 lps */ 82 #define DM_DIG_FA_TH2_LPS 30 /* @-> 30 lps */ 83 84 #define RSSI_OFFSET_DIG_LPS 5 85 #define DIG_RECORD_NUM 4 86 87 /*==== [FA duration] =======================================*/ 88 /*[PHYDM-406]*/ 89 #define OFDM_FA_EXP_DURATION 12 /*us*/ 90 #define CCK_FA_EXP_DURATION 175 /*us*/ 91 92 /*@--------------------Enum-----------------------------------*/ 93 enum phydm_dig_mode { 94 PHYDM_DIG_PERFORAMNCE_MODE = 0, 95 PHYDM_DIG_COVERAGE_MODE = 1, 96 }; 97 98 enum phydm_dig_trend { 99 DIG_STABLE = 0, 100 DIG_INCREASING = 1, 101 DIG_DECREASING = 2 102 }; 103 104 enum phydm_fw_dig_mode_e { 105 DIG_PERFORMANCE_MODE = 0, 106 DIG_COVERAGE_MODE = 1, 107 DIG_LPS_MODE = 2 108 }; 109 110 #ifdef PHYDM_TDMA_DIG_SUPPORT 111 enum upd_type { 112 ENABLE_TDMA, 113 MODE_DECISION 114 }; 115 116 enum tdma_opmode { 117 MODE_PERFORMANCE = 1, 118 MODE_COVERAGE = 2 119 }; 120 121 #ifdef IS_USE_NEW_TDMA 122 enum tdma_dig_timer { 123 INIT_TDMA_DIG_TIMMER, 124 CANCEL_TDMA_DIG_TIMMER, 125 RELEASE_TDMA_DIG_TIMMER 126 }; 127 128 enum tdma_dig_state { 129 TDMA_DIG_LOW_STATE = 0, 130 TDMA_DIG_HIGH_STATE = 1, 131 NORMAL_DIG = 2 132 }; 133 #endif 134 #endif 135 136 /*@--------------------Define Struct-----------------------------------*/ 137 #ifdef CFG_DIG_DAMPING_CHK 138 struct phydm_dig_recorder_strcut { 139 u8 igi_bitmap; /*@Don't add any new parameter before this*/ 140 u8 igi_history[DIG_RECORD_NUM]; 141 u32 fa_history[DIG_RECORD_NUM]; 142 u8 damping_limit_en; 143 u8 damping_limit_val; /*@Limit IGI_dyn_min*/ 144 u32 limit_time; 145 u8 limit_rssi; 146 }; 147 #endif 148 149 struct phydm_mcc_dig { 150 u8 mcc_rssi_A; 151 u8 mcc_rssi_B; 152 }; 153 154 struct phydm_dig_struct { 155 #ifdef CFG_DIG_DAMPING_CHK 156 struct phydm_dig_recorder_strcut dig_recorder_t; 157 u8 dig_dl_en; /*@damping limit function enable*/ 158 #endif 159 boolean fw_dig_enable; 160 boolean is_dbg_fa_th; 161 u8 cur_ig_value; 162 boolean igi_dyn_up_hit; 163 u8 igi_trend; 164 u32 rvrt_val; /*all rvrt_val for pause API must set to u32*/ 165 u8 igi_backup; 166 u8 rx_gain_range_max; /*@dig_dynamic_max*/ 167 u8 rx_gain_range_min; /*@dig_dynamic_min*/ 168 u8 dm_dig_max; /*@Absolutly upper bound*/ 169 u8 dm_dig_min; /*@Absolutly lower bound*/ 170 u8 dig_max_of_min; /*@Absolutly max of min*/ 171 u32 ant_div_rssi_max; 172 u8 *is_p2p_in_process; 173 u32 fa_th[3]; 174 u32 dm_dig_fa_th1; 175 u8 fa_source; 176 #if (RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8821C_SUPPORT ||\ 177 RTL8198F_SUPPORT || RTL8192F_SUPPORT || RTL8195B_SUPPORT ||\ 178 RTL8822C_SUPPORT || RTL8814B_SUPPORT || RTL8721D_SUPPORT ||\ 179 RTL8710C_SUPPORT || RTL8812F_SUPPORT || RTL8197G_SUPPORT ||\ 180 RTL8723F_SUPPORT) 181 u8 rf_gain_idx; 182 u8 agc_table_idx; 183 u8 big_jump_lmt[16]; 184 u8 enable_adjust_big_jump:1; 185 u8 big_jump_step1:3; 186 u8 big_jump_step2:2; 187 u8 big_jump_step3:2; 188 #endif 189 u8 upcheck_init_val; 190 u8 lv0_ratio_reciprocal; 191 u8 lv1_ratio_reciprocal; 192 #ifdef PHYDM_TDMA_DIG_SUPPORT 193 u8 cur_ig_value_tdma; 194 u8 low_ig_value; 195 u8 tdma_dig_state; /*@To distinguish which state is now.(L-sate or H-state)*/ 196 u8 tdma_dig_cnt; /*@for phydm_tdma_dig_timer_check use*/ 197 u8 pre_tdma_dig_cnt; 198 u8 sec_factor; 199 u32 cur_timestamp; 200 u32 pre_timestamp; 201 u32 fa_start_timestamp; 202 u32 fa_end_timestamp; 203 u32 fa_acc_1sec_timestamp; 204 #ifdef IS_USE_NEW_TDMA 205 u8 tdma_dig_block_cnt;/*@for 1 second dump indicator use*/ 206 /*@dynamic upper bound for L/H state*/ 207 u8 tdma_rx_gain_max[DIG_NUM_OF_TDMA_STATES]; 208 /*@dynamic lower bound for L/H state*/ 209 u8 tdma_rx_gain_min[DIG_NUM_OF_TDMA_STATES]; 210 /*To distinguish current state(L-sate or H-state)*/ 211 #endif 212 u8 tdma_force_l_igi; 213 u8 tdma_force_h_igi; 214 #endif 215 }; 216 217 struct phydm_fa_struct { 218 u32 cnt_parity_fail; 219 u32 cnt_rate_illegal; 220 u32 cnt_crc8_fail; 221 u32 cnt_crc8_fail_vhta; 222 u32 cnt_crc8_fail_vhtb; 223 u32 cnt_mcs_fail; 224 u32 cnt_mcs_fail_vht; 225 u32 cnt_ofdm_fail; 226 u32 cnt_ofdm_fail_pre; /* @For RTL8881A */ 227 u32 cnt_cck_fail; 228 u32 cnt_all; 229 u32 cnt_all_accumulated; 230 u32 cnt_all_pre; 231 u32 cnt_fast_fsync; 232 u32 cnt_sb_search_fail; 233 u32 cnt_ofdm_cca; 234 u32 cnt_cck_cca; 235 u32 cnt_cca_all; 236 u32 cnt_bw_usc; 237 u32 cnt_bw_lsc; 238 u32 cnt_cck_crc32_error; 239 u32 cnt_cck_crc32_ok; 240 u32 cnt_ofdm_crc32_error; 241 u32 cnt_ofdm_crc32_ok; 242 u32 cnt_ht_crc32_error; 243 u32 cnt_ht_crc32_ok; 244 u32 cnt_ht_crc32_error_agg; 245 u32 cnt_ht_crc32_ok_agg; 246 u32 cnt_vht_crc32_error; 247 u32 cnt_vht_crc32_ok; 248 u32 cnt_crc32_error_all; 249 u32 cnt_crc32_ok_all; 250 u32 time_fa_all; 251 u32 time_fa_exp; /*FA duration, [PHYDM-406]*/ 252 u32 time_fa_ifs_clm; /*FA duration, [PHYDM-406]*/ 253 u32 time_fa_fahm; /*FA duration, [PHYDM-406]*/ 254 boolean cck_block_enable; 255 boolean ofdm_block_enable; 256 u32 dbg_port0; 257 boolean edcca_flag; 258 u8 ofdm2_rate_idx; 259 u32 cnt_ofdm2_crc32_error; 260 u32 cnt_ofdm2_crc32_ok; 261 u8 ofdm2_pcr; 262 u8 ht2_rate_idx; 263 u32 cnt_ht2_crc32_error; 264 u32 cnt_ht2_crc32_ok; 265 u8 ht2_pcr; 266 u8 vht2_rate_idx; 267 u32 cnt_vht2_crc32_error; 268 u32 cnt_vht2_crc32_ok; 269 u8 vht2_pcr; 270 u32 cnt_cck_txen; 271 u32 cnt_cck_txon; 272 u32 cnt_ofdm_txen; 273 u32 cnt_ofdm_txon; 274 }; 275 276 #ifdef PHYDM_TDMA_DIG_SUPPORT 277 struct phydm_fa_acc_struct { 278 u32 cnt_parity_fail; 279 u32 cnt_rate_illegal; 280 u32 cnt_crc8_fail; 281 u32 cnt_mcs_fail; 282 u32 cnt_ofdm_fail; 283 u32 cnt_ofdm_fail_pre; /*@For RTL8881A*/ 284 u32 cnt_cck_fail; 285 u32 cnt_all; 286 u32 cnt_all_pre; 287 u32 cnt_fast_fsync; 288 u32 cnt_sb_search_fail; 289 u32 cnt_ofdm_cca; 290 u32 cnt_cck_cca; 291 u32 cnt_cca_all; 292 u32 cnt_cck_crc32_error; 293 u32 cnt_cck_crc32_ok; 294 u32 cnt_ofdm_crc32_error; 295 u32 cnt_ofdm_crc32_ok; 296 u32 cnt_ht_crc32_error; 297 u32 cnt_ht_crc32_ok; 298 u32 cnt_vht_crc32_error; 299 u32 cnt_vht_crc32_ok; 300 u32 cnt_crc32_error_all; 301 u32 cnt_crc32_ok_all; 302 u32 cnt_all_1sec; 303 u32 cnt_cca_all_1sec; 304 u32 cnt_cck_fail_1sec; 305 }; 306 307 #endif /*@#ifdef PHYDM_TDMA_DIG_SUPPORT*/ 308 309 /*@--------------------Function declaration-----------------------------*/ 310 void phydm_write_dig_reg(void *dm_void, u8 igi); 311 312 void odm_write_dig(void *dm_void, u8 current_igi); 313 314 u8 phydm_get_igi(void *dm_void, enum bb_path path); 315 316 void phydm_set_dig_val(void *dm_void, u32 *val_buf, u8 val_len); 317 318 void odm_pause_dig(void *dm_void, enum phydm_pause_type pause_type, 319 enum phydm_pause_level pause_level, u8 igi_value); 320 321 #ifdef PHYDM_HW_IGI 322 void phydm_hwigi(void *dm_void); 323 324 void phydm_hwigi_dbg(void *dm_void, char input[][16], u32 *_used, 325 char *output, u32 *_out_len); 326 #endif 327 328 void phydm_dig_init(void *dm_void); 329 330 void phydm_dig(void *dm_void); 331 332 void phydm_dig_lps_32k(void *dm_void); 333 334 void phydm_dig_by_rssi_lps(void *dm_void); 335 336 void phydm_get_dig_coverage(void *dm_void, u8 *max, u8 *min); 337 338 u8 phydm_get_igi_for_target_pin_scan(void *dm_void, u8 rssi); 339 340 void phydm_false_alarm_counter_statistics(void *dm_void); 341 342 u32 phydm_get_edcca_report(void * dm_void); 343 344 #ifdef PHYDM_TDMA_DIG_SUPPORT 345 void phydm_set_tdma_dig_timer(void *dm_void); 346 347 void phydm_tdma_dig_timer_check(void *dm_void); 348 349 void phydm_tdma_dig(void *dm_void); 350 351 void phydm_tdma_false_alarm_counter_check(void *dm_void); 352 353 void phydm_tdma_dig_add_interrupt_mask_handler(void *dm_void); 354 355 void phydm_false_alarm_counter_reset(void *dm_void); 356 357 void phydm_false_alarm_counter_acc(void *dm_void, boolean rssi_dump_en); 358 359 void phydm_false_alarm_counter_acc_reset(void *dm_void); 360 361 void phydm_tdma_dig_para_upd(void *dm_void, enum upd_type type, u8 input); 362 363 #ifdef IS_USE_NEW_TDMA 364 void phydm_tdma_dig_timers(void *dm_void, u8 state); 365 366 void phydm_tdma_dig_cbk(void *dm_void); 367 368 void phydm_tdma_dig_workitem_callback(void *dm_void); 369 370 void phydm_tdma_fa_cnt_chk(void *dm_void); 371 372 void phydm_tdma_low_dig(void *dm_void); 373 374 void phydm_tdma_high_dig(void *dm_void); 375 376 void phydm_fa_cnt_acc(void *dm_void, boolean rssi_dump_en, 377 u8 cur_tdma_dig_state); 378 #endif /*@#ifdef IS_USE_NEW_TDMA*/ 379 #endif /*@#ifdef PHYDM_TDMA_DIG_SUPPORT*/ 380 381 void phydm_set_ofdm_agc_tab(void *dm_void, u8 tab_sel); 382 383 void phydm_dig_debug(void *dm_void, char input[][16], u32 *_used, char *output, 384 u32 *_out_len); 385 386 void phydm_fill_fw_dig_info(void *dm_void, boolean *enable, 387 u8 *para4, u8 *para8); 388 389 void phydm_crc32_cnt_dbg(void *dm_void, char input[][16], u32 *_used, 390 char *output, u32 *_out_len); 391 392 #ifdef CONFIG_MCC_DM 393 void phydm_mcc_igi_cal(void *dm_void); 394 #endif 395 396 #endif 397