1 /******************************************************************************
2 *
3 * Copyright(c) 2007 - 2017 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26 /*************************************************************
27 * include files
28 ************************************************************/
29 #include "mp_precomp.h"
30 #include "phydm_precomp.h"
31
32 #ifdef CONFIG_DYNAMIC_TX_TWR
33 #ifdef BB_RAM_SUPPORT
phydm_rd_reg_pwr(void * dm_void,u32 * _used,char * output,u32 * _out_len)34 void phydm_rd_reg_pwr(void *dm_void, u32 *_used, char *output, u32 *_out_len)
35 {
36 struct dm_struct *dm = (struct dm_struct *)dm_void;
37 u32 used = *_used;
38 u32 out_len = *_out_len;
39 boolean pwr_ofst0_en = false;
40 boolean pwr_ofst1_en = false;
41 s8 pwr_ofst0 = 0;
42 s8 pwr_ofst1 = 0;
43
44 pwr_ofst0_en = (boolean)odm_get_bb_reg(dm, R_0x1e70, BIT(23));
45 pwr_ofst1_en = (boolean)odm_get_bb_reg(dm, R_0x1e70, BIT(31));
46 pwr_ofst0 = (s8)odm_get_bb_reg(dm, R_0x1e70, 0x7f0000);
47 pwr_ofst1 = (s8)odm_get_bb_reg(dm, R_0x1e70, 0x7f000000);
48
49 PDM_SNPF(out_len, used, output + used, out_len - used,
50 "reg0: en:%d, pwr_ofst:0x%x, reg1: en:%d, pwr_ofst:0x%x\n",
51 pwr_ofst0_en, pwr_ofst0, pwr_ofst1_en, pwr_ofst1);
52
53 *_used = used;
54 *_out_len = out_len;
55 };
56
phydm_wt_reg_pwr(void * dm_void,boolean is_ofst1,boolean pwr_ofst_en,s8 pwr_ofst)57 void phydm_wt_reg_pwr(void *dm_void, boolean is_ofst1, boolean pwr_ofst_en,
58 s8 pwr_ofst)
59 {
60 struct dm_struct *dm = (struct dm_struct *)dm_void;
61 struct phydm_bb_ram_ctrl *bb_ctrl = &dm->p_bb_ram_ctrl;
62 u8 reg_0x1e70 = 0;
63
64 if (!is_ofst1) {
65 bb_ctrl->tx_pwr_ofst_reg0_en = pwr_ofst_en;
66 bb_ctrl->tx_pwr_ofst_reg0 = pwr_ofst;
67
68 reg_0x1e70 |= (pwr_ofst_en << 7) + (pwr_ofst & 0x7f);
69 odm_set_bb_reg(dm, R_0x1e70, 0x00ff0000, reg_0x1e70);
70 } else {
71 bb_ctrl->tx_pwr_ofst_reg1_en = pwr_ofst_en;
72 bb_ctrl->tx_pwr_ofst_reg1 = pwr_ofst;
73
74 reg_0x1e70 |= (pwr_ofst_en << 7) + (pwr_ofst & 0x7f);
75 odm_set_bb_reg(dm, R_0x1e70, 0xff000000, reg_0x1e70);
76 }
77 };
78
phydm_rd_ram_pwr(void * dm_void,u8 macid,u32 * _used,char * output,u32 * _out_len)79 void phydm_rd_ram_pwr(void *dm_void, u8 macid, u32 *_used, char *output,
80 u32 *_out_len)
81 {
82 struct dm_struct *dm = (struct dm_struct *)dm_void;
83 u32 used = *_used;
84 u32 out_len = *_out_len;
85 boolean pwr_ofst0_en = false;
86 boolean pwr_ofst1_en = false;
87 s8 pwr_ofst0 = 0;
88 s8 pwr_ofst1 = 0;
89 u32 reg_0x1e84 = 0;
90
91 reg_0x1e84 |= (macid & 0x3f) << 24; /* macid*/
92 reg_0x1e84 |= BIT(31); /* read_en*/
93 odm_set_bb_reg(dm, R_0x1e84, MASKDWORD, reg_0x1e84);
94
95 pwr_ofst0_en = (boolean)odm_get_bb_reg(dm, R_0x2de8, BIT(23));
96 pwr_ofst1_en = (boolean)odm_get_bb_reg(dm, R_0x2de8, BIT(31));
97 pwr_ofst0 = (s8)odm_get_bb_reg(dm, R_0x2de8, 0x7f0000);
98 pwr_ofst1 = (s8)odm_get_bb_reg(dm, R_0x2de8, 0x7f000000);
99 odm_set_bb_reg(dm, R_0x1e84, MASKDWORD, 0x0); /* disable rd/wt*/
100
101 PDM_SNPF(out_len, used, output + used, out_len - used,
102 "(macid:%d) ram0: en:%d, pwr_ofst:0x%x, ram1: en:%d, pwr_ofst:0x%x\n",
103 macid, pwr_ofst0_en, pwr_ofst0, pwr_ofst1_en, pwr_ofst1);
104
105 *_used = used;
106 *_out_len = out_len;
107 };
108
phydm_wt_ram_pwr(void * dm_void,u8 macid,boolean is_ofst1,boolean pwr_ofst_en,s8 pwr_ofst)109 void phydm_wt_ram_pwr(void *dm_void, u8 macid, boolean is_ofst1,
110 boolean pwr_ofst_en, s8 pwr_ofst)
111 {
112 struct dm_struct *dm = (struct dm_struct *)dm_void;
113 struct phydm_bb_ram_per_sta *dm_ram_per_sta = NULL;
114 u32 reg_0x1e84 = 0;
115 boolean pwr_ofst_ano_en = false;
116 s8 pwr_ofst_ano = 0;
117
118 if (macid > 63)
119 macid = 63;
120
121 dm_ram_per_sta = &dm->p_bb_ram_ctrl.pram_sta_ctrl[macid];
122 reg_0x1e84 = (dm_ram_per_sta->hw_igi_en << 7) + dm_ram_per_sta->hw_igi;
123 if (!is_ofst1) {
124 dm_ram_per_sta->tx_pwr_offset0_en = pwr_ofst_en;
125 dm_ram_per_sta->tx_pwr_offset0 = pwr_ofst;
126
127 pwr_ofst_ano_en = dm_ram_per_sta->tx_pwr_offset1_en;
128 pwr_ofst_ano = dm_ram_per_sta->tx_pwr_offset1;
129
130 reg_0x1e84 |= (pwr_ofst_en << 15) + ((pwr_ofst & 0x7f) << 8) +
131 (pwr_ofst_ano_en << 23) +
132 ((pwr_ofst_ano & 0x7f) << 16);
133 } else {
134 dm_ram_per_sta->tx_pwr_offset1_en = pwr_ofst_en;
135 dm_ram_per_sta->tx_pwr_offset1 = pwr_ofst;
136
137 pwr_ofst_ano_en = dm_ram_per_sta->tx_pwr_offset0_en;
138 pwr_ofst_ano = dm_ram_per_sta->tx_pwr_offset0;
139
140 reg_0x1e84 |= (pwr_ofst_ano_en << 15) +
141 ((pwr_ofst_ano & 0x7f) << 8) +
142 (pwr_ofst_en << 23) + ((pwr_ofst & 0x7f) << 16);
143 }
144 reg_0x1e84 |= (macid & 0x3f) << 24;/* macid*/
145 reg_0x1e84 |= BIT(30); /* write_en*/
146 odm_set_bb_reg(dm, R_0x1e84, MASKDWORD, reg_0x1e84);
147 odm_set_bb_reg(dm, R_0x1e84, MASKDWORD, 0x80000000); /* read_en*/
148 odm_set_bb_reg(dm, R_0x1e84, MASKDWORD, 0x0); /* disable rd/wt*/
149 };
150
phydm_rst_ram_pwr(void * dm_void)151 void phydm_rst_ram_pwr(void *dm_void)
152 {
153 struct dm_struct *dm = (struct dm_struct *)dm_void;
154 struct phydm_bb_ram_per_sta *dm_ram_per_sta = NULL;
155 u32 reg_0x1e84 = 0;
156 u8 i = 0;
157
158 for (i = 0; i < 64; i++) {
159 dm_ram_per_sta = &dm->p_bb_ram_ctrl.pram_sta_ctrl[i];
160 dm_ram_per_sta->tx_pwr_offset0_en = false;
161 dm_ram_per_sta->tx_pwr_offset1_en = false;
162 dm_ram_per_sta->tx_pwr_offset0 = 0x0;
163 dm_ram_per_sta->tx_pwr_offset1 = 0x0;
164 reg_0x1e84 = (dm_ram_per_sta->hw_igi_en << 7) +
165 dm_ram_per_sta->hw_igi;
166 reg_0x1e84 |= (i & 0x3f) << 24;
167 reg_0x1e84 |= BIT(30);
168 odm_set_bb_reg(dm, R_0x1e84, MASKDWORD, reg_0x1e84);
169 }
170
171 odm_set_bb_reg(dm, R_0x1e84, MASKDWORD, 0x80000000);
172 odm_set_bb_reg(dm, R_0x1e84, MASKDWORD, 0x0);
173 };
174
phydm_pwr_lv_mapping_2nd(u8 tx_pwr_lv)175 u8 phydm_pwr_lv_mapping_2nd(u8 tx_pwr_lv)
176 {
177 if (tx_pwr_lv == tx_high_pwr_level_level3)
178 return PHYDM_2ND_OFFSET_MINUS_11DB;
179 else if (tx_pwr_lv == tx_high_pwr_level_level2)
180 return PHYDM_2ND_OFFSET_MINUS_7DB;
181 else if (tx_pwr_lv == tx_high_pwr_level_level1)
182 return PHYDM_2ND_OFFSET_MINUS_3DB;
183 else
184 return PHYDM_2ND_OFFSET_ZERO;
185 }
186
phydm_pwr_lv_ctrl(void * dm_void,u8 macid,u8 tx_pwr_lv)187 void phydm_pwr_lv_ctrl(void *dm_void, u8 macid, u8 tx_pwr_lv)
188 {
189 struct dm_struct *dm = (struct dm_struct *)dm_void;
190 s8 pwr_offset = 0;
191
192 if (tx_pwr_lv == tx_high_pwr_level_level3)
193 pwr_offset = PHYDM_BBRAM_OFFSET_MINUS_11DB;
194 else if (tx_pwr_lv == tx_high_pwr_level_level2)
195 pwr_offset = PHYDM_BBRAM_OFFSET_MINUS_7DB;
196 else if (tx_pwr_lv == tx_high_pwr_level_level1)
197 pwr_offset = PHYDM_BBRAM_OFFSET_MINUS_3DB;
198 else
199 pwr_offset = PHYDM_BBRAM_OFFSET_ZERO;
200
201 phydm_wt_ram_pwr(dm, macid, RAM_PWR_OFST0, true, pwr_offset);
202 }
203
phydm_dtp_fill_cmninfo_2nd(void * dm_void,u8 sta_id,u8 dtp_lvl)204 void phydm_dtp_fill_cmninfo_2nd(void *dm_void, u8 sta_id, u8 dtp_lvl)
205 {
206 struct dm_struct *dm = (struct dm_struct *)dm_void;
207 struct cmn_sta_info *sta = dm->phydm_sta_info[sta_id];
208 struct dtp_info *dtp = NULL;
209
210 if (!is_sta_active(sta))
211 return;
212
213 dtp = &dm->phydm_sta_info[sta_id]->dtp_stat;
214 dtp->dyn_tx_power = phydm_pwr_lv_mapping_2nd(dtp_lvl);
215 phydm_pwr_lv_ctrl(dm, sta->mac_id, dtp_lvl);
216
217 PHYDM_DBG(dm, DBG_DYN_TXPWR,
218 "Fill cmninfo TxPwr: sta_id=(%d), macid=(%d), PwrLv (%d)\n",
219 sta_id, sta->mac_id, dtp->dyn_tx_power);
220 }
221
phydm_dtp_init_2nd(void * dm_void)222 void phydm_dtp_init_2nd(void *dm_void)
223 {
224 struct dm_struct *dm = (struct dm_struct *)dm_void;
225
226 if (!(dm->support_ability & ODM_BB_DYNAMIC_TXPWR))
227 return;
228
229 #if (RTL8822C_SUPPORT || RTL8812F_SUPPORT)
230 if (dm->support_ic_type & (ODM_RTL8822C | ODM_RTL8812F)) {
231 phydm_rst_ram_pwr(dm);
232 /* rsp tx use type 0*/
233 odm_set_mac_reg(dm, R_0x6d8, BIT(19) | BIT(18), RAM_PWR_OFST0);
234 }
235 #endif
236 };
237 #endif
238
239 boolean
phydm_check_rates(void * dm_void,u8 rate_idx)240 phydm_check_rates(void *dm_void, u8 rate_idx)
241 {
242 struct dm_struct *dm = (struct dm_struct *)dm_void;
243 u32 check_rate_bitmap0 = 0x08080808; /* @check CCK11M, OFDM54M, MCS7, MCS15*/
244 u32 check_rate_bitmap1 = 0x80200808; /* @check MCS23, MCS31, VHT1SS M9, VHT2SS M9*/
245 u32 check_rate_bitmap2 = 0x00080200; /* @check VHT3SS M9, VHT4SS M9*/
246 u32 bitmap_result;
247
248 #if (RTL8822B_SUPPORT)
249 if (dm->support_ic_type & ODM_RTL8822B) {
250 check_rate_bitmap2 &= 0;
251 check_rate_bitmap1 &= 0xfffff000;
252 check_rate_bitmap0 &= 0x0fffffff;
253 }
254 #endif
255 #if (RTL8197F_SUPPORT)
256 if (dm->support_ic_type & ODM_RTL8197F) {
257 check_rate_bitmap2 &= 0;
258 check_rate_bitmap1 &= 0;
259 check_rate_bitmap0 &= 0x0fffffff;
260 }
261 #endif
262 #if (RTL8192E_SUPPORT)
263 if (dm->support_ic_type & ODM_RTL8192E) {
264 check_rate_bitmap2 &= 0;
265 check_rate_bitmap1 &= 0;
266 check_rate_bitmap0 &= 0x0fffffff;
267 }
268 #endif
269 #if (RTL8192F_SUPPORT)
270 if (dm->support_ic_type & ODM_RTL8192F) {
271 check_rate_bitmap2 &= 0;
272 check_rate_bitmap1 &= 0;
273 check_rate_bitmap0 &= 0x0fffffff;
274 }
275 #endif
276 #if (RTL8721D_SUPPORT)
277 if (dm->support_ic_type & ODM_RTL8721D) {
278 check_rate_bitmap2 &= 0;
279 check_rate_bitmap1 &= 0;
280 check_rate_bitmap0 &= 0x000fffff;
281 }
282 #endif
283 #if (RTL8821C_SUPPORT)
284 if (dm->support_ic_type & ODM_RTL8821C) {
285 check_rate_bitmap2 &= 0;
286 check_rate_bitmap1 &= 0x003ff000;
287 check_rate_bitmap0 &= 0x000fffff;
288 }
289 #endif
290 if (rate_idx >= 64)
291 bitmap_result = BIT(rate_idx - 64) & check_rate_bitmap2;
292 else if (rate_idx >= 32)
293 bitmap_result = BIT(rate_idx - 32) & check_rate_bitmap1;
294 else if (rate_idx <= 31)
295 bitmap_result = BIT(rate_idx) & check_rate_bitmap0;
296
297 if (bitmap_result != 0)
298 return true;
299 else
300 return false;
301 }
302
303 enum rf_path
phydm_check_paths(void * dm_void)304 phydm_check_paths(void *dm_void)
305 {
306 struct dm_struct *dm = (struct dm_struct *)dm_void;
307 enum rf_path max_path = RF_PATH_A;
308
309 if (dm->num_rf_path == 1)
310 max_path = RF_PATH_A;
311 if (dm->num_rf_path == 2)
312 max_path = RF_PATH_B;
313 if (dm->num_rf_path == 3)
314 max_path = RF_PATH_C;
315 if (dm->num_rf_path == 4)
316 max_path = RF_PATH_D;
317
318 return max_path;
319 }
320
321 #ifdef PHYDM_COMMON_API_NOT_SUPPORT
phydm_dtp_get_txagc(void * dm_void,enum rf_path path,u8 hw_rate)322 u8 phydm_dtp_get_txagc(void *dm_void, enum rf_path path, u8 hw_rate)
323 {
324 struct dm_struct *dm = (struct dm_struct *)dm_void;
325 u8 ret = 0xff;
326
327 ret = config_phydm_read_txagc_n(dm, path, hw_rate);
328
329 return ret;
330 }
331 #endif
332
phydm_search_min_power_index(void * dm_void)333 u8 phydm_search_min_power_index(void *dm_void)
334 {
335 struct dm_struct *dm = (struct dm_struct *)dm_void;
336 enum rf_path path;
337 enum rf_path max_path;
338 u8 min_gain_index = 0x3f;
339 u8 gain_index = 0;
340 u8 i;
341
342 PHYDM_DBG(dm, DBG_DYN_TXPWR, "%s\n", __func__);
343 max_path = phydm_check_paths(dm);
344 for (path = 0; path <= max_path; path++)
345 for (i = 0; i < 84; i++)
346 if (phydm_check_rates(dm, i)) {
347
348 if (dm->support_ic_type & PHYDM_COMMON_API_IC) {
349 #ifdef PHYDM_COMMON_API_SUPPORT
350 /*97F,8822B,92F,8821C*/
351 gain_index = phydm_api_get_txagc(dm, path, i);
352 #endif
353 } else {
354 /*92E*/
355 #ifdef PHYDM_COMMON_API_NOT_SUPPORT
356 gain_index = phydm_dtp_get_txagc(dm, path, i);
357 #endif
358 }
359
360 if (gain_index == 0xff) {
361 min_gain_index = 0x20;
362 PHYDM_DBG(dm, DBG_DYN_TXPWR,
363 "Error Gain idx!! Rewite to: ((%d))\n",
364 min_gain_index);
365 break;
366 }
367 PHYDM_DBG(dm, DBG_DYN_TXPWR,
368 "Support Rate: ((%d)) -> Gain idx: ((%d))\n",
369 i, gain_index);
370 if (gain_index < min_gain_index)
371 min_gain_index = gain_index;
372 }
373 return min_gain_index;
374 }
375
phydm_dynamic_tx_power_init(void * dm_void)376 void phydm_dynamic_tx_power_init(void *dm_void)
377 {
378 struct dm_struct *dm = (struct dm_struct *)dm_void;
379 u8 i = 0;
380
381 dm->last_dtp_lvl = tx_high_pwr_level_normal;
382 dm->dynamic_tx_high_power_lvl = tx_high_pwr_level_normal;
383
384 switch (dm->ic_ip_series) {
385 #ifdef BB_RAM_SUPPORT
386 case PHYDM_IC_JGR3:
387 dm->set_pwr_th[0] = TX_PWR_NEAR_FIELD_TH_JGR3_LVL1;
388 dm->set_pwr_th[1] = TX_PWR_NEAR_FIELD_TH_JGR3_LVL2;
389 dm->set_pwr_th[2] = TX_PWR_NEAR_FIELD_TH_JGR3_LVL3;
390 phydm_dtp_init_2nd(dm);
391 break;
392 #endif
393 default:
394 for (i = 0; i < 3; i++)
395 dm->enhance_pwr_th[i] = 0xff;
396
397 dm->set_pwr_th[0] = TX_POWER_NEAR_FIELD_THRESH_LVL1;
398 dm->set_pwr_th[1] = TX_POWER_NEAR_FIELD_THRESH_LVL2;
399 dm->set_pwr_th[2] = 0xff;
400 dm->min_power_index = phydm_search_min_power_index(dm);
401 PHYDM_DBG(dm, DBG_DYN_TXPWR, "DTP init: Min Gain idx: ((%d))\n",
402 dm->min_power_index);
403 break;
404 }
405 }
406
phydm_noisy_enhance_hp_th(void * dm_void,u8 noisy_state)407 void phydm_noisy_enhance_hp_th(void *dm_void, u8 noisy_state)
408 {
409 struct dm_struct *dm = (struct dm_struct *)dm_void;
410
411 if (noisy_state == 0) {
412 dm->enhance_pwr_th[0] = dm->set_pwr_th[0];
413 dm->enhance_pwr_th[1] = dm->set_pwr_th[1];
414 dm->enhance_pwr_th[2] = dm->set_pwr_th[2];
415 } else {
416 dm->enhance_pwr_th[0] = dm->set_pwr_th[0] + 8;
417 dm->enhance_pwr_th[1] = dm->set_pwr_th[1] + 5;
418 dm->enhance_pwr_th[2] = dm->set_pwr_th[2];
419 }
420 PHYDM_DBG(dm, DBG_DYN_TXPWR,
421 "DTP hp_enhance_th: Lv1_th =%d ,Lv2_th = %d ,Lv3_th = %d\n",
422 dm->enhance_pwr_th[0], dm->enhance_pwr_th[1],
423 dm->enhance_pwr_th[2]);
424 }
425
phydm_pwr_lvl_check(void * dm_void,u8 input_rssi,u8 last_pwr_lv)426 u8 phydm_pwr_lvl_check(void *dm_void, u8 input_rssi, u8 last_pwr_lv)
427 {
428 struct dm_struct *dm = (struct dm_struct *)dm_void;
429 u8 th[DTP_POWER_LEVEL_SIZE];
430 u8 i;
431
432 if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
433 for (i = 0; i < DTP_POWER_LEVEL_SIZE; i++)
434 th[i] = dm->set_pwr_th[i];
435
436 PHYDM_DBG(dm, DBG_DYN_TXPWR,
437 "Ori-DTP th: Lv1_th = %d, Lv2_th = %d, Lv3_th = %d\n",
438 th[0], th[1], th[2]);
439
440 for (i = 0; i < DTP_POWER_LEVEL_SIZE; i++) {
441 if (i >= (last_pwr_lv))
442 th[i] += DTP_FLOOR_UP_GAP;
443 }
444
445 PHYDM_DBG(dm, DBG_DYN_TXPWR,
446 "Mod-DTP th: Lv1_th = %d, Lv2_th = %d, Lv3_th = %d\n",
447 th[0], th[1], th[2]);
448 } else {
449 for (i = 0; i < DTP_POWER_LEVEL_SIZE; i++)
450 th[i] = dm->enhance_pwr_th[i];
451 for (i = 0; i < DTP_POWER_LEVEL_SIZE; i++) {
452 if (i >= (last_pwr_lv))
453 th[i] += DTP_FLOOR_UP_GAP;
454 }
455 }
456
457 if (input_rssi >= th[2])
458 return tx_high_pwr_level_level3;
459 else if (input_rssi < th[2] && input_rssi >= th[1])
460 return tx_high_pwr_level_level2;
461 else if (input_rssi < th[1] && input_rssi >= th[0])
462 return tx_high_pwr_level_level1;
463 else
464 return tx_high_pwr_level_normal;
465 }
466
phydm_pwr_lv_mapping(u8 tx_pwr_lv)467 u8 phydm_pwr_lv_mapping(u8 tx_pwr_lv)
468 {
469 if (tx_pwr_lv == tx_high_pwr_level_level3)
470 return PHYDM_OFFSET_MINUS_11DB;
471 else if (tx_pwr_lv == tx_high_pwr_level_level2)
472 return PHYDM_OFFSET_MINUS_7DB;
473 else if (tx_pwr_lv == tx_high_pwr_level_level1)
474 return PHYDM_OFFSET_MINUS_3DB;
475 else
476 return PHYDM_OFFSET_ZERO;
477 }
478
phydm_dynamic_response_power(void * dm_void)479 void phydm_dynamic_response_power(void *dm_void)
480 {
481 struct dm_struct *dm = (struct dm_struct *)dm_void;
482 u8 rpwr = 0;
483
484 if (!(dm->support_ability & ODM_BB_DYNAMIC_TXPWR))
485 return;
486
487 if (dm->dynamic_tx_high_power_lvl == dm->last_dtp_lvl) {
488 PHYDM_DBG(dm, DBG_DYN_TXPWR, "RespPwr not change\n");
489 return;
490 }
491 PHYDM_DBG(dm, DBG_DYN_TXPWR,
492 "RespPwr update_DTP_lv: ((%d)) -> ((%d))\n", dm->last_dtp_lvl,
493 dm->dynamic_tx_high_power_lvl);
494 dm->last_dtp_lvl = dm->dynamic_tx_high_power_lvl;
495 rpwr = phydm_pwr_lv_mapping(dm->dynamic_tx_high_power_lvl);
496 odm_set_mac_reg(dm, ODM_REG_RESP_TX_11AC, BIT(20) | BIT(19) | BIT(18),
497 rpwr);
498 PHYDM_DBG(dm, DBG_DYN_TXPWR, "RespPwr Set TxPwr: Lv (%d)\n",
499 dm->dynamic_tx_high_power_lvl);
500 }
501
phydm_dtp_fill_cmninfo(void * dm_void,u8 sta_id,u8 dtp_lvl)502 void phydm_dtp_fill_cmninfo(void *dm_void, u8 sta_id, u8 dtp_lvl)
503 {
504 struct dm_struct *dm = (struct dm_struct *)dm_void;
505 struct cmn_sta_info *sta = dm->phydm_sta_info[sta_id];
506 struct dtp_info *dtp = NULL;
507
508 if (!is_sta_active(sta))
509 return;
510
511 dtp = &sta->dtp_stat;
512 dtp->dyn_tx_power = phydm_pwr_lv_mapping(dtp_lvl);
513 PHYDM_DBG(dm, DBG_DYN_TXPWR,
514 "Fill cmninfo TxPwr: sta_id=(%d), macid=(%d), PwrLv (%d)\n",
515 sta_id, sta->mac_id, dtp->dyn_tx_power);
516 }
517
phydm_dtp_per_sta(void * dm_void)518 void phydm_dtp_per_sta(void *dm_void)
519 {
520 struct dm_struct *dm = (struct dm_struct *)dm_void;
521 struct cmn_sta_info *sta = NULL;
522 struct dtp_info *dtp = NULL;
523 struct rssi_info *rssi = NULL;
524 struct phydm_bb_ram_ctrl *bb_ctrl = &dm->p_bb_ram_ctrl;
525 u8 sta_cnt = 0;
526 u8 i = 0;
527 u8 curr_pwr_lv = 0;
528 u8 last_pwr_lv = 0;
529 u8 mac_id_cnt = 0;
530 u64 macid_cur = 0;
531 u64 macid_diff = 0;
532 u64 macid_mask = 0;
533
534 for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
535 sta = dm->phydm_sta_info[i];
536 if (is_sta_active(sta)) {
537 sta_cnt++;
538
539 dtp = &sta->dtp_stat;
540 rssi = &sta->rssi_stat;
541 macid_mask = (u64)BIT(sta->mac_id);
542 if (!(bb_ctrl->macid_is_linked & macid_mask))
543 dtp->sta_last_dtp_lvl = tx_high_pwr_level_normal;
544
545 last_pwr_lv = dtp->sta_last_dtp_lvl;
546 curr_pwr_lv = phydm_pwr_lvl_check(dm, rssi->rssi,
547 last_pwr_lv);
548 dtp->sta_tx_high_power_lvl = curr_pwr_lv;
549 PHYDM_DBG(dm, DBG_DYN_TXPWR,
550 "STA_id=%d, MACID=%d , RSSI: %d , GetPwrLv: %d\n",
551 i, sta->mac_id, rssi->rssi, curr_pwr_lv);
552
553 bb_ctrl->macid_is_linked |= macid_mask;
554 macid_cur |= macid_mask;
555 PHYDM_DBG(dm, DBG_DYN_TXPWR,
556 "macid_is_linked: (0x%llx), macid_cur: (0x%llx)\n",
557 bb_ctrl->macid_is_linked, macid_cur);
558
559 if (curr_pwr_lv == last_pwr_lv && dtp->sta_is_alive) {
560 dtp->sta_tx_high_power_lvl = last_pwr_lv;
561 PHYDM_DBG(dm, DBG_DYN_TXPWR,
562 "DTP_lv not change: ((%d))\n",
563 curr_pwr_lv);
564 } else {
565 PHYDM_DBG(dm, DBG_DYN_TXPWR,
566 "DTP_lv update: ((%d)) -> ((%d))\n",
567 last_pwr_lv, curr_pwr_lv);
568
569 dtp->sta_last_dtp_lvl = curr_pwr_lv;
570
571 switch (dm->ic_ip_series) {
572 #ifdef BB_RAM_SUPPORT
573 case PHYDM_IC_JGR3:
574 phydm_dtp_fill_cmninfo_2nd(dm, i, curr_pwr_lv);
575 break;
576 #endif
577 default:
578 phydm_dtp_fill_cmninfo(dm, i, curr_pwr_lv);
579 break;
580 }
581 if(!dtp->sta_is_alive)
582 dtp->sta_is_alive = true;
583 }
584
585 if (sta_cnt == dm->number_linked_client)
586 break;
587 }
588 }
589
590 macid_diff = bb_ctrl->macid_is_linked ^ macid_cur;
591 if (macid_diff)
592 bb_ctrl->macid_is_linked &= ~macid_diff;
593 while (macid_diff) {
594 if (macid_diff & 0x1)
595 phydm_pwr_lv_ctrl(dm, mac_id_cnt, tx_high_pwr_level_normal);
596 mac_id_cnt++;
597 macid_diff >>= 1;
598 }
599 }
600
odm_set_dyntxpwr(void * dm_void,u8 * desc,u8 sta_id)601 void odm_set_dyntxpwr(void *dm_void, u8 *desc, u8 sta_id)
602 {
603 struct dm_struct *dm = (struct dm_struct *)dm_void;
604 struct cmn_sta_info *sta = dm->phydm_sta_info[sta_id];
605 struct dtp_info *dtp = NULL;
606
607 if (!is_sta_active(sta))
608 return;
609 dtp = &sta->dtp_stat;
610
611 if (!(dm->support_ability & ODM_BB_DYNAMIC_TXPWR))
612 return;
613
614 if (dm->fill_desc_dyntxpwr)
615 dm->fill_desc_dyntxpwr(dm, desc, dtp->dyn_tx_power);
616 else
617 PHYDM_DBG(dm, DBG_DYN_TXPWR,
618 "%s: fill_desc_dyntxpwr is null!\n", __func__);
619
620 if (dtp->last_tx_power != dtp->dyn_tx_power) {
621 PHYDM_DBG(dm, DBG_DYN_TXPWR,
622 "%s: last_offset=%d, txpwr_offset=%d\n", __func__,
623 dtp->last_tx_power, dtp->dyn_tx_power);
624 dtp->last_tx_power = dtp->dyn_tx_power;
625 }
626 }
627
phydm_dtp_debug(void * dm_void,char input[][16],u32 * _used,char * output,u32 * _out_len)628 void phydm_dtp_debug(void *dm_void, char input[][16], u32 *_used, char *output,
629 u32 *_out_len)
630 {
631 u32 used = *_used;
632 u32 out_len = *_out_len;
633
634 struct dm_struct *dm = (struct dm_struct *)dm_void;
635 char help[] = "-h";
636 u32 var1[7] = {0};
637 u8 set_pwr_th1, set_pwr_th2, set_pwr_th3;
638 u8 i = 0;
639 #ifdef BB_RAM_SUPPORT
640 s8 pwr_ofst_tmp = 0x0;
641 #endif
642
643 if ((strcmp(input[1], help) == 0)) {
644 PDM_SNPF(out_len, used, output + used, out_len - used,
645 "Set DTP threhosld: {1} {Lv1_th} {Lv2_th} {Lv3_th}\n");
646 #ifdef BB_RAM_SUPPORT
647 PDM_SNPF(out_len, used, output + used, out_len - used,
648 "Set pwr_tx_offset: {2} {0:reg 1:macid} {en} {offset 0/1} {0:-, 1:+} {Pwr Offset} {macid}\n");
649 PDM_SNPF(out_len, used, output + used, out_len - used,
650 "Read pwr_tx_offset : {3} {0:reg 1:macid} {macid(0~63), 255:all}\n");
651 PDM_SNPF(out_len, used, output + used, out_len - used,
652 "Reset all ram pwr_tx_offset : {4}\n");
653 #endif
654 } else {
655 for (i = 0; i < 7; i++) {
656 if (input[i + 1])
657 PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL,
658 &var1[i]);
659 }
660 switch (var1[0]) {
661 case 1:
662 for (i = 0; i < 3; i++) {
663 if (var1[i] == 0 || var1[i] > 100)
664 dm->set_pwr_th[i] = 0xff;
665 else
666 dm->set_pwr_th[i] = (u8)var1[1 + i];
667 }
668
669 PDM_SNPF(out_len, used, output + used, out_len - used,
670 "DTP_TH[0:2] = {%d, %d, %d}\n",
671 dm->set_pwr_th[0], dm->set_pwr_th[1],
672 dm->set_pwr_th[2]);
673 break;
674 #ifdef BB_RAM_SUPPORT
675 case 2:
676 if ((boolean)var1[4])
677 pwr_ofst_tmp = (s8)var1[5];
678 else
679 pwr_ofst_tmp = 0x0 - (s8)var1[5];
680
681 if ((boolean)var1[1])
682 phydm_wt_ram_pwr(dm, (u8)var1[6],
683 (boolean)var1[3],
684 (boolean)var1[2],
685 pwr_ofst_tmp);
686 else
687 phydm_wt_reg_pwr(dm, (boolean)var1[3],
688 (boolean)var1[2],
689 pwr_ofst_tmp);
690 break;
691 case 3:
692 if ((boolean)var1[1]) {
693 if ((u8)var1[2] == 0xff)
694 for (i = 0; i < 64; i++)
695 phydm_rd_ram_pwr(dm, i, &used,
696 output,
697 &out_len);
698 else
699 phydm_rd_ram_pwr(dm, (u8)var1[2], &used,
700 output, &out_len);
701 } else {
702 phydm_rd_reg_pwr(dm, &used, output, &out_len);
703 }
704 break;
705 case 4:
706 phydm_rst_ram_pwr(dm);
707 break;
708 #endif
709 }
710 }
711 *_used = used;
712 *_out_len = out_len;
713 }
714
phydm_dynamic_tx_power(void * dm_void)715 void phydm_dynamic_tx_power(void *dm_void)
716 {
717 struct dm_struct *dm = (struct dm_struct *)dm_void;
718 struct cmn_sta_info *sta = NULL;
719 u8 i = 0;
720
721 u8 rssi_min = dm->rssi_min;
722 u8 rssi_tmp = 0;
723
724 if (!(dm->support_ability & ODM_BB_DYNAMIC_TXPWR))
725 return;
726
727 if (!(dm->support_ic_type & ODM_IC_JGR3_SERIES)) {
728 PHYDM_DBG(dm, DBG_DYN_TXPWR,
729 "[%s] RSSI_min = %d, Noisy_dec = %d\n", __func__,
730 rssi_min, dm->noisy_decision);
731 phydm_noisy_enhance_hp_th(dm, dm->noisy_decision);
732 /* Response Power */
733 dm->dynamic_tx_high_power_lvl = phydm_pwr_lvl_check(dm,
734 rssi_min,
735 dm->last_dtp_lvl);
736 phydm_dynamic_response_power(dm);
737 }
738 /* Per STA Tx power */
739 phydm_dtp_per_sta(dm);
740 }
741 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
742
phydm_dynamic_tx_power_init_win(void * dm_void)743 void phydm_dynamic_tx_power_init_win(void *dm_void)
744 {
745 struct dm_struct *dm = (struct dm_struct *)dm_void;
746 void *adapter = dm->adapter;
747 PMGNT_INFO mgnt_info = &((PADAPTER)adapter)->MgntInfo;
748 HAL_DATA_TYPE *hal_data = GET_HAL_DATA((PADAPTER)adapter);
749
750 mgnt_info->bDynamicTxPowerEnable = false;
751 #if DEV_BUS_TYPE == RT_USB_INTERFACE
752 if (RT_GetInterfaceSelection((PADAPTER)adapter) ==
753 INTF_SEL1_USB_High_Power) {
754 mgnt_info->bDynamicTxPowerEnable = true;
755 }
756 #endif
757
758 hal_data->LastDTPLvl = tx_high_pwr_level_normal;
759 hal_data->DynamicTxHighPowerLvl = tx_high_pwr_level_normal;
760
761 PHYDM_DBG(dm, DBG_DYN_TXPWR, "[%s] DTP=%d\n", __func__,
762 mgnt_info->bDynamicTxPowerEnable);
763 }
764
phydm_dynamic_tx_power_win(void * dm_void)765 void phydm_dynamic_tx_power_win(void *dm_void)
766 {
767 struct dm_struct *dm = (struct dm_struct *)dm_void;
768
769 if (!(dm->support_ability & ODM_BB_DYNAMIC_TXPWR))
770 return;
771
772 #if (RTL8814A_SUPPORT)
773 if (dm->support_ic_type == ODM_RTL8814A)
774 odm_dynamic_tx_power_8814a(dm);
775 #endif
776
777 #if (RTL8821A_SUPPORT)
778 if (dm->support_ic_type & ODM_RTL8821) {
779 void *adapter = dm->adapter;
780 PMGNT_INFO mgnt_info = GetDefaultMgntInfo((PADAPTER)adapter);
781
782 if (mgnt_info->RegRspPwr == 1) {
783 if (dm->rssi_min > 60) {
784 /*Resp TXAGC offset = -3dB*/
785 odm_set_mac_reg(dm, R_0x6d8, 0x1C0000, 1);
786 } else if (dm->rssi_min < 55) {
787 /*Resp TXAGC offset = 0dB*/
788 odm_set_mac_reg(dm, R_0x6d8, 0x1C0000, 0);
789 }
790 }
791 }
792 #endif
793 }
794 #endif /*@#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)*/
795 #endif /* @#ifdef CONFIG_DYNAMIC_TX_TWR */
796