1 /****************************************************************************** 2 * 3 * Copyright(c) 2007 - 2017 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * The full GNU General Public License is included in this distribution in the 15 * file called LICENSE. 16 * 17 * Contact Information: 18 * wlanfae <wlanfae@realtek.com> 19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 20 * Hsinchu 300, Taiwan. 21 * 22 * Larry Finger <Larry.Finger@lwfinger.net> 23 * 24 *****************************************************************************/ 25 26 #ifndef __PHYDMDYNAMICTXPOWER_H__ 27 #define __PHYDMDYNAMICTXPOWER_H__ 28 29 #ifdef CONFIG_DYNAMIC_TX_TWR 30 /* @============================================================ 31 * Definition 32 * ============================================================ 33 */ 34 35 /* 2020.6.23, Let gain_idx be initialized to 0 for linux compile warning*/ 36 #define DYNAMIC_TXPWR_VERSION "2.1" 37 38 #define DTP_POWER_LEVEL_SIZE 3 39 40 #if (DM_ODM_SUPPORT_TYPE == ODM_AP) 41 #define TX_POWER_NEAR_FIELD_THRESH_LVL2 74 42 #define TX_POWER_NEAR_FIELD_THRESH_LVL1 60 43 #define TX_POWER_NEAR_FIELD_THRESH_AP 0x3F 44 #elif (DM_ODM_SUPPORT_TYPE == ODM_WIN) 45 #define TX_POWER_NEAR_FIELD_THRESH_LVL2 74 46 #define TX_POWER_NEAR_FIELD_THRESH_LVL1 67 47 #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) 48 #define TX_POWER_NEAR_FIELD_THRESH_LVL2 74 49 #define TX_POWER_NEAR_FIELD_THRESH_LVL1 60 50 #endif 51 52 #if (DM_ODM_SUPPORT_TYPE == ODM_AP) 53 #define TX_PWR_NEAR_FIELD_TH_JGR3_LVL3 80 54 #define TX_PWR_NEAR_FIELD_TH_JGR3_LVL2 63 55 #define TX_PWR_NEAR_FIELD_TH_JGR3_LVL1 55 56 #elif (DM_ODM_SUPPORT_TYPE == ODM_WIN) 57 #define TX_PWR_NEAR_FIELD_TH_JGR3_LVL3 90 58 #define TX_PWR_NEAR_FIELD_TH_JGR3_LVL2 85 59 #define TX_PWR_NEAR_FIELD_TH_JGR3_LVL1 80 60 #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) 61 #define TX_PWR_NEAR_FIELD_TH_JGR3_LVL3 90 62 #define TX_PWR_NEAR_FIELD_TH_JGR3_LVL2 85 63 #define TX_PWR_NEAR_FIELD_TH_JGR3_LVL1 80 64 #endif 65 66 #define tx_high_pwr_level_normal 0 67 #define tx_high_pwr_level_level1 1 68 #define tx_high_pwr_level_level2 2 69 #define tx_high_pwr_level_level3 3 70 #define tx_high_pwr_level_unchange 4 71 #define DTP_FLOOR_UP_GAP 3 72 73 /* @============================================================ 74 * enumrate 75 * ============================================================ 76 */ 77 enum phydm_dtp_power_offset { 78 PHYDM_OFFSET_ZERO = 0, 79 PHYDM_OFFSET_MINUS_3DB = 1, 80 PHYDM_OFFSET_MINUS_7DB = 2, 81 PHYDM_OFFSET_MINUS_11DB = 3, 82 PHYDM_OFFSET_ADD_3DB = 4, 83 PHYDM_OFFSET_ADD_6DB = 5 84 }; 85 86 enum phydm_dtp_power_offset_2nd { 87 PHYDM_2ND_OFFSET_ZERO = 0, 88 PHYDM_2ND_OFFSET_MINUS_3DB = 1, 89 PHYDM_2ND_OFFSET_MINUS_7DB = 2, 90 PHYDM_2ND_OFFSET_MINUS_11DB = 3 91 }; 92 93 enum phydm_dtp_power_offset_bbram { 94 /*@ HW min use 1dB*/ 95 PHYDM_BBRAM_OFFSET_ZERO = 0, 96 PHYDM_BBRAM_OFFSET_MINUS_3DB = -3, 97 PHYDM_BBRAM_OFFSET_MINUS_7DB = -7, 98 PHYDM_BBRAM_OFFSET_MINUS_11DB = -11 99 }; 100 101 enum phydm_dtp_power_pkt_type { 102 RAM_PWR_OFST0 = 0, 103 RAM_PWR_OFST1 = 1, 104 REG_PWR_OFST0 = 2, 105 REG_PWR_OFST1 = 3 106 }; 107 108 /* @============================================================ 109 * structure 110 * ============================================================ 111 */ 112 113 /* @============================================================ 114 * Function Prototype 115 * ============================================================ 116 */ 117 118 extern void 119 odm_set_dyntxpwr(void *dm_void, u8 *desc, u8 mac_id); 120 121 void phydm_dynamic_tx_power(void *dm_void); 122 123 void phydm_dynamic_tx_power_init(void *dm_void); 124 125 void phydm_dtp_debug(void *dm_void, char input[][16], u32 *_used, char *output, 126 u32 *_out_len); 127 128 void phydm_rd_reg_pwr(void *dm_void, u32 *_used, char *output, u32 *_out_len); 129 130 void phydm_wt_reg_pwr(void *dm_void, boolean is_ofst1, boolean pwr_ofst_en, 131 s8 pwr_ofst); 132 133 void phydm_wt_ram_pwr(void *dm_void, u8 macid, boolean is_ofst1, 134 boolean pwr_ofst_en, s8 pwr_ofst); 135 136 137 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) 138 void odm_dynamic_tx_power_win(void *dm_void); 139 #endif 140 141 #endif 142 #endif 143