1 /****************************************************************************** 2 * 3 * Copyright(c) 2007 - 2017 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * The full GNU General Public License is included in this distribution in the 15 * file called LICENSE. 16 * 17 * Contact Information: 18 * wlanfae <wlanfae@realtek.com> 19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 20 * Hsinchu 300, Taiwan. 21 * 22 * Larry Finger <Larry.Finger@lwfinger.net> 23 * 24 *****************************************************************************/ 25 /************************************************************* 26 * File Name: odm_reg.h 27 * 28 * Description: 29 * 30 * This file is for general register definition. 31 * 32 * 33 ************************************************************/ 34 #ifndef __HAL_ODM_REG_H__ 35 #define __HAL_ODM_REG_H__ 36 37 /*@ 38 * Register Definition 39 * 40 */ 41 42 /* @MAC REG */ 43 #define ODM_BB_RESET 0x002 44 #define ODM_DUMMY 0x4fe 45 #define RF_T_METER_OLD 0x24 46 #define RF_T_METER_NEW 0x42 47 48 #define ODM_EDCA_VO_PARAM 0x500 49 #define ODM_EDCA_VI_PARAM 0x504 50 #define ODM_EDCA_BE_PARAM 0x508 51 #define ODM_EDCA_BK_PARAM 0x50C 52 #define ODM_TXPAUSE 0x522 53 54 /* @LTE_COEX */ 55 #define REG_LTECOEX_CTRL 0x07C0 56 #define REG_LTECOEX_WRITE_DATA 0x07C4 57 #define REG_LTECOEX_READ_DATA 0x07C8 58 #define REG_LTECOEX_PATH_CONTROL 0x70 59 60 /* @BB REG */ 61 #define ODM_FPGA_PHY0_PAGE8 0x800 62 #define ODM_PSD_SETTING 0x808 63 #define ODM_AFE_SETTING 0x818 64 #define ODM_TXAGC_B_6_18 0x830 65 #define ODM_TXAGC_B_24_54 0x834 66 #define ODM_TXAGC_B_MCS32_5 0x838 67 #define ODM_TXAGC_B_MCS0_MCS3 0x83c 68 #define ODM_TXAGC_B_MCS4_MCS7 0x848 69 #define ODM_TXAGC_B_MCS8_MCS11 0x84c 70 #define ODM_ANALOG_REGISTER 0x85c 71 #define ODM_RF_INTERFACE_OUTPUT 0x860 72 #define ODM_TXAGC_B_MCS12_MCS15 0x868 73 #define ODM_TXAGC_B_11_A_2_11 0x86c 74 #define ODM_AD_DA_LSB_MASK 0x874 75 #define ODM_ENABLE_3_WIRE 0x88c 76 #define ODM_PSD_REPORT 0x8b4 77 #define ODM_R_ANT_SELECT 0x90c 78 #define ODM_CCK_ANT_SELECT 0xa07 79 #define ODM_CCK_PD_THRESH 0xa0a 80 #define ODM_CCK_RF_REG1 0xa11 81 #define ODM_CCK_MATCH_FILTER 0xa20 82 #define ODM_CCK_RAKE_MAC 0xa2e 83 #define ODM_CCK_CNT_RESET 0xa2d 84 #define ODM_CCK_TX_DIVERSITY 0xa2f 85 #define ODM_CCK_FA_CNT_MSB 0xa5b 86 #define ODM_CCK_FA_CNT_LSB 0xa5c 87 #define ODM_CCK_NEW_FUNCTION 0xa75 88 #define ODM_OFDM_PHY0_PAGE_C 0xc00 89 #define ODM_OFDM_RX_ANT 0xc04 90 #define ODM_R_A_RXIQI 0xc14 91 #define ODM_R_A_AGC_CORE1 0xc50 92 #define ODM_R_A_AGC_CORE2 0xc54 93 #define ODM_R_B_AGC_CORE1 0xc58 94 #define ODM_R_AGC_PAR 0xc70 95 #define ODM_R_HTSTF_AGC_PAR 0xc7c 96 #define ODM_TX_PWR_TRAINING_A 0xc90 97 #define ODM_TX_PWR_TRAINING_B 0xc98 98 #define ODM_OFDM_FA_CNT1 0xcf0 99 #define ODM_OFDM_PHY0_PAGE_D 0xd00 100 #define ODM_OFDM_FA_CNT2 0xda0 101 #define ODM_OFDM_FA_CNT3 0xda4 102 #define ODM_OFDM_FA_CNT4 0xda8 103 #define ODM_TXAGC_A_6_18 0xe00 104 #define ODM_TXAGC_A_24_54 0xe04 105 #define ODM_TXAGC_A_1_MCS32 0xe08 106 #define ODM_TXAGC_A_MCS0_MCS3 0xe10 107 #define ODM_TXAGC_A_MCS4_MCS7 0xe14 108 #define ODM_TXAGC_A_MCS8_MCS11 0xe18 109 #define ODM_TXAGC_A_MCS12_MCS15 0xe1c 110 111 /* RF REG */ 112 #define ODM_GAIN_SETTING 0x00 113 #define ODM_CHANNEL 0x18 114 #define ODM_RF_T_METER 0x24 115 #define ODM_RF_T_METER_92D 0x42 116 #define ODM_RF_T_METER_88E 0x42 117 #define ODM_RF_T_METER_92E 0x42 118 #define ODM_RF_T_METER_8812 0x42 119 #define REG_RF_TX_GAIN_OFFSET 0x55 120 121 /* @ant Detect Reg */ 122 #define ODM_DPDT 0x300 123 124 /* PSD Init */ 125 #define ODM_PSDREG 0x808 126 127 /* @92D path Div */ 128 #define PATHDIV_REG 0xB30 129 #define PATHDIV_TRI 0xBA0 130 131 132 /*@ 133 * Bitmap Definition 134 */ 135 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) 136 /* TX AGC */ 137 #define REG_TX_AGC_A_CCK_11_CCK_1_JAGUAR 0xc20 138 #define REG_TX_AGC_A_OFDM18_OFDM6_JAGUAR 0xc24 139 #define REG_TX_AGC_A_OFDM54_OFDM24_JAGUAR 0xc28 140 #define REG_TX_AGC_A_MCS3_MCS0_JAGUAR 0xc2c 141 #define REG_TX_AGC_A_MCS7_MCS4_JAGUAR 0xc30 142 #define REG_TX_AGC_A_MCS11_MCS8_JAGUAR 0xc34 143 #define REG_TX_AGC_A_MCS15_MCS12_JAGUAR 0xc38 144 #define REG_TX_AGC_A_NSS1_INDEX3_NSS1_INDEX0_JAGUAR 0xc3c 145 #define REG_TX_AGC_A_NSS1_INDEX7_NSS1_INDEX4_JAGUAR 0xc40 146 #define REG_TX_AGC_A_NSS2_INDEX1_NSS1_INDEX8_JAGUAR 0xc44 147 #define REG_TX_AGC_A_NSS2_INDEX5_NSS2_INDEX2_JAGUAR 0xc48 148 #define REG_TX_AGC_A_NSS2_INDEX9_NSS2_INDEX6_JAGUAR 0xc4c 149 #if defined(CONFIG_WLAN_HAL_8814AE) 150 #define REG_TX_AGC_A_MCS19_MCS16_JAGUAR 0xcd8 151 #define REG_TX_AGC_A_MCS23_MCS20_JAGUAR 0xcdc 152 #define REG_TX_AGC_A_NSS3_INDEX3_NSS3_INDEX0_JAGUAR 0xce0 153 #define REG_TX_AGC_A_NSS3_INDEX7_NSS3_INDEX4_JAGUAR 0xce4 154 #define REG_TX_AGC_A_NSS3_INDEX9_NSS3_INDEX8_JAGUAR 0xce8 155 #endif 156 #define REG_TX_AGC_B_CCK_11_CCK_1_JAGUAR 0xe20 157 #define REG_TX_AGC_B_OFDM18_OFDM6_JAGUAR 0xe24 158 #define REG_TX_AGC_B_OFDM54_OFDM24_JAGUAR 0xe28 159 #define REG_TX_AGC_B_MCS3_MCS0_JAGUAR 0xe2c 160 #define REG_TX_AGC_B_MCS7_MCS4_JAGUAR 0xe30 161 #define REG_TX_AGC_B_MCS11_MCS8_JAGUAR 0xe34 162 #define REG_TX_AGC_B_MCS15_MCS12_JAGUAR 0xe38 163 #define REG_TX_AGC_B_NSS1_INDEX3_NSS1_INDEX0_JAGUAR 0xe3c 164 #define REG_TX_AGC_B_NSS1_INDEX7_NSS1_INDEX4_JAGUAR 0xe40 165 #define REG_TX_AGC_B_NSS2_INDEX1_NSS1_INDEX8_JAGUAR 0xe44 166 #define REG_TX_AGC_B_NSS2_INDEX5_NSS2_INDEX2_JAGUAR 0xe48 167 #define REG_TX_AGC_B_NSS2_INDEX9_NSS2_INDEX6_JAGUAR 0xe4c 168 #if defined(CONFIG_WLAN_HAL_8814AE) 169 #define REG_TX_AGC_B_MCS19_MCS16_JAGUAR 0xed8 170 #define REG_TX_AGC_B_MCS23_MCS20_JAGUAR 0xedc 171 #define REG_TX_AGC_B_NSS3_INDEX3_NSS3_INDEX0_JAGUAR 0xee0 172 #define REG_TX_AGC_B_NSS3_INDEX7_NSS3_INDEX4_JAGUAR 0xee4 173 #define REG_TX_AGC_B_NSS3_INDEX9_NSS3_INDEX8_JAGUAR 0xee8 174 #define REG_TX_AGC_C_CCK_11_CCK_1_JAGUAR 0x1820 175 #define REG_TX_AGC_C_OFDM18_OFDM6_JAGUAR 0x1824 176 #define REG_TX_AGC_C_OFDM54_OFDM24_JAGUAR 0x1828 177 #define REG_TX_AGC_C_MCS3_MCS0_JAGUAR 0x182c 178 #define REG_TX_AGC_C_MCS7_MCS4_JAGUAR 0x1830 179 #define REG_TX_AGC_C_MCS11_MCS8_JAGUAR 0x1834 180 #define REG_TX_AGC_C_MCS15_MCS12_JAGUAR 0x1838 181 #define REG_TX_AGC_C_NSS1_INDEX3_NSS1_INDEX0_JAGUAR 0x183c 182 #define REG_TX_AGC_C_NSS1_INDEX7_NSS1_INDEX4_JAGUAR 0x1840 183 #define REG_TX_AGC_C_NSS2_INDEX1_NSS1_INDEX8_JAGUAR 0x1844 184 #define REG_TX_AGC_C_NSS2_INDEX5_NSS2_INDEX2_JAGUAR 0x1848 185 #define REG_TX_AGC_C_NSS2_INDEX9_NSS2_INDEX6_JAGUAR 0x184c 186 #define REG_TX_AGC_C_MCS19_MCS16_JAGUAR 0x18d8 187 #define REG_TX_AGC_C_MCS23_MCS20_JAGUAR 0x18dc 188 #define REG_TX_AGC_C_NSS3_INDEX3_NSS3_INDEX0_JAGUAR 0x18e0 189 #define REG_TX_AGC_C_NSS3_INDEX7_NSS3_INDEX4_JAGUAR 0x18e4 190 #define REG_TX_AGC_C_NSS3_INDEX9_NSS3_INDEX8_JAGUAR 0x18e8 191 #define REG_TX_AGC_D_CCK_11_CCK_1_JAGUAR 0x1a20 192 #define REG_TX_AGC_D_OFDM18_OFDM6_JAGUAR 0x1a24 193 #define REG_TX_AGC_D_OFDM54_OFDM24_JAGUAR 0x1a28 194 #define REG_TX_AGC_D_MCS3_MCS0_JAGUAR 0x1a2c 195 #define REG_TX_AGC_D_MCS7_MCS4_JAGUAR 0x1a30 196 #define REG_TX_AGC_D_MCS11_MCS8_JAGUAR 0x1a34 197 #define REG_TX_AGC_D_MCS15_MCS12_JAGUAR 0x1a38 198 #define REG_TX_AGC_D_NSS1_INDEX3_NSS1_INDEX0_JAGUAR 0x1a3c 199 #define REG_TX_AGC_D_NSS1_INDEX7_NSS1_INDEX4_JAGUAR 0x1a40 200 #define REG_TX_AGC_D_NSS2_INDEX1_NSS1_INDEX8_JAGUAR 0x1a44 201 #define REG_TX_AGC_D_NSS2_INDEX5_NSS2_INDEX2_JAGUAR 0x1a48 202 #define REG_TX_AGC_D_NSS2_INDEX9_NSS2_INDEX6_JAGUAR 0x1a4c 203 #define REG_TX_AGC_D_MCS19_MCS16_JAGUAR 0x1ad8 204 #define REG_TX_AGC_D_MCS23_MCS20_JAGUAR 0x1adc 205 #define REG_TX_AGC_D_NSS3_INDEX3_NSS3_INDEX0_JAGUAR 0x1ae0 206 #define REG_TX_AGC_D_NSS3_INDEX7_NSS3_INDEX4_JAGUAR 0x1ae4 207 #define REG_TX_AGC_D_NSS3_INDEX9_NSS3_INDEX8_JAGUAR 0x1ae8 208 #endif 209 210 #define is_tx_agc_byte0_jaguar 0xff 211 #define is_tx_agc_byte1_jaguar 0xff00 212 #define is_tx_agc_byte2_jaguar 0xff0000 213 #define is_tx_agc_byte3_jaguar 0xff000000 214 #if defined(CONFIG_WLAN_HAL_8198F) || defined(CONFIG_WLAN_HAL_8822CE) ||\ 215 defined(CONFIG_WLAN_HAL_8814BE) || defined(CONFIG_WLAN_HAL_8812FE) ||\ 216 defined(CONFIG_WLAN_HAL_8197G) 217 #define REG_TX_AGC_CCK_11_CCK_1_JAGUAR3 0x3a00 218 #define REG_TX_AGC_OFDM_18_CCK_6_JAGUAR3 0x3a04 219 #define REG_TX_AGC_OFDM_54_CCK_24_JAGUAR3 0x3a08 220 #define REG_TX_AGC_MCS3_0_JAGUAR3 0x3a0c 221 #define REG_TX_AGC_MCS7_4_JAGUAR3 0x3a10 222 #define REG_TX_AGC_MCS11_8_JAGUAR3 0x3a14 223 #define REG_TX_AGC_MCS15_12_JAGUAR3 0x3a18 224 #define REG_TX_AGC_MCS19_16_JAGUAR3 0x3a1c 225 #define REG_TX_AGC_MCS23_20_JAGUAR3 0x3a20 226 #define REG_TX_AGC_MCS27_24_JAGUAR3 0x3a24 227 #define REG_TX_AGC_MCS31_28_JAGUAR3 0x3a28 228 #define REG_TX_AGC_VHT_Nss1_MCS3_0_JAGUAR3 0x3a2c 229 #define REG_TX_AGC_VHT_Nss1_MCS7_4_JAGUAR3 0x3a30 230 #define REG_TX_AGC_VHT_NSS2_MCS1_NSS1_MCS8_JAGUAR3 0x3a34 231 #define REG_TX_AGC_VHT_Nss2_MCS5_2_JAGUAR3 0x3a38 232 #define REG_TX_AGC_VHT_Nss2_MCS9_6_JAGUAR3 0x3a3c 233 #define REG_TX_AGC_VHT_Nss3_MCS3_0_JAGUAR3 0x3a40 234 #define REG_TX_AGC_VHT_Nss3_MCS7_4_JAGUAR3 0x3a44 235 #define REG_TX_AGC_VHT_Nss4_MCS1_Nss3_MCS8_JAGUAR3 0x3a48 236 #define REG_TX_AGC_VHT_Nss4_MCS5_2_JAGUAR3 0x3a4c 237 #define REG_TX_AGC_VHT_Nss4_MCS9_6_JAGUAR3 0x3a50 238 #endif 239 #endif 240 241 #define BIT_FA_RESET BIT(0) 242 243 #endif 244