1 /****************************************************************************** 2 * 3 * Copyright(c) 2007 - 2017 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * The full GNU General Public License is included in this distribution in the 15 * file called LICENSE. 16 * 17 * Contact Information: 18 * wlanfae <wlanfae@realtek.com> 19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 20 * Hsinchu 300, Taiwan. 21 * 22 * Larry Finger <Larry.Finger@lwfinger.net> 23 * 24 *****************************************************************************/ 25 26 #ifndef __ODM_REGDEFINE11AC_H__ 27 #define __ODM_REGDEFINE11AC_H__ 28 29 /* @2 RF REG LIST */ 30 31 32 33 /* @2 BB REG LIST */ 34 /* PAGE 8 */ 35 #define ODM_REG_CCK_RPT_FORMAT_11AC 0x804 36 #define ODM_REG_BB_RX_PATH_11AC 0x808 37 #define ODM_REG_BB_TX_PATH_11AC 0x80c 38 #define ODM_REG_BB_ATC_11AC 0x860 39 #define ODM_REG_EDCCA_POWER_CAL 0x8dc 40 #define ODM_REG_DBG_RPT_11AC 0x8fc 41 /* PAGE 9 */ 42 #define ODM_REG_EDCCA_DOWN_OPT 0x900 43 #define ODM_REG_ACBB_EDCCA_ENHANCE 0x944 44 #define odm_adc_trigger_jaguar2 0x95C /*@ADC sample mode*/ 45 #define ODM_REG_OFDM_FA_RST_11AC 0x9A4 46 #define ODM_REG_CCX_PERIOD_11AC 0x990 47 #define ODM_REG_NHM_TH9_TH10_11AC 0x994 48 #define ODM_REG_CLM_11AC 0x994 49 #define ODM_REG_NHM_TH3_TO_TH0_11AC 0x998 50 #define ODM_REG_NHM_TH7_TO_TH4_11AC 0x99c 51 #define ODM_REG_NHM_TH8_11AC 0x9a0 52 #define ODM_REG_NHM_9E8_11AC 0x9e8 53 #define ODM_REG_CSI_CONTENT_VALUE 0x9b4 54 /* PAGE A */ 55 #define ODM_REG_CCK_CCA_11AC 0xA0A 56 #define ODM_REG_CCK_FA_RST_11AC 0xA2C 57 #define ODM_REG_CCK_FA_11AC 0xA5C 58 /* PAGE B */ 59 #define ODM_REG_RST_RPT_11AC 0xB58 60 /* PAGE C */ 61 #define ODM_REG_TRMUX_11AC 0xC08 62 #define ODM_REG_IGI_A_11AC 0xC50 63 /* PAGE E */ 64 #define ODM_REG_IGI_B_11AC 0xE50 65 #define ODM_REG_ANT_11AC_B 0xE08 66 /* PAGE F */ 67 #define ODM_REG_CCK_CRC32_CNT_11AC 0xF04 68 #define ODM_REG_CCK_CCA_CNT_11AC 0xF08 69 #define ODM_REG_VHT_CRC32_CNT_11AC 0xF0c 70 #define ODM_REG_HT_CRC32_CNT_11AC 0xF10 71 #define ODM_REG_OFDM_CRC32_CNT_11AC 0xF14 72 #define ODM_REG_OFDM_FA_11AC 0xF48 73 #define ODM_REG_OFDM_FA_TYPE1_11AC 0xFCC 74 #define ODM_REG_OFDM_FA_TYPE2_11AC 0xFD0 75 #define ODM_REG_OFDM_FA_TYPE3_11AC 0xFBC 76 #define ODM_REG_OFDM_FA_TYPE4_11AC 0xFC0 77 #define ODM_REG_OFDM_FA_TYPE5_11AC 0xFC4 78 #define ODM_REG_OFDM_FA_TYPE6_11AC 0xFC8 79 #define ODM_REG_RPT_11AC 0xfa0 80 #define ODM_REG_CLM_RESULT_11AC 0xfa4 81 #define ODM_REG_NHM_CNT_11AC 0xfa8 82 #define ODM_REG_NHM_DUR_READY_11AC 0xfb4 83 84 #define ODM_REG_NHM_CNT7_TO_CNT4_11AC 0xfac 85 #define ODM_REG_NHM_CNT11_TO_CNT8_11AC 0xfb0 86 /* PAGE 18 */ 87 #define ODM_REG_IGI_C_11AC 0x1850 88 /* PAGE 1A */ 89 #define ODM_REG_IGI_D_11AC 0x1A50 90 91 /* PAGE 1D */ 92 #define ODM_REG_IGI_11AC3 0x1D70 93 94 /* @2 MAC REG LIST */ 95 #define ODM_REG_RESP_TX_11AC 0x6D8 96 97 98 99 /* @DIG Related */ 100 #define ODM_BIT_IGI_11AC 0x0000007F 101 #define ODM_BIT_IGI_B_11AC3 0x00007F00 102 #define ODM_BIT_IGI_C_11AC3 0x007F0000 103 #define ODM_BIT_IGI_D_11AC3 0x7F000000 104 #define ODM_BIT_CCK_RPT_FORMAT_11AC BIT(16) 105 #define ODM_BIT_BB_RX_PATH_11AC 0xF 106 #define ODM_BIT_BB_TX_PATH_11AC 0xF 107 #define ODM_BIT_BB_ATC_11AC BIT(14) 108 109 #endif 110