1 /****************************************************************************** 2 * 3 * Copyright(c) 2007 - 2017 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * The full GNU General Public License is included in this distribution in the 15 * file called LICENSE. 16 * 17 * Contact Information: 18 * wlanfae <wlanfae@realtek.com> 19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 20 * Hsinchu 300, Taiwan. 21 * 22 * Larry Finger <Larry.Finger@lwfinger.net> 23 * 24 *****************************************************************************/ 25 26 #ifndef __ODM_REGDEFINE11N_H__ 27 #define __ODM_REGDEFINE11N_H__ 28 29 /* @2 RF REG LIST */ 30 #define ODM_REG_RF_MODE_11N 0x00 31 #define ODM_REG_RF_0B_11N 0x0B 32 #define ODM_REG_CHNBW_11N 0x18 33 #define ODM_REG_T_METER_11N 0x24 34 #define ODM_REG_RF_25_11N 0x25 35 #define ODM_REG_RF_26_11N 0x26 36 #define ODM_REG_RF_27_11N 0x27 37 #define ODM_REG_RF_2B_11N 0x2B 38 #define ODM_REG_RF_2C_11N 0x2C 39 #define ODM_REG_RXRF_A3_11N 0x3C 40 #define ODM_REG_T_METER_92D_11N 0x42 41 #define ODM_REG_T_METER_88E_11N 0x42 42 #define ODM_REF_RF_DF_11N 0xDF 43 44 45 46 /* @2 BB REG LIST 47 * PAGE 8 48 */ 49 #define ODM_REG_BB_CTRL_11N 0x800 50 #define ODM_REG_RF_PIN_11N 0x804 51 #define ODM_REG_PSD_CTRL_11N 0x808 52 #define ODM_REG_TX_ANT_CTRL_11N 0x80C 53 #define ODM_REG_BB_PWR_SAV5_11N 0x818 54 #define ODM_REG_CCK_RPT_FORMAT_11N 0x824 55 #define ODM_REG_CCK_RPT_FORMAT_11N_B 0x82C 56 #define ODM_REG_RX_DEFAULT_A_11N 0x858 57 #define ODM_REG_RX_DEFAULT_B_11N 0x85A 58 #define ODM_REG_BB_PWR_SAV3_11N 0x85C 59 #define ODM_REG_ANTSEL_CTRL_11N 0x860 60 #define ODM_REG_RX_ANT_CTRL_11N 0x864 61 #define ODM_REG_PIN_CTRL_11N 0x870 62 #define ODM_REG_BB_PWR_SAV1_11N 0x874 63 #define ODM_REG_ANTSEL_PATH_11N 0x878 64 #define ODM_REG_BB_3WIRE_11N 0x88C 65 #define ODM_REG_SC_CNT_11N 0x8C4 66 #define ODM_REG_PSD_DATA_11N 0x8B4 67 #define ODM_REG_CCX_PERIOD_11N 0x894 68 #define ODM_REG_NHM_TH9_TH10_11N 0x890 69 #define ODM_REG_CLM_11N 0x890 70 #define ODM_REG_NHM_TH3_TO_TH0_11N 0x898 71 #define ODM_REG_NHM_TH7_TO_TH4_11N 0x89c 72 #define ODM_REG_NHM_TH8_11N 0xe28 73 #define ODM_REG_CLM_READY_11N 0x8b4 74 #define ODM_REG_CLM_RESULT_11N 0x8d0 75 #define ODM_REG_NHM_CNT_11N 0x8d8 76 77 /* @For struct acs_info, Jeffery, 2014-12-26 */ 78 #define ODM_REG_NHM_CNT7_TO_CNT4_11N 0x8dc 79 #define ODM_REG_NHM_CNT9_TO_CNT8_11N 0x8d0 80 #define ODM_REG_NHM_CNT10_TO_CNT11_11N 0x8d4 81 82 /* PAGE 9 */ 83 #define ODM_REG_BB_CTRL_PAGE9_11N 0x900 84 #define ODM_REG_DBG_RPT_11N 0x908 85 #define ODM_REG_BB_TX_PATH_11N 0x90c 86 #define ODM_REG_ANT_MAPPING1_11N 0x914 87 #define ODM_REG_ANT_MAPPING2_11N 0x918 88 #define ODM_REG_EDCCA_DOWN_OPT_11N 0x948 89 #define ODM_REG_RX_DFIR_MOD_97F 0x948 90 #define ODM_REG_SOML_97F 0x998 91 92 /* PAGE A */ 93 #define ODM_REG_CCK_ANTDIV_PARA1_11N 0xA00 94 #define ODM_REG_CCK_ANT_SEL_11N 0xA04 95 #define ODM_REG_CCK_CCA_11N 0xA0A 96 #define ODM_REG_CCK_ANTDIV_PARA2_11N 0xA0C 97 #define ODM_REG_CCK_ANTDIV_PARA3_11N 0xA10 98 #define ODM_REG_CCK_ANTDIV_PARA4_11N 0xA14 99 #define ODM_REG_CCK_FILTER_PARA1_11N 0xA22 100 #define ODM_REG_CCK_FILTER_PARA2_11N 0xA23 101 #define ODM_REG_CCK_FILTER_PARA3_11N 0xA24 102 #define ODM_REG_CCK_FILTER_PARA4_11N 0xA25 103 #define ODM_REG_CCK_FILTER_PARA5_11N 0xA26 104 #define ODM_REG_CCK_FILTER_PARA6_11N 0xA27 105 #define ODM_REG_CCK_FILTER_PARA7_11N 0xA28 106 #define ODM_REG_CCK_FILTER_PARA8_11N 0xA29 107 #define ODM_REG_CCK_FA_RST_11N 0xA2C 108 #define ODM_REG_CCK_FA_MSB_11N 0xA58 109 #define ODM_REG_CCK_FA_LSB_11N 0xA5C 110 #define ODM_REG_CCK_CCA_CNT_11N 0xA60 111 #define ODM_REG_BB_PWR_SAV4_11N 0xA74 112 /* PAGE B */ 113 #define ODM_REG_LNA_SWITCH_11N 0xB2C 114 #define ODM_REG_PATH_SWITCH_11N 0xB30 115 #define ODM_REG_RSSI_CTRL_11N 0xB38 116 #define ODM_REG_CONFIG_ANTA_11N 0xB68 117 #define ODM_REG_RSSI_BT_11N 0xB9C 118 #define ODM_REG_RXCK_RFMOD 0xBB0 119 #define ODM_REG_EDCCA_DCNF_97F 0xBC0 120 121 /* PAGE C */ 122 #define ODM_REG_OFDM_FA_HOLDC_11N 0xC00 123 #define ODM_REG_BB_RX_PATH_11N 0xC04 124 #define ODM_REG_TRMUX_11N 0xC08 125 #define ODM_REG_OFDM_FA_RSTC_11N 0xC0C 126 #define ODM_REG_DOWNSAM_FACTOR_11N 0xC10 127 #define ODM_REG_RXIQI_MATRIX_11N 0xC14 128 #define ODM_REG_TXIQK_MATRIX_LSB1_11N 0xC4C 129 #define ODM_REG_IGI_A_11N 0xC50 130 #define ODM_REG_ANTDIV_PARA2_11N 0xC54 131 #define ODM_REG_IGI_B_11N 0xC58 132 #define ODM_REG_ANTDIV_PARA3_11N 0xC5C 133 #define ODM_REG_L1SBD_PD_CH_11N 0XC6C 134 #define ODM_REG_BB_PWR_SAV2_11N 0xC70 135 #define ODM_REG_BB_AGC_SET_2_11N 0xc74 136 #define ODM_REG_RX_OFF_11N 0xC7C 137 #define ODM_REG_TXIQK_MATRIXA_11N 0xC80 138 #define ODM_REG_TXIQK_MATRIXB_11N 0xC88 139 #define ODM_REG_TXIQK_MATRIXA_LSB2_11N 0xC94 140 #define ODM_REG_TXIQK_MATRIXB_LSB2_11N 0xC9C 141 #define ODM_REG_RXIQK_MATRIX_LSB_11N 0xCA0 142 #define ODM_REG_ANTDIV_PARA1_11N 0xCA4 143 #define ODM_REG_SMALL_BANDWIDTH_11N 0xCE4 144 #define ODM_REG_OFDM_FA_TYPE1_11N 0xCF0 145 /* PAGE D */ 146 #define ODM_REG_OFDM_FA_RSTD_11N 0xD00 147 #define ODM_REG_BB_RX_ANT_11N 0xD04 148 #define ODM_REG_BB_ATC_11N 0xD2C 149 #define ODM_REG_OFDM_FA_TYPE2_11N 0xDA0 150 #define ODM_REG_OFDM_FA_TYPE3_11N 0xDA4 151 #define ODM_REG_OFDM_FA_TYPE4_11N 0xDA8 152 #define ODM_REG_RPT_11N 0xDF4 153 /* PAGE E */ 154 #define ODM_REG_TXAGC_A_6_18_11N 0xE00 155 #define ODM_REG_TXAGC_A_24_54_11N 0xE04 156 #define ODM_REG_TXAGC_A_1_MCS32_11N 0xE08 157 #define ODM_REG_TXAGC_A_MCS0_3_11N 0xE10 158 #define ODM_REG_TXAGC_A_MCS4_7_11N 0xE14 159 #define ODM_REG_TXAGC_A_MCS8_11_11N 0xE18 160 #define ODM_REG_TXAGC_A_MCS12_15_11N 0xE1C 161 #define ODM_REG_EDCCA_DCNF_11N 0xE24 162 #define ODM_REG_TAP_UPD_97F 0xE24 163 #define ODM_REG_FPGA0_IQK_11N 0xE28 164 #define ODM_REG_PAGE_B1_97F 0xE28 165 #define ODM_REG_TXIQK_TONE_A_11N 0xE30 166 #define ODM_REG_RXIQK_TONE_A_11N 0xE34 167 #define ODM_REG_TXIQK_PI_A_11N 0xE38 168 #define ODM_REG_RXIQK_PI_A_11N 0xE3C 169 #define ODM_REG_TXIQK_11N 0xE40 170 #define ODM_REG_RXIQK_11N 0xE44 171 #define ODM_REG_IQK_AGC_PTS_11N 0xE48 172 #define ODM_REG_IQK_AGC_RSP_11N 0xE4C 173 #define ODM_REG_BLUETOOTH_11N 0xE6C 174 #define ODM_REG_RX_WAIT_CCA_11N 0xE70 175 #define ODM_REG_TX_CCK_RFON_11N 0xE74 176 #define ODM_REG_TX_CCK_BBON_11N 0xE78 177 #define ODM_REG_OFDM_RFON_11N 0xE7C 178 #define ODM_REG_OFDM_BBON_11N 0xE80 179 #define ODM_REG_TX2RX_11N 0xE84 180 #define ODM_REG_TX2TX_11N 0xE88 181 #define ODM_REG_RX_CCK_11N 0xE8C 182 #define ODM_REG_RX_OFDM_11N 0xED0 183 #define ODM_REG_RX_WAIT_RIFS_11N 0xED4 184 #define ODM_REG_RX2RX_11N 0xED8 185 #define ODM_REG_STANDBY_11N 0xEDC 186 #define ODM_REG_SLEEP_11N 0xEE0 187 #define ODM_REG_PMPD_ANAEN_11N 0xEEC 188 /* PAGE F */ 189 #define ODM_REG_PAGE_F_RST_11N 0xF14 190 #define ODM_REG_IGI_C_11N 0xF84 191 #define ODM_REG_IGI_D_11N 0xF88 192 #define ODM_REG_CCK_CRC32_ERROR_CNT_11N 0xF84 193 #define ODM_REG_CCK_CRC32_OK_CNT_11N 0xF88 194 #define ODM_REG_HT_CRC32_CNT_11N 0xF90 195 #define ODM_REG_OFDM_CRC32_CNT_11N 0xF94 196 #define ODM_REG_HT_CRC32_CNT_11N_AGG 0xFB8 197 198 /* @2 MAC REG LIST */ 199 #define ODM_REG_BB_RST_11N 0x02 200 #define ODM_REG_ANTSEL_PIN_11N 0x4C 201 #define ODM_REG_EARLY_MODE_11N 0x4D0 202 #define ODM_REG_RSSI_MONITOR_11N 0x4FE 203 #define ODM_REG_EDCA_VO_11N 0x500 204 #define ODM_REG_EDCA_VI_11N 0x504 205 #define ODM_REG_EDCA_BE_11N 0x508 206 #define ODM_REG_EDCA_BK_11N 0x50C 207 #define ODM_REG_TXPAUSE_11N 0x522 208 #define ODM_REG_RESP_TX_11N 0x6D8 209 #define ODM_REG_ANT_TRAIN_PARA1_11N 0x7b0 210 #define ODM_REG_ANT_TRAIN_PARA2_11N 0x7b4 211 212 213 /* @DIG Related */ 214 #define ODM_BIT_IGI_11N 0x0000007F 215 #define ODM_BIT_CCK_RPT_FORMAT_11N BIT(9) 216 #define ODM_BIT_BB_RX_PATH_11N 0xF 217 #define ODM_BIT_BB_TX_PATH_11N 0xF 218 #define ODM_BIT_BB_ATC_11N BIT(11) 219 #endif 220 221