1 /****************************************************************************** 2 * 3 * Copyright(c) 2007 - 2017 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 *****************************************************************************/ 15 #ifndef __HAL_PHY_REG_H__ 16 #define __HAL_PHY_REG_H__ 17 18 /* for PutRFRegsetting & GetRFRegSetting BitMask*/ 19 #define bRFRegOffsetMask 0xfffff 20 21 /* alias for phydm coding style */ 22 #define REG_OFDM_0_XA_TX_IQ_IMBALANCE rOFDM0_XATxIQImbalance 23 #define REG_OFDM_0_ECCA_THRESHOLD rOFDM0_ECCAThreshold 24 #define REG_FPGA0_XB_LSSI_READ_BACK rFPGA0_XB_LSSIReadBack 25 #define REG_FPGA0_TX_GAIN_STAGE rFPGA0_TxGainStage 26 #define REG_OFDM_0_XA_AGC_CORE1 rOFDM0_XAAGCCore1 27 #define REG_OFDM_0_XB_AGC_CORE1 rOFDM0_XBAGCCore1 28 #define REG_A_TX_SCALE_JAGUAR rA_TxScale_Jaguar 29 #define REG_B_TX_SCALE_JAGUAR rB_TxScale_Jaguar 30 31 #define REG_FPGA0_XAB_RF_INTERFACE_SW rFPGA0_XAB_RFInterfaceSW 32 #define REG_FPGA0_XAB_RF_PARAMETER rFPGA0_XAB_RFParameter 33 #define REG_FPGA0_XA_HSSI_PARAMETER1 rFPGA0_XA_HSSIParameter1 34 #define REG_FPGA0_XA_LSSI_PARAMETER rFPGA0_XA_LSSIParameter 35 #define REG_FPGA0_XA_RF_INTERFACE_OE rFPGA0_XA_RFInterfaceOE 36 #define REG_FPGA0_XB_HSSI_PARAMETER1 rFPGA0_XB_HSSIParameter1 37 #define REG_FPGA0_XB_LSSI_PARAMETER rFPGA0_XB_LSSIParameter 38 #define REG_FPGA0_XB_LSSI_READ_BACK rFPGA0_XB_LSSIReadBack 39 #define REG_FPGA0_XB_RF_INTERFACE_OE rFPGA0_XB_RFInterfaceOE 40 #define REG_FPGA0_XCD_RF_INTERFACE_SW rFPGA0_XCD_RFInterfaceSW 41 #define REG_FPGA0_XCD_SWITCH_CONTROL rFPGA0_XCD_SwitchControl 42 #define REG_FPGA1_TX_BLOCK rFPGA1_TxBlock 43 #define REG_FPGA1_TX_INFO rFPGA1_TxInfo 44 #define REG_IQK_AGC_CONT rIQK_AGC_Cont 45 #define REG_IQK_AGC_PTS rIQK_AGC_Pts 46 #define REG_IQK_AGC_RSP rIQK_AGC_Rsp 47 #define REG_OFDM_0_AGC_RSSI_TABLE rOFDM0_AGCRSSITable 48 #define REG_OFDM_0_ECCA_THRESHOLD rOFDM0_ECCAThreshold 49 #define REG_OFDM_0_RX_IQ_EXT_ANTA rOFDM0_RxIQExtAnta 50 #define REG_OFDM_0_TR_MUX_PAR rOFDM0_TRMuxPar 51 #define REG_OFDM_0_TRX_PATH_ENABLE rOFDM0_TRxPathEnable 52 #define REG_OFDM_0_XA_AGC_CORE1 rOFDM0_XAAGCCore1 53 #define REG_OFDM_0_XA_RX_IQ_IMBALANCE rOFDM0_XARxIQImbalance 54 #define REG_OFDM_0_XA_TX_IQ_IMBALANCE rOFDM0_XATxIQImbalance 55 #define REG_OFDM_0_XB_AGC_CORE1 rOFDM0_XBAGCCore1 56 #define REG_OFDM_0_XB_RX_IQ_IMBALANCE rOFDM0_XBRxIQImbalance 57 #define REG_OFDM_0_XB_TX_IQ_IMBALANCE rOFDM0_XBTxIQImbalance 58 #define REG_OFDM_0_XC_TX_AFE rOFDM0_XCTxAFE 59 #define REG_OFDM_0_XD_TX_AFE rOFDM0_XDTxAFE 60 61 /*#define REG_A_CFO_LONG_DUMP_92E rA_CfoLongDump_92E*/ 62 #define REG_A_CFO_LONG_DUMP_JAGUAR rA_CfoLongDump_Jaguar 63 /*#define REG_A_CFO_SHORT_DUMP_92E rA_CfoShortDump_92E*/ 64 #define REG_A_CFO_SHORT_DUMP_JAGUAR rA_CfoShortDump_Jaguar 65 #define REG_A_RFE_PINMUX_JAGUAR rA_RFE_Pinmux_Jaguar 66 /*#define REG_A_RSSI_DUMP_92E rA_RSSIDump_92E*/ 67 #define REG_A_RSSI_DUMP_JAGUAR rA_RSSIDump_Jaguar 68 /*#define REG_A_RX_SNR_DUMP_92E rA_RXsnrDump_92E*/ 69 #define REG_A_RX_SNR_DUMP_JAGUAR rA_RXsnrDump_Jaguar 70 /*#define REG_A_TX_AGC rA_TXAGC*/ 71 #define REG_A_TX_SCALE_JAGUAR rA_TxScale_Jaguar 72 #define REG_BW_INDICATION_JAGUAR rBWIndication_Jaguar 73 /*#define REG_B_BBSWING rB_BBSWING*/ 74 /*#define REG_B_CFO_LONG_DUMP_92E rB_CfoLongDump_92E*/ 75 #define REG_B_CFO_LONG_DUMP_JAGUAR rB_CfoLongDump_Jaguar 76 /*#define REG_B_CFO_SHORT_DUMP_92E rB_CfoShortDump_92E*/ 77 #define REG_B_CFO_SHORT_DUMP_JAGUAR rB_CfoShortDump_Jaguar 78 /*#define REG_B_RSSI_DUMP_92E rB_RSSIDump_92E*/ 79 #define REG_B_RSSI_DUMP_JAGUAR rB_RSSIDump_Jaguar 80 /*#define REG_B_RX_SNR_DUMP_92E rB_RXsnrDump_92E*/ 81 #define REG_B_RX_SNR_DUMP_JAGUAR rB_RXsnrDump_Jaguar 82 /*#define REG_B_TX_AGC rB_TXAGC*/ 83 #define REG_B_TX_SCALE_JAGUAR rB_TxScale_Jaguar 84 #define REG_BLUE_TOOTH rBlue_Tooth 85 #define REG_CCK_0_AFE_SETTING rCCK0_AFESetting 86 /*#define REG_C_BBSWING rC_BBSWING*/ 87 /*#define REG_C_TX_AGC rC_TXAGC*/ 88 #define REG_C_TX_SCALE_JAGUAR2 rC_TxScale_Jaguar2 89 #define REG_CONFIG_ANT_A rConfig_AntA 90 #define REG_CONFIG_ANT_B rConfig_AntB 91 #define REG_CONFIG_PMPD_ANT_A rConfig_Pmpd_AntA 92 #define REG_CONFIG_PMPD_ANT_B rConfig_Pmpd_AntB 93 #define REG_DPDT_CONTROL rDPDT_control 94 /*#define REG_D_BBSWING rD_BBSWING*/ 95 /*#define REG_D_TX_AGC rD_TXAGC*/ 96 #define REG_D_TX_SCALE_JAGUAR2 rD_TxScale_Jaguar2 97 #define REG_FPGA0_ANALOG_PARAMETER4 rFPGA0_AnalogParameter4 98 #define REG_FPGA0_IQK rFPGA0_IQK 99 #define REG_FPGA0_PSD_FUNCTION rFPGA0_PSDFunction 100 #define REG_FPGA0_PSD_REPORT rFPGA0_PSDReport 101 #define REG_FPGA0_RFMOD rFPGA0_RFMOD 102 #define REG_FPGA0_TX_GAIN_STAGE rFPGA0_TxGainStage 103 #define REG_FPGA0_XAB_RF_INTERFACE_SW rFPGA0_XAB_RFInterfaceSW 104 #define REG_FPGA0_XAB_RF_PARAMETER rFPGA0_XAB_RFParameter 105 #define REG_FPGA0_XA_HSSI_PARAMETER1 rFPGA0_XA_HSSIParameter1 106 #define REG_FPGA0_XA_LSSI_PARAMETER rFPGA0_XA_LSSIParameter 107 #define REG_FPGA0_XA_RF_INTERFACE_OE rFPGA0_XA_RFInterfaceOE 108 #define REG_FPGA0_XB_HSSI_PARAMETER1 rFPGA0_XB_HSSIParameter1 109 #define REG_FPGA0_XB_LSSI_PARAMETER rFPGA0_XB_LSSIParameter 110 #define REG_FPGA0_XB_LSSI_READ_BACK rFPGA0_XB_LSSIReadBack 111 #define REG_FPGA0_XB_RF_INTERFACE_OE rFPGA0_XB_RFInterfaceOE 112 #define REG_FPGA0_XCD_RF_INTERFACE_SW rFPGA0_XCD_RFInterfaceSW 113 #define REG_FPGA0_XCD_SWITCH_CONTROL rFPGA0_XCD_SwitchControl 114 #define REG_FPGA1_TX_BLOCK rFPGA1_TxBlock 115 #define REG_FPGA1_TX_INFO rFPGA1_TxInfo 116 #define REG_IQK_AGC_CONT rIQK_AGC_Cont 117 #define REG_IQK_AGC_PTS rIQK_AGC_Pts 118 #define REG_IQK_AGC_RSP rIQK_AGC_Rsp 119 #define REG_OFDM_0_AGC_RSSI_TABLE rOFDM0_AGCRSSITable 120 #define REG_OFDM_0_ECCA_THRESHOLD rOFDM0_ECCAThreshold 121 #define REG_OFDM_0_RX_IQ_EXT_ANTA rOFDM0_RxIQExtAnta 122 #define REG_OFDM_0_TR_MUX_PAR rOFDM0_TRMuxPar 123 #define REG_OFDM_0_TRX_PATH_ENABLE rOFDM0_TRxPathEnable 124 #define REG_OFDM_0_XA_AGC_CORE1 rOFDM0_XAAGCCore1 125 #define REG_OFDM_0_XA_RX_IQ_IMBALANCE rOFDM0_XARxIQImbalance 126 #define REG_OFDM_0_XA_TX_IQ_IMBALANCE rOFDM0_XATxIQImbalance 127 #define REG_OFDM_0_XB_AGC_CORE1 rOFDM0_XBAGCCore1 128 #define REG_OFDM_0_XB_RX_IQ_IMBALANCE rOFDM0_XBRxIQImbalance 129 #define REG_OFDM_0_XB_TX_IQ_IMBALANCE rOFDM0_XBTxIQImbalance 130 #define REG_OFDM_0_XC_TX_AFE rOFDM0_XCTxAFE 131 #define REG_OFDM_0_XD_TX_AFE rOFDM0_XDTxAFE 132 #define REG_PMPD_ANAEN rPMPD_ANAEN 133 #define REG_PDP_ANT_A rPdp_AntA 134 #define REG_PDP_ANT_A_4 rPdp_AntA_4 135 #define REG_PDP_ANT_B rPdp_AntB 136 #define REG_PDP_ANT_B_4 rPdp_AntB_4 137 #define REG_PWED_TH_JAGUAR rPwed_TH_Jaguar 138 #define REG_RX_CCK rRx_CCK 139 #define REG_RX_IQK rRx_IQK 140 #define REG_RX_IQK_PI_A rRx_IQK_PI_A 141 #define REG_RX_IQK_PI_B rRx_IQK_PI_B 142 #define REG_RX_IQK_TONE_A rRx_IQK_Tone_A 143 #define REG_RX_IQK_TONE_B rRx_IQK_Tone_B 144 #define REG_RX_OFDM rRx_OFDM 145 #define REG_RX_POWER_AFTER_IQK_A_2 rRx_Power_After_IQK_A_2 146 #define REG_RX_POWER_AFTER_IQK_B_2 rRx_Power_After_IQK_B_2 147 #define REG_RX_POWER_BEFORE_IQK_A_2 rRx_Power_Before_IQK_A_2 148 #define REG_RX_POWER_BEFORE_IQK_B_2 rRx_Power_Before_IQK_B_2 149 #define REG_RX_TO_RX rRx_TO_Rx 150 #define REG_RX_WAIT_CCA rRx_Wait_CCA 151 #define REG_RX_WAIT_RIFS rRx_Wait_RIFS 152 #define REG_S0_S1_PATH_SWITCH rS0S1_PathSwitch 153 /*#define REG_S1_RXEVM_DUMP_92E rS1_RXevmDump_92E*/ 154 #define REG_S1_RXEVM_DUMP_JAGUAR rS1_RXevmDump_Jaguar 155 /*#define REG_S2_RXEVM_DUMP_92E rS2_RXevmDump_92E*/ 156 #define REG_S2_RXEVM_DUMP_JAGUAR rS2_RXevmDump_Jaguar 157 #define REG_SYM_WLBT_PAPE_SEL rSYM_WLBT_PAPE_SEL 158 #define REG_SINGLE_TONE_CONT_TX_JAGUAR rSingleTone_ContTx_Jaguar 159 #define REG_SLEEP rSleep 160 #define REG_STANDBY rStandby 161 #define REG_TX_AGC_A_CCK_11_CCK_1_JAGUAR rTxAGC_A_CCK11_CCK1_JAguar 162 #define REG_TX_AGC_A_CCK_1_MCS32 rTxAGC_A_CCK1_Mcs32 163 #define REG_TX_AGC_A_MCS11_MCS8_JAGUAR rTxAGC_A_MCS11_MCS8_JAguar 164 #define REG_TX_AGC_A_MCS15_MCS12_JAGUAR rTxAGC_A_MCS15_MCS12_JAguar 165 #define REG_TX_AGC_A_MCS19_MCS16_JAGUAR rTxAGC_A_MCS19_MCS16_JAguar 166 #define REG_TX_AGC_A_MCS23_MCS20_JAGUAR rTxAGC_A_MCS23_MCS20_JAguar 167 #define REG_TX_AGC_A_MCS3_MCS0_JAGUAR rTxAGC_A_MCS3_MCS0_JAguar 168 #define REG_TX_AGC_A_MCS7_MCS4_JAGUAR rTxAGC_A_MCS7_MCS4_JAguar 169 #define REG_TX_AGC_A_MCS03_MCS00 rTxAGC_A_Mcs03_Mcs00 170 #define REG_TX_AGC_A_MCS07_MCS04 rTxAGC_A_Mcs07_Mcs04 171 #define REG_TX_AGC_A_MCS11_MCS08 rTxAGC_A_Mcs11_Mcs08 172 #define REG_TX_AGC_A_MCS15_MCS12 rTxAGC_A_Mcs15_Mcs12 173 #define REG_TX_AGC_A_NSS1_INDEX3_NSS1_INDEX0_JAGUAR rTxAGC_A_Nss1Index3_Nss1Index0_JAguar 174 #define REG_TX_AGC_A_NSS1_INDEX7_NSS1_INDEX4_JAGUAR rTxAGC_A_Nss1Index7_Nss1Index4_JAguar 175 #define REG_TX_AGC_A_NSS2_INDEX1_NSS1_INDEX8_JAGUAR rTxAGC_A_Nss2Index1_Nss1Index8_JAguar 176 #define REG_TX_AGC_A_NSS2_INDEX5_NSS2_INDEX2_JAGUAR rTxAGC_A_Nss2Index5_Nss2Index2_JAguar 177 #define REG_TX_AGC_A_NSS2_INDEX9_NSS2_INDEX6_JAGUAR rTxAGC_A_Nss2Index9_Nss2Index6_JAguar 178 #define REG_TX_AGC_A_NSS3_INDEX3_NSS3_INDEX0_JAGUAR rTxAGC_A_Nss3Index3_Nss3Index0_JAguar 179 #define REG_TX_AGC_A_NSS3_INDEX7_NSS3_INDEX4_JAGUAR rTxAGC_A_Nss3Index7_Nss3Index4_JAguar 180 #define REG_TX_AGC_A_NSS3_INDEX9_NSS3_INDEX8_JAGUAR rTxAGC_A_Nss3Index9_Nss3Index8_JAguar 181 #define REG_TX_AGC_A_OFDM18_OFDM6_JAGUAR rTxAGC_A_Ofdm18_Ofdm6_JAguar 182 #define REG_TX_AGC_A_OFDM54_OFDM24_JAGUAR rTxAGC_A_Ofdm54_Ofdm24_JAguar 183 #define REG_TX_AGC_A_RATE18_06 rTxAGC_A_Rate18_06 184 #define REG_TX_AGC_A_RATE54_24 rTxAGC_A_Rate54_24 185 #define REG_TX_AGC_B_CCK_11_A_CCK_2_11 rTxAGC_B_CCK11_A_CCK2_11 186 #define REG_TX_AGC_B_CCK_11_CCK_1_JAGUAR rTxAGC_B_CCK11_CCK1_JAguar 187 #define REG_TX_AGC_B_CCK_1_55_MCS32 rTxAGC_B_CCK1_55_Mcs32 188 #define REG_TX_AGC_B_MCS11_MCS8_JAGUAR rTxAGC_B_MCS11_MCS8_JAguar 189 #define REG_TX_AGC_B_MCS15_MCS12_JAGUAR rTxAGC_B_MCS15_MCS12_JAguar 190 #define REG_TX_AGC_B_MCS19_MCS16_JAGUAR rTxAGC_B_MCS19_MCS16_JAguar 191 #define REG_TX_AGC_B_MCS23_MCS20_JAGUAR rTxAGC_B_MCS23_MCS20_JAguar 192 #define REG_TX_AGC_B_MCS3_MCS0_JAGUAR rTxAGC_B_MCS3_MCS0_JAguar 193 #define REG_TX_AGC_B_MCS7_MCS4_JAGUAR rTxAGC_B_MCS7_MCS4_JAguar 194 #define REG_TX_AGC_B_MCS03_MCS00 rTxAGC_B_Mcs03_Mcs00 195 #define REG_TX_AGC_B_MCS07_MCS04 rTxAGC_B_Mcs07_Mcs04 196 #define REG_TX_AGC_B_MCS11_MCS08 rTxAGC_B_Mcs11_Mcs08 197 #define REG_TX_AGC_B_MCS15_MCS12 rTxAGC_B_Mcs15_Mcs12 198 #define REG_TX_AGC_B_NSS1_INDEX3_NSS1_INDEX0_JAGUAR rTxAGC_B_Nss1Index3_Nss1Index0_JAguar 199 #define REG_TX_AGC_B_NSS1_INDEX7_NSS1_INDEX4_JAGUAR rTxAGC_B_Nss1Index7_Nss1Index4_JAguar 200 #define REG_TX_AGC_B_NSS2_INDEX1_NSS1_INDEX8_JAGUAR rTxAGC_B_Nss2Index1_Nss1Index8_JAguar 201 #define REG_TX_AGC_B_NSS2_INDEX5_NSS2_INDEX2_JAGUAR rTxAGC_B_Nss2Index5_Nss2Index2_JAguar 202 #define REG_TX_AGC_B_NSS2_INDEX9_NSS2_INDEX6_JAGUAR rTxAGC_B_Nss2Index9_Nss2Index6_JAguar 203 #define REG_TX_AGC_B_NSS3_INDEX3_NSS3_INDEX0_JAGUAR rTxAGC_B_Nss3Index3_Nss3Index0_JAguar 204 #define REG_TX_AGC_B_NSS3_INDEX7_NSS3_INDEX4_JAGUAR rTxAGC_B_Nss3Index7_Nss3Index4_JAguar 205 #define REG_TX_AGC_B_NSS3_INDEX9_NSS3_INDEX8_JAGUAR rTxAGC_B_Nss3Index9_Nss3Index8_JAguar 206 #define REG_TX_AGC_B_OFDM18_OFDM6_JAGUAR rTxAGC_B_Ofdm18_Ofdm6_JAguar 207 #define REG_TX_AGC_B_OFDM54_OFDM24_JAGUAR rTxAGC_B_Ofdm54_Ofdm24_JAguar 208 #define REG_TX_AGC_B_RATE18_06 rTxAGC_B_Rate18_06 209 #define REG_TX_AGC_B_RATE54_24 rTxAGC_B_Rate54_24 210 #define REG_TX_AGC_C_CCK_11_CCK_1_JAGUAR rTxAGC_C_CCK11_CCK1_JAguar 211 #define REG_TX_AGC_C_MCS11_MCS8_JAGUAR rTxAGC_C_MCS11_MCS8_JAguar 212 #define REG_TX_AGC_C_MCS15_MCS12_JAGUAR rTxAGC_C_MCS15_MCS12_JAguar 213 #define REG_TX_AGC_C_MCS19_MCS16_JAGUAR rTxAGC_C_MCS19_MCS16_JAguar 214 #define REG_TX_AGC_C_MCS23_MCS20_JAGUAR rTxAGC_C_MCS23_MCS20_JAguar 215 #define REG_TX_AGC_C_MCS3_MCS0_JAGUAR rTxAGC_C_MCS3_MCS0_JAguar 216 #define REG_TX_AGC_C_MCS7_MCS4_JAGUAR rTxAGC_C_MCS7_MCS4_JAguar 217 #define REG_TX_AGC_C_NSS1_INDEX3_NSS1_INDEX0_JAGUAR rTxAGC_C_Nss1Index3_Nss1Index0_JAguar 218 #define REG_TX_AGC_C_NSS1_INDEX7_NSS1_INDEX4_JAGUAR rTxAGC_C_Nss1Index7_Nss1Index4_JAguar 219 #define REG_TX_AGC_C_NSS2_INDEX1_NSS1_INDEX8_JAGUAR rTxAGC_C_Nss2Index1_Nss1Index8_JAguar 220 #define REG_TX_AGC_C_NSS2_INDEX5_NSS2_INDEX2_JAGUAR rTxAGC_C_Nss2Index5_Nss2Index2_JAguar 221 #define REG_TX_AGC_C_NSS2_INDEX9_NSS2_INDEX6_JAGUAR rTxAGC_C_Nss2Index9_Nss2Index6_JAguar 222 #define REG_TX_AGC_C_NSS3_INDEX3_NSS3_INDEX0_JAGUAR rTxAGC_C_Nss3Index3_Nss3Index0_JAguar 223 #define REG_TX_AGC_C_NSS3_INDEX7_NSS3_INDEX4_JAGUAR rTxAGC_C_Nss3Index7_Nss3Index4_JAguar 224 #define REG_TX_AGC_C_NSS3_INDEX9_NSS3_INDEX8_JAGUAR rTxAGC_C_Nss3Index9_Nss3Index8_JAguar 225 #define REG_TX_AGC_C_OFDM18_OFDM6_JAGUAR rTxAGC_C_Ofdm18_Ofdm6_JAguar 226 #define REG_TX_AGC_C_OFDM54_OFDM24_JAGUAR rTxAGC_C_Ofdm54_Ofdm24_JAguar 227 #define REG_TX_AGC_D_CCK_11_CCK_1_JAGUAR rTxAGC_D_CCK11_CCK1_JAguar 228 #define REG_TX_AGC_D_MCS11_MCS8_JAGUAR rTxAGC_D_MCS11_MCS8_JAguar 229 #define REG_TX_AGC_D_MCS15_MCS12_JAGUAR rTxAGC_D_MCS15_MCS12_JAguar 230 #define REG_TX_AGC_D_MCS19_MCS16_JAGUAR rTxAGC_D_MCS19_MCS16_JAguar 231 #define REG_TX_AGC_D_MCS23_MCS20_JAGUAR rTxAGC_D_MCS23_MCS20_JAguar 232 #define REG_TX_AGC_D_MCS3_MCS0_JAGUAR rTxAGC_D_MCS3_MCS0_JAguar 233 #define REG_TX_AGC_D_MCS7_MCS4_JAGUAR rTxAGC_D_MCS7_MCS4_JAguar 234 #define REG_TX_AGC_D_NSS1_INDEX3_NSS1_INDEX0_JAGUAR rTxAGC_D_Nss1Index3_Nss1Index0_JAguar 235 #define REG_TX_AGC_D_NSS1_INDEX7_NSS1_INDEX4_JAGUAR rTxAGC_D_Nss1Index7_Nss1Index4_JAguar 236 #define REG_TX_AGC_D_NSS2_INDEX1_NSS1_INDEX8_JAGUAR rTxAGC_D_Nss2Index1_Nss1Index8_JAguar 237 #define REG_TX_AGC_D_NSS2_INDEX5_NSS2_INDEX2_JAGUAR rTxAGC_D_Nss2Index5_Nss2Index2_JAguar 238 #define REG_TX_AGC_D_NSS2_INDEX9_NSS2_INDEX6_JAGUAR rTxAGC_D_Nss2Index9_Nss2Index6_JAguar 239 #define REG_TX_AGC_D_NSS3_INDEX3_NSS3_INDEX0_JAGUAR rTxAGC_D_Nss3Index3_Nss3Index0_JAguar 240 #define REG_TX_AGC_D_NSS3_INDEX7_NSS3_INDEX4_JAGUAR rTxAGC_D_Nss3Index7_Nss3Index4_JAguar 241 #define REG_TX_AGC_D_NSS3_INDEX9_NSS3_INDEX8_JAGUAR rTxAGC_D_Nss3Index9_Nss3Index8_JAguar 242 #define REG_TX_AGC_D_OFDM18_OFDM6_JAGUAR rTxAGC_D_Ofdm18_Ofdm6_JAguar 243 #define REG_TX_AGC_D_OFDM54_OFDM24_JAGUAR rTxAGC_D_Ofdm54_Ofdm24_JAguar 244 #define REG_TX_PATH_JAGUAR rTxPath_Jaguar 245 #define REG_TX_CCK_BBON rTx_CCK_BBON 246 #define REG_TX_CCK_RFON rTx_CCK_RFON 247 #define REG_TX_IQK rTx_IQK 248 #define REG_TX_IQK_PI_A rTx_IQK_PI_A 249 #define REG_TX_IQK_PI_B rTx_IQK_PI_B 250 #define REG_TX_IQK_TONE_A rTx_IQK_Tone_A 251 #define REG_TX_IQK_TONE_B rTx_IQK_Tone_B 252 #define REG_TX_OFDM_BBON rTx_OFDM_BBON 253 #define REG_TX_OFDM_RFON rTx_OFDM_RFON 254 #define REG_TX_POWER_AFTER_IQK_A rTx_Power_After_IQK_A 255 #define REG_TX_POWER_AFTER_IQK_B rTx_Power_After_IQK_B 256 #define REG_TX_POWER_BEFORE_IQK_A rTx_Power_Before_IQK_A 257 #define REG_TX_POWER_BEFORE_IQK_B rTx_Power_Before_IQK_B 258 #define REG_TX_TO_RX rTx_To_Rx 259 #define REG_TX_TO_TX rTx_To_Tx 260 #define REG_APK rAPK 261 #define REG_ANTSEL_SW_JAGUAR r_ANTSEL_SW_Jaguar 262 263 #define rf_welut_jaguar RF_WeLut_Jaguar 264 #define rf_mode_table_addr RF_ModeTableAddr 265 #define rf_mode_table_data0 RF_ModeTableData0 266 #define rf_mode_table_data1 RF_ModeTableData1 267 268 #define RX_SMOOTH_FACTOR Rx_Smooth_Factor 269 270 #endif /* __HAL_PHY_REG_H__ */ 271