1 /****************************************************************************** 2 * 3 * Copyright(c) 2015 - 2017 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 *****************************************************************************/ 15 #ifndef _RTL8822B_HAL_H_ 16 #define _RTL8822B_HAL_H_ 17 18 #include <osdep_service.h> /* BIT(x) */ 19 #include <drv_types.h> /* PADAPTER */ 20 #include "../hal/halmac/halmac_api.h" /* MAC REG definition */ 21 22 23 #ifdef CONFIG_SUPPORT_TRX_SHARED 24 #define MAX_RECVBUF_SZ 46080 /* 45KB, TX: (256-64)KB */ 25 #else /* !CONFIG_SUPPORT_TRX_SHARED */ 26 #ifdef CONFIG_PCI_HCI 27 #define MAX_RECVBUF_SZ 12288 /* 12KB */ 28 #else 29 #define MAX_RECVBUF_SZ 24576 /* 24KB, TX: 256KB */ 30 #endif /* !CONFIG_PCI_HCI */ 31 #endif /* !CONFIG_SUPPORT_TRX_SHARED */ 32 33 /* 34 * MAC Register definition 35 */ 36 #define REG_AFE_XTAL_CTRL REG_AFE_CTRL1_8822B /* hal_com.c & phydm */ 37 #define REG_AFE_PLL_CTRL REG_AFE_CTRL2_8822B /* hal_com.c & phydm */ 38 #define REG_MAC_PHY_CTRL REG_AFE_CTRL3_8822B /* phydm only */ 39 #define REG_LEDCFG0 REG_LED_CFG_8822B /* rtw_mp.c */ 40 #define MSR (REG_CR_8822B + 2) /* rtw_mp.c & hal_com.c */ 41 #define MSR1 REG_CR_EXT_8822B /* rtw_mp.c & hal_com.c */ 42 #define REG_C2HEVT_MSG_NORMAL 0x1A0 /* hal_com.c */ 43 #define REG_C2HEVT_CLEAR 0x1AF /* hal_com.c */ 44 #define REG_BCN_CTRL_1 REG_BCN_CTRL_CLINT0_8822B /* hal_com.c */ 45 46 #define REG_WOWLAN_WAKE_REASON 0x01C7 /* hal_com.c */ 47 #define REG_GPIO_PIN_CTRL_2 REG_GPIO_EXT_CTRL_8822B /* hal_com.c */ 48 49 /* RXERR_RPT, for rtw_mp.c */ 50 #define RXERR_TYPE_OFDM_PPDU 0 51 #define RXERR_TYPE_OFDM_FALSE_ALARM 2 52 #define RXERR_TYPE_OFDM_MPDU_OK 0 53 #define RXERR_TYPE_OFDM_MPDU_FAIL 1 54 #define RXERR_TYPE_CCK_PPDU 3 55 #define RXERR_TYPE_CCK_FALSE_ALARM 5 56 #define RXERR_TYPE_CCK_MPDU_OK 3 57 #define RXERR_TYPE_CCK_MPDU_FAIL 4 58 #define RXERR_TYPE_HT_PPDU 8 59 #define RXERR_TYPE_HT_FALSE_ALARM 9 60 #define RXERR_TYPE_HT_MPDU_TOTAL 6 61 #define RXERR_TYPE_HT_MPDU_OK 6 62 #define RXERR_TYPE_HT_MPDU_FAIL 7 63 #define RXERR_TYPE_RX_FULL_DROP 10 64 65 #define RXERR_COUNTER_MASK BIT_MASK_RPT_COUNTER_8822B 66 #define RXERR_RPT_RST BIT_RXERR_RPT_RST_8822B 67 #define _RXERR_RPT_SEL(type) (BIT_RXERR_RPT_SEL_V1_3_0_8822B(type) \ 68 | ((type & 0x10) ? BIT_RXERR_RPT_SEL_V1_4_8822B : 0)) 69 70 /* 71 * BB Register definition 72 */ 73 #define rPMAC_Reset 0x100 /* hal_mp.c */ 74 75 #define rFPGA0_RFMOD 0x800 76 #define rFPGA0_TxInfo 0x804 77 #define rOFDMCCKEN_Jaguar 0x808 /* hal_mp.c */ 78 #define rFPGA0_TxGainStage 0x80C /* phydm only */ 79 #define rFPGA0_XA_HSSIParameter1 0x820 /* hal_mp.c */ 80 #define rFPGA0_XA_HSSIParameter2 0x824 /* hal_mp.c */ 81 #define rFPGA0_XB_HSSIParameter1 0x828 /* hal_mp.c */ 82 #define rFPGA0_XB_HSSIParameter2 0x82C /* hal_mp.c */ 83 #define rTxAGC_B_Rate18_06 0x830 84 #define rTxAGC_B_Rate54_24 0x834 85 #define rTxAGC_B_CCK1_55_Mcs32 0x838 86 #define rCCAonSec_Jaguar 0x838 /* hal_mp.c */ 87 #define rTxAGC_B_Mcs03_Mcs00 0x83C 88 #define rTxAGC_B_Mcs07_Mcs04 0x848 89 #define rTxAGC_B_Mcs11_Mcs08 0x84C 90 #define rFPGA0_XA_RFInterfaceOE 0x860 91 #define rFPGA0_XB_RFInterfaceOE 0x864 92 #define rTxAGC_B_Mcs15_Mcs12 0x868 93 #define rTxAGC_B_CCK11_A_CCK2_11 0x86C 94 #define rFPGA0_XAB_RFInterfaceSW 0x870 95 #define rFPGA0_XAB_RFParameter 0x878 96 #define rFPGA0_AnalogParameter4 0x88C /* hal_mp.c & phydm */ 97 #define rFPGA0_XB_LSSIReadBack 0x8A4 /* phydm */ 98 #define rHSSIRead_Jaguar 0x8B0 /* RF read addr (rtl8822b_phy.c) */ 99 100 #define rC_TxScale_Jaguar2 0x181C /* Pah_C TX scaling factor (hal_mp.c) */ 101 #define rC_IGI_Jaguar2 0x1850 /* Initial Gain for path-C (hal_mp.c) */ 102 103 #define rFPGA1_TxInfo 0x90C /* hal_mp.c */ 104 #define rSingleTone_ContTx_Jaguar 0x914 /* hal_mp.c */ 105 /* TX BeamForming */ 106 #define REG_BB_TX_PATH_SEL_1_8822B 0x93C /* rtl8822b_phy.c */ 107 #define REG_BB_TX_PATH_SEL_2_8822B 0x940 /* rtl8822b_phy.c */ 108 109 /* TX BeamForming */ 110 #define REG_BB_TXBF_ANT_SET_BF1_8822B 0x19AC /* rtl8822b_phy.c */ 111 #define REG_BB_TXBF_ANT_SET_BF0_8822B 0x19B4 /* rtl8822b_phy.c */ 112 113 #define rCCK0_System 0xA00 114 #define rCCK0_AFESetting 0xA04 115 116 #define rCCK0_DSPParameter2 0xA1C 117 #define rCCK0_TxFilter1 0xA20 118 #define rCCK0_TxFilter2 0xA24 119 #define rCCK0_DebugPort 0xA28 120 #define rCCK0_FalseAlarmReport 0xA2C 121 122 #define rD_TxScale_Jaguar2 0x1A1C /* Path_D TX scaling factor (hal_mp.c) */ 123 #define rD_IGI_Jaguar2 0x1A50 /* Initial Gain for path-D (hal_mp.c) */ 124 125 #define rOFDM0_TRxPathEnable 0xC04 126 #define rOFDM0_TRMuxPar 0xC08 127 #define rA_TxScale_Jaguar 0xC1C /* Pah_A TX scaling factor (hal_mp.c) */ 128 #define rOFDM0_RxDetector1 0xC30 /* rtw_mp.c */ 129 #define rOFDM0_ECCAThreshold 0xC4C /* phydm only */ 130 #define rOFDM0_XAAGCCore1 0xC50 /* phydm only */ 131 #define rA_IGI_Jaguar 0xC50 /* Initial Gain for path-A (hal_mp.c) */ 132 #define rOFDM0_XBAGCCore1 0xC58 /* phydm only */ 133 #define rOFDM0_XATxIQImbalance 0xC80 /* phydm only */ 134 #define rA_LSSIWrite_Jaguar 0xC90 /* RF write addr, LSSI Parameter (rtl8822b_phy.c) */ 135 136 #define rOFDM1_LSTF 0xD00 137 #define rOFDM1_TRxPathEnable 0xD04 /* hal_mp.c */ 138 #define rA_PIRead_Jaguar 0xD04 /* RF readback with PI (rtl8822b_phy.c) */ 139 #define rA_SIRead_Jaguar 0xD08 /* RF readback with SI (rtl8822b_phy.c) */ 140 #define rB_PIRead_Jaguar 0xD44 /* RF readback with PI (rtl8822b_phy.c) */ 141 #define rB_SIRead_Jaguar 0xD48 /* RF readback with SI (rtl8822b_phy.c) */ 142 143 #define rTxAGC_A_Rate18_06 0xE00 144 #define rTxAGC_A_Rate54_24 0xE04 145 #define rTxAGC_A_CCK1_Mcs32 0xE08 146 #define rTxAGC_A_Mcs03_Mcs00 0xE10 147 #define rTxAGC_A_Mcs07_Mcs04 0xE14 148 #define rTxAGC_A_Mcs11_Mcs08 0xE18 149 #define rTxAGC_A_Mcs15_Mcs12 0xE1C 150 #define rB_TxScale_Jaguar 0xE1C /* Path_B TX scaling factor (hal_mp.c) */ 151 #define rB_IGI_Jaguar 0xE50 /* Initial Gain for path-B (hal_mp.c) */ 152 #define rB_LSSIWrite_Jaguar 0xE90 /* RF write addr, LSSI Parameter (rtl8822b_phy.c) */ 153 /* RFE */ 154 #define rA_RFE_Pinmux_Jaguar 0xCB0 /* hal_mp.c */ 155 #define rB_RFE_Pinmux_Jaguar 0xEB0 /* Path_B RFE control pinmux */ 156 #define rA_RFE_Inv_Jaguar 0xCB4 /* Path_A RFE cotrol */ 157 #define rB_RFE_Inv_Jaguar 0xEB4 /* Path_B RFE control */ 158 #define rA_RFE_Jaguar 0xCB8 /* Path_A RFE cotrol */ 159 #define rB_RFE_Jaguar 0xEB8 /* Path_B RFE control */ 160 #define rA_RFE_Inverse_Jaguar 0xCBC /* Path_A RFE control inverse */ 161 #define rB_RFE_Inverse_Jaguar 0xEBC /* Path_B RFE control inverse */ 162 #define r_ANTSEL_SW_Jaguar 0x900 /* ANTSEL SW Control */ 163 #define bMask_RFEInv_Jaguar 0x3FF00000 164 #define bMask_AntselPathFollow_Jaguar 0x00030000 165 166 #define rC_RFE_Pinmux_Jaguar 0x18B4 /* Path_C RFE cotrol pinmux*/ 167 #define rD_RFE_Pinmux_Jaguar 0x1AB4 /* Path_D RFE cotrol pinmux*/ 168 #define rA_RFE_Sel_Jaguar2 0x1990 169 170 /* Page1(0x100) */ 171 #define bBBResetB 0x100 172 173 /* Page8(0x800) */ 174 #define bCCKEn 0x1000000 175 #define bOFDMEn 0x2000000 176 /* Reg 0x80C rFPGA0_TxGainStage */ 177 #define bXBTxAGC 0xF00 178 #define bXCTxAGC 0xF000 179 #define bXDTxAGC 0xF0000 180 181 /* PageA(0xA00) */ 182 #define bCCKBBMode 0x3 183 184 #define bCCKScramble 0x8 185 #define bCCKTxRate 0x3000 186 187 /* General */ 188 #define bMaskByte0 0xFF /* mp, rtw_odm.c & phydm */ 189 #define bMaskByte1 0xFF00 /* hal_mp.c & phydm */ 190 #define bMaskByte2 0xFF0000 /* hal_mp.c & phydm */ 191 #define bMaskByte3 0xFF000000 /* hal_mp.c & phydm */ 192 #define bMaskHWord 0xFFFF0000 /* hal_com.c, rtw_mp.c */ 193 #define bMaskLWord 0x0000FFFF /* mp, hal_com.c & phydm */ 194 #define bMaskDWord 0xFFFFFFFF /* mp, hal, rtw_odm.c & phydm */ 195 196 #define bEnable 0x1 /* hal_mp.c, rtw_mp.c */ 197 #define bDisable 0x0 /* rtw_mp.c */ 198 199 #define MAX_STALL_TIME 50 /* unit: us, hal_com_phycfg.c */ 200 201 #define Rx_Smooth_Factor 20 /* phydm only */ 202 203 /* 204 * RF Register definition 205 */ 206 #define RF_AC 0x00 207 #define RF_AC_Jaguar 0x00 /* hal_mp.c */ 208 #define RF_CHNLBW 0x18 /* rtl8822b_phy.c */ 209 #define RF_ModeTableAddr 0x30 /* rtl8822b_phy.c */ 210 #define RF_ModeTableData0 0x31 /* rtl8822b_phy.c */ 211 #define RF_ModeTableData1 0x32 /* rtl8822b_phy.c */ 212 #define RF_0x52 0x52 213 #define RF_WeLut_Jaguar 0xEF /* rtl8822b_phy.c */ 214 215 /* General Functions */ 216 void rtl8822b_init_hal_spec(PADAPTER); /* hal/hal_com.c */ 217 218 #ifdef CONFIG_MP_INCLUDED 219 /* MP Functions */ 220 #include <rtw_mp.h> /* struct mp_priv */ 221 void rtl8822b_prepare_mp_txdesc(PADAPTER, struct mp_priv *); /* rtw_mp.c */ 222 void rtl8822b_mp_config_rfpath(PADAPTER); /* hal_mp.c */ 223 #endif 224 void hw_var_set_dl_rsvd_page(PADAPTER adapter, u8 mstatus); 225 226 #ifdef CONFIG_USB_HCI 227 #include <rtl8822bu_hal.h> 228 #elif defined(CONFIG_SDIO_HCI) 229 #include <rtl8822bs_hal.h> 230 #elif defined(CONFIG_PCI_HCI) 231 #include <rtl8822be_hal.h> 232 #endif 233 234 #endif /* _RTL8822B_HAL_H_ */ 235