1 /* 2 * Copyright (c) 2022 Unionman Technology Co., Ltd. 3 * 4 * HDF is dual licensed: you can use it either under the terms of 5 * the GPL, or the BSD license, at your option. 6 * See the LICENSE file in the root of this repository for complete details. 7 */ 8 9 #ifndef NAU8540_H 10 #define NAU8540_H 11 12 #ifdef __cplusplus 13 #if __cplusplus 14 extern "C" { 15 #endif 16 #endif /* __cplusplus */ 17 18 #define NAU8540_REG_SW_RESET 0x00 19 #define NAU8540_REG_POWER_MANAGEMENT 0x01 20 #define NAU8540_REG_CLOCK_CTRL 0x02 21 #define NAU8540_REG_CLOCK_SRC 0x03 22 #define NAU8540_REG_FLL1 0x04 23 #define NAU8540_REG_FLL2 0x05 24 #define NAU8540_REG_FLL3 0x06 25 #define NAU8540_REG_FLL4 0x07 26 #define NAU8540_REG_FLL5 0x08 27 #define NAU8540_REG_FLL6 0x09 28 #define NAU8540_REG_FLL_VCO_RSV 0x0A 29 #define NAU8540_REG_PCM_CTRL0 0x10 30 #define NAU8540_REG_PCM_CTRL1 0x11 31 #define NAU8540_REG_PCM_CTRL2 0x12 32 #define NAU8540_REG_PCM_CTRL3 0x13 33 #define NAU8540_REG_PCM_CTRL4 0x14 34 #define NAU8540_REG_ALC_CONTROL_1 0x20 35 #define NAU8540_REG_ALC_CONTROL_2 0x21 36 #define NAU8540_REG_ALC_CONTROL_3 0x22 37 #define NAU8540_REG_ALC_CONTROL_4 0x23 38 #define NAU8540_REG_ALC_CONTROL_5 0x24 39 #define NAU8540_REG_ALC_GAIN_CH12 0x2D 40 #define NAU8540_REG_ALC_GAIN_CH34 0x2E 41 #define NAU8540_REG_ALC_STATUS 0x2F 42 #define NAU8540_REG_NOTCH_FIL1_CH1 0x30 43 #define NAU8540_REG_NOTCH_FIL2_CH1 0x31 44 #define NAU8540_REG_NOTCH_FIL1_CH2 0x32 45 #define NAU8540_REG_NOTCH_FIL2_CH2 0x33 46 #define NAU8540_REG_NOTCH_FIL1_CH3 0x34 47 #define NAU8540_REG_NOTCH_FIL2_CH3 0x35 48 #define NAU8540_REG_NOTCH_FIL1_CH4 0x36 49 #define NAU8540_REG_NOTCH_FIL2_CH4 0x37 50 #define NAU8540_REG_HPF_FILTER_CH12 0x38 51 #define NAU8540_REG_HPF_FILTER_CH34 0x39 52 #define NAU8540_REG_ADC_SAMPLE_RATE 0x3A 53 #define NAU8540_REG_DIGITAL_GAIN_CH1 0x40 54 #define NAU8540_REG_DIGITAL_GAIN_CH2 0x41 55 #define NAU8540_REG_DIGITAL_GAIN_CH3 0x42 56 #define NAU8540_REG_DIGITAL_GAIN_CH4 0x43 57 #define NAU8540_REG_DIGITAL_MUX 0x44 58 #define NAU8540_REG_P2P_CH1 0x48 59 #define NAU8540_REG_P2P_CH2 0x49 60 #define NAU8540_REG_P2P_CH3 0x4A 61 #define NAU8540_REG_P2P_CH4 0x4B 62 #define NAU8540_REG_PEAK_CH1 0x4C 63 #define NAU8540_REG_PEAK_CH2 0x4D 64 #define NAU8540_REG_PEAK_CH3 0x4E 65 #define NAU8540_REG_PEAK_CH4 0x4F 66 #define NAU8540_REG_GPIO_CTRL 0x50 67 #define NAU8540_REG_MISC_CTRL 0x51 68 #define NAU8540_REG_I2C_CTRL 0x52 69 #define NAU8540_REG_I2C_DEVICE_ID 0x58 70 #define NAU8540_REG_RST 0x5A 71 #define NAU8540_REG_VMID_CTRL 0x60 72 #define NAU8540_REG_MUTE 0x61 73 #define NAU8540_REG_ANALOG_ADC1 0x64 74 #define NAU8540_REG_ANALOG_ADC2 0x65 75 #define NAU8540_REG_ANALOG_PWR 0x66 76 #define NAU8540_REG_MIC_BIAS 0x67 77 #define NAU8540_REG_REFERENCE 0x68 78 #define NAU8540_REG_FEPGA1 0x69 79 #define NAU8540_REG_FEPGA2 0x6A 80 #define NAU8540_REG_FEPGA3 0x6B 81 #define NAU8540_REG_FEPGA4 0x6C 82 #define NAU8540_REG_PWR 0x6D 83 #define NAU8540_REG_MAX NAU8540_REG_PWR 84 85 86 /* POWER_MANAGEMENT (0x01) */ 87 #define NAU8540_ADC4_EN (0x1 << 3) 88 #define NAU8540_ADC3_EN (0x1 << 2) 89 #define NAU8540_ADC2_EN (0x1 << 1) 90 #define NAU8540_ADC1_EN 0x1 91 92 /* CLOCK_CTRL (0x02) */ 93 #define NAU8540_CLK_ADC_EN (0x1 << 15) 94 #define NAU8540_CLK_I2S_EN (0x1 << 1) 95 96 /* CLOCK_SRC (0x03) */ 97 #define NAU8540_CLK_SRC_SFT 15 98 #define NAU8540_CLK_SRC_MASK (1 << NAU8540_CLK_SRC_SFT) 99 #define NAU8540_CLK_SRC_VCO (1 << NAU8540_CLK_SRC_SFT) 100 #define NAU8540_CLK_SRC_MCLK (0 << NAU8540_CLK_SRC_SFT) 101 #define NAU8540_CLK_ADC_SRC_SFT 6 102 #define NAU8540_CLK_ADC_SRC_MASK (0x3 << NAU8540_CLK_ADC_SRC_SFT) 103 #define NAU8540_CLK_MCLK_SRC_MASK 0xf 104 105 /* FLL1 (0x04) */ 106 #define NAU8540_ICTRL_LATCH_SFT 10 107 #define NAU8540_ICTRL_LATCH_MASK (0x7 << NAU8540_ICTRL_LATCH_SFT) 108 #define NAU8540_FLL_RATIO_MASK 0x7f 109 110 /* FLL3 (0x06) */ 111 #define NAU8540_GAIN_ERR_SFT 12 112 #define NAU8540_GAIN_ERR_MASK (0xf << NAU8540_GAIN_ERR_SFT) 113 #define NAU8540_FLL_CLK_SRC_SFT 10 114 #define NAU8540_FLL_CLK_SRC_MASK (0x3 << NAU8540_FLL_CLK_SRC_SFT) 115 #define NAU8540_FLL_CLK_SRC_MCLK (0 << NAU8540_FLL_CLK_SRC_SFT) 116 #define NAU8540_FLL_CLK_SRC_BLK (0x2 << NAU8540_FLL_CLK_SRC_SFT) 117 #define NAU8540_FLL_CLK_SRC_FS (0x3 << NAU8540_FLL_CLK_SRC_SFT) 118 #define NAU8540_FLL_INTEGER_MASK 0x3ff 119 120 /* FLL4 (0x07) */ 121 #define NAU8540_FLL_REF_DIV_SFT 10 122 #define NAU8540_FLL_REF_DIV_MASK (0x3 << NAU8540_FLL_REF_DIV_SFT) 123 124 /* FLL5 (0x08) */ 125 #define NAU8540_FLL_PDB_DAC_EN (0x1 << 15) 126 #define NAU8540_FLL_LOOP_FTR_EN (0x1 << 14) 127 #define NAU8540_FLL_CLK_SW_MASK (0x1 << 13) 128 #define NAU8540_FLL_CLK_SW_N2 (0x1 << 13) 129 #define NAU8540_FLL_CLK_SW_REF (0x0 << 13) 130 #define NAU8540_FLL_FTR_SW_MASK (0x1 << 12) 131 #define NAU8540_FLL_FTR_SW_ACCU (0x1 << 12) 132 #define NAU8540_FLL_FTR_SW_FILTER (0x0 << 12) 133 134 /* FLL6 (0x9) */ 135 #define NAU8540_DCO_EN (0x1 << 15) 136 #define NAU8540_SDM_EN (0x1 << 14) 137 #define NAU8540_CUTOFF500 (0x1 << 13) 138 139 /* PCM_CTRL0 (0x10) */ 140 #define NAU8540_I2S_BP_SFT 7 141 #define NAU8540_I2S_BP_INV (0x1 << NAU8540_I2S_BP_SFT) 142 #define NAU8540_I2S_PCMB_SFT 6 143 #define NAU8540_I2S_PCMB_EN (0x1 << NAU8540_I2S_PCMB_SFT) 144 #define NAU8540_I2S_DL_SFT 2 145 #define NAU8540_I2S_DL_MASK (0x3 << NAU8540_I2S_DL_SFT) 146 #define NAU8540_I2S_DL_16 (0 << NAU8540_I2S_DL_SFT) 147 #define NAU8540_I2S_DL_20 (0x1 << NAU8540_I2S_DL_SFT) 148 #define NAU8540_I2S_DL_24 (0x2 << NAU8540_I2S_DL_SFT) 149 #define NAU8540_I2S_DL_32 (0x3 << NAU8540_I2S_DL_SFT) 150 #define NAU8540_I2S_DF_MASK 0x3 151 #define NAU8540_I2S_DF_RIGTH 0 152 #define NAU8540_I2S_DF_LEFT 0x1 153 #define NAU8540_I2S_DF_I2S 0x2 154 #define NAU8540_I2S_DF_PCM_AB 0x3 155 156 /* PCM_CTRL1 (0x11) */ 157 #define NAU8540_I2S_DO12_TRI (0x1 << 15) 158 #define NAU8540_I2S_LRC_DIV_SFT 12 159 #define NAU8540_I2S_LRC_DIV_MASK (0x3 << NAU8540_I2S_LRC_DIV_SFT) 160 #define NAU8540_I2S_DO12_OE (0x1 << 4) 161 #define NAU8540_I2S_MS_SFT 3 162 #define NAU8540_I2S_MS_MASK (0x1 << NAU8540_I2S_MS_SFT) 163 #define NAU8540_I2S_MS_MASTER (0x1 << NAU8540_I2S_MS_SFT) 164 #define NAU8540_I2S_MS_SLAVE (0x0 << NAU8540_I2S_MS_SFT) 165 #define NAU8540_I2S_BLK_DIV_MASK 0x7 166 167 /* PCM_CTRL1 (0x12) */ 168 #define NAU8540_I2S_DO34_TRI (0x1 << 15) 169 #define NAU8540_I2S_DO34_OE (0x1 << 11) 170 #define NAU8540_I2S_TSLOT_L_MASK 0x3ff 171 172 /* PCM_CTRL4 (0x14) */ 173 #define NAU8540_TDM_MODE (0x1 << 15) 174 #define NAU8540_TDM_OFFSET_EN (0x1 << 14) 175 #define NAU8540_TDM_TX_MASK 0xf 176 177 /* ADC_SAMPLE_RATE (0x3A) */ 178 #define NAU8540_CH_SYNC (0x1 << 14) 179 #define NAU8540_ADC_OSR_MASK 0x3 180 #define NAU8540_ADC_OSR_256 0x3 181 #define NAU8540_ADC_OSR_128 0x2 182 #define NAU8540_ADC_OSR_64 0x1 183 #define NAU8540_ADC_OSR_32 0x0 184 185 /* VMID_CTRL (0x60) */ 186 #define NAU8540_VMID_EN (1 << 6) 187 #define NAU8540_VMID_SEL_SFT 4 188 #define NAU8540_VMID_SEL_MASK (0x3 << NAU8540_VMID_SEL_SFT) 189 190 /* MIC_BIAS (0x67) */ 191 #define NAU8540_PU_PRE (0x1 << 8) 192 193 /* REFERENCE (0x68) */ 194 #define NAU8540_PRECHARGE_DIS (0x1 << 13) 195 #define NAU8540_GLOBAL_BIAS_EN (0x1 << 12) 196 197 /* FEPGA1 (0x69) */ 198 #define NAU8540_FEPGA1_MODCH2_SHT_SFT 7 199 #define NAU8540_FEPGA1_MODCH2_SHT (0x1 << NAU8540_FEPGA1_MODCH2_SHT_SFT) 200 #define NAU8540_FEPGA1_MODCH1_SHT_SFT 3 201 #define NAU8540_FEPGA1_MODCH1_SHT (0x1 << NAU8540_FEPGA1_MODCH1_SHT_SFT) 202 203 /* FEPGA2 (0x6A) */ 204 #define NAU8540_FEPGA2_MODCH4_SHT_SFT 7 205 #define NAU8540_FEPGA2_MODCH4_SHT (0x1 << NAU8540_FEPGA2_MODCH4_SHT_SFT) 206 #define NAU8540_FEPGA2_MODCH3_SHT_SFT 3 207 #define NAU8540_FEPGA2_MODCH3_SHT (0x1 << NAU8540_FEPGA2_MODCH3_SHT_SFT) 208 209 /* System Clock Source */ 210 enum { 211 NAU8540_CLK_DIS, 212 NAU8540_CLK_MCLK, 213 NAU8540_CLK_INTERNAL, 214 NAU8540_CLK_FLL_MCLK, 215 NAU8540_CLK_FLL_BLK, 216 NAU8540_CLK_FLL_FS, 217 }; 218 219 struct nau8540 { 220 struct device *dev; 221 struct regmap *regmap; 222 }; 223 224 struct nau8540_fll { 225 int mclk_src; 226 int ratio; 227 int fll_frac; 228 int fll_int; 229 int clk_ref_div; 230 }; 231 232 struct nau8540_fll_attr { 233 unsigned int param; 234 unsigned int val; 235 }; 236 237 /* over sampling rate */ 238 struct nau8540_osr_attr { 239 unsigned int osr; 240 unsigned int clk_src; 241 }; 242 243 int nau8540_set_fmt(unsigned int fmt); 244 245 int nau8540_set_tdm_slot(unsigned int tx_mask, 246 unsigned int rx_mask, int slots, int slot_width); 247 248 int nau8540_hw_params(unsigned int rate, unsigned int bit_width); 249 250 int nau8540_set_pll(int pll_id, unsigned int freq_in, 251 unsigned int freq_out); 252 253 int nau8540_adc_enable(bool enable); 254 255 int nau8540_suspend(void); 256 257 int nau8540_resume(void); 258 259 #ifdef __cplusplus 260 #if __cplusplus 261 } 262 #endif 263 #endif /* __cplusplus */ 264 265 #endif /* NAU8540_H */ 266