1 /*
2 * Copyright (c) 2022 Unionman Technology Co., Ltd.
3 *
4 * HDF is dual licensed: you can use it either under the terms of
5 * the GPL, or the BSD license, at your option.
6 * See the LICENSE file in the root of this repository for complete details.
7 */
8
9 #include <linux/module.h>
10 #include <linux/moduleparam.h>
11 #include <linux/init.h>
12 #include <linux/delay.h>
13 #include <linux/pm.h>
14 #include <linux/i2c.h>
15 #include <linux/regmap.h>
16 #include <linux/regulator/consumer.h>
17 #include <linux/spi/spi.h>
18 #include <linux/slab.h>
19 #include <linux/of_device.h>
20 #include "sound/soc.h"
21
22 #include "axg_common.h"
23 #include "nau8540.h"
24
25 #define NAU_FREF_MAX 13500000
26 #define NAU_FVCO_MAX 100000000
27 #define NAU_FVCO_MIN 90000000
28
29 /* the maximum frequency of CLK_ADC */
30 #define CLK_ADC_MAX 6144000
31
32 /* scaling for mclk from sysclk_src output */
33 static const struct nau8540_fll_attr mclk_src_scaling[] = {
34 {1, 0x0},
35 {2, 0x2},
36 {4, 0x3},
37 {8, 0x4},
38 {16, 0x5},
39 {32, 0x6},
40 {3, 0x7},
41 {6, 0xa},
42 {12, 0xb},
43 {24, 0xc},
44 };
45
46 /* ratio for input clk freq */
47 static const struct nau8540_fll_attr fll_ratio[] = {
48 {512000, 0x01},
49 {256000, 0x02},
50 {128000, 0x04},
51 {64000, 0x08},
52 {32000, 0x10},
53 {8000, 0x20},
54 {4000, 0x40},
55 };
56
57 static const struct nau8540_fll_attr fll_pre_scalar[] = {
58 {1, 0x0},
59 {2, 0x1},
60 {4, 0x2},
61 {8, 0x3},
62 };
63
64 /* over sampling rate */
65 static const struct nau8540_osr_attr osr_adc_sel[] = {
66 {32, 3}, /* OSR 32, SRC 1/8 */
67 {64, 2}, /* OSR 64, SRC 1/4 */
68 {128, 1}, /* OSR 128, SRC 1/2 */
69 {256, 0}, /* OSR 256, SRC 1 */
70 };
71
72 static const struct reg_default nau8540_reg_defaults[] = {
73 {NAU8540_REG_POWER_MANAGEMENT, 0x0000},
74 {NAU8540_REG_CLOCK_CTRL, 0x0000},
75 {NAU8540_REG_CLOCK_SRC, 0x0000},
76 {NAU8540_REG_FLL1, 0x0001},
77 {NAU8540_REG_FLL2, 0x3126},
78 {NAU8540_REG_FLL3, 0x0008},
79 {NAU8540_REG_FLL4, 0x0010},
80 {NAU8540_REG_FLL5, 0xC000},
81 {NAU8540_REG_FLL6, 0x6000},
82 {NAU8540_REG_FLL_VCO_RSV, 0xF13C},
83 {NAU8540_REG_PCM_CTRL0, 0x000B},
84 {NAU8540_REG_PCM_CTRL1, 0x3010},
85 {NAU8540_REG_PCM_CTRL2, 0x0800},
86 {NAU8540_REG_PCM_CTRL3, 0x0000},
87 {NAU8540_REG_PCM_CTRL4, 0x000F},
88 {NAU8540_REG_ALC_CONTROL_1, 0x0000},
89 {NAU8540_REG_ALC_CONTROL_2, 0x700B},
90 {NAU8540_REG_ALC_CONTROL_3, 0x0022},
91 {NAU8540_REG_ALC_CONTROL_4, 0x1010},
92 {NAU8540_REG_ALC_CONTROL_5, 0x1010},
93 {NAU8540_REG_NOTCH_FIL1_CH1, 0x0000},
94 {NAU8540_REG_NOTCH_FIL2_CH1, 0x0000},
95 {NAU8540_REG_NOTCH_FIL1_CH2, 0x0000},
96 {NAU8540_REG_NOTCH_FIL2_CH2, 0x0000},
97 {NAU8540_REG_NOTCH_FIL1_CH3, 0x0000},
98 {NAU8540_REG_NOTCH_FIL2_CH3, 0x0000},
99 {NAU8540_REG_NOTCH_FIL1_CH4, 0x0000},
100 {NAU8540_REG_NOTCH_FIL2_CH4, 0x0000},
101 {NAU8540_REG_HPF_FILTER_CH12, 0x0000},
102 {NAU8540_REG_HPF_FILTER_CH34, 0x0000},
103 {NAU8540_REG_ADC_SAMPLE_RATE, 0x0002},
104 {NAU8540_REG_DIGITAL_GAIN_CH1, 0x0400},
105 {NAU8540_REG_DIGITAL_GAIN_CH2, 0x0400},
106 {NAU8540_REG_DIGITAL_GAIN_CH3, 0x0400},
107 {NAU8540_REG_DIGITAL_GAIN_CH4, 0x0400},
108 {NAU8540_REG_DIGITAL_MUX, 0x00E4},
109 {NAU8540_REG_GPIO_CTRL, 0x0000},
110 {NAU8540_REG_MISC_CTRL, 0x0000},
111 {NAU8540_REG_I2C_CTRL, 0xEFFF},
112 {NAU8540_REG_VMID_CTRL, 0x0000},
113 {NAU8540_REG_MUTE, 0x0000},
114 {NAU8540_REG_ANALOG_ADC1, 0x0011},
115 {NAU8540_REG_ANALOG_ADC2, 0x0020},
116 {NAU8540_REG_ANALOG_PWR, 0x0000},
117 {NAU8540_REG_MIC_BIAS, 0x0004},
118 {NAU8540_REG_REFERENCE, 0x0000},
119 {NAU8540_REG_FEPGA1, 0x0000},
120 {NAU8540_REG_FEPGA2, 0x0000},
121 {NAU8540_REG_FEPGA3, 0x0101},
122 {NAU8540_REG_FEPGA4, 0x0101},
123 {NAU8540_REG_PWR, 0x0000},
124 };
125
126 static struct nau8540 *g_nau8540 = NULL;
127
nau8540_readable_reg(struct device * dev,unsigned int reg)128 static bool nau8540_readable_reg(struct device *dev, unsigned int reg)
129 {
130 switch (reg) {
131 case NAU8540_REG_POWER_MANAGEMENT ... NAU8540_REG_FLL_VCO_RSV:
132 case NAU8540_REG_PCM_CTRL0 ... NAU8540_REG_PCM_CTRL4:
133 case NAU8540_REG_ALC_CONTROL_1 ... NAU8540_REG_ALC_CONTROL_5:
134 case NAU8540_REG_ALC_GAIN_CH12 ... NAU8540_REG_ADC_SAMPLE_RATE:
135 case NAU8540_REG_DIGITAL_GAIN_CH1 ... NAU8540_REG_DIGITAL_MUX:
136 case NAU8540_REG_P2P_CH1 ... NAU8540_REG_I2C_CTRL:
137 case NAU8540_REG_I2C_DEVICE_ID:
138 case NAU8540_REG_VMID_CTRL ... NAU8540_REG_MUTE:
139 case NAU8540_REG_ANALOG_ADC1 ... NAU8540_REG_PWR:
140 return true;
141 default:
142 return false;
143 }
144 }
145
nau8540_writeable_reg(struct device * dev,unsigned int reg)146 static bool nau8540_writeable_reg(struct device *dev, unsigned int reg)
147 {
148 switch (reg) {
149 case NAU8540_REG_SW_RESET ... NAU8540_REG_FLL_VCO_RSV:
150 case NAU8540_REG_PCM_CTRL0 ... NAU8540_REG_PCM_CTRL4:
151 case NAU8540_REG_ALC_CONTROL_1 ... NAU8540_REG_ALC_CONTROL_5:
152 case NAU8540_REG_NOTCH_FIL1_CH1 ... NAU8540_REG_ADC_SAMPLE_RATE:
153 case NAU8540_REG_DIGITAL_GAIN_CH1 ... NAU8540_REG_DIGITAL_MUX:
154 case NAU8540_REG_GPIO_CTRL ... NAU8540_REG_I2C_CTRL:
155 case NAU8540_REG_RST:
156 case NAU8540_REG_VMID_CTRL ... NAU8540_REG_MUTE:
157 case NAU8540_REG_ANALOG_ADC1 ... NAU8540_REG_PWR:
158 return true;
159 default:
160 return false;
161 }
162 }
163
nau8540_volatile_reg(struct device * dev,unsigned int reg)164 static bool nau8540_volatile_reg(struct device *dev, unsigned int reg)
165 {
166 switch (reg) {
167 case NAU8540_REG_SW_RESET:
168 case NAU8540_REG_ALC_GAIN_CH12 ... NAU8540_REG_ALC_STATUS:
169 case NAU8540_REG_P2P_CH1 ... NAU8540_REG_PEAK_CH4:
170 case NAU8540_REG_I2C_DEVICE_ID:
171 case NAU8540_REG_RST:
172 return true;
173 default:
174 return false;
175 }
176 }
177
nau8540_powerup(struct nau8540 * nau8540)178 static void nau8540_powerup(struct nau8540 *nau8540)
179 {
180 /* MICBIAS1 */
181 regmap_update_bits(nau8540->regmap, NAU8540_REG_MIC_BIAS,
182 BIT(10U), BIT(10U));
183 /* ADC CH1 */
184 regmap_update_bits(nau8540->regmap, NAU8540_REG_ANALOG_PWR,
185 BIT(0), BIT(0));
186 /* Frontend PGA1 */
187 regmap_update_bits(nau8540->regmap, NAU8540_REG_PWR,
188 BIT(12U), BIT(12U));
189 /* ADC1 */
190 regmap_update_bits(nau8540->regmap, NAU8540_REG_POWER_MANAGEMENT,
191 BIT(0), BIT(0));
192 }
193
nau8540_powerdown(struct nau8540 * nau8540)194 static void nau8540_powerdown(struct nau8540 *nau8540)
195 {
196 /* ADC1 */
197 regmap_update_bits(nau8540->regmap, NAU8540_REG_POWER_MANAGEMENT,
198 BIT(0), 0);
199 /* ADC CH1 */
200 regmap_update_bits(nau8540->regmap, NAU8540_REG_ANALOG_PWR,
201 BIT(0), 0);
202 /* Frontend PGA1 */
203 regmap_update_bits(nau8540->regmap, NAU8540_REG_PWR,
204 BIT(12U), 0);
205 /* MICBIAS1 */
206 regmap_update_bits(nau8540->regmap, NAU8540_REG_MIC_BIAS,
207 BIT(10U), 0);
208 }
209
nau8540_adc_enable(bool enable)210 int nau8540_adc_enable(bool enable)
211 {
212 struct nau8540 *nau8540 = g_nau8540;
213
214 if (!g_nau8540) {
215 pr_err("FATAL: g_nau8540 is NULL.\n");
216 return -1;
217 }
218
219 if (enable) {
220 nau8540_powerup(nau8540);
221 msleep(300U);
222 /* DO12 and DO34 pad output enable */
223 regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL1,
224 NAU8540_I2S_DO12_TRI, 0);
225 regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL2,
226 NAU8540_I2S_DO34_TRI, 0);
227 } else {
228 regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL1,
229 NAU8540_I2S_DO12_TRI, NAU8540_I2S_DO12_TRI);
230 regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL2,
231 NAU8540_I2S_DO34_TRI, NAU8540_I2S_DO34_TRI);
232 nau8540_powerdown(nau8540);
233 /* reset */
234 regmap_write(nau8540->regmap, NAU8540_REG_RST, 0x0001);
235 regmap_write(nau8540->regmap, NAU8540_REG_RST, 0x0000);
236 }
237
238 pr_info("%s(%d) SUCCESS\n", __FUNCTION__, enable);
239 return 0;
240 }
241
nau8540_clock_check(struct nau8540 * nau8540,int rate,int osr)242 static int nau8540_clock_check(struct nau8540 *nau8540, int rate, int osr)
243 {
244 if (osr >= ARRAY_SIZE(osr_adc_sel)) {
245 return -EINVAL;
246 }
247
248 if (rate * osr > CLK_ADC_MAX) {
249 dev_err(nau8540->dev, "exceed the maximum frequency of CLK_ADC\n");
250 return -EINVAL;
251 }
252
253 return 0;
254 }
255
nau8540_set_sysclk(int clk_id)256 static int nau8540_set_sysclk(int clk_id)
257 {
258 struct nau8540 *nau8540 = g_nau8540;
259
260 switch (clk_id) {
261 case NAU8540_CLK_DIS:
262 case NAU8540_CLK_MCLK:
263 regmap_update_bits(nau8540->regmap, NAU8540_REG_CLOCK_SRC,
264 NAU8540_CLK_SRC_MASK, NAU8540_CLK_SRC_MCLK);
265 regmap_update_bits(nau8540->regmap, NAU8540_REG_FLL6,
266 NAU8540_DCO_EN, 0);
267 break;
268 case NAU8540_CLK_INTERNAL:
269 regmap_update_bits(nau8540->regmap, NAU8540_REG_FLL6,
270 NAU8540_DCO_EN, NAU8540_DCO_EN);
271 regmap_update_bits(nau8540->regmap, NAU8540_REG_CLOCK_SRC,
272 NAU8540_CLK_SRC_MASK, NAU8540_CLK_SRC_VCO);
273 break;
274 default:
275 dev_err(nau8540->dev, "Invalid clock id (%d)\n", clk_id);
276 return -EINVAL;
277 }
278
279 dev_dbg(nau8540->dev, "clock id is %d\n", clk_id);
280
281 return 0;
282 }
283
nau8540_hw_params(unsigned int rate,unsigned int bit_width)284 int nau8540_hw_params(unsigned int rate, unsigned int bit_width)
285 {
286 int ret;
287 struct nau8540 *nau8540 = g_nau8540;
288 unsigned int val_len = 0, osr;
289
290 if (!g_nau8540) {
291 pr_err("FATAL: g_nau8540 is NULL.\n");
292 return -1;
293 }
294
295 ret = nau8540_set_sysclk(NAU8540_CLK_DIS);
296 if (ret) {
297 return ret;
298 }
299
300 /* CLK_ADC = OSR * FS
301 * ADC clock frequency is defined as Over Sampling Rate (OSR)
302 * multiplied by the audio sample rate (Fs). Note that the OSR and Fs
303 * values must be selected such that the maximum frequency is less
304 * than 6.144 MHz.
305 */
306 regmap_read(nau8540->regmap, NAU8540_REG_ADC_SAMPLE_RATE, &osr);
307 osr &= NAU8540_ADC_OSR_MASK;
308 if (nau8540_clock_check(nau8540, rate, osr)) {
309 return -EINVAL;
310 }
311
312 regmap_update_bits(nau8540->regmap, NAU8540_REG_CLOCK_SRC,
313 NAU8540_CLK_ADC_SRC_MASK,
314 osr_adc_sel[osr].clk_src << NAU8540_CLK_ADC_SRC_SFT);
315
316 switch (bit_width) {
317 case AXG_BIT_WIDTH16:
318 val_len |= NAU8540_I2S_DL_16;
319 break;
320 case AXG_BIT_WIDTH20:
321 val_len |= NAU8540_I2S_DL_20;
322 break;
323 case AXG_BIT_WIDTH24:
324 val_len |= NAU8540_I2S_DL_24;
325 break;
326 case AXG_BIT_WIDTH32:
327 val_len |= NAU8540_I2S_DL_32;
328 break;
329 default:
330 return -EINVAL;
331 }
332
333 regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL0,
334 NAU8540_I2S_DL_MASK, val_len);
335
336 pr_info("%s(rate=%u, bit_width=%u) SUCCESS\n",
337 __FUNCTION__, rate, bit_width);
338 return 0;
339 }
340
nau8540_fmt_ctrl_val_determine(unsigned int fmt,unsigned int * pctrl1_val,unsigned int * pctrl2_val)341 static int nau8540_fmt_ctrl_val_determine(unsigned int fmt,
342 unsigned int *pctrl1_val,
343 unsigned int *pctrl2_val)
344 {
345 *pctrl1_val = 0;
346 *pctrl2_val = 0;
347
348 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
349 case SND_SOC_DAIFMT_CBM_CFM:
350 *pctrl2_val |= NAU8540_I2S_MS_MASTER;
351 break;
352 case SND_SOC_DAIFMT_CBS_CFS:
353 break;
354 default:
355 return -EINVAL;
356 }
357
358 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
359 case SND_SOC_DAIFMT_NB_NF:
360 break;
361 case SND_SOC_DAIFMT_IB_NF:
362 *pctrl1_val |= NAU8540_I2S_BP_INV;
363 break;
364 default:
365 return -EINVAL;
366 }
367
368 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
369 case SND_SOC_DAIFMT_I2S:
370 *pctrl1_val |= NAU8540_I2S_DF_I2S;
371 break;
372 case SND_SOC_DAIFMT_LEFT_J:
373 *pctrl1_val |= NAU8540_I2S_DF_LEFT;
374 break;
375 case SND_SOC_DAIFMT_RIGHT_J:
376 *pctrl1_val |= NAU8540_I2S_DF_RIGTH;
377 break;
378 case SND_SOC_DAIFMT_DSP_A:
379 *pctrl1_val |= NAU8540_I2S_DF_PCM_AB;
380 break;
381 case SND_SOC_DAIFMT_DSP_B:
382 *pctrl1_val |= NAU8540_I2S_DF_PCM_AB;
383 *pctrl1_val |= NAU8540_I2S_PCMB_EN;
384 break;
385 default:
386 return -EINVAL;
387 }
388
389 return 0;
390 }
391
nau8540_set_fmt(unsigned int fmt)392 int nau8540_set_fmt(unsigned int fmt)
393 {
394 struct nau8540 *nau8540 = g_nau8540;
395 unsigned int ctrl1_val = 0, ctrl2_val = 0;
396 int ret;
397
398 if (!g_nau8540) {
399 pr_err("FATAL: g_nau8540 is NULL.\n");
400 return -1;
401 }
402
403 ret = nau8540_fmt_ctrl_val_determine(fmt, &ctrl1_val, &ctrl2_val);
404 if (ret) {
405 pr_err("nau8540_fmt_ctrl_val_determine failed: %d\n", ret);
406 return ret;
407 }
408
409 regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL0,
410 NAU8540_I2S_DL_MASK | NAU8540_I2S_DF_MASK |
411 NAU8540_I2S_BP_INV | NAU8540_I2S_PCMB_EN,
412 ctrl1_val);
413 regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL1,
414 NAU8540_I2S_MS_MASK | NAU8540_I2S_DO12_OE,
415 ctrl2_val);
416 regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL2,
417 NAU8540_I2S_DO34_OE,
418 0);
419
420 pr_info("%s(fmt=0x%x) SUCCESS\n", __FUNCTION__, fmt);
421 return 0;
422 }
423
424 /**
425 * nau8540_set_tdm_slot - configure DAI TX TDM.
426 * @dai: DAI
427 * @tx_mask: bitmask representing active TX slots. Ex.
428 * 0xf for normal 4 channel TDM.
429 * 0xf0 for shifted 4 channel TDM
430 * @rx_mask: no used.
431 * @slots: Number of slots in use.
432 * @slot_width: Width in bits for each slot.
433 *
434 * Configures a DAI for TDM operation. Only support 4 slots TDM.
435 */
nau8540_set_tdm_slot(unsigned int tx_mask,unsigned int rx_mask,int slots,int slot_width)436 int nau8540_set_tdm_slot(unsigned int tx_mask,
437 unsigned int rx_mask, int slots, int slot_width)
438 {
439 struct nau8540 *nau8540 = g_nau8540;
440 unsigned int ctrl2_val = 0, ctrl4_val = 0;
441
442 if (!g_nau8540) {
443 pr_err("FATAL: g_nau8540 is NULL.\n");
444 return -1;
445 }
446
447 if (slots > 4U || ((tx_mask & 0xf0) && (tx_mask & 0xf))) {
448 return -EINVAL;
449 }
450
451 ctrl4_val |= (NAU8540_TDM_MODE | NAU8540_TDM_OFFSET_EN);
452 if (tx_mask & 0xf0) {
453 ctrl2_val = 4U * slot_width;
454 ctrl4_val |= (tx_mask >> 4U);
455 } else {
456 ctrl4_val |= tx_mask;
457 }
458 regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL4,
459 NAU8540_TDM_MODE | NAU8540_TDM_OFFSET_EN |
460 NAU8540_TDM_TX_MASK,
461 ctrl4_val);
462 regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL1,
463 NAU8540_I2S_DO12_OE, NAU8540_I2S_DO12_OE);
464 regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL2,
465 NAU8540_I2S_DO34_OE | NAU8540_I2S_TSLOT_L_MASK,
466 NAU8540_I2S_DO34_OE | ctrl2_val);
467
468 pr_info("%s(tx_mask=0x%x, rx_mask=0x%x, slots=%d, slot_width=%d) SUCCESS\n",
469 __FUNCTION__, tx_mask, rx_mask, slots, slot_width);
470 return 0;
471 }
472
473 /**
474 * nau8540_calc_fll_param - Calculate FLL parameters.
475 * @fll_in: external clock provided to codec.
476 * @fs: sampling rate.
477 * @fll_param: Pointer to structure of FLL parameters.
478 *
479 * Calculate FLL parameters to configure codec.
480 *
481 * Returns 0 for success or negative error code.
482 */
nau8540_calc_fll_param(unsigned int fll_in,unsigned int fs,struct nau8540_fll * fll_param)483 static int nau8540_calc_fll_param(unsigned int fll_in,
484 unsigned int fs, struct nau8540_fll *fll_param)
485 {
486 u64 fvco, fvco_max;
487 unsigned int fref, i, fvco_sel;
488
489 /* Ensure the reference clock frequency (FREF) is <= 13.5MHz by dividing
490 * freq_in by 1, 2, 4, or 8 using FLL pre-scalar.
491 * FREF = freq_in / NAU8540_FLL_REF_DIV_MASK
492 */
493 for (i = 0; i < ARRAY_SIZE(fll_pre_scalar); i++) {
494 fref = fll_in / fll_pre_scalar[i].param;
495 if (fref <= NAU_FREF_MAX) {
496 break;
497 }
498 }
499 if (i == ARRAY_SIZE(fll_pre_scalar)) {
500 return -EINVAL;
501 }
502
503 fll_param->clk_ref_div = fll_pre_scalar[i].val;
504
505 /* Choose the FLL ratio based on FREF */
506 for (i = 0; i < ARRAY_SIZE(fll_ratio); i++) {
507 if (fref >= fll_ratio[i].param) {
508 break;
509 }
510 }
511 if (i == ARRAY_SIZE(fll_ratio)) {
512 return -EINVAL;
513 }
514
515 fll_param->ratio = fll_ratio[i].val;
516
517 /* Calculate the frequency of DCO (FDCO) given freq_out = 256 * Fs.
518 * FDCO must be within the 90MHz - 124MHz or the FFL cannot be
519 * guaranteed across the full range of operation.
520 * FDCO = freq_out * 2 * mclk_src_scaling
521 */
522 fvco_max = 0;
523 fvco_sel = ARRAY_SIZE(mclk_src_scaling);
524 for (i = 0; i < ARRAY_SIZE(mclk_src_scaling); i++) {
525 fvco = 256ULL * fs * 2ULL * mclk_src_scaling[i].param;
526 if (fvco > NAU_FVCO_MIN && fvco < NAU_FVCO_MAX &&
527 fvco_max < fvco) {
528 fvco_max = fvco;
529 fvco_sel = i;
530 }
531 }
532 if (ARRAY_SIZE(mclk_src_scaling) == fvco_sel) {
533 return -EINVAL;
534 }
535
536 fll_param->mclk_src = mclk_src_scaling[fvco_sel].val;
537
538 /* Calculate the FLL 10-bit integer input and the FLL 16-bit fractional
539 * input based on FDCO, FREF and FLL ratio.
540 */
541 fvco = div_u64(fvco_max << 16U, fref * fll_param->ratio);
542 fll_param->fll_int = (fvco >> 16U) & 0x3FF;
543 fll_param->fll_frac = fvco & 0xFFFF;
544 return 0;
545 }
546
nau8540_fll_apply(struct regmap * regmap,struct nau8540_fll * fll_param)547 static void nau8540_fll_apply(struct regmap *regmap,
548 struct nau8540_fll *fll_param)
549 {
550 regmap_update_bits(regmap, NAU8540_REG_CLOCK_SRC,
551 NAU8540_CLK_SRC_MASK | NAU8540_CLK_MCLK_SRC_MASK,
552 NAU8540_CLK_SRC_MCLK | fll_param->mclk_src);
553 regmap_update_bits(regmap, NAU8540_REG_FLL1,
554 NAU8540_FLL_RATIO_MASK | NAU8540_ICTRL_LATCH_MASK,
555 fll_param->ratio | (0x6 << NAU8540_ICTRL_LATCH_SFT));
556 /* FLL 16-bit fractional input */
557 regmap_write(regmap, NAU8540_REG_FLL2, fll_param->fll_frac);
558 /* FLL 10-bit integer input */
559 regmap_update_bits(regmap, NAU8540_REG_FLL3,
560 NAU8540_FLL_INTEGER_MASK, fll_param->fll_int);
561 /* FLL pre-scaler */
562 regmap_update_bits(regmap, NAU8540_REG_FLL4,
563 NAU8540_FLL_REF_DIV_MASK,
564 fll_param->clk_ref_div << NAU8540_FLL_REF_DIV_SFT);
565 regmap_update_bits(regmap, NAU8540_REG_FLL5,
566 NAU8540_FLL_CLK_SW_MASK, NAU8540_FLL_CLK_SW_REF);
567 regmap_update_bits(regmap,
568 NAU8540_REG_FLL6, NAU8540_DCO_EN, 0);
569 if (fll_param->fll_frac) {
570 regmap_update_bits(regmap, NAU8540_REG_FLL5,
571 NAU8540_FLL_PDB_DAC_EN | NAU8540_FLL_LOOP_FTR_EN |
572 NAU8540_FLL_FTR_SW_MASK,
573 NAU8540_FLL_PDB_DAC_EN | NAU8540_FLL_LOOP_FTR_EN |
574 NAU8540_FLL_FTR_SW_FILTER);
575 regmap_update_bits(regmap, NAU8540_REG_FLL6,
576 NAU8540_SDM_EN | NAU8540_CUTOFF500,
577 NAU8540_SDM_EN | NAU8540_CUTOFF500);
578 } else {
579 regmap_update_bits(regmap, NAU8540_REG_FLL5,
580 NAU8540_FLL_PDB_DAC_EN | NAU8540_FLL_LOOP_FTR_EN |
581 NAU8540_FLL_FTR_SW_MASK,
582 NAU8540_FLL_FTR_SW_ACCU);
583 regmap_update_bits(regmap, NAU8540_REG_FLL6,
584 NAU8540_SDM_EN | NAU8540_CUTOFF500, 0);
585 }
586 }
587
588 /* freq_out must be 256*Fs in order to achieve the best performance */
nau8540_set_pll(int pll_id,unsigned int freq_in,unsigned int freq_out)589 int nau8540_set_pll(int pll_id, unsigned int freq_in,
590 unsigned int freq_out)
591 {
592 struct nau8540 *nau8540 = g_nau8540;
593 struct nau8540_fll fll_param;
594 int ret, fs;
595
596 if (!g_nau8540) {
597 pr_err("FATAL: g_nau8540 is NULL.\n");
598 return -1;
599 }
600
601 switch (pll_id) {
602 case NAU8540_CLK_FLL_MCLK:
603 regmap_update_bits(nau8540->regmap, NAU8540_REG_FLL3,
604 NAU8540_FLL_CLK_SRC_MASK | NAU8540_GAIN_ERR_MASK,
605 NAU8540_FLL_CLK_SRC_MCLK | 0);
606 break;
607 case NAU8540_CLK_FLL_BLK:
608 regmap_update_bits(nau8540->regmap, NAU8540_REG_FLL3,
609 NAU8540_FLL_CLK_SRC_MASK | NAU8540_GAIN_ERR_MASK,
610 NAU8540_FLL_CLK_SRC_BLK |
611 (0xf << NAU8540_GAIN_ERR_SFT));
612 break;
613 case NAU8540_CLK_FLL_FS:
614 regmap_update_bits(nau8540->regmap, NAU8540_REG_FLL3,
615 NAU8540_FLL_CLK_SRC_MASK | NAU8540_GAIN_ERR_MASK,
616 NAU8540_FLL_CLK_SRC_FS |
617 (0xf << NAU8540_GAIN_ERR_SFT));
618 break;
619
620 default:
621 dev_err(nau8540->dev, "Invalid clock id (%d)\n", pll_id);
622 return -EINVAL;
623 }
624 dev_dbg(nau8540->dev, "Sysclk is %dHz and clock id is %d\n",
625 freq_out, pll_id);
626
627 fs = freq_out / 256U;
628 ret = nau8540_calc_fll_param(freq_in, fs, &fll_param);
629 if (ret < 0) {
630 dev_err(nau8540->dev, "Unsupported input clock %d\n", freq_in);
631 return ret;
632 }
633 dev_info(nau8540->dev, "mclk_src=%x ratio=%x fll_frac=%x fll_int=%x clk_ref_div=%x\n",
634 fll_param.mclk_src, fll_param.ratio, fll_param.fll_frac,
635 fll_param.fll_int, fll_param.clk_ref_div);
636
637 nau8540_fll_apply(nau8540->regmap, &fll_param);
638 mdelay(2U);
639 regmap_update_bits(nau8540->regmap, NAU8540_REG_CLOCK_SRC,
640 NAU8540_CLK_SRC_MASK, NAU8540_CLK_SRC_VCO);
641
642 return 0;
643 }
644
nau8540_reset_chip(struct regmap * regmap)645 static void nau8540_reset_chip(struct regmap *regmap)
646 {
647 regmap_write(regmap, NAU8540_REG_SW_RESET, 0x00);
648 regmap_write(regmap, NAU8540_REG_SW_RESET, 0x00);
649 }
650
nau8540_init_regs(struct nau8540 * nau8540)651 static void nau8540_init_regs(struct nau8540 *nau8540)
652 {
653 struct regmap *regmap = nau8540->regmap;
654
655 /* Enable Bias/VMID/VMID Tieoff */
656 regmap_update_bits(regmap, NAU8540_REG_VMID_CTRL,
657 NAU8540_VMID_EN | NAU8540_VMID_SEL_MASK,
658 NAU8540_VMID_EN | (0x2 << NAU8540_VMID_SEL_SFT));
659 regmap_update_bits(regmap, NAU8540_REG_REFERENCE,
660 NAU8540_PRECHARGE_DIS | NAU8540_GLOBAL_BIAS_EN,
661 NAU8540_PRECHARGE_DIS | NAU8540_GLOBAL_BIAS_EN);
662 mdelay(2U);
663 regmap_update_bits(regmap, NAU8540_REG_MIC_BIAS,
664 NAU8540_PU_PRE, NAU8540_PU_PRE);
665 regmap_update_bits(regmap, NAU8540_REG_CLOCK_CTRL,
666 NAU8540_CLK_ADC_EN | NAU8540_CLK_I2S_EN,
667 NAU8540_CLK_ADC_EN | NAU8540_CLK_I2S_EN);
668 /* ADC OSR selection, CLK_ADC = Fs * OSR;
669 * Channel time alignment enable.
670 */
671 regmap_update_bits(regmap, NAU8540_REG_ADC_SAMPLE_RATE,
672 NAU8540_CH_SYNC | NAU8540_ADC_OSR_MASK,
673 NAU8540_CH_SYNC | NAU8540_ADC_OSR_128);
674 /* PGA input mode selection */
675 regmap_update_bits(regmap, NAU8540_REG_FEPGA1,
676 NAU8540_FEPGA1_MODCH2_SHT | NAU8540_FEPGA1_MODCH1_SHT,
677 NAU8540_FEPGA1_MODCH2_SHT | NAU8540_FEPGA1_MODCH1_SHT);
678 regmap_update_bits(regmap, NAU8540_REG_FEPGA2,
679 NAU8540_FEPGA2_MODCH4_SHT | NAU8540_FEPGA2_MODCH3_SHT,
680 NAU8540_FEPGA2_MODCH4_SHT | NAU8540_FEPGA2_MODCH3_SHT);
681 /* DO12 and DO34 pad output disable */
682 regmap_update_bits(regmap, NAU8540_REG_PCM_CTRL1,
683 NAU8540_I2S_DO12_TRI, NAU8540_I2S_DO12_TRI);
684 regmap_update_bits(regmap, NAU8540_REG_PCM_CTRL2,
685 NAU8540_I2S_DO34_TRI, NAU8540_I2S_DO34_TRI);
686 /* Update 14th bit always out */
687 regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL1,
688 0x4000, 0X4000);
689 regmap_write(nau8540->regmap, NAU8540_REG_FEPGA3, 0x1717);
690 regmap_write(nau8540->regmap, NAU8540_REG_DIGITAL_GAIN_CH1, 0x0520);
691 regmap_write(nau8540->regmap, NAU8540_REG_DIGITAL_GAIN_CH2, 0x0520);
692 regmap_write(nau8540->regmap, NAU8540_REG_DIGITAL_GAIN_CH3, 0x0520);
693 regmap_write(nau8540->regmap, NAU8540_REG_DIGITAL_GAIN_CH4, 0x0520);
694 regmap_write(nau8540->regmap, NAU8540_REG_DIGITAL_MUX, 0x0000);
695 regmap_write(nau8540->regmap, NAU8540_REG_HPF_FILTER_CH12, 0x1F1F);
696 regmap_write(nau8540->regmap, NAU8540_REG_HPF_FILTER_CH34, 0x1F1F);
697 }
698
nau8540_suspend(void)699 int nau8540_suspend(void)
700 {
701 struct nau8540 *nau8540 = g_nau8540;
702
703 if (!g_nau8540) {
704 pr_err("FATAL: g_nau8540 is NULL.\n");
705 return -1;
706 }
707
708 regcache_cache_only(nau8540->regmap, true);
709 regcache_mark_dirty(nau8540->regmap);
710
711 return 0;
712 }
713
nau8540_resume(void)714 int nau8540_resume(void)
715 {
716 struct nau8540 *nau8540 = g_nau8540;
717
718 if (!g_nau8540) {
719 pr_err("FATAL: g_nau8540 is NULL.\n");
720 return -1;
721 }
722
723 regcache_cache_only(nau8540->regmap, false);
724 regcache_sync(nau8540->regmap);
725
726 return 0;
727 }
728
729 static const struct regmap_config nau8540_regmap_config = {
730 .val_bits = 16,
731 .reg_bits = 16,
732
733 .max_register = NAU8540_REG_MAX,
734 .readable_reg = nau8540_readable_reg,
735 .writeable_reg = nau8540_writeable_reg,
736 .volatile_reg = nau8540_volatile_reg,
737
738 .cache_type = REGCACHE_RBTREE,
739 .reg_defaults = nau8540_reg_defaults,
740 .num_reg_defaults = ARRAY_SIZE(nau8540_reg_defaults),
741 };
742
nau8540_i2c_probe(struct i2c_client * i2c,const struct i2c_device_id * id)743 static int nau8540_i2c_probe(struct i2c_client *i2c,
744 const struct i2c_device_id *id)
745 {
746 struct device *dev = &i2c->dev;
747 struct nau8540 *nau8540 = dev_get_platdata(dev);
748 int ret, value;
749
750 if (!nau8540) {
751 nau8540 = devm_kzalloc(dev, sizeof(*nau8540), GFP_KERNEL);
752 if (!nau8540) {
753 return -ENOMEM;
754 }
755 }
756 i2c_set_clientdata(i2c, nau8540);
757
758 nau8540->regmap = devm_regmap_init_i2c(i2c, &nau8540_regmap_config);
759 if (IS_ERR(nau8540->regmap)) {
760 return PTR_ERR(nau8540->regmap);
761 }
762
763 ret = regmap_read(nau8540->regmap, NAU8540_REG_I2C_DEVICE_ID, &value);
764 if (ret < 0) {
765 dev_err(dev, "Failed to read device id from the NAU85L40: %d\n", ret);
766 return ret;
767 }
768
769 nau8540->dev = dev;
770 nau8540_reset_chip(nau8540->regmap);
771 nau8540_init_regs(nau8540);
772
773 g_nau8540 = nau8540;
774
775 dev_info(dev, "nau8540 probe SUCCESS\n");
776 return 0;
777 }
778
779 static const struct i2c_device_id nau8540_i2c_ids[] = {
780 { "nau8540", 0 },
781 {}
782 };
783 MODULE_DEVICE_TABLE(i2c, nau8540_i2c_ids);
784
785 static const struct of_device_id nau8540_of_ids[] = {
786 { .compatible = "nuvoton,nau8540", },
787 {}
788 };
789 MODULE_DEVICE_TABLE(of, nau8540_of_ids);
790
791 static struct i2c_driver nau8540_i2c_driver = {
792 .driver = {
793 .name = "nau8540",
794 .of_match_table = of_match_ptr(nau8540_of_ids),
795 },
796 .probe = nau8540_i2c_probe,
797 .id_table = nau8540_i2c_ids,
798 };
799 module_i2c_driver(nau8540_i2c_driver);
800
801