1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2022 Unionman Technology Co., Ltd. 4 * Copyright (c) 2018 Amlogic, Inc. All rights reserved. 5 */ 6 7#include <dt-bindings/phy/phy.h> 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/clock/g12a-clkc.h> 10#include <dt-bindings/clock/g12a-aoclkc.h> 11#include <dt-bindings/interrupt-controller/irq.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13#include <dt-bindings/reset/amlogic,meson-g12a-reset.h> 14#include <dt-bindings/thermal/thermal.h> 15 16/ { 17 interrupt-parent = <&gic>; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 aliases { 22 mmc0 = &sd_emmc_c; /* eMMC */ 23 mmc1 = &sd_emmc_b; /* SD card */ 24 mmc2 = &sd_emmc_a; /* SDIO */ 25 }; 26 27 chosen { 28 #address-cells = <2>; 29 #size-cells = <2>; 30 ranges; 31 32 simplefb_cvbs: framebuffer-cvbs { 33 compatible = "amlogic,simple-framebuffer", 34 "simple-framebuffer"; 35 amlogic,pipeline = "vpu-cvbs"; 36 clocks = <&clkc CLKID_HDMI>, 37 <&clkc CLKID_HTX_PCLK>, 38 <&clkc CLKID_VPU_INTR>; 39 status = "disabled"; 40 }; 41 42 simplefb_hdmi: framebuffer-hdmi { 43 compatible = "amlogic,simple-framebuffer", 44 "simple-framebuffer"; 45 amlogic,pipeline = "vpu-hdmi"; 46 clocks = <&clkc CLKID_HDMI>, 47 <&clkc CLKID_HTX_PCLK>, 48 <&clkc CLKID_VPU_INTR>; 49 status = "disabled"; 50 }; 51 }; 52 53 system-suspend { 54 compatible = "amlogic,meson-gx-pm"; 55 }; 56 57 efuse: efuse { 58 compatible = "amlogic,meson-gxbb-efuse"; 59 clocks = <&clkc CLKID_EFUSE>; 60 #address-cells = <1>; 61 #size-cells = <1>; 62 read-only; 63 secure-monitor = <&sm>; 64 }; 65 66 gpu_opp_table: gpu-opp-table { 67 compatible = "operating-points-v2"; 68 69 opp-249999996 { 70 opp-hz = /bits/ 64 <249999996>; 71 opp-microvolt = <800000>; 72 }; 73 opp-285714281 { 74 opp-hz = /bits/ 64 <285714281>; 75 opp-microvolt = <800000>; 76 }; 77 opp-399999994 { 78 opp-hz = /bits/ 64 <399999994>; 79 opp-microvolt = <800000>; 80 }; 81 opp-499999992 { 82 opp-hz = /bits/ 64 <499999992>; 83 opp-microvolt = <800000>; 84 }; 85 opp-666666656 { 86 opp-hz = /bits/ 64 <666666656>; 87 opp-microvolt = <800000>; 88 }; 89 opp-799999987 { 90 opp-hz = /bits/ 64 <799999987>; 91 opp-microvolt = <800000>; 92 }; 93 }; 94 95 psci { 96 compatible = "arm,psci-1.0"; 97 method = "smc"; 98 }; 99 100 reserved-memory { 101 #address-cells = <2>; 102 #size-cells = <2>; 103 ranges; 104 105 /* 3 MiB reserved for ARM Trusted Firmware (BL31) */ 106 secmon_reserved:linux,secmon { 107 compatible = "shared-dma-pool"; 108 reusable; 109 size = <0x0 0x3400000>; 110 alignment = <0x0 0x400000>; 111 alloc-ranges = <0x0 0x05000000 0x0 0x3400000>; 112 clear-map; 113 }; 114 115 linux,cma { 116 compatible = "shared-dma-pool"; 117 reusable; 118 size = <0x0 0x38000000>; 119 alignment = <0x0 0x400000>; 120 linux,cma-default; 121 }; 122 }; 123 124 sm: secure-monitor { 125 compatible = "amlogic,meson-gxbb-sm"; 126 }; 127 128 secmon { 129 compatible = "amlogic, secmon"; 130 memory-region = <&secmon_reserved>; 131 in_base_func = <0x82000020>; 132 out_base_func = <0x82000021>; 133 inout_size_func = <0x8200002a>; 134 reserve_mem_size = <0x00300000>; 135 clear_range = <0x05100000 0x200000>; 136 }; 137 138 soc { 139 compatible = "simple-bus"; 140 #address-cells = <2>; 141 #size-cells = <2>; 142 ranges; 143 144 pcie: pcie@fc000000 { 145 compatible = "amlogic,g12a-pcie", "snps,dw-pcie"; 146 reg = <0x0 0xfc000000 0x0 0x400000 147 0x0 0xff648000 0x0 0x2000 148 0x0 0xfc400000 0x0 0x200000>; 149 reg-names = "elbi", "cfg", "config"; 150 interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 151 #interrupt-cells = <1>; 152 interrupt-map-mask = <0 0 0 0>; 153 interrupt-map = <0 0 0 0 &gic GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 154 bus-range = <0x0 0xff>; 155 #address-cells = <3>; 156 #size-cells = <2>; 157 device_type = "pci"; 158 ranges = <0x81000000 0 0 0x0 0xfc600000 0 0x00100000 159 0x82000000 0 0xfc700000 0x0 0xfc700000 0 0x1900000>; 160 161 clocks = <&clkc CLKID_PCIE_PHY 162 &clkc CLKID_PCIE_COMB 163 &clkc CLKID_PCIE_PLL>; 164 clock-names = "general", 165 "pclk", 166 "port"; 167 resets = <&reset RESET_PCIE_CTRL_A>, 168 <&reset RESET_PCIE_APB>; 169 reset-names = "port", 170 "apb"; 171 num-lanes = <1>; 172 phys = <&usb3_pcie_phy PHY_TYPE_PCIE>; 173 phy-names = "pcie"; 174 status = "disabled"; 175 }; 176 177 thermal-zones { 178 cpu_thermal: cpu-thermal { 179 polling-delay = <1000>; 180 polling-delay-passive = <100>; 181 thermal-sensors = <&cpu_temp>; 182 183 trips { 184 cpu_passive: cpu-passive { 185 temperature = <85000>; /* millicelsius */ 186 hysteresis = <2000>; /* millicelsius */ 187 type = "passive"; 188 }; 189 190 cpu_hot: cpu-hot { 191 temperature = <95000>; /* millicelsius */ 192 hysteresis = <2000>; /* millicelsius */ 193 type = "hot"; 194 }; 195 196 cpu_critical: cpu-critical { 197 temperature = <110000>; /* millicelsius */ 198 hysteresis = <2000>; /* millicelsius */ 199 type = "critical"; 200 }; 201 }; 202 }; 203 204 ddr_thermal: ddr-thermal { 205 polling-delay = <1000>; 206 polling-delay-passive = <100>; 207 thermal-sensors = <&ddr_temp>; 208 209 trips { 210 ddr_passive: ddr-passive { 211 temperature = <85000>; /* millicelsius */ 212 hysteresis = <2000>; /* millicelsius */ 213 type = "passive"; 214 }; 215 216 ddr_critical: ddr-critical { 217 temperature = <110000>; /* millicelsius */ 218 hysteresis = <2000>; /* millicelsius */ 219 type = "critical"; 220 }; 221 }; 222 223 cooling-maps { 224 map { 225 trip = <&ddr_passive>; 226 cooling-device = <&mali THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 227 }; 228 }; 229 }; 230 }; 231 232 ethmac: ethernet@ff3f0000 { 233 compatible = "amlogic,meson-g12a-dwmac", 234 "snps,dwmac-3.70a", 235 "snps,dwmac"; 236 reg = <0x0 0xff3f0000 0x0 0x10000>, 237 <0x0 0xff634540 0x0 0x8>; 238 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 239 interrupt-names = "macirq"; 240 clocks = <&clkc CLKID_ETH>, 241 <&clkc CLKID_FCLK_DIV2>, 242 <&clkc CLKID_MPLL2>, 243 <&clkc CLKID_FCLK_DIV2>; 244 clock-names = "stmmaceth", "clkin0", "clkin1", 245 "timing-adjustment"; 246 rx-fifo-depth = <4096>; 247 tx-fifo-depth = <2048>; 248 resets = <&reset RESET_ETHERNET>; 249 reset-names = "stmmaceth"; 250 status = "disabled"; 251 252 mdio0: mdio { 253 #address-cells = <1>; 254 #size-cells = <0>; 255 compatible = "snps,dwmac-mdio"; 256 }; 257 }; 258 259 apb: bus@ff600000 { 260 compatible = "simple-bus"; 261 reg = <0x0 0xff600000 0x0 0x200000>; 262 #address-cells = <2>; 263 #size-cells = <2>; 264 ranges = <0x0 0x0 0x0 0xff600000 0x0 0x200000>; 265 266 hdmi_tx: hdmi-tx@0 { 267 compatible = "amlogic,meson-g12a-dw-hdmi"; 268 reg = <0x0 0x0 0x0 0x10000>; 269 interrupts = <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>; 270 resets = <&reset RESET_HDMITX_CAPB3>, 271 <&reset RESET_HDMITX_PHY>, 272 <&reset RESET_HDMITX>; 273 reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy"; 274 clocks = <&clkc CLKID_HDMI>, 275 <&clkc CLKID_HTX_PCLK>, 276 <&clkc CLKID_VPU_INTR>; 277 clock-names = "isfr", "iahb", "venci"; 278 #address-cells = <1>; 279 #size-cells = <0>; 280 #sound-dai-cells = <0>; 281 status = "disabled"; 282 283 /* VPU VENC Input */ 284 hdmi_tx_venc_port: port@0 { 285 reg = <0>; 286 287 hdmi_tx_in: endpoint { 288 remote-endpoint = <&hdmi_tx_out>; 289 }; 290 }; 291 292 /* TMDS Output */ 293 hdmi_tx_tmds_port: port@1 { 294 reg = <1>; 295 }; 296 }; 297 298 apb_efuse: bus@30000 { 299 compatible = "simple-bus"; 300 reg = <0x0 0x30000 0x0 0x2000>; 301 #address-cells = <2>; 302 #size-cells = <2>; 303 ranges = <0x0 0x0 0x0 0x30000 0x0 0x2000>; 304 305 hwrng: rng@218 { 306 compatible = "amlogic,meson-rng"; 307 reg = <0x0 0x218 0x0 0x4>; 308 clocks = <&clkc CLKID_RNG0>; 309 clock-names = "core"; 310 }; 311 }; 312 313 acodec: audio-controller@32000 { 314 compatible = "amlogic,t9015"; 315 reg = <0x0 0x32000 0x0 0x14>; 316 #sound-dai-cells = <0>; 317 sound-name-prefix = "ACODEC"; 318 clocks = <&clkc CLKID_AUDIO_CODEC>; 319 clock-names = "pclk"; 320 resets = <&reset RESET_AUDIO_CODEC>; 321 status = "disabled"; 322 }; 323 324 periphs: bus@34400 { 325 compatible = "simple-bus"; 326 reg = <0x0 0x34400 0x0 0x400>; 327 #address-cells = <2>; 328 #size-cells = <2>; 329 ranges = <0x0 0x0 0x0 0x34400 0x0 0x400>; 330 331 periphs_pinctrl: pinctrl@40 { 332 compatible = "amlogic,meson-g12a-periphs-pinctrl"; 333 #address-cells = <2>; 334 #size-cells = <2>; 335 ranges; 336 337 gpio: bank@40 { 338 reg = <0x0 0x40 0x0 0x4c>, 339 <0x0 0xe8 0x0 0x18>, 340 <0x0 0x120 0x0 0x18>, 341 <0x0 0x2c0 0x0 0x40>, 342 <0x0 0x340 0x0 0x1c>; 343 reg-names = "gpio", 344 "pull", 345 "pull-enable", 346 "mux", 347 "ds"; 348 gpio-controller; 349 #gpio-cells = <2>; 350 gpio-ranges = <&periphs_pinctrl 0 0 86>; 351 }; 352 353 cec_ao_a_h_pins: cec_ao_a_h { 354 mux { 355 groups = "cec_ao_a_h"; 356 function = "cec_ao_a_h"; 357 bias-disable; 358 }; 359 }; 360 361 cec_ao_b_h_pins: cec_ao_b_h { 362 mux { 363 groups = "cec_ao_b_h"; 364 function = "cec_ao_b_h"; 365 bias-disable; 366 }; 367 }; 368 369 emmc_ctrl_pins: emmc-ctrl { 370 mux-0 { 371 groups = "emmc_cmd"; 372 function = "emmc"; 373 bias-pull-up; 374 drive-strength-microamp = <4000>; 375 }; 376 377 mux-1 { 378 groups = "emmc_clk"; 379 function = "emmc"; 380 bias-disable; 381 drive-strength-microamp = <4000>; 382 }; 383 }; 384 385 emmc_data_4b_pins: emmc-data-4b { 386 mux-0 { 387 groups = "emmc_nand_d0", 388 "emmc_nand_d1", 389 "emmc_nand_d2", 390 "emmc_nand_d3"; 391 function = "emmc"; 392 bias-pull-up; 393 drive-strength-microamp = <4000>; 394 }; 395 }; 396 397 emmc_data_8b_pins: emmc-data-8b { 398 mux-0 { 399 groups = "emmc_nand_d0", 400 "emmc_nand_d1", 401 "emmc_nand_d2", 402 "emmc_nand_d3", 403 "emmc_nand_d4", 404 "emmc_nand_d5", 405 "emmc_nand_d6", 406 "emmc_nand_d7"; 407 function = "emmc"; 408 bias-pull-up; 409 drive-strength-microamp = <4000>; 410 }; 411 }; 412 413 emmc_ds_pins: emmc-ds { 414 mux { 415 groups = "emmc_nand_ds"; 416 function = "emmc"; 417 bias-pull-down; 418 drive-strength-microamp = <4000>; 419 }; 420 }; 421 422 emmc_clk_gate_pins: emmc_clk_gate { 423 mux { 424 groups = "BOOT_8"; 425 function = "gpio_periphs"; 426 bias-pull-down; 427 drive-strength-microamp = <4000>; 428 }; 429 }; 430 431 hdmitx_ddc_pins: hdmitx_ddc { 432 mux { 433 groups = "hdmitx_sda", 434 "hdmitx_sck"; 435 function = "hdmitx"; 436 bias-disable; 437 drive-strength-microamp = <4000>; 438 }; 439 }; 440 441 hdmitx_hpd_pins: hdmitx_hpd { 442 mux { 443 groups = "hdmitx_hpd_in"; 444 function = "hdmitx"; 445 bias-disable; 446 }; 447 }; 448 449 450 i2c0_sda_c_pins: i2c0-sda-c { 451 mux { 452 groups = "i2c0_sda_c"; 453 function = "i2c0"; 454 bias-disable; 455 drive-strength-microamp = <3000>; 456 457 }; 458 }; 459 460 i2c0_sck_c_pins: i2c0-sck-c { 461 mux { 462 groups = "i2c0_sck_c"; 463 function = "i2c0"; 464 bias-disable; 465 drive-strength-microamp = <3000>; 466 }; 467 }; 468 469 i2c0_sda_z0_pins: i2c0-sda-z0 { 470 mux { 471 groups = "i2c0_sda_z0"; 472 function = "i2c0"; 473 bias-disable; 474 drive-strength-microamp = <3000>; 475 }; 476 }; 477 478 i2c0_sck_z1_pins: i2c0-sck-z1 { 479 mux { 480 groups = "i2c0_sck_z1"; 481 function = "i2c0"; 482 bias-disable; 483 drive-strength-microamp = <3000>; 484 }; 485 }; 486 487 i2c0_sda_z7_pins: i2c0-sda-z7 { 488 mux { 489 groups = "i2c0_sda_z7"; 490 function = "i2c0"; 491 bias-disable; 492 drive-strength-microamp = <3000>; 493 }; 494 }; 495 496 i2c0_sda_z8_pins: i2c0-sda-z8 { 497 mux { 498 groups = "i2c0_sda_z8"; 499 function = "i2c0"; 500 bias-disable; 501 drive-strength-microamp = <3000>; 502 }; 503 }; 504 505 i2c1_sda_x_pins: i2c1-sda-x { 506 mux { 507 groups = "i2c1_sda_x"; 508 function = "i2c1"; 509 bias-disable; 510 drive-strength-microamp = <3000>; 511 }; 512 }; 513 514 i2c1_sck_x_pins: i2c1-sck-x { 515 mux { 516 groups = "i2c1_sck_x"; 517 function = "i2c1"; 518 bias-disable; 519 drive-strength-microamp = <3000>; 520 }; 521 }; 522 523 i2c1_sda_h2_pins: i2c1-sda-h2 { 524 mux { 525 groups = "i2c1_sda_h2"; 526 function = "i2c1"; 527 bias-disable; 528 drive-strength-microamp = <3000>; 529 }; 530 }; 531 532 i2c1_sck_h3_pins: i2c1-sck-h3 { 533 mux { 534 groups = "i2c1_sck_h3"; 535 function = "i2c1"; 536 bias-disable; 537 drive-strength-microamp = <3000>; 538 }; 539 }; 540 541 i2c1_sda_h6_pins: i2c1-sda-h6 { 542 mux { 543 groups = "i2c1_sda_h6"; 544 function = "i2c1"; 545 bias-disable; 546 drive-strength-microamp = <3000>; 547 }; 548 }; 549 550 i2c1_sck_h7_pins: i2c1-sck-h7 { 551 mux { 552 groups = "i2c1_sck_h7"; 553 function = "i2c1"; 554 bias-disable; 555 drive-strength-microamp = <3000>; 556 }; 557 }; 558 559 i2c2_sda_x_pins: i2c2-sda-x { 560 mux { 561 groups = "i2c2_sda_x"; 562 function = "i2c2"; 563 bias-disable; 564 drive-strength-microamp = <3000>; 565 }; 566 }; 567 568 i2c2_sck_x_pins: i2c2-sck-x { 569 mux { 570 groups = "i2c2_sck_x"; 571 function = "i2c2"; 572 bias-disable; 573 drive-strength-microamp = <3000>; 574 }; 575 }; 576 577 i2c2_sda_z_pins: i2c2-sda-z { 578 mux { 579 groups = "i2c2_sda_z"; 580 function = "i2c2"; 581 bias-disable; 582 drive-strength-microamp = <3000>; 583 }; 584 }; 585 586 i2c2_sck_z_pins: i2c2-sck-z { 587 mux { 588 groups = "i2c2_sck_z"; 589 function = "i2c2"; 590 bias-disable; 591 drive-strength-microamp = <3000>; 592 }; 593 }; 594 595 i2c3_sda_h_pins: i2c3-sda-h { 596 mux { 597 groups = "i2c3_sda_h"; 598 function = "i2c3"; 599 bias-disable; 600 drive-strength-microamp = <3000>; 601 }; 602 }; 603 604 i2c3_sck_h_pins: i2c3-sck-h { 605 mux { 606 groups = "i2c3_sck_h"; 607 function = "i2c3"; 608 bias-disable; 609 drive-strength-microamp = <3000>; 610 }; 611 }; 612 613 i2c3_sda_a_pins: i2c3-sda-a { 614 mux { 615 groups = "i2c3_sda_a"; 616 function = "i2c3"; 617 bias-disable; 618 drive-strength-microamp = <3000>; 619 }; 620 }; 621 622 i2c3_sck_a_pins: i2c3-sck-a { 623 mux { 624 groups = "i2c3_sck_a"; 625 function = "i2c3"; 626 bias-disable; 627 drive-strength-microamp = <3000>; 628 }; 629 }; 630 631 mclk0_a_pins: mclk0-a { 632 mux { 633 groups = "mclk0_a"; 634 function = "mclk0"; 635 bias-disable; 636 drive-strength-microamp = <3000>; 637 }; 638 }; 639 640 mclk1_a_pins: mclk1-a { 641 mux { 642 groups = "mclk1_a"; 643 function = "mclk1"; 644 bias-disable; 645 drive-strength-microamp = <3000>; 646 }; 647 }; 648 649 mclk1_x_pins: mclk1-x { 650 mux { 651 groups = "mclk1_x"; 652 function = "mclk1"; 653 bias-disable; 654 drive-strength-microamp = <3000>; 655 }; 656 }; 657 658 mclk1_z_pins: mclk1-z { 659 mux { 660 groups = "mclk1_z"; 661 function = "mclk1"; 662 bias-disable; 663 drive-strength-microamp = <3000>; 664 }; 665 }; 666 667 nor_pins: nor { 668 mux { 669 groups = "nor_d", 670 "nor_q", 671 "nor_c", 672 "nor_cs"; 673 function = "nor"; 674 bias-disable; 675 }; 676 }; 677 678 pdm_din0_a_pins: pdm-din0-a { 679 mux { 680 groups = "pdm_din0_a"; 681 function = "pdm"; 682 bias-disable; 683 }; 684 }; 685 686 pdm_din0_c_pins: pdm-din0-c { 687 mux { 688 groups = "pdm_din0_c"; 689 function = "pdm"; 690 bias-disable; 691 }; 692 }; 693 694 pdm_din0_x_pins: pdm-din0-x { 695 mux { 696 groups = "pdm_din0_x"; 697 function = "pdm"; 698 bias-disable; 699 }; 700 }; 701 702 pdm_din0_z_pins: pdm-din0-z { 703 mux { 704 groups = "pdm_din0_z"; 705 function = "pdm"; 706 bias-disable; 707 }; 708 }; 709 710 pdm_din1_a_pins: pdm-din1-a { 711 mux { 712 groups = "pdm_din1_a"; 713 function = "pdm"; 714 bias-disable; 715 }; 716 }; 717 718 pdm_din1_c_pins: pdm-din1-c { 719 mux { 720 groups = "pdm_din1_c"; 721 function = "pdm"; 722 bias-disable; 723 }; 724 }; 725 726 pdm_din1_x_pins: pdm-din1-x { 727 mux { 728 groups = "pdm_din1_x"; 729 function = "pdm"; 730 bias-disable; 731 }; 732 }; 733 734 pdm_din1_z_pins: pdm-din1-z { 735 mux { 736 groups = "pdm_din1_z"; 737 function = "pdm"; 738 bias-disable; 739 }; 740 }; 741 742 pdm_din2_a_pins: pdm-din2-a { 743 mux { 744 groups = "pdm_din2_a"; 745 function = "pdm"; 746 bias-disable; 747 }; 748 }; 749 750 pdm_din2_c_pins: pdm-din2-c { 751 mux { 752 groups = "pdm_din2_c"; 753 function = "pdm"; 754 bias-disable; 755 }; 756 }; 757 758 pdm_din2_x_pins: pdm-din2-x { 759 mux { 760 groups = "pdm_din2_x"; 761 function = "pdm"; 762 bias-disable; 763 }; 764 }; 765 766 pdm_din2_z_pins: pdm-din2-z { 767 mux { 768 groups = "pdm_din2_z"; 769 function = "pdm"; 770 bias-disable; 771 }; 772 }; 773 774 pdm_din3_a_pins: pdm-din3-a { 775 mux { 776 groups = "pdm_din3_a"; 777 function = "pdm"; 778 bias-disable; 779 }; 780 }; 781 782 pdm_din3_c_pins: pdm-din3-c { 783 mux { 784 groups = "pdm_din3_c"; 785 function = "pdm"; 786 bias-disable; 787 }; 788 }; 789 790 pdm_din3_x_pins: pdm-din3-x { 791 mux { 792 groups = "pdm_din3_x"; 793 function = "pdm"; 794 bias-disable; 795 }; 796 }; 797 798 pdm_din3_z_pins: pdm-din3-z { 799 mux { 800 groups = "pdm_din3_z"; 801 function = "pdm"; 802 bias-disable; 803 }; 804 }; 805 806 pdm_dclk_a_pins: pdm-dclk-a { 807 mux { 808 groups = "pdm_dclk_a"; 809 function = "pdm"; 810 bias-disable; 811 drive-strength-microamp = <500>; 812 }; 813 }; 814 815 pdm_dclk_c_pins: pdm-dclk-c { 816 mux { 817 groups = "pdm_dclk_c"; 818 function = "pdm"; 819 bias-disable; 820 drive-strength-microamp = <500>; 821 }; 822 }; 823 824 pdm_dclk_x_pins: pdm-dclk-x { 825 mux { 826 groups = "pdm_dclk_x"; 827 function = "pdm"; 828 bias-disable; 829 drive-strength-microamp = <500>; 830 }; 831 }; 832 833 pdm_dclk_z_pins: pdm-dclk-z { 834 mux { 835 groups = "pdm_dclk_z"; 836 function = "pdm"; 837 bias-disable; 838 drive-strength-microamp = <500>; 839 }; 840 }; 841 842 pwm_a_pins: pwm-a { 843 mux { 844 groups = "pwm_a"; 845 function = "pwm_a"; 846 bias-disable; 847 }; 848 }; 849 850 pwm_b_x7_pins: pwm-b-x7 { 851 mux { 852 groups = "pwm_b_x7"; 853 function = "pwm_b"; 854 bias-disable; 855 }; 856 }; 857 858 pwm_b_x19_pins: pwm-b-x19 { 859 mux { 860 groups = "pwm_b_x19"; 861 function = "pwm_b"; 862 bias-disable; 863 }; 864 }; 865 866 pwm_c_c_pins: pwm-c-c { 867 mux { 868 groups = "pwm_c_c"; 869 function = "pwm_c"; 870 bias-disable; 871 }; 872 }; 873 874 pwm_c_x5_pins: pwm-c-x5 { 875 mux { 876 groups = "pwm_c_x5"; 877 function = "pwm_c"; 878 bias-disable; 879 }; 880 }; 881 882 pwm_c_x8_pins: pwm-c-x8 { 883 mux { 884 groups = "pwm_c_x8"; 885 function = "pwm_c"; 886 bias-disable; 887 }; 888 }; 889 890 pwm_d_x3_pins: pwm-d-x3 { 891 mux { 892 groups = "pwm_d_x3"; 893 function = "pwm_d"; 894 bias-disable; 895 }; 896 }; 897 898 pwm_d_x6_pins: pwm-d-x6 { 899 mux { 900 groups = "pwm_d_x6"; 901 function = "pwm_d"; 902 bias-disable; 903 }; 904 }; 905 906 pwm_e_pins: pwm-e { 907 mux { 908 groups = "pwm_e"; 909 function = "pwm_e"; 910 bias-disable; 911 }; 912 }; 913 914 pwm_f_x_pins: pwm-f-x { 915 mux { 916 groups = "pwm_f_x"; 917 function = "pwm_f"; 918 bias-disable; 919 }; 920 }; 921 922 pwm_f_h_pins: pwm-f-h { 923 mux { 924 groups = "pwm_f_h"; 925 function = "pwm_f"; 926 bias-disable; 927 }; 928 }; 929 930 sdcard_c_pins: sdcard_c { 931 mux-0 { 932 groups = "sdcard_d0_c", 933 "sdcard_d1_c", 934 "sdcard_d2_c", 935 "sdcard_d3_c", 936 "sdcard_cmd_c"; 937 function = "sdcard"; 938 bias-pull-up; 939 drive-strength-microamp = <4000>; 940 }; 941 942 mux-1 { 943 groups = "sdcard_clk_c"; 944 function = "sdcard"; 945 bias-disable; 946 drive-strength-microamp = <4000>; 947 }; 948 }; 949 950 sdcard_clk_gate_c_pins: sdcard_clk_gate_c { 951 mux { 952 groups = "GPIOC_4"; 953 function = "gpio_periphs"; 954 bias-pull-down; 955 drive-strength-microamp = <4000>; 956 }; 957 }; 958 959 sdcard_z_pins: sdcard_z { 960 mux-0 { 961 groups = "sdcard_d0_z", 962 "sdcard_d1_z", 963 "sdcard_d2_z", 964 "sdcard_d3_z", 965 "sdcard_cmd_z"; 966 function = "sdcard"; 967 bias-pull-up; 968 drive-strength-microamp = <4000>; 969 }; 970 971 mux-1 { 972 groups = "sdcard_clk_z"; 973 function = "sdcard"; 974 bias-disable; 975 drive-strength-microamp = <4000>; 976 }; 977 }; 978 979 sdcard_clk_gate_z_pins: sdcard_clk_gate_z { 980 mux { 981 groups = "GPIOZ_6"; 982 function = "gpio_periphs"; 983 bias-pull-down; 984 drive-strength-microamp = <4000>; 985 }; 986 }; 987 988 sdio_pins: sdio { 989 mux { 990 groups = "sdio_d0", 991 "sdio_d1", 992 "sdio_d2", 993 "sdio_d3", 994 "sdio_clk", 995 "sdio_cmd"; 996 function = "sdio"; 997 bias-disable; 998 drive-strength-microamp = <4000>; 999 }; 1000 }; 1001 1002 sdio_clk_gate_pins: sdio_clk_gate { 1003 mux { 1004 groups = "GPIOX_4"; 1005 function = "gpio_periphs"; 1006 bias-pull-down; 1007 drive-strength-microamp = <4000>; 1008 }; 1009 }; 1010 1011 spdif_in_a10_pins: spdif-in-a10 { 1012 mux { 1013 groups = "spdif_in_a10"; 1014 function = "spdif_in"; 1015 bias-disable; 1016 }; 1017 }; 1018 1019 spdif_in_a12_pins: spdif-in-a12 { 1020 mux { 1021 groups = "spdif_in_a12"; 1022 function = "spdif_in"; 1023 bias-disable; 1024 }; 1025 }; 1026 1027 spdif_in_h_pins: spdif-in-h { 1028 mux { 1029 groups = "spdif_in_h"; 1030 function = "spdif_in"; 1031 bias-disable; 1032 }; 1033 }; 1034 1035 spdif_out_h_pins: spdif-out-h { 1036 mux { 1037 groups = "spdif_out_h"; 1038 function = "spdif_out"; 1039 drive-strength-microamp = <500>; 1040 bias-disable; 1041 }; 1042 }; 1043 1044 spdif_out_a11_pins: spdif-out-a11 { 1045 mux { 1046 groups = "spdif_out_a11"; 1047 function = "spdif_out"; 1048 drive-strength-microamp = <500>; 1049 bias-disable; 1050 }; 1051 }; 1052 1053 spdif_out_a13_pins: spdif-out-a13 { 1054 mux { 1055 groups = "spdif_out_a13"; 1056 function = "spdif_out"; 1057 drive-strength-microamp = <500>; 1058 bias-disable; 1059 }; 1060 }; 1061 1062 spicc0_x_pins: spicc0-x { 1063 mux { 1064 groups = "spi0_mosi_x", 1065 "spi0_miso_x", 1066 "spi0_clk_x"; 1067 function = "spi0"; 1068 drive-strength-microamp = <4000>; 1069 bias-disable; 1070 }; 1071 }; 1072 1073 spicc0_ss0_x_pins: spicc0-ss0-x { 1074 mux { 1075 groups = "spi0_ss0_x"; 1076 function = "spi0"; 1077 drive-strength-microamp = <4000>; 1078 bias-disable; 1079 }; 1080 }; 1081 1082 spicc0_c_pins: spicc0-c { 1083 mux { 1084 groups = "spi0_mosi_c", 1085 "spi0_miso_c", 1086 "spi0_ss0_c", 1087 "spi0_clk_c"; 1088 function = "spi0"; 1089 drive-strength-microamp = <4000>; 1090 bias-disable; 1091 }; 1092 }; 1093 1094 spicc1_pins: spicc1 { 1095 mux { 1096 groups = "spi1_mosi", 1097 "spi1_miso", 1098 "spi1_clk"; 1099 function = "spi1"; 1100 drive-strength-microamp = <4000>; 1101 }; 1102 }; 1103 1104 spicc1_ss0_pins: spicc1-ss0 { 1105 mux { 1106 groups = "spi1_ss0"; 1107 function = "spi1"; 1108 drive-strength-microamp = <4000>; 1109 bias-disable; 1110 }; 1111 }; 1112 1113 tdm_a_din0_pins: tdm-a-din0 { 1114 mux { 1115 groups = "tdm_a_din0"; 1116 function = "tdm_a"; 1117 bias-disable; 1118 }; 1119 }; 1120 1121 1122 tdm_a_din1_pins: tdm-a-din1 { 1123 mux { 1124 groups = "tdm_a_din1"; 1125 function = "tdm_a"; 1126 bias-disable; 1127 }; 1128 }; 1129 1130 tdm_a_dout0_pins: tdm-a-dout0 { 1131 mux { 1132 groups = "tdm_a_dout0"; 1133 function = "tdm_a"; 1134 bias-disable; 1135 drive-strength-microamp = <3000>; 1136 }; 1137 }; 1138 1139 tdm_a_dout1_pins: tdm-a-dout1 { 1140 mux { 1141 groups = "tdm_a_dout1"; 1142 function = "tdm_a"; 1143 bias-disable; 1144 drive-strength-microamp = <3000>; 1145 }; 1146 }; 1147 1148 tdm_a_fs_pins: tdm-a-fs { 1149 mux { 1150 groups = "tdm_a_fs"; 1151 function = "tdm_a"; 1152 bias-disable; 1153 drive-strength-microamp = <3000>; 1154 }; 1155 }; 1156 1157 tdm_a_sclk_pins: tdm-a-sclk { 1158 mux { 1159 groups = "tdm_a_sclk"; 1160 function = "tdm_a"; 1161 bias-disable; 1162 drive-strength-microamp = <3000>; 1163 }; 1164 }; 1165 1166 tdm_a_slv_fs_pins: tdm-a-slv-fs { 1167 mux { 1168 groups = "tdm_a_slv_fs"; 1169 function = "tdm_a"; 1170 bias-disable; 1171 }; 1172 }; 1173 1174 1175 tdm_a_slv_sclk_pins: tdm-a-slv-sclk { 1176 mux { 1177 groups = "tdm_a_slv_sclk"; 1178 function = "tdm_a"; 1179 bias-disable; 1180 }; 1181 }; 1182 1183 tdm_b_din0_pins: tdm-b-din0 { 1184 mux { 1185 groups = "tdm_b_din0"; 1186 function = "tdm_b"; 1187 bias-disable; 1188 }; 1189 }; 1190 1191 tdm_b_din1_pins: tdm-b-din1 { 1192 mux { 1193 groups = "tdm_b_din1"; 1194 function = "tdm_b"; 1195 bias-disable; 1196 }; 1197 }; 1198 1199 tdm_b_din2_pins: tdm-b-din2 { 1200 mux { 1201 groups = "tdm_b_din2"; 1202 function = "tdm_b"; 1203 bias-disable; 1204 }; 1205 }; 1206 1207 tdm_b_din3_a_pins: tdm-b-din3-a { 1208 mux { 1209 groups = "tdm_b_din3_a"; 1210 function = "tdm_b"; 1211 bias-disable; 1212 }; 1213 }; 1214 1215 tdm_b_din3_h_pins: tdm-b-din3-h { 1216 mux { 1217 groups = "tdm_b_din3_h"; 1218 function = "tdm_b"; 1219 bias-disable; 1220 }; 1221 }; 1222 1223 tdm_b_dout0_pins: tdm-b-dout0 { 1224 mux { 1225 groups = "tdm_b_dout0"; 1226 function = "tdm_b"; 1227 bias-disable; 1228 drive-strength-microamp = <3000>; 1229 }; 1230 }; 1231 1232 tdm_b_dout1_pins: tdm-b-dout1 { 1233 mux { 1234 groups = "tdm_b_dout1"; 1235 function = "tdm_b"; 1236 bias-disable; 1237 drive-strength-microamp = <3000>; 1238 }; 1239 }; 1240 1241 tdm_b_dout2_pins: tdm-b-dout2 { 1242 mux { 1243 groups = "tdm_b_dout2"; 1244 function = "tdm_b"; 1245 bias-disable; 1246 drive-strength-microamp = <3000>; 1247 }; 1248 }; 1249 1250 tdm_b_dout3_a_pins: tdm-b-dout3-a { 1251 mux { 1252 groups = "tdm_b_dout3_a"; 1253 function = "tdm_b"; 1254 bias-disable; 1255 drive-strength-microamp = <3000>; 1256 }; 1257 }; 1258 1259 tdm_b_dout3_h_pins: tdm-b-dout3-h { 1260 mux { 1261 groups = "tdm_b_dout3_h"; 1262 function = "tdm_b"; 1263 bias-disable; 1264 drive-strength-microamp = <3000>; 1265 }; 1266 }; 1267 1268 tdm_b_fs_pins: tdm-b-fs { 1269 mux { 1270 groups = "tdm_b_fs"; 1271 function = "tdm_b"; 1272 bias-disable; 1273 drive-strength-microamp = <3000>; 1274 }; 1275 }; 1276 1277 tdm_b_sclk_pins: tdm-b-sclk { 1278 mux { 1279 groups = "tdm_b_sclk"; 1280 function = "tdm_b"; 1281 bias-disable; 1282 drive-strength-microamp = <3000>; 1283 }; 1284 }; 1285 1286 tdm_b_slv_fs_pins: tdm-b-slv-fs { 1287 mux { 1288 groups = "tdm_b_slv_fs"; 1289 function = "tdm_b"; 1290 bias-disable; 1291 }; 1292 }; 1293 1294 tdm_b_slv_sclk_pins: tdm-b-slv-sclk { 1295 mux { 1296 groups = "tdm_b_slv_sclk"; 1297 function = "tdm_b"; 1298 bias-disable; 1299 }; 1300 }; 1301 1302 tdm_c_din0_a_pins: tdm-c-din0-a { 1303 mux { 1304 groups = "tdm_c_din0_a"; 1305 function = "tdm_c"; 1306 bias-disable; 1307 }; 1308 }; 1309 1310 tdm_c_din0_z_pins: tdm-c-din0-z { 1311 mux { 1312 groups = "tdm_c_din0_z"; 1313 function = "tdm_c"; 1314 bias-disable; 1315 }; 1316 }; 1317 1318 tdm_c_din1_a_pins: tdm-c-din1-a { 1319 mux { 1320 groups = "tdm_c_din1_a"; 1321 function = "tdm_c"; 1322 bias-disable; 1323 }; 1324 }; 1325 1326 tdm_c_din1_z_pins: tdm-c-din1-z { 1327 mux { 1328 groups = "tdm_c_din1_z"; 1329 function = "tdm_c"; 1330 bias-disable; 1331 }; 1332 }; 1333 1334 tdm_c_din2_a_pins: tdm-c-din2-a { 1335 mux { 1336 groups = "tdm_c_din2_a"; 1337 function = "tdm_c"; 1338 bias-disable; 1339 }; 1340 }; 1341 1342 eth_leds_pins: eth-leds { 1343 mux { 1344 groups = "eth_link_led", 1345 "eth_act_led"; 1346 function = "eth"; 1347 bias-disable; 1348 }; 1349 }; 1350 1351 eth_pins: eth { 1352 mux { 1353 groups = "eth_mdio", 1354 "eth_mdc", 1355 "eth_rgmii_rx_clk", 1356 "eth_rx_dv", 1357 "eth_rxd0", 1358 "eth_rxd1", 1359 "eth_txen", 1360 "eth_txd0", 1361 "eth_txd1"; 1362 function = "eth"; 1363 drive-strength-microamp = <4000>; 1364 bias-disable; 1365 }; 1366 }; 1367 1368 eth_rgmii_pins: eth-rgmii { 1369 mux { 1370 groups = "eth_rxd2_rgmii", 1371 "eth_rxd3_rgmii", 1372 "eth_rgmii_tx_clk", 1373 "eth_txd2_rgmii", 1374 "eth_txd3_rgmii"; 1375 function = "eth"; 1376 drive-strength-microamp = <4000>; 1377 bias-disable; 1378 }; 1379 }; 1380 1381 tdm_c_din2_z_pins: tdm-c-din2-z { 1382 mux { 1383 groups = "tdm_c_din2_z"; 1384 function = "tdm_c"; 1385 bias-disable; 1386 }; 1387 }; 1388 1389 tdm_c_din3_a_pins: tdm-c-din3-a { 1390 mux { 1391 groups = "tdm_c_din3_a"; 1392 function = "tdm_c"; 1393 bias-disable; 1394 }; 1395 }; 1396 1397 tdm_c_din3_z_pins: tdm-c-din3-z { 1398 mux { 1399 groups = "tdm_c_din3_z"; 1400 function = "tdm_c"; 1401 bias-disable; 1402 }; 1403 }; 1404 1405 tdm_c_dout0_a_pins: tdm-c-dout0-a { 1406 mux { 1407 groups = "tdm_c_dout0_a"; 1408 function = "tdm_c"; 1409 bias-disable; 1410 drive-strength-microamp = <3000>; 1411 }; 1412 }; 1413 1414 tdm_c_dout0_z_pins: tdm-c-dout0-z { 1415 mux { 1416 groups = "tdm_c_dout0_z"; 1417 function = "tdm_c"; 1418 bias-disable; 1419 drive-strength-microamp = <3000>; 1420 }; 1421 }; 1422 1423 tdm_c_dout1_a_pins: tdm-c-dout1-a { 1424 mux { 1425 groups = "tdm_c_dout1_a"; 1426 function = "tdm_c"; 1427 bias-disable; 1428 drive-strength-microamp = <3000>; 1429 }; 1430 }; 1431 1432 tdm_c_dout1_z_pins: tdm-c-dout1-z { 1433 mux { 1434 groups = "tdm_c_dout1_z"; 1435 function = "tdm_c"; 1436 bias-disable; 1437 drive-strength-microamp = <3000>; 1438 }; 1439 }; 1440 1441 tdm_c_dout2_a_pins: tdm-c-dout2-a { 1442 mux { 1443 groups = "tdm_c_dout2_a"; 1444 function = "tdm_c"; 1445 bias-disable; 1446 drive-strength-microamp = <3000>; 1447 }; 1448 }; 1449 1450 tdm_c_dout2_z_pins: tdm-c-dout2-z { 1451 mux { 1452 groups = "tdm_c_dout2_z"; 1453 function = "tdm_c"; 1454 bias-disable; 1455 drive-strength-microamp = <3000>; 1456 }; 1457 }; 1458 1459 tdm_c_dout3_a_pins: tdm-c-dout3-a { 1460 mux { 1461 groups = "tdm_c_dout3_a"; 1462 function = "tdm_c"; 1463 bias-disable; 1464 drive-strength-microamp = <3000>; 1465 }; 1466 }; 1467 1468 tdm_c_dout3_z_pins: tdm-c-dout3-z { 1469 mux { 1470 groups = "tdm_c_dout3_z"; 1471 function = "tdm_c"; 1472 bias-disable; 1473 drive-strength-microamp = <3000>; 1474 }; 1475 }; 1476 1477 tdm_c_fs_a_pins: tdm-c-fs-a { 1478 mux { 1479 groups = "tdm_c_fs_a"; 1480 function = "tdm_c"; 1481 bias-disable; 1482 drive-strength-microamp = <3000>; 1483 }; 1484 }; 1485 1486 tdm_c_fs_z_pins: tdm-c-fs-z { 1487 mux { 1488 groups = "tdm_c_fs_z"; 1489 function = "tdm_c"; 1490 bias-disable; 1491 drive-strength-microamp = <3000>; 1492 }; 1493 }; 1494 1495 tdm_c_sclk_a_pins: tdm-c-sclk-a { 1496 mux { 1497 groups = "tdm_c_sclk_a"; 1498 function = "tdm_c"; 1499 bias-disable; 1500 drive-strength-microamp = <3000>; 1501 }; 1502 }; 1503 1504 tdm_c_sclk_z_pins: tdm-c-sclk-z { 1505 mux { 1506 groups = "tdm_c_sclk_z"; 1507 function = "tdm_c"; 1508 bias-disable; 1509 drive-strength-microamp = <3000>; 1510 }; 1511 }; 1512 1513 tdm_c_slv_fs_a_pins: tdm-c-slv-fs-a { 1514 mux { 1515 groups = "tdm_c_slv_fs_a"; 1516 function = "tdm_c"; 1517 bias-disable; 1518 }; 1519 }; 1520 1521 tdm_c_slv_fs_z_pins: tdm-c-slv-fs-z { 1522 mux { 1523 groups = "tdm_c_slv_fs_z"; 1524 function = "tdm_c"; 1525 bias-disable; 1526 }; 1527 }; 1528 1529 tdm_c_slv_sclk_a_pins: tdm-c-slv-sclk-a { 1530 mux { 1531 groups = "tdm_c_slv_sclk_a"; 1532 function = "tdm_c"; 1533 bias-disable; 1534 }; 1535 }; 1536 1537 tdm_c_slv_sclk_z_pins: tdm-c-slv-sclk-z { 1538 mux { 1539 groups = "tdm_c_slv_sclk_z"; 1540 function = "tdm_c"; 1541 bias-disable; 1542 }; 1543 }; 1544 1545 uart_a_pins: uart-a { 1546 mux { 1547 groups = "uart_a_tx", 1548 "uart_a_rx"; 1549 function = "uart_a"; 1550 bias-disable; 1551 }; 1552 }; 1553 1554 uart_a_cts_rts_pins: uart-a-cts-rts { 1555 mux { 1556 groups = "uart_a_cts", 1557 "uart_a_rts"; 1558 function = "uart_a"; 1559 bias-disable; 1560 }; 1561 }; 1562 1563 uart_b_pins: uart-b { 1564 mux { 1565 groups = "uart_b_tx", 1566 "uart_b_rx"; 1567 function = "uart_b"; 1568 bias-disable; 1569 }; 1570 }; 1571 1572 uart_c_pins: uart-c { 1573 mux { 1574 groups = "uart_c_tx", 1575 "uart_c_rx"; 1576 function = "uart_c"; 1577 bias-disable; 1578 }; 1579 }; 1580 1581 uart_c_cts_rts_pins: uart-c-cts-rts { 1582 mux { 1583 groups = "uart_c_cts", 1584 "uart_c_rts"; 1585 function = "uart_c"; 1586 bias-disable; 1587 }; 1588 }; 1589 }; 1590 }; 1591 1592 cpu_temp: temperature-sensor@34800 { 1593 compatible = "amlogic,g12a-cpu-thermal", 1594 "amlogic,g12a-thermal"; 1595 reg = <0x0 0x34800 0x0 0x50>; 1596 interrupts = <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>; 1597 clocks = <&clkc CLKID_TS>; 1598 #thermal-sensor-cells = <0>; 1599 amlogic,ao-secure = <&sec_AO>; 1600 }; 1601 1602 ddr_temp: temperature-sensor@34c00 { 1603 compatible = "amlogic,g12a-ddr-thermal", 1604 "amlogic,g12a-thermal"; 1605 reg = <0x0 0x34c00 0x0 0x50>; 1606 interrupts = <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>; 1607 clocks = <&clkc CLKID_TS>; 1608 #thermal-sensor-cells = <0>; 1609 amlogic,ao-secure = <&sec_AO>; 1610 }; 1611 1612 usb2_phy0: phy@36000 { 1613 compatible = "amlogic,g12a-usb2-phy"; 1614 reg = <0x0 0x36000 0x0 0x2000>; 1615 clocks = <&xtal>; 1616 clock-names = "xtal"; 1617 resets = <&reset RESET_USB_PHY20>; 1618 reset-names = "phy"; 1619 #phy-cells = <0>; 1620 }; 1621 1622 dmc: bus@38000 { 1623 compatible = "simple-bus"; 1624 reg = <0x0 0x38000 0x0 0x400>; 1625 #address-cells = <2>; 1626 #size-cells = <2>; 1627 ranges = <0x0 0x0 0x0 0x38000 0x0 0x400>; 1628 1629 canvas: video-lut@48 { 1630 compatible = "amlogic,canvas"; 1631 reg = <0x0 0x48 0x0 0x14>; 1632 }; 1633 }; 1634 1635 usb2_phy1: phy@3a000 { 1636 compatible = "amlogic,g12a-usb2-phy"; 1637 reg = <0x0 0x3a000 0x0 0x2000>; 1638 clocks = <&xtal>; 1639 clock-names = "xtal"; 1640 resets = <&reset RESET_USB_PHY21>; 1641 reset-names = "phy"; 1642 #phy-cells = <0>; 1643 }; 1644 1645 hiu: bus@3c000 { 1646 compatible = "simple-bus"; 1647 reg = <0x0 0x3c000 0x0 0x1400>; 1648 #address-cells = <2>; 1649 #size-cells = <2>; 1650 ranges = <0x0 0x0 0x0 0x3c000 0x0 0x1400>; 1651 1652 hhi: system-controller@0 { 1653 compatible = "amlogic,meson-gx-hhi-sysctrl", 1654 "simple-mfd", "syscon"; 1655 reg = <0 0 0 0x400>; 1656 1657 clkc: clock-controller { 1658 compatible = "amlogic,g12a-clkc"; 1659 #clock-cells = <1>; 1660 clocks = <&xtal>; 1661 clock-names = "xtal"; 1662 }; 1663 1664 pwrc: power-controller { 1665 compatible = "amlogic,meson-g12a-pwrc"; 1666 #power-domain-cells = <1>; 1667 amlogic,ao-sysctrl = <&rti>; 1668 resets = <&reset RESET_VIU>, 1669 <&reset RESET_VENC>, 1670 <&reset RESET_VCBUS>, 1671 <&reset RESET_BT656>, 1672 <&reset RESET_RDMA>, 1673 <&reset RESET_VENCI>, 1674 <&reset RESET_VENCP>, 1675 <&reset RESET_VDAC>, 1676 <&reset RESET_VDI6>, 1677 <&reset RESET_VENCL>, 1678 <&reset RESET_VID_LOCK>; 1679 reset-names = "viu", "venc", "vcbus", "bt656", 1680 "rdma", "venci", "vencp", "vdac", 1681 "vdi6", "vencl", "vid_lock"; 1682 clocks = <&clkc CLKID_VPU>, 1683 <&clkc CLKID_VAPB>; 1684 clock-names = "vpu", "vapb"; 1685 /* 1686 * VPU clocking is provided by two identical clock paths 1687 * VPU_0 and VPU_1 muxed to a single clock by a glitch 1688 * free mux to safely change frequency while running. 1689 * Same for VAPB but with a final gate after the glitch free mux. 1690 */ 1691 assigned-clocks = <&clkc CLKID_VPU_0_SEL>, 1692 <&clkc CLKID_VPU_0>, 1693 <&clkc CLKID_VPU>, /* Glitch free mux */ 1694 <&clkc CLKID_VAPB_0_SEL>, 1695 <&clkc CLKID_VAPB_0>, 1696 <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */ 1697 assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>, 1698 <0>, /* Do Nothing */ 1699 <&clkc CLKID_VPU_0>, 1700 <&clkc CLKID_FCLK_DIV4>, 1701 <0>, /* Do Nothing */ 1702 <&clkc CLKID_VAPB_0>; 1703 assigned-clock-rates = <0>, /* Do Nothing */ 1704 <666666666>, 1705 <0>, /* Do Nothing */ 1706 <0>, /* Do Nothing */ 1707 <500000000>, 1708 <0>; /* Do Nothing */ 1709 }; 1710 1711 mipi_analog_dphy: phy { 1712 compatible = "amlogic,g12a-mipi-dphy-analog"; 1713 #phy-cells = <0>; 1714 status = "disabled"; 1715 }; 1716 }; 1717 }; 1718 1719 mipi_dphy: phy@44000 { 1720 compatible = "amlogic,axg-mipi-dphy"; 1721 reg = <0x0 0x44000 0x0 0x2000>; 1722 clocks = <&clkc CLKID_MIPI_DSI_PHY>; 1723 clock-names = "pclk"; 1724 resets = <&reset RESET_MIPI_DSI_PHY>; 1725 reset-names = "phy"; 1726 phys = <&mipi_analog_dphy>; 1727 phy-names = "analog"; 1728 #phy-cells = <0>; 1729 status = "disabled"; 1730 }; 1731 1732 usb3_pcie_phy: phy@46000 { 1733 compatible = "amlogic,g12a-usb3-pcie-phy"; 1734 reg = <0x0 0x46000 0x0 0x2000>; 1735 clocks = <&clkc CLKID_PCIE_PLL>; 1736 clock-names = "ref_clk"; 1737 resets = <&reset RESET_PCIE_PHY>; 1738 reset-names = "phy"; 1739 assigned-clocks = <&clkc CLKID_PCIE_PLL>; 1740 assigned-clock-rates = <100000000>; 1741 #phy-cells = <1>; 1742 }; 1743 1744 eth_phy: mdio-multiplexer@4c000 { 1745 compatible = "amlogic,g12a-mdio-mux"; 1746 reg = <0x0 0x4c000 0x0 0xa4>; 1747 clocks = <&clkc CLKID_ETH_PHY>, 1748 <&xtal>, 1749 <&clkc CLKID_MPLL_50M>; 1750 clock-names = "pclk", "clkin0", "clkin1"; 1751 mdio-parent-bus = <&mdio0>; 1752 #address-cells = <1>; 1753 #size-cells = <0>; 1754 1755 ext_mdio: mdio@0 { 1756 reg = <0>; 1757 #address-cells = <1>; 1758 #size-cells = <0>; 1759 }; 1760 1761 int_mdio: mdio@1 { 1762 reg = <1>; 1763 #address-cells = <1>; 1764 #size-cells = <0>; 1765 1766 internal_ephy: ethernet_phy@8 { 1767 compatible = "ethernet-phy-id0180.3301", 1768 "ethernet-phy-ieee802.3-c22"; 1769 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 1770 reg = <8>; 1771 max-speed = <100>; 1772 }; 1773 }; 1774 }; 1775 }; 1776 1777 aobus: bus@ff800000 { 1778 compatible = "simple-bus"; 1779 reg = <0x0 0xff800000 0x0 0x100000>; 1780 #address-cells = <2>; 1781 #size-cells = <2>; 1782 ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>; 1783 1784 rti: sys-ctrl@0 { 1785 compatible = "amlogic,meson-gx-ao-sysctrl", 1786 "simple-mfd", "syscon"; 1787 reg = <0x0 0x0 0x0 0x100>; 1788 #address-cells = <2>; 1789 #size-cells = <2>; 1790 ranges = <0x0 0x0 0x0 0x0 0x0 0x100>; 1791 1792 clkc_AO: clock-controller { 1793 compatible = "amlogic,meson-g12a-aoclkc"; 1794 #clock-cells = <1>; 1795 #reset-cells = <1>; 1796 clocks = <&xtal>, <&clkc CLKID_CLK81>; 1797 clock-names = "xtal", "mpeg-clk"; 1798 }; 1799 1800 ao_pinctrl: pinctrl@14 { 1801 compatible = "amlogic,meson-g12a-aobus-pinctrl"; 1802 #address-cells = <2>; 1803 #size-cells = <2>; 1804 ranges; 1805 1806 gpio_ao: bank@14 { 1807 reg = <0x0 0x14 0x0 0x8>, 1808 <0x0 0x1c 0x0 0x8>, 1809 <0x0 0x24 0x0 0x14>; 1810 reg-names = "mux", 1811 "ds", 1812 "gpio"; 1813 gpio-controller; 1814 #gpio-cells = <2>; 1815 gpio-ranges = <&ao_pinctrl 0 0 15>; 1816 }; 1817 1818 i2c_ao_sck_pins: i2c_ao_sck_pins { 1819 mux { 1820 groups = "i2c_ao_sck"; 1821 function = "i2c_ao"; 1822 bias-disable; 1823 drive-strength-microamp = <3000>; 1824 }; 1825 }; 1826 1827 i2c_ao_sda_pins: i2c_ao_sda { 1828 mux { 1829 groups = "i2c_ao_sda"; 1830 function = "i2c_ao"; 1831 bias-disable; 1832 drive-strength-microamp = <3000>; 1833 }; 1834 }; 1835 1836 i2c_ao_sck_e_pins: i2c_ao_sck_e { 1837 mux { 1838 groups = "i2c_ao_sck_e"; 1839 function = "i2c_ao"; 1840 bias-disable; 1841 drive-strength-microamp = <3000>; 1842 }; 1843 }; 1844 1845 i2c_ao_sda_e_pins: i2c_ao_sda_e { 1846 mux { 1847 groups = "i2c_ao_sda_e"; 1848 function = "i2c_ao"; 1849 bias-disable; 1850 drive-strength-microamp = <3000>; 1851 }; 1852 }; 1853 1854 mclk0_ao_pins: mclk0-ao { 1855 mux { 1856 groups = "mclk0_ao"; 1857 function = "mclk0_ao"; 1858 bias-disable; 1859 drive-strength-microamp = <3000>; 1860 }; 1861 }; 1862 1863 tdm_ao_b_din0_pins: tdm-ao-b-din0 { 1864 mux { 1865 groups = "tdm_ao_b_din0"; 1866 function = "tdm_ao_b"; 1867 bias-disable; 1868 }; 1869 }; 1870 1871 spdif_ao_out_pins: spdif-ao-out { 1872 mux { 1873 groups = "spdif_ao_out"; 1874 function = "spdif_ao_out"; 1875 drive-strength-microamp = <500>; 1876 bias-disable; 1877 }; 1878 }; 1879 1880 tdm_ao_b_din1_pins: tdm-ao-b-din1 { 1881 mux { 1882 groups = "tdm_ao_b_din1"; 1883 function = "tdm_ao_b"; 1884 bias-disable; 1885 }; 1886 }; 1887 1888 tdm_ao_b_din2_pins: tdm-ao-b-din2 { 1889 mux { 1890 groups = "tdm_ao_b_din2"; 1891 function = "tdm_ao_b"; 1892 bias-disable; 1893 }; 1894 }; 1895 1896 tdm_ao_b_dout0_pins: tdm-ao-b-dout0 { 1897 mux { 1898 groups = "tdm_ao_b_dout0"; 1899 function = "tdm_ao_b"; 1900 bias-disable; 1901 drive-strength-microamp = <3000>; 1902 }; 1903 }; 1904 1905 tdm_ao_b_dout1_pins: tdm-ao-b-dout1 { 1906 mux { 1907 groups = "tdm_ao_b_dout1"; 1908 function = "tdm_ao_b"; 1909 bias-disable; 1910 drive-strength-microamp = <3000>; 1911 }; 1912 }; 1913 1914 tdm_ao_b_dout2_pins: tdm-ao-b-dout2 { 1915 mux { 1916 groups = "tdm_ao_b_dout2"; 1917 function = "tdm_ao_b"; 1918 bias-disable; 1919 drive-strength-microamp = <3000>; 1920 }; 1921 }; 1922 1923 tdm_ao_b_fs_pins: tdm-ao-b-fs { 1924 mux { 1925 groups = "tdm_ao_b_fs"; 1926 function = "tdm_ao_b"; 1927 bias-disable; 1928 drive-strength-microamp = <3000>; 1929 }; 1930 }; 1931 1932 tdm_ao_b_sclk_pins: tdm-ao-b-sclk { 1933 mux { 1934 groups = "tdm_ao_b_sclk"; 1935 function = "tdm_ao_b"; 1936 bias-disable; 1937 drive-strength-microamp = <3000>; 1938 }; 1939 }; 1940 1941 tdm_ao_b_slv_fs_pins: tdm-ao-b-slv-fs { 1942 mux { 1943 groups = "tdm_ao_b_slv_fs"; 1944 function = "tdm_ao_b"; 1945 bias-disable; 1946 }; 1947 }; 1948 1949 tdm_ao_b_slv_sclk_pins: tdm-ao-b-slv-sclk { 1950 mux { 1951 groups = "tdm_ao_b_slv_sclk"; 1952 function = "tdm_ao_b"; 1953 bias-disable; 1954 }; 1955 }; 1956 1957 uart_ao_a_pins: uart-a-ao { 1958 mux { 1959 groups = "uart_ao_a_tx", 1960 "uart_ao_a_rx"; 1961 function = "uart_ao_a"; 1962 bias-disable; 1963 }; 1964 }; 1965 1966 uart_ao_a_cts_rts_pins: uart-ao-a-cts-rts { 1967 mux { 1968 groups = "uart_ao_a_cts", 1969 "uart_ao_a_rts"; 1970 function = "uart_ao_a"; 1971 bias-disable; 1972 }; 1973 }; 1974 1975 uart_ao_b_1_pins: uart-ao-b-1 { 1976 mux { 1977 groups = "uart_ao_b_tx_2", 1978 "uart_ao_b_rx_3"; 1979 function = "uart_ao_b"; 1980 bias-disable; 1981 }; 1982 }; 1983 1984 uart_ao_b_2_pins: uart-ao-b-2 { 1985 mux { 1986 groups = "uart_ao_b_tx_8", 1987 "uart_ao_b_rx_9"; 1988 function = "uart_ao_b"; 1989 bias-disable; 1990 }; 1991 }; 1992 1993 uart_ao_b_cts_rts_pins: uart-ao-b-cts-rts { 1994 mux { 1995 groups = "uart_ao_b_cts", 1996 "uart_ao_b_rts"; 1997 function = "uart_ao_b"; 1998 bias-disable; 1999 }; 2000 }; 2001 2002 pwm_a_e_pins: pwm-a-e { 2003 mux { 2004 groups = "pwm_a_e"; 2005 function = "pwm_a_e"; 2006 bias-disable; 2007 }; 2008 }; 2009 2010 pwm_ao_a_pins: pwm-ao-a { 2011 mux { 2012 groups = "pwm_ao_a"; 2013 function = "pwm_ao_a"; 2014 bias-disable; 2015 }; 2016 }; 2017 2018 pwm_ao_b_pins: pwm-ao-b { 2019 mux { 2020 groups = "pwm_ao_b"; 2021 function = "pwm_ao_b"; 2022 bias-disable; 2023 }; 2024 }; 2025 2026 pwm_ao_c_4_pins: pwm-ao-c-4 { 2027 mux { 2028 groups = "pwm_ao_c_4"; 2029 function = "pwm_ao_c"; 2030 bias-disable; 2031 }; 2032 }; 2033 2034 pwm_ao_c_6_pins: pwm-ao-c-6 { 2035 mux { 2036 groups = "pwm_ao_c_6"; 2037 function = "pwm_ao_c"; 2038 bias-disable; 2039 }; 2040 }; 2041 2042 pwm_ao_d_5_pins: pwm-ao-d-5 { 2043 mux { 2044 groups = "pwm_ao_d_5"; 2045 function = "pwm_ao_d"; 2046 bias-disable; 2047 }; 2048 }; 2049 2050 pwm_ao_d_10_pins: pwm-ao-d-10 { 2051 mux { 2052 groups = "pwm_ao_d_10"; 2053 function = "pwm_ao_d"; 2054 bias-disable; 2055 }; 2056 }; 2057 2058 pwm_ao_d_e_pins: pwm-ao-d-e { 2059 mux { 2060 groups = "pwm_ao_d_e"; 2061 function = "pwm_ao_d"; 2062 }; 2063 }; 2064 2065 remote_input_ao_pins: remote-input-ao { 2066 mux { 2067 groups = "remote_ao_input"; 2068 function = "remote_ao_input"; 2069 bias-disable; 2070 }; 2071 }; 2072 }; 2073 }; 2074 2075 vrtc: rtc@a8 { 2076 compatible = "amlogic,meson-vrtc"; 2077 reg = <0x0 0x000a8 0x0 0x4>; 2078 }; 2079 2080 cec_AO: cec@100 { 2081 compatible = "amlogic,meson-gx-ao-cec"; 2082 reg = <0x0 0x00100 0x0 0x14>; 2083 interrupts = <GIC_SPI 199 IRQ_TYPE_EDGE_RISING>; 2084 clocks = <&clkc_AO CLKID_AO_CEC>; 2085 clock-names = "core"; 2086 status = "disabled"; 2087 }; 2088 2089 sec_AO: ao-secure@140 { 2090 compatible = "amlogic,meson-gx-ao-secure", "syscon"; 2091 reg = <0x0 0x140 0x0 0x140>; 2092 amlogic,has-chip-id; 2093 }; 2094 2095 cecb_AO: cec@280 { 2096 compatible = "amlogic,meson-g12a-ao-cec"; 2097 reg = <0x0 0x00280 0x0 0x1c>; 2098 interrupts = <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>; 2099 clocks = <&clkc_AO CLKID_AO_CTS_OSCIN>; 2100 clock-names = "oscin"; 2101 status = "disabled"; 2102 }; 2103 2104 pwm_AO_cd: pwm@2000 { 2105 compatible = "amlogic,meson-g12a-ao-pwm-cd"; 2106 reg = <0x0 0x2000 0x0 0x20>; 2107 #pwm-cells = <3>; 2108 status = "disabled"; 2109 }; 2110 2111 uart_AO: serial@3000 { 2112 compatible = "amlogic,meson-gx-uart", 2113 "amlogic,meson-ao-uart"; 2114 reg = <0x0 0x3000 0x0 0x18>; 2115 interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>; 2116 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART>, <&xtal>; 2117 clock-names = "xtal", "pclk", "baud"; 2118 status = "disabled"; 2119 }; 2120 2121 uart_AO_B: serial@4000 { 2122 compatible = "amlogic,meson-gx-uart", 2123 "amlogic,meson-ao-uart"; 2124 reg = <0x0 0x4000 0x0 0x18>; 2125 interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>; 2126 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>; 2127 clock-names = "xtal", "pclk", "baud"; 2128 status = "disabled"; 2129 }; 2130 2131 i2c_AO: i2c@5000 { 2132 compatible = "amlogic,meson-axg-i2c"; 2133 status = "disabled"; 2134 reg = <0x0 0x05000 0x0 0x20>; 2135 interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>; 2136 #address-cells = <1>; 2137 #size-cells = <0>; 2138 clocks = <&clkc CLKID_I2C>; 2139 }; 2140 2141 pwm_AO_ab: pwm@7000 { 2142 compatible = "amlogic,meson-g12a-ao-pwm-ab"; 2143 reg = <0x0 0x7000 0x0 0x20>; 2144 #pwm-cells = <3>; 2145 status = "disabled"; 2146 }; 2147 2148 ir: ir@8000 { 2149 compatible = "amlogic,meson-gxbb-ir"; 2150 reg = <0x0 0x8000 0x0 0x20>; 2151 interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>; 2152 status = "disabled"; 2153 }; 2154 2155 saradc: adc@9000 { 2156 compatible = "amlogic,meson-g12a-saradc", 2157 "amlogic,meson-saradc"; 2158 reg = <0x0 0x9000 0x0 0x48>; 2159 #io-channel-cells = <1>; 2160 interrupts = <GIC_SPI 200 IRQ_TYPE_EDGE_RISING>; 2161 clocks = <&xtal>, 2162 <&clkc_AO CLKID_AO_SAR_ADC>, 2163 <&clkc_AO CLKID_AO_SAR_ADC_CLK>, 2164 <&clkc_AO CLKID_AO_SAR_ADC_SEL>; 2165 clock-names = "clkin", "core", "adc_clk", "adc_sel"; 2166 status = "disabled"; 2167 }; 2168 }; 2169 2170 vdec: video-decoder@ff620000 { 2171 compatible = "amlogic,g12a-vdec"; 2172 reg = <0x0 0xff620000 0x0 0x10000>, 2173 <0x0 0xffd0e180 0x0 0xe4>; 2174 reg-names = "dos", "esparser"; 2175 interrupts = <GIC_SPI 44 IRQ_TYPE_EDGE_RISING>, 2176 <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>; 2177 interrupt-names = "vdec", "esparser"; 2178 2179 amlogic,ao-sysctrl = <&rti>; 2180 amlogic,canvas = <&canvas>; 2181 2182 clocks = <&clkc CLKID_PARSER>, 2183 <&clkc CLKID_DOS>, 2184 <&clkc CLKID_VDEC_1>, 2185 <&clkc CLKID_VDEC_HEVC>, 2186 <&clkc CLKID_VDEC_HEVCF>; 2187 clock-names = "dos_parser", "dos", "vdec_1", 2188 "vdec_hevc", "vdec_hevcf"; 2189 resets = <&reset RESET_PARSER>; 2190 reset-names = "esparser"; 2191 }; 2192 2193 vpu: vpu@ff900000 { 2194 compatible = "amlogic,meson-g12a-vpu"; 2195 reg = <0x0 0xff900000 0x0 0x100000>, 2196 <0x0 0xff63c000 0x0 0x1000>; 2197 reg-names = "vpu", "hhi"; 2198 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>; 2199 #address-cells = <1>; 2200 #size-cells = <0>; 2201 amlogic,canvas = <&canvas>; 2202 2203 /* CVBS VDAC output port */ 2204 cvbs_vdac_port: port@0 { 2205 reg = <0>; 2206 }; 2207 2208 /* HDMI-TX output port */ 2209 hdmi_tx_port: port@1 { 2210 reg = <1>; 2211 2212 hdmi_tx_out: endpoint { 2213 remote-endpoint = <&hdmi_tx_in>; 2214 }; 2215 }; 2216 2217 /* DPI output port */ 2218 dpi_port: port@2 { 2219 reg = <2>; 2220 2221 dpi_out: endpoint { 2222 remote-endpoint = <&mipi_dsi_in>; 2223 }; 2224 }; 2225 }; 2226 2227 gic: interrupt-controller@ffc01000 { 2228 compatible = "arm,gic-400"; 2229 reg = <0x0 0xffc01000 0 0x1000>, 2230 <0x0 0xffc02000 0 0x2000>, 2231 <0x0 0xffc04000 0 0x2000>, 2232 <0x0 0xffc06000 0 0x2000>; 2233 interrupt-controller; 2234 interrupts = <GIC_PPI 9 2235 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 2236 #interrupt-cells = <3>; 2237 #address-cells = <0>; 2238 }; 2239 2240 cbus: bus@ffd00000 { 2241 compatible = "simple-bus"; 2242 reg = <0x0 0xffd00000 0x0 0x100000>; 2243 #address-cells = <2>; 2244 #size-cells = <2>; 2245 ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x100000>; 2246 2247 reset: reset-controller@1004 { 2248 compatible = "amlogic,meson-axg-reset"; 2249 reg = <0x0 0x1004 0x0 0x9c>; 2250 #reset-cells = <1>; 2251 }; 2252 2253 gpio_intc: interrupt-controller@f080 { 2254 compatible = "amlogic,meson-g12a-gpio-intc", 2255 "amlogic,meson-gpio-intc"; 2256 reg = <0x0 0xf080 0x0 0x10>; 2257 interrupt-controller; 2258 #interrupt-cells = <2>; 2259 amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>; 2260 }; 2261 2262 mipi_dsi: mipi-dsi@7000 { 2263 compatible = "amlogic,meson-g12a-dw-mipi-dsi"; 2264 reg = <0x0 0x7000 0x0 0x1000>; 2265 resets = <&reset RESET_MIPI_DSI_HOST>; 2266 reset-names = "top"; 2267 clocks = <&clkc CLKID_MIPI_DSI_HOST>, 2268 <&clkc CLKID_MIPI_DSI_PXCLK>; 2269 clock-names = "pclk", "px_clk"; 2270 phys = <&mipi_dphy>; 2271 phy-names = "dphy"; 2272 #address-cells = <1>; 2273 #size-cells = <0>; 2274 status = "disabled"; 2275 2276 assigned-clocks = <&clkc CLKID_MIPI_DSI_PXCLK_SEL>; 2277 assigned-clock-parents = <&clkc CLKID_GP0_PLL>; 2278 2279 ports { 2280 #address-cells = <1>; 2281 #size-cells = <0>; 2282 2283 /* VPU VENC Input */ 2284 mipi_dsi_venc_port: port@0 { 2285 reg = <0>; 2286 2287 mipi_dsi_in: endpoint { 2288 remote-endpoint = <&dpi_out>; 2289 }; 2290 }; 2291 2292 /* DSI Output */ 2293 mipi_dsi_panel_port: port@1 { 2294 reg = <1>; 2295 }; 2296 }; 2297 }; 2298 2299 watchdog: wdt@f0d0 { 2300 compatible = "amlogic,meson-gxbb-wdt"; 2301 reg = <0x0 0xf0d0 0x0 0x10>; 2302 clocks = <&xtal>; 2303 }; 2304 2305 spicc0: spi@13000 { 2306 compatible = "amlogic,meson-g12a-spicc"; 2307 reg = <0x0 0x13000 0x0 0x44>; 2308 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 2309 clocks = <&clkc CLKID_SPICC0>, 2310 <&clkc CLKID_SPICC0_SCLK>; 2311 clock-names = "core", "pclk"; 2312 #address-cells = <1>; 2313 #size-cells = <0>; 2314 status = "disabled"; 2315 }; 2316 2317 spicc1: spi@15000 { 2318 compatible = "amlogic,meson-g12a-spicc"; 2319 reg = <0x0 0x15000 0x0 0x44>; 2320 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 2321 clocks = <&clkc CLKID_SPICC1>, 2322 <&clkc CLKID_SPICC1_SCLK>; 2323 clock-names = "core", "pclk"; 2324 #address-cells = <1>; 2325 #size-cells = <0>; 2326 status = "disabled"; 2327 }; 2328 2329 spifc: spi@14000 { 2330 compatible = "amlogic,meson-gxbb-spifc"; 2331 status = "disabled"; 2332 reg = <0x0 0x14000 0x0 0x80>; 2333 #address-cells = <1>; 2334 #size-cells = <0>; 2335 clocks = <&clkc CLKID_CLK81>; 2336 }; 2337 2338 pwm_ef: pwm@19000 { 2339 compatible = "amlogic,meson-g12a-ee-pwm"; 2340 reg = <0x0 0x19000 0x0 0x20>; 2341 #pwm-cells = <3>; 2342 status = "disabled"; 2343 }; 2344 2345 pwm_cd: pwm@1a000 { 2346 compatible = "amlogic,meson-g12a-ee-pwm"; 2347 reg = <0x0 0x1a000 0x0 0x20>; 2348 #pwm-cells = <3>; 2349 status = "disabled"; 2350 }; 2351 2352 pwm_ab: pwm@1b000 { 2353 compatible = "amlogic,meson-g12a-ee-pwm"; 2354 reg = <0x0 0x1b000 0x0 0x20>; 2355 #pwm-cells = <3>; 2356 status = "disabled"; 2357 }; 2358 2359 i2c3: i2c@1c000 { 2360 compatible = "amlogic,meson-axg-i2c"; 2361 status = "disabled"; 2362 reg = <0x0 0x1c000 0x0 0x20>; 2363 interrupts = <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>; 2364 #address-cells = <1>; 2365 #size-cells = <0>; 2366 clocks = <&clkc CLKID_I2C>; 2367 }; 2368 2369 i2c2: i2c@1d000 { 2370 compatible = "amlogic,meson-axg-i2c"; 2371 status = "disabled"; 2372 reg = <0x0 0x1d000 0x0 0x20>; 2373 interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>; 2374 #address-cells = <1>; 2375 #size-cells = <0>; 2376 clocks = <&clkc CLKID_I2C>; 2377 }; 2378 2379 i2c1: i2c@1e000 { 2380 compatible = "amlogic,meson-axg-i2c"; 2381 status = "disabled"; 2382 reg = <0x0 0x1e000 0x0 0x20>; 2383 interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>; 2384 #address-cells = <1>; 2385 #size-cells = <0>; 2386 clocks = <&clkc CLKID_I2C>; 2387 }; 2388 2389 i2c0: i2c@1f000 { 2390 compatible = "amlogic,meson-axg-i2c"; 2391 status = "disabled"; 2392 reg = <0x0 0x1f000 0x0 0x20>; 2393 interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>; 2394 #address-cells = <1>; 2395 #size-cells = <0>; 2396 clocks = <&clkc CLKID_I2C>; 2397 }; 2398 2399 clk_msr: clock-measure@18000 { 2400 compatible = "amlogic,meson-g12a-clk-measure"; 2401 reg = <0x0 0x18000 0x0 0x10>; 2402 }; 2403 2404 uart_C: serial@22000 { 2405 compatible = "amlogic,meson-gx-uart"; 2406 reg = <0x0 0x22000 0x0 0x18>; 2407 interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>; 2408 clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>; 2409 clock-names = "xtal", "pclk", "baud"; 2410 status = "disabled"; 2411 }; 2412 2413 uart_B: serial@23000 { 2414 compatible = "amlogic,meson-gx-uart"; 2415 reg = <0x0 0x23000 0x0 0x18>; 2416 interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>; 2417 clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>; 2418 clock-names = "xtal", "pclk", "baud"; 2419 status = "disabled"; 2420 }; 2421 2422 uart_A: serial@24000 { 2423 compatible = "amlogic,meson-gx-uart"; 2424 reg = <0x0 0x24000 0x0 0x18>; 2425 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>; 2426 clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>; 2427 clock-names = "xtal", "pclk", "baud"; 2428 status = "disabled"; 2429 fifo-size = <128>; 2430 }; 2431 }; 2432 2433 sd_emmc_a: sd@ffe03000 { 2434 compatible = "amlogic,meson-axg-mmc"; 2435 reg = <0x0 0xffe03000 0x0 0x800>; 2436 interrupts = <GIC_SPI 189 IRQ_TYPE_EDGE_RISING>; 2437 status = "disabled"; 2438 clocks = <&clkc CLKID_SD_EMMC_A>, 2439 <&clkc CLKID_SD_EMMC_A_CLK0>, 2440 <&clkc CLKID_FCLK_DIV2>; 2441 clock-names = "core", "clkin0", "clkin1"; 2442 resets = <&reset RESET_SD_EMMC_A>; 2443 }; 2444 2445 sd_emmc_b: sd@ffe05000 { 2446 compatible = "amlogic,meson-axg-mmc"; 2447 reg = <0x0 0xffe05000 0x0 0x800>; 2448 interrupts = <GIC_SPI 190 IRQ_TYPE_EDGE_RISING>; 2449 status = "disabled"; 2450 clocks = <&clkc CLKID_SD_EMMC_B>, 2451 <&clkc CLKID_SD_EMMC_B_CLK0>, 2452 <&clkc CLKID_FCLK_DIV2>; 2453 clock-names = "core", "clkin0", "clkin1"; 2454 resets = <&reset RESET_SD_EMMC_B>; 2455 }; 2456 2457 sd_emmc_c: mmc@ffe07000 { 2458 compatible = "amlogic,meson-axg-mmc"; 2459 reg = <0x0 0xffe07000 0x0 0x800>; 2460 interrupts = <GIC_SPI 191 IRQ_TYPE_EDGE_RISING>; 2461 status = "disabled"; 2462 clocks = <&clkc CLKID_SD_EMMC_C>, 2463 <&clkc CLKID_SD_EMMC_C_CLK0>, 2464 <&clkc CLKID_FCLK_DIV2>; 2465 clock-names = "core", "clkin0", "clkin1"; 2466 resets = <&reset RESET_SD_EMMC_C>; 2467 }; 2468 2469 usb: usb@ffe09000 { 2470 status = "disabled"; 2471 compatible = "amlogic,meson-g12a-usb-ctrl"; 2472 reg = <0x0 0xffe09000 0x0 0xa0>; 2473 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 2474 #address-cells = <2>; 2475 #size-cells = <2>; 2476 ranges; 2477 2478 clocks = <&clkc CLKID_USB>; 2479 resets = <&reset RESET_USB>; 2480 2481 dr_mode = "otg"; 2482 2483 phys = <&usb2_phy0>, <&usb2_phy1>, 2484 <&usb3_pcie_phy PHY_TYPE_USB3>; 2485 phy-names = "usb2-phy0", "usb2-phy1", "usb3-phy0"; 2486 2487 dwc2: usb@ff400000 { 2488 compatible = "amlogic,meson-g12a-usb", "snps,dwc2"; 2489 reg = <0x0 0xff400000 0x0 0x40000>; 2490 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 2491 clocks = <&clkc CLKID_USB1_DDR_BRIDGE>; 2492 clock-names = "otg"; 2493 phys = <&usb2_phy1>; 2494 phy-names = "usb2-phy"; 2495 dr_mode = "peripheral"; 2496 g-rx-fifo-size = <192>; 2497 g-np-tx-fifo-size = <128>; 2498 g-tx-fifo-size = <128 128 16 16 16>; 2499 }; 2500 2501 dwc3: usb@ff500000 { 2502 compatible = "snps,dwc3"; 2503 reg = <0x0 0xff500000 0x0 0x100000>; 2504 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 2505 dr_mode = "host"; 2506 snps,dis_u2_susphy_quirk; 2507 snps,quirk-frame-length-adjustment = <0x20>; 2508 snps,parkmode-disable-ss-quirk; 2509 }; 2510 }; 2511 2512 mali: gpu@ffe40000 { 2513 compatible = "amlogic,meson-g12a-mali", "arm,mali-bifrost"; 2514 reg = <0x0 0xffe40000 0x0 0x40000>; 2515 interrupt-parent = <&gic>; 2516 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, 2517 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, 2518 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 2519 interrupt-names = "job", "mmu", "gpu"; 2520 clocks = <&clkc CLKID_MALI>; 2521 resets = <&reset RESET_DVALIN_CAPB3>, <&reset RESET_DVALIN>; 2522 operating-points-v2 = <&gpu_opp_table>; 2523 #cooling-cells = <2>; 2524 }; 2525 2526 isp_sc: isp-sc@ff655400 { 2527 compatible = "amlogic, isp-sc"; 2528 reg = <0x0 0xff655400 0x0 0x00001000>; 2529 reg-names = "isp_sc"; 2530 interrupts = <0 17 IRQ_TYPE_EDGE_RISING>; 2531 interrupt-names = "isp_sc"; 2532 }; 2533 2534 isp: isp@ff140000 { 2535 compatible = "arm, isp"; 2536 reg = <0x0 0xff140000 0x0 0x00040000>; 2537 reg-names = "ISP"; 2538 isp-efuse = <0xff630038 0x4000>; 2539 interrupts = <0 142 4>; 2540 interrupt-names = "ISP"; 2541 temper-buf-size = <24>; 2542 clocks = <&clkc CLKID_MIPI_ISP_CLK_COMP>, 2543 <&clkc CLKID_MIPI_CSI_PHY_CLK0_COMP>; 2544 clock-names = "cts_mipi_isp_clk_composite", 2545 "cts_mipi_csi_phy_clk0_composite"; 2546 link-device = <&isp_sc>; 2547 }; 2548 2549 adapter: isp-adapter@ff650000 { 2550 compatible = "amlogic, isp-adapter"; 2551 reg = <0x0 0xff650000 0x0 0x00006000>; 2552 reg-names = "adapter"; 2553 interrupts = <0 179 IRQ_TYPE_EDGE_RISING>; 2554 interrupt-names = "adapter-irq"; 2555 mem_alloc = <48>; 2556 }; 2557 2558 phycsi: phy-csi@ff650000 { 2559 compatible = "amlogic, phy-csi"; 2560 reg = <0x0 0xff650000 0x0 0x00002000>, 2561 <0x0 0xff652000 0x0 0x00002000>, 2562 <0x0 0xff63c300 0x0 0x00000100>, 2563 <0x0 0xff654000 0x0 0x00000100>, 2564 <0x0 0xff654400 0x0 0x00000100>; 2565 reg-names = "csi2_phy0", "csi2_phy1", "aphy_reg", 2566 "csi0_host", "csi1_host"; 2567 interrupts = <0 41 IRQ_TYPE_EDGE_RISING>, 2568 <0 42 IRQ_TYPE_EDGE_RISING>, 2569 <0 72 IRQ_TYPE_EDGE_RISING>, 2570 <0 74 IRQ_TYPE_EDGE_RISING>, 2571 <0 87 IRQ_TYPE_EDGE_RISING>, 2572 <0 88 IRQ_TYPE_EDGE_RISING>; 2573 interrupt-names = "phy0-irq", 2574 "phy1-irq", 2575 "csi-host0-intr2", 2576 "csi-host0-intr1", 2577 "csi-host1-intr2", 2578 "csi-host1-intr1"; 2579 link-device = <&adapter>; 2580 }; 2581 }; 2582 2583 timer { 2584 compatible = "arm,armv8-timer"; 2585 interrupts = <GIC_PPI 13 2586 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 2587 <GIC_PPI 14 2588 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 2589 <GIC_PPI 11 2590 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 2591 <GIC_PPI 10 2592 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>; 2593 arm,no-tick-in-suspend; 2594 }; 2595 2596 xtal: xtal-clk { 2597 compatible = "fixed-clock"; 2598 clock-frequency = <24000000>; 2599 clock-output-names = "xtal"; 2600 #clock-cells = <0>; 2601 }; 2602 2603 osc8M: osc8M { 2604 compatible = "fixed-clock"; 2605 clock-output-names = "osc8M"; 2606 clock-frequency = <8000000>; 2607 #clock-cells = <0>; 2608 }; 2609}; 2610