1 /******************************************************************************
2 * @file mpu_armv7.h
3 * @brief CMSIS MPU API for Armv7-M MPU
4 * @version V5.0.4
5 * @date 10. January 2018
6 ******************************************************************************/
7 /*
8 * Copyright (c) 2017-2018 Arm Limited. All rights reserved.
9 *
10 * SPDX-License-Identifier: Apache-2.0
11 *
12 * Licensed under the Apache License, Version 2.0 (the License); you may
13 * not use this file except in compliance with the License.
14 * You may obtain a copy of the License at
15 *
16 * www.apache.org/licenses/LICENSE-2.0
17 *
18 * Unless required by applicable law or agreed to in writing, software
19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21 * See the License for the specific language governing permissions and
22 * limitations under the License.
23 */
24
25 #if defined ( __ICCARM__ )
26 #pragma system_include /* treat file as system include file for MISRA check */
27 #elif defined (__clang__)
28 #pragma clang system_header /* treat file as system include file */
29 #endif
30
31 #ifndef ARM_MPU_ARMV7_H
32 #define ARM_MPU_ARMV7_H
33
34 #define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U)
35 #define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U)
36 #define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U)
37 #define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U)
38 #define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U)
39 #define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U)
40 #define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU)
41 #define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU)
42 #define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU)
43 #define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU)
44 #define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU)
45 #define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU)
46 #define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U)
47 #define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U)
48 #define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U)
49 #define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U)
50 #define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U)
51 #define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U)
52 #define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U)
53 #define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U)
54 #define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U)
55 #define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U)
56 #define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU)
57 #define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU)
58 #define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU)
59 #define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU)
60 #define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU)
61 #define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU)
62
63 #define ARM_MPU_AP_NONE 0U
64 #define ARM_MPU_AP_PRIV 1U
65 #define ARM_MPU_AP_URO 2U
66 #define ARM_MPU_AP_FULL 3U
67 #define ARM_MPU_AP_PRO 5U
68 #define ARM_MPU_AP_RO 6U
69
70 /** MPU Region Base Address Register Value
71 *
72 * \param Region The region to be configured, number 0 to 15.
73 * \param BaseAddress The base address for the region.
74 */
75 #define ARM_MPU_RBAR(Region, BaseAddress) \
76 (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \
77 ((Region) & MPU_RBAR_REGION_Msk) | \
78 (MPU_RBAR_VALID_Msk))
79
80 /**
81 * MPU Region Attribute and Size Register Value
82 *
83 * \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
84 * \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
85 * \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
86 * \param IsShareable Region is shareable between multiple bus masters.
87 * \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
88 * \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
89 * \param SubRegionDisable Sub-region disable field.
90 * \param Size Region size of the region to be configured, for example 4K, 8K.
91 */
92 #define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
93 ((((DisableExec ) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \
94 (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \
95 (((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
96 (((IsShareable ) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \
97 (((IsCacheable ) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \
98 (((IsBufferable ) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk) | \
99 (((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \
100 (((Size ) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \
101 (MPU_RASR_ENABLE_Msk))
102
103
104 /**
105 * Struct for a single MPU Region
106 */
107 typedef struct {
108 uint32_t RBAR; //!< The region base address register value (RBAR)
109 uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
110 } ARM_MPU_Region_t;
111
112 /** Enable the MPU.
113 * \param MPU_Control Default access permissions for unconfigured regions.
114 */
ARM_MPU_Enable(uint32_t MPU_Control)115 __STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
116 {
117 __DSB();
118 __ISB();
119 MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
120 #ifdef SCB_SHCSR_MEMFAULTENA_Msk
121 SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
122 #endif
123 }
124
125 /** Disable the MPU.
126 */
ARM_MPU_Disable(void)127 __STATIC_INLINE void ARM_MPU_Disable(void)
128 {
129 __DSB();
130 __ISB();
131 #ifdef SCB_SHCSR_MEMFAULTENA_Msk
132 SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
133 #endif
134 MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
135 }
136
137 /** Clear and disable the given MPU region.
138 * \param rnr Region number to be cleared.
139 */
ARM_MPU_ClrRegion(uint32_t rnr)140 __STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
141 {
142 MPU->RNR = rnr;
143 MPU->RASR = 0U;
144 }
145
146 /** Configure an MPU region.
147 * \param rbar Value for RBAR register.
148 * \param rsar Value for RSAR register.
149 */
ARM_MPU_SetRegion(uint32_t rbar,uint32_t rasr)150 __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
151 {
152 MPU->RBAR = rbar;
153 MPU->RASR = rasr;
154 }
155
156 /** Configure the given MPU region.
157 * \param rnr Region number to be configured.
158 * \param rbar Value for RBAR register.
159 * \param rsar Value for RSAR register.
160 */
ARM_MPU_SetRegionEx(uint32_t rnr,uint32_t rbar,uint32_t rasr)161 __STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
162 {
163 MPU->RNR = rnr;
164 MPU->RBAR = rbar;
165 MPU->RASR = rasr;
166 }
167
168 /** Memcopy with strictly ordered memory access, e.g. for register targets.
169 * \param dst Destination data is copied to.
170 * \param src Source data is copied from.
171 * \param len Amount of data words to be copied.
172 */
orderedCpy(volatile uint32_t * dst,const uint32_t * __RESTRICT src,uint32_t len)173 __STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
174 {
175 uint32_t i;
176 for (i = 0U; i < len; ++i)
177 {
178 dst[i] = src[i];
179 }
180 }
181
182 /** Load the given number of MPU regions from a table.
183 * \param table Pointer to the MPU configuration table.
184 * \param cnt Amount of regions to be configured.
185 */
ARM_MPU_Load(ARM_MPU_Region_t const * table,uint32_t cnt)186 __STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt)
187 {
188 const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
189 while (cnt > MPU_TYPE_RALIASES) {
190 orderedCpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
191 table += MPU_TYPE_RALIASES;
192 cnt -= MPU_TYPE_RALIASES;
193 }
194 orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
195 }
196
197 #endif
198