1 /* 2 * Copyright (c) 2021 Chipsea Technologies (Shenzhen) Corp., Ltd. All rights reserved. 3 * Licensed under the Apache License, Version 2.0 (the "License"); 4 * you may not use this file except in compliance with the License. 5 * You may obtain a copy of the License at 6 * 7 * http://www.apache.org/licenses/LICENSE-2.0 8 * 9 * Unless required by applicable law or agreed to in writing, software 10 * distributed under the License is distributed on an "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 * See the License for the specific language governing permissions and 13 * limitations under the License. 14 */ 15 #ifndef _REG_SYSCTRL_H_ 16 #define _REG_SYSCTRL_H_ 17 18 #include "chip.h" 19 20 /* ================================================================================ */ 21 /* ================ CPU System Control ================ */ 22 /* ================================================================================ */ 23 typedef struct { 24 __IO uint32_t SYSREM; /* 0x000: System matrix remap */ 25 __IO uint32_t CLKSEL; /* 0x004: Clock selection */ 26 __IO uint32_t HCLKCM; /* 0x008: HCLK control mode */ 27 __IO uint32_t PCLKCM; /* 0x00C: PCLK control mode */ 28 __IO uint32_t OCLKCM; /* 0x010: Others CLK control mode */ 29 __IO uint32_t USBCCFG; /* 0x014: USB controller config */ 30 __IO uint32_t VPCCLKCTL; /* 0x018: VPC clock control */ 31 __IO uint32_t ROMCFG; /* 0x01C: ROM config */ 32 __IO uint32_t SRAMCFG[5]; /* 0x020: SRAM0 ~ SRAM4 config */ 33 __IO uint32_t ASDMAMCFG; /* 0x034: ASDMA memory config */ 34 __IO uint32_t CACHEMCFG; /* 0x038: Cache memory config */ 35 __IO uint32_t SDIOMCFG; /* 0x03C: SDIO memory config */ 36 __IO uint32_t SPIMCFG; /* 0x040: SPI memory config */ 37 __IO uint32_t USBCMCFG; /* 0x044: USBC memory config */ 38 __IO uint32_t DMAMCFG; /* 0x048: DMA memory config */ 39 __IO uint32_t CEMCFG; /* 0x04C: CE memory config */ 40 __IO uint32_t VPCMCFG; /* 0x050: VPC memory config */ 41 __IO uint32_t TPSEL; /* 0x054: Tports selection */ 42 __IO uint32_t TRAPBP; /* 0x058: TRAP bypass */ 43 __IO uint32_t CACHEBP; /* 0x05C: Cache bypass */ 44 __IO uint32_t HCLK1CM; /* 0x060: HCLK1 control mode */ 45 __IO uint32_t SRAMCFG5; /* 0x064: SRAM5 config */ 46 __IO uint32_t UARTMCFG; /* 0x068: UART memory config */ 47 __IO uint32_t CRCLKDIV; /* 0x06C: Camera ref clock div */ 48 __IO uint32_t JPEGENCMCFG; /* 0x070: JPEG encoder memory config */ 49 __IO uint32_t BTROMCFG; /* 0x074: BTROM memory config */ 50 __IO uint32_t ASDMACLKDIV; /* 0x078: ASDMA clock div */ 51 __IO uint32_t PSRMDSEL; /* 0x07C: PSRAM mode selection */ 52 __IO uint32_t SRAMCFG6; /* 0x080: SRAM6 config */ 53 __IO uint32_t PCLKDIV; /* 0x084: PCLK div */ 54 __IO uint32_t CMCLKDIV; /* 0x088: Codec MCLK div */ 55 __IO uint32_t CBCLKSEL; /* 0x08C: Codec BCLK selection */ 56 __IO uint32_t ULPICD; /* 0x090: ULPI clock detection */ 57 __IO uint32_t ULPICS; /* 0x094: ULPI clock status */ 58 __IO uint32_t PSRDBGSEL; /* 0x098: PSRAM debug selection */ 59 __IO uint32_t RESERVED0[25]; /* 0x09C: Reserved */ 60 __IO uint32_t HCLKME; /* 0x100: HCLK manual enable */ 61 __IO uint32_t HCLKMD; /* 0x104: HCLK manual disable */ 62 __IO uint32_t PCLKME; /* 0x108: PCLK manual enable */ 63 __IO uint32_t PCLKMD; /* 0x10C: PCLK manual disable */ 64 __IO uint32_t OCLKME; /* 0x110: Others CLK manual enable */ 65 __IO uint32_t OCLKMD; /* 0x114: Others CLK manual disable */ 66 __IO uint32_t HCLKRS; /* 0x118: HCLK soft resetn set register */ 67 __IO uint32_t HCLKRC; /* 0x11C: HCLK soft resetn clear register */ 68 __IO uint32_t PCLKRS; /* 0x120: PCLK soft resetn set register */ 69 __IO uint32_t PCLKRC; /* 0x124: PCLK soft resetn clear register */ 70 __IO uint32_t OCLKRS; /* 0x128: Others CLK soft resetn set register */ 71 __IO uint32_t OCLKRC; /* 0x12C: Others CLK soft resetn clear register */ 72 __IO uint32_t HCLK1ME; /* 0x130: HCLK1 manual enable */ 73 __IO uint32_t HCLK1MD; /* 0x134: HCLK1 manual disable */ 74 __IO uint32_t HCLK1RS; /* 0x138: HCLK1 soft resetn set register */ 75 __IO uint32_t HCLK1RC; /* 0x13C: HCLK1 soft resetn clear register */ 76 } CS_CPUSYSCTRL_TypeDef; 77 78 /* ================================================================================ */ 79 /* ================ AON System Control ================ */ 80 /* ================================================================================ */ 81 typedef struct { 82 __I uint32_t CHIPID; /* 0x000: Chip ID */ 83 __IO uint32_t CLKSEL; /* 0x004: Clock selection */ 84 __IO uint32_t HCLKCM; /* 0x008: HCLK control mode */ 85 __IO uint32_t FCLKCM; /* 0x00C: FCLK control mode */ 86 __IO uint32_t OCLKCM; /* 0x010: Others CLK control mode */ 87 __IO uint32_t HCLKDIV; /* 0x014: HCLK div */ 88 __IO uint32_t FCLKDIV; /* 0x018: FCLK div */ 89 __IO uint32_t AONSRAMCFG0; /* 0x01C: AON SRAM0 config */ 90 __I uint32_t RSTCAUSE; /* 0x020: Reset cause */ 91 __IO uint32_t SYSTPSEL; /* 0x024: AON system tports selection */ 92 __IO uint32_t TOPTPSEL; /* 0x028: digital top tports selection */ 93 __IO uint32_t PSRCLKDIV; /* 0x02C: PSRAM clock div */ 94 __IO uint32_t PSRCLKSEL; /* 0x030: PSRAM clock selection */ 95 __IO uint32_t R480MCLKDIV; /* 0x034: Real 480M CLK div */ 96 __IO uint32_t R320MCLKDIV; /* 0x038: Real 320M CLK div */ 97 __IO uint32_t CPUSWRA; /* 0x03C: CPU sw reset address */ 98 __IO uint32_t DSPRA; /* 0x040: DSP reset address */ 99 __IO uint32_t AONSRAMCFG1; /* 0x044: AON SRAM1 config */ 100 __IO uint32_t AONSRAMCFG2; /* 0x048: AON SRAM2 config */ 101 __IO uint32_t SRAMSDCFG; /* 0x04C: SRAM SD config */ 102 __IO uint32_t AONCLKDIV; /* 0x050: AON clock div */ 103 __IO uint32_t AONRAMMUX; /* 0x054: AON RAM mux */ 104 __IO uint32_t CPUSBRA; /* 0x058: CPU sb reset address */ 105 __IO uint32_t CPUAONRA; /* 0x05C: CPU AON reset address */ 106 __IO uint32_t AONROMCFG; /* 0x060: AON ROM config */ 107 __IO uint32_t AONTRAPC; /* 0x064: AON TRAP control */ 108 __IO uint32_t AONTRAPI[2]; /* 0x068: AON TRAP in 0~1, 2~3 */ 109 __IO uint32_t AONTRAPOB; /* 0x070: AON TRAP out base */ 110 __IO uint32_t OSCEN; /* 0x074: OSC enable */ 111 __IO uint32_t RESERVED0[34]; /* 0x078: Reserved */ 112 __IO uint32_t HCLKME; /* 0x100: HCLK manual enable */ 113 __IO uint32_t HCLKMD; /* 0x104: HCLK manual disable */ 114 __IO uint32_t FCLKME; /* 0x108: FCLK manual enable */ 115 __IO uint32_t FCLKMD; /* 0x10C: FCLK manual disable */ 116 __IO uint32_t OCLKME; /* 0x110: Others CLK manual enable */ 117 __IO uint32_t OCLKMD; /* 0x114: Others CLK manual disable */ 118 __IO uint32_t GLBRS; /* 0x118: Global soft resetn set register */ 119 __IO uint32_t GLBRC; /* 0x11C: Global soft resetn clear register */ 120 __IO uint32_t HCLKRS; /* 0x120: HCLK soft resetn set register */ 121 __IO uint32_t HCLKRC; /* 0x124: HCLK soft resetn clear register */ 122 __IO uint32_t FCLKRS; /* 0x128: FCLK soft resetn set register */ 123 __IO uint32_t FCLKRC; /* 0x12C: FCLK soft resetn clear register */ 124 __IO uint32_t OCLKRS; /* 0x130: Others CLK soft resetn set register */ 125 __IO uint32_t OCLKRC; /* 0x134: Others CLK soft resetn clear register */ 126 __IO uint32_t BOOTMD; /* 0x138: Boot mode */ 127 __IO uint32_t WDTRE; /* 0x13C: Watch dog timer reset enable */ 128 union { 129 __IO uint32_t AONCOMREG[8]; /* 0x140~0x15C: Aon common regs, sw defined below */ 130 struct { 131 __IO uint32_t BTFWCTRL; /* 0x140: Bt fw stack top & bt_core sw ctrl mode */ 132 __IO uint32_t WIFIFWCTRL; /* 0x144: Wifi fw stack top & wifi_core sw ctrl mode */ 133 __IO uint32_t BOOTENTRY; /* 0x148: Boot entry */ 134 __IO uint32_t BOOTSTACK; /* 0x14C: Boot stack */ 135 __IO uint32_t HOSTTCLSB; /* 0x150: Host time count lsb */ 136 __IO uint32_t HOSTTCMSB; /* 0x154: Host time count msb */ 137 __IO uint32_t HOSTSYST; /* 0x158: Host systick */ 138 __IO uint32_t BTPWRCTRL; /* 0x15C: BT power control */ 139 }; 140 }; 141 } CS_AONSYSCTRL_TypeDef; 142 143 /* ================================================================================ */ 144 /* ================ Power Control ================ */ 145 /* ================================================================================ */ 146 typedef struct { 147 __IO uint32_t CPUSYS; /* 0x000: CPU system */ 148 __IO uint32_t BTCORE; /* 0x004: BT core */ 149 __IO uint32_t WIFICORE; /* 0x008: WIFI core */ 150 __IO uint32_t RESERVED0; /* 0x00C: Reserved */ 151 __IO uint32_t PWRSYS; /* 0x010: Power system */ 152 __IO uint32_t OFFTIMTH[2]; /* 0x014: Power off timer th 0 ~ 1 */ 153 __IO uint32_t CTRLDLY[2]; /* 0x01C: Power control delay 0 ~ 1 */ 154 __IO uint32_t SYSDLY[2]; /* 0x024: Power system delay 0 ~ 1 */ 155 __IO uint32_t RESERVED1; /* 0x02C: Reserved */ 156 __I uint32_t STATE[2]; /* 0x030: State 0 ~ 1 */ 157 __IO uint32_t SOFTMD1; /* 0x038: Soft mode 1 */ 158 __IO uint32_t AONRAM1; /* 0x03C: Aon RAM1 */ 159 __IO uint32_t AONRAM2; /* 0x040: Aon RAM2 */ 160 __IO uint32_t IRQCTRL; /* 0x044: IRQ control */ 161 __IO uint32_t IRQSTATUS; /* 0x048: IRQ status */ 162 __IO uint32_t MMSYS; /* 0x04C: Memory system */ 163 __IO uint32_t SOFTMD2; /* 0x050: Soft mode 2 */ 164 __IO uint32_t VCORESYS; /* 0x054: vcore system */ 165 __IO uint32_t OFFTIMTH3; /* 0x058: Power off timer th 3 */ 166 __IO uint32_t PWRMD; /* 0x05C: Power mode */ 167 } CS_PWRCTRL_TypeDef; 168 169 static CS_CPUSYSCTRL_TypeDef * const CS_CPUSYSCTRL = ((CS_CPUSYSCTRL_TypeDef *)CS_CPUSYSCTRL_BASE); 170 static CS_AONSYSCTRL_TypeDef * const CS_AONSYSCTRL = ((CS_AONSYSCTRL_TypeDef *)CS_AONSYSCTRL_BASE); 171 static CS_PWRCTRL_TypeDef * const CS_PWRCTRL = ((CS_PWRCTRL_TypeDef *)CS_PWRCTRL_BASE); 172 173 /** 174 * Address Offset: 0x000 175 * Register Name : ASC CHIPID 176 */ 177 178 #define ASC_CHIPID_CHIP_ID_LSB (0) 179 #define ASC_CHIPID_CHIP_ID_WIDTH (16) 180 #define ASC_CHIPID_CHIP_ID_MASK (((0x01UL << ASC_CHIPID_CHIP_ID_WIDTH) - 1) << ASC_CHIPID_CHIP_ID_LSB) 181 #define ASC_CHIPID_METAL_ID_LSB (16) 182 #define ASC_CHIPID_METAL_ID_WIDTH (8) 183 #define ASC_CHIPID_METAL_ID_MASK (((0x01UL << ASC_CHIPID_METAL_ID_WIDTH) - 1) << ASC_CHIPID_METAL_ID_LSB) 184 #define ASC_CHIPID_BOND_ID_LSB (24) 185 #define ASC_CHIPID_BOND_ID_WIDTH (8) 186 #define ASC_CHIPID_BOND_ID_MASK (((0x01UL << ASC_CHIPID_BOND_ID_WIDTH) - 1) << ASC_CHIPID_BOND_ID_LSB) 187 aonsysctrl_chipid_chip_id_getf(void)188__STATIC_INLINE uint16_t aonsysctrl_chipid_chip_id_getf(void) 189 { 190 return ((CS_AONSYSCTRL->CHIPID & ASC_CHIPID_CHIP_ID_MASK) >> ASC_CHIPID_CHIP_ID_LSB); 191 } 192 aonsysctrl_chipid_metal_id_getf(void)193__STATIC_INLINE uint8_t aonsysctrl_chipid_metal_id_getf(void) 194 { 195 return ((CS_AONSYSCTRL->CHIPID & ASC_CHIPID_METAL_ID_MASK) >> ASC_CHIPID_METAL_ID_LSB); 196 } 197 aonsysctrl_chipid_bond_id_getf(void)198__STATIC_INLINE uint8_t aonsysctrl_chipid_bond_id_getf(void) 199 { 200 return ((CS_AONSYSCTRL->CHIPID & ASC_CHIPID_BOND_ID_MASK) >> ASC_CHIPID_BOND_ID_LSB); 201 } 202 203 /** 204 * Address Offset: 0x004 205 * Register Name : ASC CLKSEL 206 */ 207 208 #define ASC_CLKSEL_FASTHWEN_POS (0) 209 #define ASC_CLKSEL_FASTHWEN_BIT (0x01UL << ASC_CLKSEL_FASTHWEN_POS) 210 #define ASC_CLKSEL_FASTCLK_POS (4) 211 #define ASC_CLKSEL_FASTCLK_BIT (0x01UL << ASC_CLKSEL_FASTCLK_POS) 212 #define ASC_CLKSEL_PLL320M_POS (8) 213 #define ASC_CLKSEL_PLL320M_BIT (0x01UL << ASC_CLKSEL_PLL320M_POS) 214 #define ASC_CLKSEL_PLLFLEX_POS (12) 215 #define ASC_CLKSEL_PLLFLEX_BIT (0x01UL << ASC_CLKSEL_PLLFLEX_POS) 216 #define ASC_CLKSEL_AONCLK_POS (16) 217 #define ASC_CLKSEL_AONCLK_BIT (0x01UL << ASC_CLKSEL_AONCLK_POS) 218 aonsysctrl_clksel_get(void)219__STATIC_INLINE uint32_t aonsysctrl_clksel_get(void) 220 { 221 return CS_AONSYSCTRL->CLKSEL; 222 } 223 aonsysctrl_clksel_set(uint32_t clk_sel)224__STATIC_INLINE void aonsysctrl_clksel_set(uint32_t clk_sel) 225 { 226 CS_AONSYSCTRL->CLKSEL = clk_sel; 227 } 228 aonsysctrl_fast_hwen_getb(void)229__STATIC_INLINE uint8_t aonsysctrl_fast_hwen_getb(void) 230 { 231 return (CS_AONSYSCTRL->CLKSEL & ASC_CLKSEL_FASTHWEN_BIT) >> ASC_CLKSEL_FASTHWEN_POS; 232 } 233 aonsysctrl_fast_hwen_setb(void)234__STATIC_INLINE void aonsysctrl_fast_hwen_setb(void) 235 { 236 CS_AONSYSCTRL->CLKSEL |= ASC_CLKSEL_FASTHWEN_BIT; 237 } 238 aonsysctrl_fast_hwen_clrb(void)239__STATIC_INLINE void aonsysctrl_fast_hwen_clrb(void) 240 { 241 CS_AONSYSCTRL->CLKSEL &= ~ASC_CLKSEL_FASTHWEN_BIT; 242 } 243 aonsysctrl_fast_clk_getb(void)244__STATIC_INLINE uint8_t aonsysctrl_fast_clk_getb(void) 245 { 246 return (CS_AONSYSCTRL->CLKSEL & ASC_CLKSEL_FASTCLK_BIT) >> ASC_CLKSEL_FASTCLK_POS; 247 } 248 aonsysctrl_fast_clk_setb(void)249__STATIC_INLINE void aonsysctrl_fast_clk_setb(void) 250 { 251 CS_AONSYSCTRL->CLKSEL |= ASC_CLKSEL_FASTCLK_BIT; 252 } 253 aonsysctrl_fast_clk_clrb(void)254__STATIC_INLINE void aonsysctrl_fast_clk_clrb(void) 255 { 256 CS_AONSYSCTRL->CLKSEL &= ~ASC_CLKSEL_FASTCLK_BIT; 257 } 258 aonsysctrl_pll_320m_getb(void)259__STATIC_INLINE uint8_t aonsysctrl_pll_320m_getb(void) 260 { 261 return (CS_AONSYSCTRL->CLKSEL & ASC_CLKSEL_PLL320M_BIT) >> ASC_CLKSEL_PLL320M_POS; 262 } 263 aonsysctrl_pll_320m_setb(void)264__STATIC_INLINE void aonsysctrl_pll_320m_setb(void) 265 { 266 CS_AONSYSCTRL->CLKSEL |= ASC_CLKSEL_PLL320M_BIT; 267 } 268 aonsysctrl_pll_320m_clrb(void)269__STATIC_INLINE void aonsysctrl_pll_320m_clrb(void) 270 { 271 CS_AONSYSCTRL->CLKSEL &= ~ASC_CLKSEL_PLL320M_BIT; 272 } 273 aonsysctrl_pll_flex_getb(void)274__STATIC_INLINE uint8_t aonsysctrl_pll_flex_getb(void) 275 { 276 return (CS_AONSYSCTRL->CLKSEL & ASC_CLKSEL_PLLFLEX_BIT) >> ASC_CLKSEL_PLLFLEX_POS; 277 } 278 aonsysctrl_pll_flex_setb(void)279__STATIC_INLINE void aonsysctrl_pll_flex_setb(void) 280 { 281 CS_AONSYSCTRL->CLKSEL |= ASC_CLKSEL_PLLFLEX_BIT; 282 } 283 aonsysctrl_pll_flex_clrb(void)284__STATIC_INLINE void aonsysctrl_pll_flex_clrb(void) 285 { 286 CS_AONSYSCTRL->CLKSEL &= ~ASC_CLKSEL_PLLFLEX_BIT; 287 } 288 aonsysctrl_aon_clk_getb(void)289__STATIC_INLINE uint8_t aonsysctrl_aon_clk_getb(void) 290 { 291 return (CS_AONSYSCTRL->CLKSEL & ASC_CLKSEL_AONCLK_BIT) >> ASC_CLKSEL_AONCLK_POS; 292 } 293 aonsysctrl_aon_clk_setb(void)294__STATIC_INLINE void aonsysctrl_aon_clk_setb(void) 295 { 296 CS_AONSYSCTRL->CLKSEL |= ASC_CLKSEL_AONCLK_BIT; 297 } 298 aonsysctrl_aon_clk_clrb(void)299__STATIC_INLINE void aonsysctrl_aon_clk_clrb(void) 300 { 301 CS_AONSYSCTRL->CLKSEL &= ~ASC_CLKSEL_AONCLK_BIT; 302 } 303 304 /** 305 * Address Offset: 0x010 306 * Register Name : ASC OCLK_CTRL_MODE 307 */ 308 309 #define ASC_OCLKCM_CLK26M_AONSYS_MANUAL_POS (0) 310 #define ASC_OCLKCM_CLK26M_AONSYS_MANUAL_BIT (0x01UL << ASC_OCLKCM_CLK26M_AONSYS_MANUAL_POS) 311 #define ASC_OCLKCM_CLK26M_CPUSYS_MANUAL_POS (1) 312 #define ASC_OCLKCM_CLK26M_CPUSYS_MANUAL_BIT (0x01UL << ASC_OCLKCM_CLK26M_CPUSYS_MANUAL_POS) 313 #define ASC_OCLKCM_CLK26M_TIMER20_MANUAL_POS (2) 314 #define ASC_OCLKCM_CLK26M_TIMER20_MANUAL_BIT (0x01UL << ASC_OCLKCM_CLK26M_TIMER20_MANUAL_POS) 315 #define ASC_OCLKCM_CLK32K_TIMER21_MANUAL_POS (3) 316 #define ASC_OCLKCM_CLK32K_TIMER21_MANUAL_BIT (0x01UL << ASC_OCLKCM_CLK32K_TIMER21_MANUAL_POS) 317 #define ASC_OCLKCM_CLK32K_TIMER22_MANUAL_POS (4) 318 #define ASC_OCLKCM_CLK32K_TIMER22_MANUAL_BIT (0x01UL << ASC_OCLKCM_CLK32K_TIMER22_MANUAL_POS) 319 #define ASC_OCLKCM_CLK32K_AONSYS_MANUAL_POS (5) 320 #define ASC_OCLKCM_CLK32K_AONSYS_MANUAL_BIT (0x01UL << ASC_OCLKCM_CLK32K_AONSYS_MANUAL_POS) 321 #define ASC_OCLKCM_CLK32K_CPUSYS_MANUAL_POS (6) 322 #define ASC_OCLKCM_CLK32K_CPUSYS_MANUAL_BIT (0x01UL << ASC_OCLKCM_CLK32K_CPUSYS_MANUAL_POS) 323 #define ASC_OCLKCM_CLK32K_WIFISYS_MANUAL_POS (7) 324 #define ASC_OCLKCM_CLK32K_WIFISYS_MANUAL_BIT (0x01UL << ASC_OCLKCM_CLK32K_WIFISYS_MANUAL_POS) 325 #define ASC_OCLKCM_CLK32K_BTSYS_MANUAL_POS (8) 326 #define ASC_OCLKCM_CLK32K_BTSYS_MANUAL_BIT (0x01UL << ASC_OCLKCM_CLK32K_BTSYS_MANUAL_POS) 327 #define ASC_OCLKCM_CLK_I2CS_MANUAL_POS (9) 328 #define ASC_OCLKCM_CLK_I2CS_MANUAL_BIT (0x01UL << ASC_OCLKCM_CLK_I2CS_MANUAL_POS) 329 #define ASC_OCLKCM_CLK_MEM2X_MANUAL_POS (10) 330 #define ASC_OCLKCM_CLK_MEM2X_MANUAL_BIT (0x01UL << ASC_OCLKCM_CLK_MEM2X_MANUAL_POS) 331 #define ASC_OCLKCM_CLK_EFUSE_MANUAL_POS (11) 332 #define ASC_OCLKCM_CLK_EFUSE_MANUAL_BIT (0x01UL << ASC_OCLKCM_CLK_EFUSE_MANUAL_POS) 333 #define ASC_OCLKCM_CLK32K_WIFIAON_MANUAL_POS (12) 334 #define ASC_OCLKCM_CLK32K_WIFIAON_MANUAL_BIT (0x01UL << ASC_OCLKCM_CLK32K_WIFIAON_MANUAL_POS) 335 #define ASC_OCLKCM_CLK32K_BTAON_MANUAL_POS (13) 336 #define ASC_OCLKCM_CLK32K_BTAON_MANUAL_BIT (0x01UL << ASC_OCLKCM_CLK32K_BTAON_MANUAL_POS) 337 #define ASC_OCLKCM_CLK52M_CPUSYS_MANUAL_POS (14) 338 #define ASC_OCLKCM_CLK52M_CPUSYS_MANUAL_BIT (0x01UL << ASC_OCLKCM_CLK52M_CPUSYS_MANUAL_POS) 339 #define ASC_OCLKCM_HCLK_AONROM_MANUAL_POS (15) 340 #define ASC_OCLKCM_HCLK_AONROM_MANUAL_BIT (0x01UL << ASC_OCLKCM_HCLK_AONROM_MANUAL_POS) 341 #define ASC_OCLKCM_HCLK_APB1_MANUAL_POS (16) 342 #define ASC_OCLKCM_HCLK_APB1_MANUAL_BIT (0x01UL << ASC_OCLKCM_HCLK_APB1_MANUAL_POS) 343 #define ASC_OCLKCM_HCLK_I2CS_MANUAL_POS (17) 344 #define ASC_OCLKCM_HCLK_I2CS_MANUAL_BIT (0x01UL << ASC_OCLKCM_HCLK_I2CS_MANUAL_POS) 345 #define ASC_OCLKCM_PCLK_SYSCTRL_MANUAL_POS (18) 346 #define ASC_OCLKCM_PCLK_SYSCTRL_MANUAL_BIT (0x01UL << ASC_OCLKCM_PCLK_SYSCTRL_MANUAL_POS) 347 #define ASC_OCLKCM_PCLK_PWRCTRL_MANUAL_POS (19) 348 #define ASC_OCLKCM_PCLK_PWRCTRL_MANUAL_BIT (0x01UL << ASC_OCLKCM_PCLK_PWRCTRL_MANUAL_POS) 349 #define ASC_OCLKCM_PCLK_GPIO_MANUAL_POS (20) 350 #define ASC_OCLKCM_PCLK_GPIO_MANUAL_BIT (0x01UL << ASC_OCLKCM_PCLK_GPIO_MANUAL_POS) 351 #define ASC_OCLKCM_PCLK_TIMER2_MANUAL_POS (21) 352 #define ASC_OCLKCM_PCLK_TIMER2_MANUAL_BIT (0x01UL << ASC_OCLKCM_PCLK_TIMER2_MANUAL_POS) 353 #define ASC_OCLKCM_PCLK_IOMUX_MANUAL_POS (22) 354 #define ASC_OCLKCM_PCLK_IOMUX_MANUAL_BIT (0x01UL << ASC_OCLKCM_PCLK_IOMUX_MANUAL_POS) 355 #define ASC_OCLKCM_PCLK_EFUSE_MANUAL_POS (23) 356 #define ASC_OCLKCM_PCLK_EFUSE_MANUAL_BIT (0x01UL << ASC_OCLKCM_PCLK_EFUSE_MANUAL_POS) 357 #define ASC_OCLKCM_HCLK_ALWAYS_CPUAON_MANUAL_POS (24) 358 #define ASC_OCLKCM_HCLK_ALWAYS_CPUAON_MANUAL_BIT (0x01UL << ASC_OCLKCM_HCLK_ALWAYS_CPUAON_MANUAL_POS) 359 #define ASC_OCLKCM_HCLK_CPUAON_MANUAL_POS (25) 360 #define ASC_OCLKCM_HCLK_CPUAON_MANUAL_BIT (0x01UL << ASC_OCLKCM_HCLK_CPUAON_MANUAL_POS) 361 #define ASC_OCLKCM_HCLK_AONSRAM_MANUAL_POS (26) 362 #define ASC_OCLKCM_HCLK_AONSRAM_MANUAL_BIT (0x01UL << ASC_OCLKCM_HCLK_AONSRAM_MANUAL_POS) 363 #define ASC_OCLKCM_PCLK_WDG4_MANUAL_POS (27) 364 #define ASC_OCLKCM_PCLK_WDG4_MANUAL_BIT (0x01UL << ASC_OCLKCM_PCLK_WDG4_MANUAL_POS) 365 #define ASC_OCLKCM_PCLK_PSIM_MANUAL_POS (28) 366 #define ASC_OCLKCM_PCLK_PSIM_MANUAL_BIT (0x01UL << ASC_OCLKCM_PCLK_PSIM_MANUAL_POS) 367 #define ASC_OCLKCM_PCLK_ANAREG_MANUAL_POS (29) 368 #define ASC_OCLKCM_PCLK_ANAREG_MANUAL_BIT (0x01UL << ASC_OCLKCM_PCLK_ANAREG_MANUAL_POS) 369 #define ASC_OCLKCM_CLKRTC_WDG4_MANUAL_POS (30) 370 #define ASC_OCLKCM_CLKRTC_WDG4_MANUAL_BIT (0x01UL << ASC_OCLKCM_CLKRTC_WDG4_MANUAL_POS) 371 #define ASC_OCLKCM_HCLK_WCNAON_MANUAL_POS (31) 372 #define ASC_OCLKCM_HCLK_WCNAON_MANUAL_BIT (0x01UL << ASC_OCLKCM_HCLK_WCNAON_MANUAL_POS) 373 aonsysctrl_oclkcm_get(void)374__STATIC_INLINE uint32_t aonsysctrl_oclkcm_get(void) 375 { 376 return CS_AONSYSCTRL->OCLKCM; 377 } 378 aonsysctrl_oclkcm_set(uint32_t manual_mode)379__STATIC_INLINE void aonsysctrl_oclkcm_set(uint32_t manual_mode) 380 { 381 CS_AONSYSCTRL->OCLKCM = manual_mode; 382 } 383 384 /** 385 * Address Offset: 0x014 386 * Register Name : ASC HCLK_DIV 387 */ 388 389 #define ASC_HCLKDIV_DENOM_LSB (0) 390 #define ASC_HCLKDIV_DENOM_WIDTH (8) 391 #define ASC_HCLKDIV_DENOM_MASK (((0x01UL << ASC_HCLKDIV_DENOM_WIDTH) - 1) << ASC_HCLKDIV_DENOM_LSB) 392 #define ASC_HCLKDIV_UPDATE_POS (8) 393 #define ASC_HCLKDIV_UPDATE_BIT (0x01UL << ASC_HCLKDIV_UPDATE_POS) 394 aonsysctrl_hclkdiv_denom_getf(void)395__STATIC_INLINE uint8_t aonsysctrl_hclkdiv_denom_getf(void) 396 { 397 return ((CS_AONSYSCTRL->HCLKDIV & ASC_HCLKDIV_DENOM_MASK) >> ASC_HCLKDIV_DENOM_LSB); 398 } 399 aonsysctrl_hclkdiv_denom_setf(uint8_t div_denom)400__STATIC_INLINE void aonsysctrl_hclkdiv_denom_setf(uint8_t div_denom) 401 { 402 uint32_t local_val = CS_AONSYSCTRL->HCLKDIV & ~ASC_HCLKDIV_DENOM_MASK; 403 CS_AONSYSCTRL->HCLKDIV = local_val | ((div_denom << ASC_HCLKDIV_DENOM_LSB) & ASC_HCLKDIV_DENOM_MASK) | ASC_HCLKDIV_UPDATE_BIT; 404 } 405 406 /** 407 * Address Offset: 0x018 408 * Register Name : ASC FCLK_DIV 409 */ 410 411 #define ASC_FCLKDIV_DENOM_LSB (0) 412 #define ASC_FCLKDIV_DENOM_WIDTH (8) 413 #define ASC_FCLKDIV_DENOM_MASK (((0x01UL << ASC_FCLKDIV_DENOM_WIDTH) - 1) << ASC_FCLKDIV_DENOM_LSB) 414 #define ASC_FCLKDIV_UPDATE_POS (8) 415 #define ASC_FCLKDIV_UPDATE_BIT (0x01UL << ASC_FCLKDIV_UPDATE_POS) 416 aonsysctrl_fclkdiv_denom_getf(void)417__STATIC_INLINE uint8_t aonsysctrl_fclkdiv_denom_getf(void) 418 { 419 return ((CS_AONSYSCTRL->FCLKDIV & ASC_FCLKDIV_DENOM_MASK) >> ASC_FCLKDIV_DENOM_LSB); 420 } 421 aonsysctrl_fclkdiv_denom_setf(uint8_t div_denom)422__STATIC_INLINE void aonsysctrl_fclkdiv_denom_setf(uint8_t div_denom) 423 { 424 uint32_t local_val = CS_AONSYSCTRL->FCLKDIV & ~ASC_FCLKDIV_DENOM_MASK; 425 CS_AONSYSCTRL->FCLKDIV = local_val | ((div_denom << ASC_FCLKDIV_DENOM_LSB) & ASC_FCLKDIV_DENOM_MASK) | ASC_FCLKDIV_UPDATE_BIT; 426 } 427 428 /** 429 * Address Offset: 0x020 430 * Register Name : ASC RESET_CAUSE 431 */ 432 433 #define ASC_RSTCAUSE_WDT0_RST_POS (0) 434 #define ASC_RSTCAUSE_WDT0_RST_BIT (0x01UL << ASC_RSTCAUSE_WDT0_RST_POS) 435 #define ASC_RSTCAUSE_WDT1_RST_POS (1) 436 #define ASC_RSTCAUSE_WDT1_RST_BIT (0x01UL << ASC_RSTCAUSE_WDT1_RST_POS) 437 #define ASC_RSTCAUSE_WDT2_RST_POS (2) 438 #define ASC_RSTCAUSE_WDT2_RST_BIT (0x01UL << ASC_RSTCAUSE_WDT2_RST_POS) 439 #define ASC_RSTCAUSE_WDT3_RST_POS (3) 440 #define ASC_RSTCAUSE_WDT3_RST_BIT (0x01UL << ASC_RSTCAUSE_WDT3_RST_POS) 441 #define ASC_RSTCAUSE_WDT4_RST_POS (4) 442 #define ASC_RSTCAUSE_WDT4_RST_BIT (0x01UL << ASC_RSTCAUSE_WDT4_RST_POS) 443 #define ASC_RSTCAUSE_CPUP_SYSRST_REQ_POS (5) 444 #define ASC_RSTCAUSE_CPUP_SYSRST_REQ_BIT (0x01UL << ASC_RSTCAUSE_CPUP_SYSRST_REQ_POS) 445 #define ASC_RSTCAUSE_CPUSW_SYSRST_REQ_POS (6) 446 #define ASC_RSTCAUSE_CPUSW_SYSRST_REQ_BIT (0x01UL << ASC_RSTCAUSE_CPUSW_SYSRST_REQ_POS) 447 #define ASC_RSTCAUSE_DSP_SYSRST_REQ_POS (7) 448 #define ASC_RSTCAUSE_DSP_SYSRST_REQ_BIT (0x01UL << ASC_RSTCAUSE_DSP_SYSRST_REQ_POS) 449 #define ASC_RSTCAUSE_CPUSB_SYSRST_REQ_POS (8) 450 #define ASC_RSTCAUSE_CPUSB_SYSRST_REQ_BIT (0x01UL << ASC_RSTCAUSE_CPUSB_SYSRST_REQ_POS) 451 #define ASC_RSTCAUSE_CPUAON_SYSRST_REQ_POS (9) 452 #define ASC_RSTCAUSE_CPUAON_SYSRST_REQ_BIT (0x01UL << ASC_RSTCAUSE_CPUAON_SYSRST_REQ_POS) 453 #define ASC_RSTCAUSE_GLOBAL_SOFT_RESET_POS (10) 454 #define ASC_RSTCAUSE_GLOBAL_SOFT_RESET_BIT (0x01UL << ASC_RSTCAUSE_GLOBAL_SOFT_RESET_POS) 455 aonsysctrl_rstcause_get(void)456__STATIC_INLINE uint32_t aonsysctrl_rstcause_get(void) 457 { 458 return CS_AONSYSCTRL->RSTCAUSE; 459 } 460 aonsysctrl_rstcause_wdt0_rst_getb(void)461__STATIC_INLINE uint8_t aonsysctrl_rstcause_wdt0_rst_getb(void) 462 { 463 return (CS_AONSYSCTRL->RSTCAUSE & ASC_RSTCAUSE_WDT0_RST_BIT) >> ASC_RSTCAUSE_WDT0_RST_POS; 464 } 465 aonsysctrl_rstcause_wdt1_rst_getb(void)466__STATIC_INLINE uint8_t aonsysctrl_rstcause_wdt1_rst_getb(void) 467 { 468 return (CS_AONSYSCTRL->RSTCAUSE & ASC_RSTCAUSE_WDT1_RST_BIT) >> ASC_RSTCAUSE_WDT1_RST_POS; 469 } 470 aonsysctrl_rstcause_wdt2_rst_getb(void)471__STATIC_INLINE uint8_t aonsysctrl_rstcause_wdt2_rst_getb(void) 472 { 473 return (CS_AONSYSCTRL->RSTCAUSE & ASC_RSTCAUSE_WDT2_RST_BIT) >> ASC_RSTCAUSE_WDT2_RST_POS; 474 } 475 aonsysctrl_rstcause_wdt3_rst_getb(void)476__STATIC_INLINE uint8_t aonsysctrl_rstcause_wdt3_rst_getb(void) 477 { 478 return (CS_AONSYSCTRL->RSTCAUSE & ASC_RSTCAUSE_WDT3_RST_BIT) >> ASC_RSTCAUSE_WDT3_RST_POS; 479 } 480 aonsysctrl_rstcause_wdt4_rst_getb(void)481__STATIC_INLINE uint8_t aonsysctrl_rstcause_wdt4_rst_getb(void) 482 { 483 return (CS_AONSYSCTRL->RSTCAUSE & ASC_RSTCAUSE_WDT4_RST_BIT) >> ASC_RSTCAUSE_WDT4_RST_POS; 484 } 485 aonsysctrl_rstcause_cpup_sysrst_req_getb(void)486__STATIC_INLINE uint8_t aonsysctrl_rstcause_cpup_sysrst_req_getb(void) 487 { 488 return (CS_AONSYSCTRL->RSTCAUSE & ASC_RSTCAUSE_CPUP_SYSRST_REQ_BIT) >> ASC_RSTCAUSE_CPUP_SYSRST_REQ_POS; 489 } 490 aonsysctrl_rstcause_cpusw_sysrst_req_getb(void)491__STATIC_INLINE uint8_t aonsysctrl_rstcause_cpusw_sysrst_req_getb(void) 492 { 493 return (CS_AONSYSCTRL->RSTCAUSE & ASC_RSTCAUSE_CPUSW_SYSRST_REQ_BIT) >> ASC_RSTCAUSE_CPUSW_SYSRST_REQ_POS; 494 } 495 aonsysctrl_rstcause_dsp_sysrst_req_getb(void)496__STATIC_INLINE uint8_t aonsysctrl_rstcause_dsp_sysrst_req_getb(void) 497 { 498 return (CS_AONSYSCTRL->RSTCAUSE & ASC_RSTCAUSE_DSP_SYSRST_REQ_BIT) >> ASC_RSTCAUSE_DSP_SYSRST_REQ_POS; 499 } 500 aonsysctrl_rstcause_cpusb_sysrst_req_getb(void)501__STATIC_INLINE uint8_t aonsysctrl_rstcause_cpusb_sysrst_req_getb(void) 502 { 503 return (CS_AONSYSCTRL->RSTCAUSE & ASC_RSTCAUSE_CPUSB_SYSRST_REQ_BIT) >> ASC_RSTCAUSE_CPUSB_SYSRST_REQ_POS; 504 } 505 aonsysctrl_rstcause_cpuaon_sysrst_req_getb(void)506__STATIC_INLINE uint8_t aonsysctrl_rstcause_cpuaon_sysrst_req_getb(void) 507 { 508 return (CS_AONSYSCTRL->RSTCAUSE & ASC_RSTCAUSE_CPUAON_SYSRST_REQ_BIT) >> ASC_RSTCAUSE_CPUAON_SYSRST_REQ_POS; 509 } 510 aonsysctrl_rstcause_global_soft_reset_getb(void)511__STATIC_INLINE uint8_t aonsysctrl_rstcause_global_soft_reset_getb(void) 512 { 513 return (CS_AONSYSCTRL->RSTCAUSE & ASC_RSTCAUSE_GLOBAL_SOFT_RESET_BIT) >> ASC_RSTCAUSE_GLOBAL_SOFT_RESET_POS; 514 } 515 516 /** 517 * Address Offset: 0x02C 518 * Register Name : ASC PSRAM_CLK_DIV 519 */ 520 521 #define ASC_PSRCLKDIV_DENOM_LSB (0) 522 #define ASC_PSRCLKDIV_DENOM_WIDTH (8) 523 #define ASC_PSRCLKDIV_DENOM_MASK (((0x01UL << ASC_PSRCLKDIV_DENOM_WIDTH) - 1) << ASC_PSRCLKDIV_DENOM_LSB) 524 #define ASC_PSRCLKDIV_UPDATE_POS (8) 525 #define ASC_PSRCLKDIV_UPDATE_BIT (0x01UL << ASC_PSRCLKDIV_UPDATE_POS) 526 aonsysctrl_psrclkdiv_denom_getf(void)527__STATIC_INLINE uint8_t aonsysctrl_psrclkdiv_denom_getf(void) 528 { 529 return ((CS_AONSYSCTRL->PSRCLKDIV & ASC_PSRCLKDIV_DENOM_MASK) >> ASC_PSRCLKDIV_DENOM_LSB); 530 } 531 aonsysctrl_psrclkdiv_denom_setf(uint8_t div_denom)532__STATIC_INLINE void aonsysctrl_psrclkdiv_denom_setf(uint8_t div_denom) 533 { 534 uint32_t local_val = CS_AONSYSCTRL->PSRCLKDIV & ~ASC_PSRCLKDIV_DENOM_MASK; 535 CS_AONSYSCTRL->PSRCLKDIV = local_val | ((div_denom << ASC_PSRCLKDIV_DENOM_LSB) & ASC_PSRCLKDIV_DENOM_MASK) | ASC_PSRCLKDIV_UPDATE_BIT; 536 } 537 538 /** 539 * Address Offset: 0x030 540 * Register Name : ASC PSRAM_CLK_SEL 541 */ 542 543 #define ASC_PSRCLKSEL_FAST_POS (0) 544 #define ASC_PSRCLKSEL_FAST_BIT (0x01UL << ASC_PSRCLKSEL_FAST_POS) 545 aonsysctrl_psrclksel_fast_getb(void)546__STATIC_INLINE uint8_t aonsysctrl_psrclksel_fast_getb(void) 547 { 548 return (CS_AONSYSCTRL->PSRCLKSEL & ASC_PSRCLKSEL_FAST_BIT) >> ASC_PSRCLKSEL_FAST_POS; 549 } 550 aonsysctrl_psrclksel_fast_setb(void)551__STATIC_INLINE void aonsysctrl_psrclksel_fast_setb(void) 552 { 553 CS_AONSYSCTRL->PSRCLKSEL |= ASC_PSRCLKSEL_FAST_BIT; 554 } 555 aonsysctrl_psrclksel_fast_clrb(void)556__STATIC_INLINE void aonsysctrl_psrclksel_fast_clrb(void) 557 { 558 CS_AONSYSCTRL->PSRCLKSEL &= ~ASC_PSRCLKSEL_FAST_BIT; 559 } 560 561 /** 562 * Address Offset: 0x03C 563 * Register Name : ASC CPU_SW_RESET_ADDR 564 */ 565 aonsysctrl_cpuswra_get(void)566__STATIC_INLINE uint32_t aonsysctrl_cpuswra_get(void) 567 { 568 return CS_AONSYSCTRL->CPUSWRA; 569 } 570 aonsysctrl_cpuswra_set(uint32_t reset_addr)571__STATIC_INLINE void aonsysctrl_cpuswra_set(uint32_t reset_addr) 572 { 573 CS_AONSYSCTRL->CPUSWRA = reset_addr; 574 } 575 576 /** 577 * Address Offset: 0x040 578 * Register Name : ASC DSP_RESET_ADDR 579 */ 580 aonsysctrl_dspra_get(void)581__STATIC_INLINE uint32_t aonsysctrl_dspra_get(void) 582 { 583 return CS_AONSYSCTRL->DSPRA; 584 } 585 aonsysctrl_dspra_set(uint32_t reset_addr)586__STATIC_INLINE void aonsysctrl_dspra_set(uint32_t reset_addr) 587 { 588 CS_AONSYSCTRL->DSPRA = reset_addr; 589 } 590 591 /** 592 * Address Offset: 0x044 593 * Register Name : ASC AON_SRAM1_CONFIG 594 */ 595 aonsysctrl_aonsramcfg1_get(void)596__STATIC_INLINE uint32_t aonsysctrl_aonsramcfg1_get(void) 597 { 598 return CS_AONSYSCTRL->AONSRAMCFG1; 599 } 600 aonsysctrl_aonsramcfg1_set(uint32_t config)601__STATIC_INLINE void aonsysctrl_aonsramcfg1_set(uint32_t config) 602 { 603 CS_AONSYSCTRL->AONSRAMCFG1 = config; 604 } 605 606 /** 607 * Address Offset: 0x048 608 * Register Name : ASC AON_SRAM2_CONFIG 609 */ 610 aonsysctrl_aonsramcfg2_get(void)611__STATIC_INLINE uint32_t aonsysctrl_aonsramcfg2_get(void) 612 { 613 return CS_AONSYSCTRL->AONSRAMCFG2; 614 } 615 aonsysctrl_aonsramcfg2_set(uint32_t config)616__STATIC_INLINE void aonsysctrl_aonsramcfg2_set(uint32_t config) 617 { 618 CS_AONSYSCTRL->AONSRAMCFG2 = config; 619 } 620 621 /** 622 * Address Offset: 0x04C 623 * Register Name : ASC SRAM_SD_CONFIG 624 */ 625 626 #define ASC_SRAMSDCFG_SRAM0_POS (0) 627 #define ASC_SRAMSDCFG_SRAM0_BIT (0x01UL << ASC_SRAMSDCFG_SRAM0_POS) 628 #define ASC_SRAMSDCFG_SRAM1_POS (1) 629 #define ASC_SRAMSDCFG_SRAM1_BIT (0x01UL << ASC_SRAMSDCFG_SRAM1_POS) 630 #define ASC_SRAMSDCFG_SRAM2_POS (2) 631 #define ASC_SRAMSDCFG_SRAM2_BIT (0x01UL << ASC_SRAMSDCFG_SRAM2_POS) 632 #define ASC_SRAMSDCFG_SRAM3_POS (3) 633 #define ASC_SRAMSDCFG_SRAM3_BIT (0x01UL << ASC_SRAMSDCFG_SRAM3_POS) 634 #define ASC_SRAMSDCFG_SRAM4_POS (4) 635 #define ASC_SRAMSDCFG_SRAM4_BIT (0x01UL << ASC_SRAMSDCFG_SRAM4_POS) 636 #define ASC_SRAMSDCFG_SRAM5_POS (5) 637 #define ASC_SRAMSDCFG_SRAM5_BIT (0x01UL << ASC_SRAMSDCFG_SRAM5_POS) 638 #define ASC_SRAMSDCFG_SRAM6_POS (6) 639 #define ASC_SRAMSDCFG_SRAM6_BIT (0x01UL << ASC_SRAMSDCFG_SRAM6_POS) 640 #define ASC_SRAMSDCFG_ROM0_POS (7) 641 #define ASC_SRAMSDCFG_ROM0_BIT (0x01UL << ASC_SRAMSDCFG_ROM0_POS) 642 #define ASC_SRAMSDCFG_ROM1_POS (8) 643 #define ASC_SRAMSDCFG_ROM1_BIT (0x01UL << ASC_SRAMSDCFG_ROM1_POS) 644 #define ASC_SRAMSDCFG_ROM2_POS (9) 645 #define ASC_SRAMSDCFG_ROM2_BIT (0x01UL << ASC_SRAMSDCFG_ROM2_POS) 646 #define ASC_SRAMSDCFG_BTROM0_POS (10) 647 #define ASC_SRAMSDCFG_BTROM0_BIT (0x01UL << ASC_SRAMSDCFG_BTROM0_POS) 648 #define ASC_SRAMSDCFG_BTROM1_POS (11) 649 #define ASC_SRAMSDCFG_BTROM1_BIT (0x01UL << ASC_SRAMSDCFG_BTROM1_POS) 650 #define ASC_SRAMSDCFG_BTROM2_POS (12) 651 #define ASC_SRAMSDCFG_BTROM2_BIT (0x01UL << ASC_SRAMSDCFG_BTROM2_POS) 652 aonsysctrl_sramsdcfg_get(void)653__STATIC_INLINE uint32_t aonsysctrl_sramsdcfg_get(void) 654 { 655 return CS_AONSYSCTRL->SRAMSDCFG; 656 } 657 aonsysctrl_sramsdcfg_set(uint32_t config)658__STATIC_INLINE void aonsysctrl_sramsdcfg_set(uint32_t config) 659 { 660 CS_AONSYSCTRL->SRAMSDCFG = config; 661 } 662 aonsysctrl_sramsdcfg_sram0_getb(void)663__STATIC_INLINE uint8_t aonsysctrl_sramsdcfg_sram0_getb(void) 664 { 665 return (CS_AONSYSCTRL->SRAMSDCFG & ASC_SRAMSDCFG_SRAM0_BIT) >> ASC_SRAMSDCFG_SRAM0_POS; 666 } 667 aonsysctrl_sramsdcfg_sram0_setb(void)668__STATIC_INLINE void aonsysctrl_sramsdcfg_sram0_setb(void) 669 { 670 CS_AONSYSCTRL->SRAMSDCFG |= ASC_SRAMSDCFG_SRAM0_BIT; 671 } 672 aonsysctrl_sramsdcfg_sram0_clrb(void)673__STATIC_INLINE void aonsysctrl_sramsdcfg_sram0_clrb(void) 674 { 675 CS_AONSYSCTRL->SRAMSDCFG &= ~ASC_SRAMSDCFG_SRAM0_BIT; 676 } 677 aonsysctrl_sramsdcfg_sram1_getb(void)678__STATIC_INLINE uint8_t aonsysctrl_sramsdcfg_sram1_getb(void) 679 { 680 return (CS_AONSYSCTRL->SRAMSDCFG & ASC_SRAMSDCFG_SRAM1_BIT) >> ASC_SRAMSDCFG_SRAM1_POS; 681 } 682 aonsysctrl_sramsdcfg_sram1_setb(void)683__STATIC_INLINE void aonsysctrl_sramsdcfg_sram1_setb(void) 684 { 685 CS_AONSYSCTRL->SRAMSDCFG |= ASC_SRAMSDCFG_SRAM1_BIT; 686 } 687 aonsysctrl_sramsdcfg_sram1_clrb(void)688__STATIC_INLINE void aonsysctrl_sramsdcfg_sram1_clrb(void) 689 { 690 CS_AONSYSCTRL->SRAMSDCFG &= ~ASC_SRAMSDCFG_SRAM1_BIT; 691 } 692 aonsysctrl_sramsdcfg_sram2_getb(void)693__STATIC_INLINE uint8_t aonsysctrl_sramsdcfg_sram2_getb(void) 694 { 695 return (CS_AONSYSCTRL->SRAMSDCFG & ASC_SRAMSDCFG_SRAM2_BIT) >> ASC_SRAMSDCFG_SRAM2_POS; 696 } 697 aonsysctrl_sramsdcfg_sram2_setb(void)698__STATIC_INLINE void aonsysctrl_sramsdcfg_sram2_setb(void) 699 { 700 CS_AONSYSCTRL->SRAMSDCFG |= ASC_SRAMSDCFG_SRAM2_BIT; 701 } 702 aonsysctrl_sramsdcfg_sram2_clrb(void)703__STATIC_INLINE void aonsysctrl_sramsdcfg_sram2_clrb(void) 704 { 705 CS_AONSYSCTRL->SRAMSDCFG &= ~ASC_SRAMSDCFG_SRAM2_BIT; 706 } 707 aonsysctrl_sramsdcfg_sram3_getb(void)708__STATIC_INLINE uint8_t aonsysctrl_sramsdcfg_sram3_getb(void) 709 { 710 return (CS_AONSYSCTRL->SRAMSDCFG & ASC_SRAMSDCFG_SRAM3_BIT) >> ASC_SRAMSDCFG_SRAM3_POS; 711 } 712 aonsysctrl_sramsdcfg_sram3_setb(void)713__STATIC_INLINE void aonsysctrl_sramsdcfg_sram3_setb(void) 714 { 715 CS_AONSYSCTRL->SRAMSDCFG |= ASC_SRAMSDCFG_SRAM3_BIT; 716 } 717 aonsysctrl_sramsdcfg_SRAM3_clrb(void)718__STATIC_INLINE void aonsysctrl_sramsdcfg_SRAM3_clrb(void) 719 { 720 CS_AONSYSCTRL->SRAMSDCFG &= ~ASC_SRAMSDCFG_SRAM3_BIT; 721 } 722 aonsysctrl_sramsdcfg_sram4_getb(void)723__STATIC_INLINE uint8_t aonsysctrl_sramsdcfg_sram4_getb(void) 724 { 725 return (CS_AONSYSCTRL->SRAMSDCFG & ASC_SRAMSDCFG_SRAM4_BIT) >> ASC_SRAMSDCFG_SRAM4_POS; 726 } 727 aonsysctrl_sramsdcfg_sram4_setb(void)728__STATIC_INLINE void aonsysctrl_sramsdcfg_sram4_setb(void) 729 { 730 CS_AONSYSCTRL->SRAMSDCFG |= ASC_SRAMSDCFG_SRAM4_BIT; 731 } 732 aonsysctrl_sramsdcfg_sram4_clrb(void)733__STATIC_INLINE void aonsysctrl_sramsdcfg_sram4_clrb(void) 734 { 735 CS_AONSYSCTRL->SRAMSDCFG &= ~ASC_SRAMSDCFG_SRAM4_BIT; 736 } 737 aonsysctrl_sramsdcfg_sram5_getb(void)738__STATIC_INLINE uint8_t aonsysctrl_sramsdcfg_sram5_getb(void) 739 { 740 return (CS_AONSYSCTRL->SRAMSDCFG & ASC_SRAMSDCFG_SRAM5_BIT) >> ASC_SRAMSDCFG_SRAM5_POS; 741 } 742 aonsysctrl_sramsdcfg_sram5_setb(void)743__STATIC_INLINE void aonsysctrl_sramsdcfg_sram5_setb(void) 744 { 745 CS_AONSYSCTRL->SRAMSDCFG |= ASC_SRAMSDCFG_SRAM5_BIT; 746 } 747 aonsysctrl_sramsdcfg_sram5_clrb(void)748__STATIC_INLINE void aonsysctrl_sramsdcfg_sram5_clrb(void) 749 { 750 CS_AONSYSCTRL->SRAMSDCFG &= ~ASC_SRAMSDCFG_SRAM5_BIT; 751 } 752 aonsysctrl_sramsdcfg_sram6_getb(void)753__STATIC_INLINE uint8_t aonsysctrl_sramsdcfg_sram6_getb(void) 754 { 755 return (CS_AONSYSCTRL->SRAMSDCFG & ASC_SRAMSDCFG_SRAM6_BIT) >> ASC_SRAMSDCFG_SRAM6_POS; 756 } 757 aonsysctrl_sramsdcfg_sram6_setb(void)758__STATIC_INLINE void aonsysctrl_sramsdcfg_sram6_setb(void) 759 { 760 CS_AONSYSCTRL->SRAMSDCFG |= ASC_SRAMSDCFG_SRAM6_BIT; 761 } 762 aonsysctrl_sramsdcfg_sram6_clrb(void)763__STATIC_INLINE void aonsysctrl_sramsdcfg_sram6_clrb(void) 764 { 765 CS_AONSYSCTRL->SRAMSDCFG &= ~ASC_SRAMSDCFG_SRAM6_BIT; 766 } 767 aonsysctrl_sramsdcfg_rom0_getb(void)768__STATIC_INLINE uint8_t aonsysctrl_sramsdcfg_rom0_getb(void) 769 { 770 return (CS_AONSYSCTRL->SRAMSDCFG & ASC_SRAMSDCFG_ROM0_BIT) >> ASC_SRAMSDCFG_ROM0_POS; 771 } 772 aonsysctrl_sramsdcfg_rom0_setb(void)773__STATIC_INLINE void aonsysctrl_sramsdcfg_rom0_setb(void) 774 { 775 CS_AONSYSCTRL->SRAMSDCFG |= ASC_SRAMSDCFG_ROM0_BIT; 776 } 777 aonsysctrl_sramsdcfg_rom0_clrb(void)778__STATIC_INLINE void aonsysctrl_sramsdcfg_rom0_clrb(void) 779 { 780 CS_AONSYSCTRL->SRAMSDCFG &= ~ASC_SRAMSDCFG_ROM0_BIT; 781 } 782 aonsysctrl_sramsdcfg_rom1_getb(void)783__STATIC_INLINE uint8_t aonsysctrl_sramsdcfg_rom1_getb(void) 784 { 785 return (CS_AONSYSCTRL->SRAMSDCFG & ASC_SRAMSDCFG_ROM1_BIT) >> ASC_SRAMSDCFG_ROM1_POS; 786 } 787 aonsysctrl_sramsdcfg_rom1_setb(void)788__STATIC_INLINE void aonsysctrl_sramsdcfg_rom1_setb(void) 789 { 790 CS_AONSYSCTRL->SRAMSDCFG |= ASC_SRAMSDCFG_ROM1_BIT; 791 } 792 aonsysctrl_sramsdcfg_rom1_clrb(void)793__STATIC_INLINE void aonsysctrl_sramsdcfg_rom1_clrb(void) 794 { 795 CS_AONSYSCTRL->SRAMSDCFG &= ~ASC_SRAMSDCFG_ROM1_BIT; 796 } 797 aonsysctrl_sramsdcfg_rom2_getb(void)798__STATIC_INLINE uint8_t aonsysctrl_sramsdcfg_rom2_getb(void) 799 { 800 return (CS_AONSYSCTRL->SRAMSDCFG & ASC_SRAMSDCFG_ROM2_BIT) >> ASC_SRAMSDCFG_ROM2_POS; 801 } 802 aonsysctrl_sramsdcfg_rom2_setb(void)803__STATIC_INLINE void aonsysctrl_sramsdcfg_rom2_setb(void) 804 { 805 CS_AONSYSCTRL->SRAMSDCFG |= ASC_SRAMSDCFG_ROM2_BIT; 806 } 807 aonsysctrl_sramsdcfg_rom2_clrb(void)808__STATIC_INLINE void aonsysctrl_sramsdcfg_rom2_clrb(void) 809 { 810 CS_AONSYSCTRL->SRAMSDCFG &= ~ASC_SRAMSDCFG_ROM2_BIT; 811 } 812 aonsysctrl_sramsdcfg_btrom0_getb(void)813__STATIC_INLINE uint8_t aonsysctrl_sramsdcfg_btrom0_getb(void) 814 { 815 return (CS_AONSYSCTRL->SRAMSDCFG & ASC_SRAMSDCFG_BTROM0_BIT) >> ASC_SRAMSDCFG_BTROM0_POS; 816 } 817 aonsysctrl_sramsdcfg_btrom0_setb(void)818__STATIC_INLINE void aonsysctrl_sramsdcfg_btrom0_setb(void) 819 { 820 CS_AONSYSCTRL->SRAMSDCFG |= ASC_SRAMSDCFG_BTROM0_BIT; 821 } 822 aonsysctrl_sramsdcfg_btrom0_clrb(void)823__STATIC_INLINE void aonsysctrl_sramsdcfg_btrom0_clrb(void) 824 { 825 CS_AONSYSCTRL->SRAMSDCFG &= ~ASC_SRAMSDCFG_BTROM0_BIT; 826 } 827 aonsysctrl_sramsdcfg_btrom1_getb(void)828__STATIC_INLINE uint8_t aonsysctrl_sramsdcfg_btrom1_getb(void) 829 { 830 return (CS_AONSYSCTRL->SRAMSDCFG & ASC_SRAMSDCFG_BTROM1_BIT) >> ASC_SRAMSDCFG_BTROM1_POS; 831 } 832 aonsysctrl_sramsdcfg_btrom1_setb(void)833__STATIC_INLINE void aonsysctrl_sramsdcfg_btrom1_setb(void) 834 { 835 CS_AONSYSCTRL->SRAMSDCFG |= ASC_SRAMSDCFG_BTROM1_BIT; 836 } 837 aonsysctrl_sramsdcfg_btrom1_clrb(void)838__STATIC_INLINE void aonsysctrl_sramsdcfg_btrom1_clrb(void) 839 { 840 CS_AONSYSCTRL->SRAMSDCFG &= ~ASC_SRAMSDCFG_BTROM1_BIT; 841 } 842 aonsysctrl_sramsdcfg_btrom2_getb(void)843__STATIC_INLINE uint8_t aonsysctrl_sramsdcfg_btrom2_getb(void) 844 { 845 return (CS_AONSYSCTRL->SRAMSDCFG & ASC_SRAMSDCFG_BTROM2_BIT) >> ASC_SRAMSDCFG_BTROM2_POS; 846 } 847 aonsysctrl_sramsdcfg_btrom2_setb(void)848__STATIC_INLINE void aonsysctrl_sramsdcfg_btrom2_setb(void) 849 { 850 CS_AONSYSCTRL->SRAMSDCFG |= ASC_SRAMSDCFG_BTROM2_BIT; 851 } 852 aonsysctrl_sramsdcfg_btrom2_clrb(void)853__STATIC_INLINE void aonsysctrl_sramsdcfg_btrom2_clrb(void) 854 { 855 CS_AONSYSCTRL->SRAMSDCFG &= ~ASC_SRAMSDCFG_BTROM2_BIT; 856 } 857 858 /** 859 * Address Offset: 0x050 860 * Register Name : ASC AON_CLK_DIV 861 */ 862 863 #define ASC_AONCLKDIV_DENOM_LSB (0) 864 #define ASC_AONCLKDIV_DENOM_WIDTH (4) 865 #define ASC_AONCLKDIV_DENOM_MASK (((0x01UL << ASC_AONCLKDIV_DENOM_WIDTH) - 1) << ASC_AONCLKDIV_DENOM_LSB) 866 #define ASC_AONCLKDIV_UPDATE_POS (4) 867 #define ASC_AONCLKDIV_UPDATE_BIT (0x01UL << ASC_AONCLKDIV_UPDATE_POS) 868 aonsysctrl_aonclkdiv_denom_getf(void)869__STATIC_INLINE uint8_t aonsysctrl_aonclkdiv_denom_getf(void) 870 { 871 return ((CS_AONSYSCTRL->AONCLKDIV & ASC_AONCLKDIV_DENOM_MASK) >> ASC_AONCLKDIV_DENOM_LSB); 872 } 873 aonsysctrl_aonclkdiv_denom_setf(uint8_t div_denom)874__STATIC_INLINE void aonsysctrl_aonclkdiv_denom_setf(uint8_t div_denom) 875 { 876 uint32_t local_val = CS_AONSYSCTRL->AONCLKDIV & ~ASC_AONCLKDIV_DENOM_MASK; 877 CS_AONSYSCTRL->AONCLKDIV = local_val | ((div_denom << ASC_AONCLKDIV_DENOM_LSB) & ASC_AONCLKDIV_DENOM_MASK) | ASC_AONCLKDIV_UPDATE_BIT; 878 } 879 880 /** 881 * Address Offset: 0x054 882 * Register Name : ASC AON_RAM_MUX 883 */ 884 885 #define ASC_AONRAMMUX_HI32K_POS (0) 886 #define ASC_AONRAMMUX_HI32K_BIT (0x01UL << ASC_AONRAMMUX_HI32K_POS) 887 #define ASC_AONRAMMUX_LO32K_POS (1) 888 #define ASC_AONRAMMUX_LO32K_BIT (0x01UL << ASC_AONRAMMUX_LO32K_POS) 889 aonsysctrl_aonrammux_hi32k_getb(void)890__STATIC_INLINE uint8_t aonsysctrl_aonrammux_hi32k_getb(void) 891 { 892 return (CS_AONSYSCTRL->AONRAMMUX & ASC_AONRAMMUX_HI32K_BIT) >> ASC_AONRAMMUX_HI32K_POS; 893 } 894 aonsysctrl_aonrammux_hi32k_setb(void)895__STATIC_INLINE void aonsysctrl_aonrammux_hi32k_setb(void) 896 { 897 CS_AONSYSCTRL->AONRAMMUX |= ASC_AONRAMMUX_HI32K_BIT; 898 } 899 aonsysctrl_aonrammux_hi32k_clrb(void)900__STATIC_INLINE void aonsysctrl_aonrammux_hi32k_clrb(void) 901 { 902 CS_AONSYSCTRL->AONRAMMUX &= ~ASC_AONRAMMUX_HI32K_BIT; 903 } 904 aonsysctrl_aonrammux_lo32k_getb(void)905__STATIC_INLINE uint8_t aonsysctrl_aonrammux_lo32k_getb(void) 906 { 907 return (CS_AONSYSCTRL->AONRAMMUX & ASC_AONRAMMUX_LO32K_BIT) >> ASC_AONRAMMUX_LO32K_POS; 908 } 909 aonsysctrl_aonrammux_lo32k_setb(void)910__STATIC_INLINE void aonsysctrl_aonrammux_lo32k_setb(void) 911 { 912 CS_AONSYSCTRL->AONRAMMUX |= ASC_AONRAMMUX_LO32K_BIT; 913 } 914 aonsysctrl_aonrammux_lo32k_clrb(void)915__STATIC_INLINE void aonsysctrl_aonrammux_lo32k_clrb(void) 916 { 917 CS_AONSYSCTRL->AONRAMMUX &= ~ASC_AONRAMMUX_LO32K_BIT; 918 } 919 920 /** 921 * Address Offset: 0x058 922 * Register Name : ASC CPU_SB_RESET_ADDR 923 */ 924 aonsysctrl_cpusbra_get(void)925__STATIC_INLINE uint32_t aonsysctrl_cpusbra_get(void) 926 { 927 return CS_AONSYSCTRL->CPUSBRA; 928 } 929 aonsysctrl_cpusbra_set(uint32_t reset_addr)930__STATIC_INLINE void aonsysctrl_cpusbra_set(uint32_t reset_addr) 931 { 932 CS_AONSYSCTRL->CPUSBRA = reset_addr; 933 } 934 935 /** 936 * Address Offset: 0x05C 937 * Register Name : ASC CPU_AON_RESET_ADDR 938 */ 939 aonsysctrl_cpuaonra_get(void)940__STATIC_INLINE uint32_t aonsysctrl_cpuaonra_get(void) 941 { 942 return CS_AONSYSCTRL->CPUAONRA; 943 } 944 aonsysctrl_cpuaonra_set(uint32_t reset_addr)945__STATIC_INLINE void aonsysctrl_cpuaonra_set(uint32_t reset_addr) 946 { 947 CS_AONSYSCTRL->CPUAONRA = reset_addr; 948 } 949 950 /** 951 * Address Offset: 0x074 952 * Register Name : ASC OSCEN 953 */ 954 955 #define ASC_OSCEN_BT_OSC_EN_POS (0) 956 #define ASC_OSCEN_BT_OSC_EN_BIT (0x01UL << ASC_OSCEN_BT_OSC_EN_POS) 957 #define ASC_OSCEN_WIFI_OSC_EN_POS (1) 958 #define ASC_OSCEN_WIFI_OSC_EN_BIT (0x01UL << ASC_OSCEN_WIFI_OSC_EN_POS) 959 #define ASC_OSCEN_BT_OSC_MANUAL_POS (2) 960 #define ASC_OSCEN_BT_OSC_MANUAL_BIT (0x01UL << ASC_OSCEN_BT_OSC_MANUAL_POS) 961 #define ASC_OSCEN_WIFI_OSC_MANUAL_POS (3) 962 #define ASC_OSCEN_WIFI_OSC_MANUAL_BIT (0x01UL << ASC_OSCEN_WIFI_OSC_MANUAL_POS) 963 #define ASC_OSCEN_WIFI_OSC_COMB_EN_POS (4) 964 #define ASC_OSCEN_WIFI_OSC_COMB_EN_BIT (0x01UL << ASC_OSCEN_WIFI_OSC_COMB_EN_POS) 965 aonsysctrl_oscen_bt_osc_en_getb(void)966__STATIC_INLINE uint8_t aonsysctrl_oscen_bt_osc_en_getb(void) 967 { 968 return (CS_AONSYSCTRL->OSCEN & ASC_OSCEN_BT_OSC_EN_BIT) >> ASC_OSCEN_BT_OSC_EN_POS; 969 } 970 aonsysctrl_oscen_bt_osc_en_setb(void)971__STATIC_INLINE void aonsysctrl_oscen_bt_osc_en_setb(void) 972 { 973 CS_AONSYSCTRL->OSCEN |= ASC_OSCEN_BT_OSC_EN_BIT; 974 } 975 aonsysctrl_oscen_bt_osc_en_clrb(void)976__STATIC_INLINE void aonsysctrl_oscen_bt_osc_en_clrb(void) 977 { 978 CS_AONSYSCTRL->OSCEN &= ~ASC_OSCEN_BT_OSC_EN_BIT; 979 } 980 aonsysctrl_oscen_wifi_osc_en_getb(void)981__STATIC_INLINE uint8_t aonsysctrl_oscen_wifi_osc_en_getb(void) 982 { 983 return (CS_AONSYSCTRL->OSCEN & ASC_OSCEN_WIFI_OSC_EN_BIT) >> ASC_OSCEN_WIFI_OSC_EN_POS; 984 } 985 aonsysctrl_oscen_wifi_osc_en_setb(void)986__STATIC_INLINE void aonsysctrl_oscen_wifi_osc_en_setb(void) 987 { 988 CS_AONSYSCTRL->OSCEN |= ASC_OSCEN_WIFI_OSC_EN_BIT; 989 } 990 aonsysctrl_oscen_wifi_osc_en_clrb(void)991__STATIC_INLINE void aonsysctrl_oscen_wifi_osc_en_clrb(void) 992 { 993 CS_AONSYSCTRL->OSCEN &= ~ASC_OSCEN_WIFI_OSC_EN_BIT; 994 } 995 aonsysctrl_oscen_bt_osc_manual_getb(void)996__STATIC_INLINE uint8_t aonsysctrl_oscen_bt_osc_manual_getb(void) 997 { 998 return (CS_AONSYSCTRL->OSCEN & ASC_OSCEN_BT_OSC_MANUAL_BIT) >> ASC_OSCEN_BT_OSC_MANUAL_POS; 999 } 1000 aonsysctrl_oscen_bt_osc_manual_setb(void)1001__STATIC_INLINE void aonsysctrl_oscen_bt_osc_manual_setb(void) 1002 { 1003 CS_AONSYSCTRL->OSCEN |= ASC_OSCEN_BT_OSC_MANUAL_BIT; 1004 } 1005 aonsysctrl_oscen_bt_osc_manual_clrb(void)1006__STATIC_INLINE void aonsysctrl_oscen_bt_osc_manual_clrb(void) 1007 { 1008 CS_AONSYSCTRL->OSCEN &= ~ASC_OSCEN_BT_OSC_MANUAL_BIT; 1009 } 1010 aonsysctrl_oscen_wifi_osc_manual_getb(void)1011__STATIC_INLINE uint8_t aonsysctrl_oscen_wifi_osc_manual_getb(void) 1012 { 1013 return (CS_AONSYSCTRL->OSCEN & ASC_OSCEN_WIFI_OSC_MANUAL_BIT) >> ASC_OSCEN_WIFI_OSC_MANUAL_POS; 1014 } 1015 aonsysctrl_oscen_wifi_osc_manual_setb(void)1016__STATIC_INLINE void aonsysctrl_oscen_wifi_osc_manual_setb(void) 1017 { 1018 CS_AONSYSCTRL->OSCEN |= ASC_OSCEN_WIFI_OSC_MANUAL_BIT; 1019 } 1020 aonsysctrl_oscen_wifi_osc_manual_clrb(void)1021__STATIC_INLINE void aonsysctrl_oscen_wifi_osc_manual_clrb(void) 1022 { 1023 CS_AONSYSCTRL->OSCEN &= ~ASC_OSCEN_WIFI_OSC_MANUAL_BIT; 1024 } 1025 aonsysctrl_oscen_wifi_osc_comb_en_getb(void)1026__STATIC_INLINE uint8_t aonsysctrl_oscen_wifi_osc_comb_en_getb(void) 1027 { 1028 return (CS_AONSYSCTRL->OSCEN & ASC_OSCEN_WIFI_OSC_COMB_EN_BIT) >> ASC_OSCEN_WIFI_OSC_COMB_EN_POS; 1029 } 1030 aonsysctrl_oscen_wifi_osc_comb_en_setb(void)1031__STATIC_INLINE void aonsysctrl_oscen_wifi_osc_comb_en_setb(void) 1032 { 1033 CS_AONSYSCTRL->OSCEN |= ASC_OSCEN_WIFI_OSC_COMB_EN_BIT; 1034 } 1035 aonsysctrl_oscen_wifi_osc_comb_en_clrb(void)1036__STATIC_INLINE void aonsysctrl_oscen_wifi_osc_comb_en_clrb(void) 1037 { 1038 CS_AONSYSCTRL->OSCEN &= ~ASC_OSCEN_WIFI_OSC_COMB_EN_BIT; 1039 } 1040 1041 /** 1042 * Address Offset: 0x100 1043 * Register Name : ASC HCLK_MANUAL_ENABLE (write 1 valid) 1044 */ 1045 1046 #define ASC_HCLKME_CPUSYS_EN_POS (0) 1047 #define ASC_HCLKME_CPUSYS_EN_BIT (0x01UL << ASC_HCLKME_CPUSYS_EN_POS) 1048 #define ASC_HCLKME_BTSYS_EN_POS (1) 1049 #define ASC_HCLKME_BTSYS_EN_BIT (0x01UL << ASC_HCLKME_BTSYS_EN_POS) 1050 #define ASC_HCLKME_BTFREE_EN_POS (2) 1051 #define ASC_HCLKME_BTFREE_EN_BIT (0x01UL << ASC_HCLKME_BTFREE_EN_POS) 1052 #define ASC_HCLKME_WIFISYS_EN_POS (3) 1053 #define ASC_HCLKME_WIFISYS_EN_BIT (0x01UL << ASC_HCLKME_WIFISYS_EN_POS) 1054 #define ASC_HCLKME_AONSRAM0_EN_POS (4) 1055 #define ASC_HCLKME_AONSRAM0_EN_BIT (0x01UL << ASC_HCLKME_AONSRAM0_EN_POS) 1056 #define ASC_HCLKME_AONSRAM1_EN_POS (5) 1057 #define ASC_HCLKME_AONSRAM1_EN_BIT (0x01UL << ASC_HCLKME_AONSRAM1_EN_POS) 1058 #define ASC_HCLKME_AONSRAM2_EN_POS (6) 1059 #define ASC_HCLKME_AONSRAM2_EN_BIT (0x01UL << ASC_HCLKME_AONSRAM2_EN_POS) 1060 #define ASC_HCLKME_AONSRAMCPUSYS_EN_POS (7) 1061 #define ASC_HCLKME_AONSRAMCPUSYS_EN_BIT (0x01UL << ASC_HCLKME_AONSRAMCPUSYS_EN_POS) 1062 #define ASC_HCLKME_AONMERGE_EN_POS (8) 1063 #define ASC_HCLKME_AONMERGE_EN_BIT (0x01UL << ASC_HCLKME_AONMERGE_EN_POS) 1064 aonsysctrl_hclkme_get(void)1065__STATIC_INLINE uint32_t aonsysctrl_hclkme_get(void) 1066 { 1067 return CS_AONSYSCTRL->HCLKME; 1068 } 1069 aonsysctrl_hclkme_set(uint32_t enable_bits)1070__STATIC_INLINE void aonsysctrl_hclkme_set(uint32_t enable_bits) 1071 { 1072 CS_AONSYSCTRL->HCLKME = enable_bits; 1073 } 1074 aonsysctrl_hclkme_cpusys_en_getb(void)1075__STATIC_INLINE uint8_t aonsysctrl_hclkme_cpusys_en_getb(void) 1076 { 1077 return (CS_AONSYSCTRL->HCLKME & ASC_HCLKME_CPUSYS_EN_BIT) >> ASC_HCLKME_CPUSYS_EN_POS; 1078 } 1079 aonsysctrl_hclkme_cpusys_en_setb(void)1080__STATIC_INLINE void aonsysctrl_hclkme_cpusys_en_setb(void) 1081 { 1082 CS_AONSYSCTRL->HCLKME = ASC_HCLKME_CPUSYS_EN_BIT; 1083 } 1084 aonsysctrl_hclkme_btsys_en_getb(void)1085__STATIC_INLINE uint8_t aonsysctrl_hclkme_btsys_en_getb(void) 1086 { 1087 return (CS_AONSYSCTRL->HCLKME & ASC_HCLKME_BTSYS_EN_BIT) >> ASC_HCLKME_BTSYS_EN_POS; 1088 } 1089 aonsysctrl_hclkme_btsys_en_setb(void)1090__STATIC_INLINE void aonsysctrl_hclkme_btsys_en_setb(void) 1091 { 1092 CS_AONSYSCTRL->HCLKME = ASC_HCLKME_BTSYS_EN_BIT; 1093 } 1094 aonsysctrl_hclkme_btfree_en_getb(void)1095__STATIC_INLINE uint8_t aonsysctrl_hclkme_btfree_en_getb(void) 1096 { 1097 return (CS_AONSYSCTRL->HCLKME & ASC_HCLKME_BTFREE_EN_BIT) >> ASC_HCLKME_BTFREE_EN_POS; 1098 } 1099 aonsysctrl_hclkme_btfree_en_setb(void)1100__STATIC_INLINE void aonsysctrl_hclkme_btfree_en_setb(void) 1101 { 1102 CS_AONSYSCTRL->HCLKME = ASC_HCLKME_BTFREE_EN_BIT; 1103 } 1104 aonsysctrl_hclkme_wifisys_en_getb(void)1105__STATIC_INLINE uint8_t aonsysctrl_hclkme_wifisys_en_getb(void) 1106 { 1107 return (CS_AONSYSCTRL->HCLKME & ASC_HCLKME_WIFISYS_EN_BIT) >> ASC_HCLKME_WIFISYS_EN_POS; 1108 } 1109 aonsysctrl_hclkme_wifisys_en_setb(void)1110__STATIC_INLINE void aonsysctrl_hclkme_wifisys_en_setb(void) 1111 { 1112 CS_AONSYSCTRL->HCLKME = ASC_HCLKME_WIFISYS_EN_BIT; 1113 } 1114 1115 /** 1116 * Address Offset: 0x104 1117 * Register Name : ASC HCLK_MANUAL_DISABLE (write 1 valid) 1118 */ 1119 1120 #define ASC_HCLKMD_CPUSYS_DIS_POS (0) 1121 #define ASC_HCLKMD_CPUSYS_DIS_BIT (0x01UL << ASC_HCLKMD_CPUSYS_DIS_POS) 1122 #define ASC_HCLKMD_BTSYS_DIS_POS (1) 1123 #define ASC_HCLKMD_BTSYS_DIS_BIT (0x01UL << ASC_HCLKMD_BTSYS_DIS_POS) 1124 #define ASC_HCLKMD_BTFREE_DIS_POS (2) 1125 #define ASC_HCLKMD_BTFREE_DIS_BIT (0x01UL << ASC_HCLKMD_BTFREE_DIS_POS) 1126 #define ASC_HCLKMD_WIFISYS_DIS_POS (3) 1127 #define ASC_HCLKMD_WIFISYS_DIS_BIT (0x01UL << ASC_HCLKMD_WIFISYS_DIS_POS) 1128 #define ASC_HCLKMD_AONSRAM0_DIS_POS (4) 1129 #define ASC_HCLKMD_AONSRAM0_DIS_BIT (0x01UL << ASC_HCLKMD_AONSRAM0_DIS_POS) 1130 #define ASC_HCLKMD_AONSRAM1_DIS_POS (5) 1131 #define ASC_HCLKMD_AONSRAM1_DIS_BIT (0x01UL << ASC_HCLKMD_AONSRAM1_DIS_POS) 1132 #define ASC_HCLKMD_AONSRAM2_DIS_POS (6) 1133 #define ASC_HCLKMD_AONSRAM2_DIS_BIT (0x01UL << ASC_HCLKMD_AONSRAM2_DIS_POS) 1134 #define ASC_HCLKMD_AONSRAMCPUSYS_DIS_POS (7) 1135 #define ASC_HCLKMD_AONSRAMCPUSYS_DIS_BIT (0x01UL << ASC_HCLKMD_AONSRAMCPUSYS_DIS_POS) 1136 #define ASC_HCLKMD_AONMERGE_DIS_POS (8) 1137 #define ASC_HCLKMD_AONMERGE_DIS_BIT (0x01UL << ASC_HCLKMD_AONMERGE_DIS_POS) 1138 aonsysctrl_hclkmd_get(void)1139__STATIC_INLINE uint32_t aonsysctrl_hclkmd_get(void) 1140 { 1141 return CS_AONSYSCTRL->HCLKMD; 1142 } 1143 aonsysctrl_hclkmd_set(uint32_t disable_bits)1144__STATIC_INLINE void aonsysctrl_hclkmd_set(uint32_t disable_bits) 1145 { 1146 CS_AONSYSCTRL->HCLKMD = disable_bits; 1147 } 1148 aonsysctrl_hclkmd_cpusys_dis_getb(void)1149__STATIC_INLINE uint8_t aonsysctrl_hclkmd_cpusys_dis_getb(void) 1150 { 1151 return (CS_AONSYSCTRL->HCLKMD & ASC_HCLKMD_CPUSYS_DIS_BIT) >> ASC_HCLKMD_CPUSYS_DIS_POS; 1152 } 1153 aonsysctrl_hclkmd_cpusys_dis_setb(void)1154__STATIC_INLINE void aonsysctrl_hclkmd_cpusys_dis_setb(void) 1155 { 1156 CS_AONSYSCTRL->HCLKMD = ASC_HCLKMD_CPUSYS_DIS_BIT; 1157 } 1158 aonsysctrl_hclkmd_btsys_dis_getb(void)1159__STATIC_INLINE uint8_t aonsysctrl_hclkmd_btsys_dis_getb(void) 1160 { 1161 return (CS_AONSYSCTRL->HCLKMD & ASC_HCLKMD_BTSYS_DIS_BIT) >> ASC_HCLKMD_BTSYS_DIS_POS; 1162 } 1163 aonsysctrl_hclkmd_btsys_dis_setb(void)1164__STATIC_INLINE void aonsysctrl_hclkmd_btsys_dis_setb(void) 1165 { 1166 CS_AONSYSCTRL->HCLKMD = ASC_HCLKMD_BTSYS_DIS_BIT; 1167 } 1168 aonsysctrl_hclkmd_btfree_dis_getb(void)1169__STATIC_INLINE uint8_t aonsysctrl_hclkmd_btfree_dis_getb(void) 1170 { 1171 return (CS_AONSYSCTRL->HCLKMD & ASC_HCLKMD_BTFREE_DIS_BIT) >> ASC_HCLKMD_BTFREE_DIS_POS; 1172 } 1173 aonsysctrl_hclkmd_btfree_dis_setb(void)1174__STATIC_INLINE void aonsysctrl_hclkmd_btfree_dis_setb(void) 1175 { 1176 CS_AONSYSCTRL->HCLKMD = ASC_HCLKMD_BTFREE_DIS_BIT; 1177 } 1178 aonsysctrl_hclkmd_wifisys_dis_getb(void)1179__STATIC_INLINE uint8_t aonsysctrl_hclkmd_wifisys_dis_getb(void) 1180 { 1181 return (CS_AONSYSCTRL->HCLKMD & ASC_HCLKMD_WIFISYS_DIS_BIT) >> ASC_HCLKMD_WIFISYS_DIS_POS; 1182 } 1183 aonsysctrl_hclkmd_wifisys_dis_setb(void)1184__STATIC_INLINE void aonsysctrl_hclkmd_wifisys_dis_setb(void) 1185 { 1186 CS_AONSYSCTRL->HCLKMD = ASC_HCLKMD_WIFISYS_DIS_BIT; 1187 } 1188 1189 /** 1190 * Address Offset: 0x108 1191 * Register Name : ASC FCLK_MANUAL_ENABLE (write 1 valid) 1192 */ 1193 1194 #define ASC_FCLKME_CPUSYS_EN_POS (0) 1195 #define ASC_FCLKME_CPUSYS_EN_BIT (0x01UL << ASC_FCLKME_CPUSYS_EN_POS) 1196 aonsysctrl_fclkme_get(void)1197__STATIC_INLINE uint32_t aonsysctrl_fclkme_get(void) 1198 { 1199 return CS_AONSYSCTRL->FCLKME; 1200 } 1201 aonsysctrl_fclkme_set(uint32_t enable_bits)1202__STATIC_INLINE void aonsysctrl_fclkme_set(uint32_t enable_bits) 1203 { 1204 CS_AONSYSCTRL->FCLKME = enable_bits; 1205 } 1206 1207 /** 1208 * Address Offset: 0x10C 1209 * Register Name : ASC FCLK_MANUAL_DISABLE (write 1 valid) 1210 */ 1211 1212 #define ASC_FCLKMD_CPUSYS_DIS_POS (0) 1213 #define ASC_FCLKMD_CPUSYS_DIS_BIT (0x01UL << ASC_FCLKMD_CPUSYS_DIS_POS) 1214 aonsysctrl_fclkmd_get(void)1215__STATIC_INLINE uint32_t aonsysctrl_fclkmd_get(void) 1216 { 1217 return CS_AONSYSCTRL->FCLKMD; 1218 } 1219 aonsysctrl_fclkmd_set(uint32_t disable_bits)1220__STATIC_INLINE void aonsysctrl_fclkmd_set(uint32_t disable_bits) 1221 { 1222 CS_AONSYSCTRL->FCLKMD = disable_bits; 1223 } 1224 1225 /** 1226 * Address Offset: 0x110 1227 * Register Name : ASC OCLK_MANUAL_ENABLE (write 1 valid) 1228 */ 1229 1230 #define ASC_OCLKME_CLK26M_AONSYS_EN_POS (0) 1231 #define ASC_OCLKME_CLK26M_AONSYS_EN_BIT (0x01UL << ASC_OCLKME_CLK26M_AONSYS_EN_POS) 1232 #define ASC_OCLKME_CLK26M_CPUSYS_EN_POS (1) 1233 #define ASC_OCLKME_CLK26M_CPUSYS_EN_BIT (0x01UL << ASC_OCLKME_CLK26M_CPUSYS_EN_POS) 1234 #define ASC_OCLKME_CLK26M_TIMER20_EN_POS (2) 1235 #define ASC_OCLKME_CLK26M_TIMER20_EN_BIT (0x01UL << ASC_OCLKME_CLK26M_TIMER20_EN_POS) 1236 #define ASC_OCLKME_CLK32K_TIMER21_EN_POS (3) 1237 #define ASC_OCLKME_CLK32K_TIMER21_EN_BIT (0x01UL << ASC_OCLKME_CLK32K_TIMER21_EN_POS) 1238 #define ASC_OCLKME_CLK32K_TIMER22_EN_POS (4) 1239 #define ASC_OCLKME_CLK32K_TIMER22_EN_BIT (0x01UL << ASC_OCLKME_CLK32K_TIMER22_EN_POS) 1240 #define ASC_OCLKME_CLK32K_AONSYS_EN_POS (5) 1241 #define ASC_OCLKME_CLK32K_AONSYS_EN_BIT (0x01UL << ASC_OCLKME_CLK32K_AONSYS_EN_POS) 1242 #define ASC_OCLKME_CLK32K_CPUSYS_EN_POS (6) 1243 #define ASC_OCLKME_CLK32K_CPUSYS_EN_BIT (0x01UL << ASC_OCLKME_CLK32K_CPUSYS_EN_POS) 1244 #define ASC_OCLKME_CLK32K_WIFISYS_EN_POS (7) 1245 #define ASC_OCLKME_CLK32K_WIFISYS_EN_BIT (0x01UL << ASC_OCLKME_CLK32K_WIFISYS_EN_POS) 1246 #define ASC_OCLKME_CLK32K_BTSYS_EN_POS (8) 1247 #define ASC_OCLKME_CLK32K_BTSYS_EN_BIT (0x01UL << ASC_OCLKME_CLK32K_BTSYS_EN_POS) 1248 #define ASC_OCLKME_CLK_I2CS_EN_POS (9) 1249 #define ASC_OCLKME_CLK_I2CS_EN_BIT (0x01UL << ASC_OCLKME_CLK_I2CS_EN_POS) 1250 #define ASC_OCLKME_CLK_MEM2X_EN_POS (10) 1251 #define ASC_OCLKME_CLK_MEM2X_EN_BIT (0x01UL << ASC_OCLKME_CLK_MEM2X_EN_POS) 1252 #define ASC_OCLKME_CLK_EFUSE_EN_POS (11) 1253 #define ASC_OCLKME_CLK_EFUSE_EN_BIT (0x01UL << ASC_OCLKME_CLK_EFUSE_EN_POS) 1254 #define ASC_OCLKME_CLK32K_WIFIAON_EN_POS (12) 1255 #define ASC_OCLKME_CLK32K_WIFIAON_EN_BIT (0x01UL << ASC_OCLKME_CLK32K_WIFIAON_EN_POS) 1256 #define ASC_OCLKME_CLK32K_BTAON_EN_POS (13) 1257 #define ASC_OCLKME_CLK32K_BTAON_EN_BIT (0x01UL << ASC_OCLKME_CLK32K_BTAON_EN_POS) 1258 #define ASC_OCLKME_CLK52M_CPUSYS_EN_POS (14) 1259 #define ASC_OCLKME_CLK52M_CPUSYS_EN_BIT (0x01UL << ASC_OCLKME_CLK52M_CPUSYS_EN_POS) 1260 #define ASC_OCLKME_HCLK_AONROM_EN_POS (15) 1261 #define ASC_OCLKME_HCLK_AONROM_EN_BIT (0x01UL << ASC_OCLKME_HCLK_AONROM_EN_POS) 1262 #define ASC_OCLKME_HCLK_APB1_EN_POS (16) 1263 #define ASC_OCLKME_HCLK_APB1_EN_BIT (0x01UL << ASC_OCLKME_HCLK_APB1_EN_POS) 1264 #define ASC_OCLKME_HCLK_I2CS_EN_POS (17) 1265 #define ASC_OCLKME_HCLK_I2CS_EN_BIT (0x01UL << ASC_OCLKME_HCLK_I2CS_EN_POS) 1266 #define ASC_OCLKME_PCLK_SYSCTRL_EN_POS (18) 1267 #define ASC_OCLKME_PCLK_SYSCTRL_EN_BIT (0x01UL << ASC_OCLKME_PCLK_SYSCTRL_EN_POS) 1268 #define ASC_OCLKME_PCLK_PWRCTRL_EN_POS (19) 1269 #define ASC_OCLKME_PCLK_PWRCTRL_EN_BIT (0x01UL << ASC_OCLKME_PCLK_PWRCTRL_EN_POS) 1270 #define ASC_OCLKME_PCLK_GPIO_EN_POS (20) 1271 #define ASC_OCLKME_PCLK_GPIO_EN_BIT (0x01UL << ASC_OCLKME_PCLK_GPIO_EN_POS) 1272 #define ASC_OCLKME_PCLK_TIMER2_EN_POS (21) 1273 #define ASC_OCLKME_PCLK_TIMER2_EN_BIT (0x01UL << ASC_OCLKME_PCLK_TIMER2_EN_POS) 1274 #define ASC_OCLKME_PCLK_IOMUX_EN_POS (22) 1275 #define ASC_OCLKME_PCLK_IOMUX_EN_BIT (0x01UL << ASC_OCLKME_PCLK_IOMUX_EN_POS) 1276 #define ASC_OCLKME_PCLK_EFUSE_EN_POS (23) 1277 #define ASC_OCLKME_PCLK_EFUSE_EN_BIT (0x01UL << ASC_OCLKME_PCLK_EFUSE_EN_POS) 1278 #define ASC_OCLKME_HCLK_ALWAYS_CPUAON_EN_POS (24) 1279 #define ASC_OCLKME_HCLK_ALWAYS_CPUAON_EN_BIT (0x01UL << ASC_OCLKME_HCLK_ALWAYS_CPUAON_EN_POS) 1280 #define ASC_OCLKME_HCLK_CPUAON_EN_POS (25) 1281 #define ASC_OCLKME_HCLK_CPUAON_EN_BIT (0x01UL << ASC_OCLKME_HCLK_CPUAON_EN_POS) 1282 #define ASC_OCLKME_HCLK_AONSRAM_EN_POS (26) 1283 #define ASC_OCLKME_HCLK_AONSRAM_EN_BIT (0x01UL << ASC_OCLKME_HCLK_AONSRAM_EN_POS) 1284 #define ASC_OCLKME_PCLK_WDG4_EN_POS (27) 1285 #define ASC_OCLKME_PCLK_WDG4_EN_BIT (0x01UL << ASC_OCLKME_PCLK_WDG4_EN_POS) 1286 #define ASC_OCLKME_PCLK_PSIM_EN_POS (28) 1287 #define ASC_OCLKME_PCLK_PSIM_EN_BIT (0x01UL << ASC_OCLKME_PCLK_PSIM_EN_POS) 1288 #define ASC_OCLKME_PCLK_ANAREG_EN_POS (29) 1289 #define ASC_OCLKME_PCLK_ANAREG_EN_BIT (0x01UL << ASC_OCLKME_PCLK_ANAREG_EN_POS) 1290 #define ASC_OCLKME_CLKRTC_WDG4_EN_POS (30) 1291 #define ASC_OCLKME_CLKRTC_WDG4_EN_BIT (0x01UL << ASC_OCLKME_CLKRTC_WDG4_EN_POS) 1292 #define ASC_OCLKME_HCLK_WCNAON_EN_POS (31) 1293 #define ASC_OCLKME_HCLK_WCNAON_EN_BIT (0x01UL << ASC_OCLKME_HCLK_WCNAON_EN_POS) 1294 aonsysctrl_oclkme_get(void)1295__STATIC_INLINE uint32_t aonsysctrl_oclkme_get(void) 1296 { 1297 return CS_AONSYSCTRL->OCLKME; 1298 } 1299 aonsysctrl_oclkme_set(uint32_t enable_bits)1300__STATIC_INLINE void aonsysctrl_oclkme_set(uint32_t enable_bits) 1301 { 1302 CS_AONSYSCTRL->OCLKME = enable_bits; 1303 } 1304 1305 /** 1306 * Address Offset: 0x114 1307 * Register Name : ASC OCLK_MANUAL_DISABLE (write 1 valid) 1308 */ 1309 1310 #define ASC_OCLKMD_CLK26M_AONSYS_DIS_POS (0) 1311 #define ASC_OCLKMD_CLK26M_AONSYS_DIS_BIT (0x01UL << ASC_OCLKMD_CLK26M_AONSYS_DIS_POS) 1312 #define ASC_OCLKMD_CLK26M_CPUSYS_DIS_POS (1) 1313 #define ASC_OCLKMD_CLK26M_CPUSYS_DIS_BIT (0x01UL << ASC_OCLKMD_CLK26M_CPUSYS_DIS_POS) 1314 #define ASC_OCLKMD_CLK26M_TIMER20_DIS_POS (2) 1315 #define ASC_OCLKMD_CLK26M_TIMER20_DIS_BIT (0x01UL << ASC_OCLKMD_CLK26M_TIMER20_DIS_POS) 1316 #define ASC_OCLKMD_CLK32K_TIMER21_DIS_POS (3) 1317 #define ASC_OCLKMD_CLK32K_TIMER21_DIS_BIT (0x01UL << ASC_OCLKMD_CLK32K_TIMER21_DIS_POS) 1318 #define ASC_OCLKMD_CLK32K_TIMER22_DIS_POS (4) 1319 #define ASC_OCLKMD_CLK32K_TIMER22_DIS_BIT (0x01UL << ASC_OCLKMD_CLK32K_TIMER22_DIS_POS) 1320 #define ASC_OCLKMD_CLK32K_AONSYS_DIS_POS (5) 1321 #define ASC_OCLKMD_CLK32K_AONSYS_DIS_BIT (0x01UL << ASC_OCLKMD_CLK32K_AONSYS_DIS_POS) 1322 #define ASC_OCLKMD_CLK32K_CPUSYS_DIS_POS (6) 1323 #define ASC_OCLKMD_CLK32K_CPUSYS_DIS_BIT (0x01UL << ASC_OCLKMD_CLK32K_CPUSYS_DIS_POS) 1324 #define ASC_OCLKMD_CLK32K_WIFISYS_DIS_POS (7) 1325 #define ASC_OCLKMD_CLK32K_WIFISYS_DIS_BIT (0x01UL << ASC_OCLKMD_CLK32K_WIFISYS_DIS_POS) 1326 #define ASC_OCLKMD_CLK32K_BTSYS_DIS_POS (8) 1327 #define ASC_OCLKMD_CLK32K_BTSYS_DIS_BIT (0x01UL << ASC_OCLKMD_CLK32K_BTSYS_DIS_POS) 1328 #define ASC_OCLKMD_CLK_I2CS_DIS_POS (9) 1329 #define ASC_OCLKMD_CLK_I2CS_DIS_BIT (0x01UL << ASC_OCLKMD_CLK_I2CS_DIS_POS) 1330 #define ASC_OCLKMD_CLK_MEM2X_DIS_POS (10) 1331 #define ASC_OCLKMD_CLK_MEM2X_DIS_BIT (0x01UL << ASC_OCLKMD_CLK_MEM2X_DIS_POS) 1332 #define ASC_OCLKMD_CLK_EFUSE_DIS_POS (11) 1333 #define ASC_OCLKMD_CLK_EFUSE_DIS_BIT (0x01UL << ASC_OCLKMD_CLK_EFUSE_DIS_POS) 1334 #define ASC_OCLKMD_CLK32K_WIFIAON_DIS_POS (12) 1335 #define ASC_OCLKMD_CLK32K_WIFIAON_DIS_BIT (0x01UL << ASC_OCLKMD_CLK32K_WIFIAON_DIS_POS) 1336 #define ASC_OCLKMD_CLK32K_BTAON_DIS_POS (13) 1337 #define ASC_OCLKMD_CLK32K_BTAON_DIS_BIT (0x01UL << ASC_OCLKMD_CLK32K_BTAON_DIS_POS) 1338 #define ASC_OCLKMD_CLK52M_CPUSYS_DIS_POS (14) 1339 #define ASC_OCLKMD_CLK52M_CPUSYS_DIS_BIT (0x01UL << ASC_OCLKMD_CLK52M_CPUSYS_DIS_POS) 1340 #define ASC_OCLKMD_HCLK_AONROM_DIS_POS (15) 1341 #define ASC_OCLKMD_HCLK_AONROM_DIS_BIT (0x01UL << ASC_OCLKMD_HCLK_AONROM_DIS_POS) 1342 #define ASC_OCLKMD_HCLK_APB1_DIS_POS (16) 1343 #define ASC_OCLKMD_HCLK_APB1_DIS_BIT (0x01UL << ASC_OCLKMD_HCLK_APB1_DIS_POS) 1344 #define ASC_OCLKMD_HCLK_I2CS_DIS_POS (17) 1345 #define ASC_OCLKMD_HCLK_I2CS_DIS_BIT (0x01UL << ASC_OCLKMD_HCLK_I2CS_DIS_POS) 1346 #define ASC_OCLKMD_PCLK_SYSCTRL_DIS_POS (18) 1347 #define ASC_OCLKMD_PCLK_SYSCTRL_DIS_BIT (0x01UL << ASC_OCLKMD_PCLK_SYSCTRL_DIS_POS) 1348 #define ASC_OCLKMD_PCLK_PWRCTRL_DIS_POS (19) 1349 #define ASC_OCLKMD_PCLK_PWRCTRL_DIS_BIT (0x01UL << ASC_OCLKMD_PCLK_PWRCTRL_DIS_POS) 1350 #define ASC_OCLKMD_PCLK_GPIO_DIS_POS (20) 1351 #define ASC_OCLKMD_PCLK_GPIO_DIS_BIT (0x01UL << ASC_OCLKMD_PCLK_GPIO_DIS_POS) 1352 #define ASC_OCLKMD_PCLK_TIMER2_DIS_POS (21) 1353 #define ASC_OCLKMD_PCLK_TIMER2_DIS_BIT (0x01UL << ASC_OCLKMD_PCLK_TIMER2_DIS_POS) 1354 #define ASC_OCLKMD_PCLK_IOMUX_DIS_POS (22) 1355 #define ASC_OCLKMD_PCLK_IOMUX_DIS_BIT (0x01UL << ASC_OCLKMD_PCLK_IOMUX_DIS_POS) 1356 #define ASC_OCLKMD_PCLK_EFUSE_DIS_POS (23) 1357 #define ASC_OCLKMD_PCLK_EFUSE_DIS_BIT (0x01UL << ASC_OCLKMD_PCLK_EFUSE_DIS_POS) 1358 #define ASC_OCLKMD_HCLK_ALWAYS_CPUAON_DIS_POS (24) 1359 #define ASC_OCLKMD_HCLK_ALWAYS_CPUAON_DIS_BIT (0x01UL << ASC_OCLKMD_HCLK_ALWAYS_CPUAON_DIS_POS) 1360 #define ASC_OCLKMD_HCLK_CPUAON_DIS_POS (25) 1361 #define ASC_OCLKMD_HCLK_CPUAON_DIS_BIT (0x01UL << ASC_OCLKMD_HCLK_CPUAON_DIS_POS) 1362 #define ASC_OCLKMD_HCLK_AONSRAM_DIS_POS (26) 1363 #define ASC_OCLKMD_HCLK_AONSRAM_DIS_BIT (0x01UL << ASC_OCLKMD_HCLK_AONSRAM_DIS_POS) 1364 #define ASC_OCLKMD_PCLK_WDG4_DIS_POS (27) 1365 #define ASC_OCLKMD_PCLK_WDG4_DIS_BIT (0x01UL << ASC_OCLKMD_PCLK_WDG4_DIS_POS) 1366 #define ASC_OCLKMD_PCLK_PSIM_DIS_POS (28) 1367 #define ASC_OCLKMD_PCLK_PSIM_DIS_BIT (0x01UL << ASC_OCLKMD_PCLK_PSIM_DIS_POS) 1368 #define ASC_OCLKMD_PCLK_ANAREG_DIS_POS (29) 1369 #define ASC_OCLKMD_PCLK_ANAREG_DIS_BIT (0x01UL << ASC_OCLKMD_PCLK_ANAREG_DIS_POS) 1370 #define ASC_OCLKMD_CLKRTC_WDG4_DIS_POS (30) 1371 #define ASC_OCLKMD_CLKRTC_WDG4_DIS_BIT (0x01UL << ASC_OCLKMD_CLKRTC_WDG4_DIS_POS) 1372 #define ASC_OCLKMD_HCLK_WCNAON_DIS_POS (31) 1373 #define ASC_OCLKMD_HCLK_WCNAON_DIS_BIT (0x01UL << ASC_OCLKMD_HCLK_WCNAON_DIS_POS) 1374 aonsysctrl_oclkmd_get(void)1375__STATIC_INLINE uint32_t aonsysctrl_oclkmd_get(void) 1376 { 1377 return CS_AONSYSCTRL->OCLKMD; 1378 } 1379 aonsysctrl_oclkmd_set(uint32_t disable_bits)1380__STATIC_INLINE void aonsysctrl_oclkmd_set(uint32_t disable_bits) 1381 { 1382 CS_AONSYSCTRL->OCLKMD = disable_bits; 1383 } 1384 1385 /** 1386 * Address Offset: 0x118 1387 * Register Name : ASC GLOBAL_SOFT_RESETn_SET (write 1 valid) 1388 */ 1389 1390 #define ASC_GLBRS_SOFTSET_POS (0) 1391 #define ASC_GLBRS_SOFTSET_BIT (0x01UL << ASC_GLBRS_SOFTSET_POS) 1392 aonsysctrl_glbrs_softset_getb(void)1393__STATIC_INLINE uint8_t aonsysctrl_glbrs_softset_getb(void) 1394 { 1395 return (CS_AONSYSCTRL->GLBRS & ASC_GLBRS_SOFTSET_BIT) >> ASC_GLBRS_SOFTSET_POS; 1396 } 1397 aonsysctrl_glbrs_softset_setb(void)1398__STATIC_INLINE void aonsysctrl_glbrs_softset_setb(void) 1399 { 1400 CS_AONSYSCTRL->GLBRS = ASC_GLBRS_SOFTSET_BIT; 1401 } 1402 1403 /** 1404 * Address Offset: 0x11C 1405 * Register Name : ASC GLOBAL_SOFT_RESETn_CLEAR (write 1 valid) 1406 */ 1407 1408 #define ASC_GLBRC_SOFTCLR_POS (0) 1409 #define ASC_GLBRC_SOFTCLR_BIT (0x01UL << ASC_GLBRC_SOFTCLR_POS) 1410 aonsysctrl_glbrc_softclr_getb(void)1411__STATIC_INLINE uint8_t aonsysctrl_glbrc_softclr_getb(void) 1412 { 1413 return (CS_AONSYSCTRL->GLBRC & ASC_GLBRC_SOFTCLR_BIT) >> ASC_GLBRC_SOFTCLR_POS; 1414 } 1415 aonsysctrl_glbrc_softclr_setb(void)1416__STATIC_INLINE void aonsysctrl_glbrc_softclr_setb(void) 1417 { 1418 CS_AONSYSCTRL->GLBRC = ASC_GLBRC_SOFTCLR_BIT; 1419 } 1420 1421 /** 1422 * Address Offset: 0x120 1423 * Register Name : ASC HCLK_SOFT_RESETn_SET (write 1 valid) 1424 */ 1425 1426 #define ASC_HCLKRS_CPUSBSET_POS (5) 1427 #define ASC_HCLKRS_CPUSBSET_BIT (0x01UL << ASC_HCLKRS_CPUSBSET_POS) 1428 #define ASC_HCLKRS_CPUSWSET_POS (6) 1429 #define ASC_HCLKRS_CPUSWSET_BIT (0x01UL << ASC_HCLKRS_CPUSWSET_POS) 1430 #define ASC_HCLKRS_DSPSET_POS (7) 1431 #define ASC_HCLKRS_DSPSET_BIT (0x01UL << ASC_HCLKRS_DSPSET_POS) 1432 aonsysctrl_hclkrs_get(void)1433__STATIC_INLINE uint32_t aonsysctrl_hclkrs_get(void) 1434 { 1435 return CS_AONSYSCTRL->HCLKRS; 1436 } 1437 aonsysctrl_hclkrs_set(uint32_t reset_bits)1438__STATIC_INLINE void aonsysctrl_hclkrs_set(uint32_t reset_bits) 1439 { 1440 CS_AONSYSCTRL->HCLKRS = reset_bits; 1441 } 1442 aonsysctrl_hclkrs_cpusbset_getb(void)1443__STATIC_INLINE uint8_t aonsysctrl_hclkrs_cpusbset_getb(void) 1444 { 1445 return (CS_AONSYSCTRL->HCLKRS & ASC_HCLKRS_CPUSBSET_BIT) >> ASC_HCLKRS_CPUSBSET_POS; 1446 } 1447 aonsysctrl_hclkrs_cpusbset_setb(void)1448__STATIC_INLINE void aonsysctrl_hclkrs_cpusbset_setb(void) 1449 { 1450 CS_AONSYSCTRL->HCLKRS = ASC_HCLKRS_CPUSBSET_BIT; 1451 } 1452 aonsysctrl_hclkrs_cpuswset_getb(void)1453__STATIC_INLINE uint8_t aonsysctrl_hclkrs_cpuswset_getb(void) 1454 { 1455 return (CS_AONSYSCTRL->HCLKRS & ASC_HCLKRS_CPUSWSET_BIT) >> ASC_HCLKRS_CPUSWSET_POS; 1456 } 1457 aonsysctrl_hclkrs_cpuswset_setb(void)1458__STATIC_INLINE void aonsysctrl_hclkrs_cpuswset_setb(void) 1459 { 1460 CS_AONSYSCTRL->HCLKRS = ASC_HCLKRS_CPUSWSET_BIT; 1461 } 1462 aonsysctrl_hclkrs_dspset_getb(void)1463__STATIC_INLINE uint8_t aonsysctrl_hclkrs_dspset_getb(void) 1464 { 1465 return (CS_AONSYSCTRL->HCLKRS & ASC_HCLKRS_DSPSET_BIT) >> ASC_HCLKRS_DSPSET_POS; 1466 } 1467 aonsysctrl_hclkrs_dspset_setb(void)1468__STATIC_INLINE void aonsysctrl_hclkrs_dspset_setb(void) 1469 { 1470 CS_AONSYSCTRL->HCLKRS = ASC_HCLKRS_DSPSET_BIT; 1471 } 1472 1473 /** 1474 * Address Offset: 0x124 1475 * Register Name : ASC HCLK_SOFT_RESETn_CLEAR (write 1 valid) 1476 */ 1477 1478 #define ASC_HCLKRC_CPUSBCLR_POS (5) 1479 #define ASC_HCLKRC_CPUSBCLR_BIT (0x01UL << ASC_HCLKRC_CPUSBCLR_POS) 1480 #define ASC_HCLKRC_CPUSWCLR_POS (6) 1481 #define ASC_HCLKRC_CPUSWCLR_BIT (0x01UL << ASC_HCLKRC_CPUSWCLR_POS) 1482 #define ASC_HCLKRC_DSPCLR_POS (7) 1483 #define ASC_HCLKRC_DSPCLR_BIT (0x01UL << ASC_HCLKRC_DSPCLR_POS) 1484 aonsysctrl_hclkrc_get(void)1485__STATIC_INLINE uint32_t aonsysctrl_hclkrc_get(void) 1486 { 1487 return CS_AONSYSCTRL->HCLKRC; 1488 } 1489 aonsysctrl_hclkrc_set(uint32_t reset_bits)1490__STATIC_INLINE void aonsysctrl_hclkrc_set(uint32_t reset_bits) 1491 { 1492 CS_AONSYSCTRL->HCLKRC = reset_bits; 1493 } 1494 aonsysctrl_hclkrc_cpusbclr_getb(void)1495__STATIC_INLINE uint8_t aonsysctrl_hclkrc_cpusbclr_getb(void) 1496 { 1497 return (CS_AONSYSCTRL->HCLKRC & ASC_HCLKRC_CPUSBCLR_BIT) >> ASC_HCLKRC_CPUSBCLR_POS; 1498 } 1499 aonsysctrl_hclkrc_cpusbclr_setb(void)1500__STATIC_INLINE void aonsysctrl_hclkrc_cpusbclr_setb(void) 1501 { 1502 CS_AONSYSCTRL->HCLKRC = ASC_HCLKRC_CPUSBCLR_BIT; 1503 } 1504 aonsysctrl_hclkrc_cpuswclr_getb(void)1505__STATIC_INLINE uint8_t aonsysctrl_hclkrc_cpuswclr_getb(void) 1506 { 1507 return (CS_AONSYSCTRL->HCLKRC & ASC_HCLKRC_CPUSWCLR_BIT) >> ASC_HCLKRC_CPUSWCLR_POS; 1508 } 1509 aonsysctrl_hclkrc_cpuswclr_setb(void)1510__STATIC_INLINE void aonsysctrl_hclkrc_cpuswclr_setb(void) 1511 { 1512 CS_AONSYSCTRL->HCLKRC = ASC_HCLKRC_CPUSWCLR_BIT; 1513 } 1514 aonsysctrl_hclkrc_dspclr_getb(void)1515__STATIC_INLINE uint8_t aonsysctrl_hclkrc_dspclr_getb(void) 1516 { 1517 return (CS_AONSYSCTRL->HCLKRC & ASC_HCLKRC_DSPCLR_BIT) >> ASC_HCLKRC_DSPCLR_POS; 1518 } 1519 aonsysctrl_hclkrc_dspclr_setb(void)1520__STATIC_INLINE void aonsysctrl_hclkrc_dspclr_setb(void) 1521 { 1522 CS_AONSYSCTRL->HCLKRC = ASC_HCLKRC_DSPCLR_BIT; 1523 } 1524 1525 /** 1526 * Address Offset: 0x130 1527 * Register Name : ASC OTHERS_SOFT_RESETn_SET (write 1 valid) 1528 */ 1529 1530 #define ASC_OCLKRS_32KWIFIAONSET_POS (11) 1531 #define ASC_OCLKRS_32KWIFIAONSET_BIT (0x01UL << ASC_OCLKRS_32KWIFIAONSET_POS) 1532 #define ASC_OCLKRS_32KBTAONSET_POS (12) 1533 #define ASC_OCLKRS_32KBTAONSET_BIT (0x01UL << ASC_OCLKRS_32KBTAONSET_POS) 1534 #define ASC_OCLKRS_CPUAONSET_POS (24) 1535 #define ASC_OCLKRS_CPUAONSET_BIT (0x01UL << ASC_OCLKRS_CPUAONSET_POS) 1536 aonsysctrl_oclkrs_get(void)1537__STATIC_INLINE uint32_t aonsysctrl_oclkrs_get(void) 1538 { 1539 return CS_AONSYSCTRL->OCLKRS; 1540 } 1541 aonsysctrl_oclkrs_set(uint32_t reset_bits)1542__STATIC_INLINE void aonsysctrl_oclkrs_set(uint32_t reset_bits) 1543 { 1544 CS_AONSYSCTRL->OCLKRS = reset_bits; 1545 } 1546 aonsysctrl_oclkrs_32kwifiaonset_getb(void)1547__STATIC_INLINE uint8_t aonsysctrl_oclkrs_32kwifiaonset_getb(void) 1548 { 1549 return (CS_AONSYSCTRL->OCLKRS & ASC_OCLKRS_32KWIFIAONSET_BIT) >> ASC_OCLKRS_32KWIFIAONSET_POS; 1550 } 1551 aonsysctrl_oclkrs_32kwifiaonset_setb(void)1552__STATIC_INLINE void aonsysctrl_oclkrs_32kwifiaonset_setb(void) 1553 { 1554 CS_AONSYSCTRL->OCLKRS = ASC_OCLKRS_32KWIFIAONSET_BIT; 1555 } 1556 aonsysctrl_oclkrs_32kbtaonset_getb(void)1557__STATIC_INLINE uint8_t aonsysctrl_oclkrs_32kbtaonset_getb(void) 1558 { 1559 return (CS_AONSYSCTRL->OCLKRS & ASC_OCLKRS_32KBTAONSET_BIT) >> ASC_OCLKRS_32KBTAONSET_POS; 1560 } 1561 aonsysctrl_oclkrs_32kbtaonset_setb(void)1562__STATIC_INLINE void aonsysctrl_oclkrs_32kbtaonset_setb(void) 1563 { 1564 CS_AONSYSCTRL->OCLKRS = ASC_OCLKRS_32KBTAONSET_BIT; 1565 } 1566 aonsysctrl_oclkrs_cpuaonset_getb(void)1567__STATIC_INLINE uint8_t aonsysctrl_oclkrs_cpuaonset_getb(void) 1568 { 1569 return (CS_AONSYSCTRL->OCLKRS & ASC_OCLKRS_CPUAONSET_BIT) >> ASC_OCLKRS_CPUAONSET_POS; 1570 } 1571 aonsysctrl_oclkrs_cpuaonset_setb(void)1572__STATIC_INLINE void aonsysctrl_oclkrs_cpuaonset_setb(void) 1573 { 1574 CS_AONSYSCTRL->OCLKRS = ASC_OCLKRS_CPUAONSET_BIT; 1575 } 1576 1577 /** 1578 * Address Offset: 0x134 1579 * Register Name : ASC OTHERS_SOFT_RESETn_CLEAR (write 1 valid) 1580 */ 1581 1582 #define ASC_OCLKRC_32KWIFIAONCLR_POS (11) 1583 #define ASC_OCLKRC_32KWIFIAONCLR_BIT (0x01UL << ASC_OCLKRC_32KWIFIAONCLR_POS) 1584 #define ASC_OCLKRC_32KBTAONCLR_POS (12) 1585 #define ASC_OCLKRC_32KBTAONCLR_BIT (0x01UL << ASC_OCLKRC_32KBTAONCLR_POS) 1586 #define ASC_OCLKRC_CPUAONCLR_POS (24) 1587 #define ASC_OCLKRC_CPUAONCLR_BIT (0x01UL << ASC_OCLKRC_CPUAONCLR_POS) 1588 aonsysctrl_oclkrc_get(void)1589__STATIC_INLINE uint32_t aonsysctrl_oclkrc_get(void) 1590 { 1591 return CS_AONSYSCTRL->OCLKRC; 1592 } 1593 aonsysctrl_oclkrc_set(uint32_t reset_bits)1594__STATIC_INLINE void aonsysctrl_oclkrc_set(uint32_t reset_bits) 1595 { 1596 CS_AONSYSCTRL->OCLKRC = reset_bits; 1597 } 1598 aonsysctrl_oclkrc_32kwifiaonclr_getb(void)1599__STATIC_INLINE uint8_t aonsysctrl_oclkrc_32kwifiaonclr_getb(void) 1600 { 1601 return (CS_AONSYSCTRL->OCLKRC & ASC_OCLKRC_32KWIFIAONCLR_BIT) >> ASC_OCLKRC_32KWIFIAONCLR_POS; 1602 } 1603 aonsysctrl_oclkrc_32kwifiaonclr_setb(void)1604__STATIC_INLINE void aonsysctrl_oclkrc_32kwifiaonclr_setb(void) 1605 { 1606 CS_AONSYSCTRL->OCLKRC = ASC_OCLKRC_32KWIFIAONCLR_BIT; 1607 } 1608 aonsysctrl_oclkrc_32kbtaonclr_getb(void)1609__STATIC_INLINE uint8_t aonsysctrl_oclkrc_32kbtaonclr_getb(void) 1610 { 1611 return (CS_AONSYSCTRL->OCLKRC & ASC_OCLKRC_32KBTAONCLR_BIT) >> ASC_OCLKRC_32KBTAONCLR_POS; 1612 } 1613 aonsysctrl_oclkrc_32kbtaonclr_setb(void)1614__STATIC_INLINE void aonsysctrl_oclkrc_32kbtaonclr_setb(void) 1615 { 1616 CS_AONSYSCTRL->OCLKRC = ASC_OCLKRC_32KBTAONCLR_BIT; 1617 } 1618 aonsysctrl_oclkrc_cpuaonclr_getb(void)1619__STATIC_INLINE uint8_t aonsysctrl_oclkrc_cpuaonclr_getb(void) 1620 { 1621 return (CS_AONSYSCTRL->OCLKRC & ASC_OCLKRC_CPUAONCLR_BIT) >> ASC_OCLKRC_CPUAONCLR_POS; 1622 } 1623 aonsysctrl_oclkrc_cpuaonclr_setb(void)1624__STATIC_INLINE void aonsysctrl_oclkrc_cpuaonclr_setb(void) 1625 { 1626 CS_AONSYSCTRL->OCLKRC = ASC_OCLKRC_CPUAONCLR_BIT; 1627 } 1628 1629 /** 1630 * Address Offset: 0x138 1631 * Register Name : ASC BOOTMD 1632 */ 1633 1634 #define ASC_BOOTMD_HW_BOOT_MODE_LSB (0) 1635 #define ASC_BOOTMD_HW_BOOT_MODE_WIDTH (4) 1636 #define ASC_BOOTMD_HW_BOOT_MODE_MASK (((0x01UL << ASC_BOOTMD_HW_BOOT_MODE_WIDTH) - 1) << ASC_BOOTMD_HW_BOOT_MODE_LSB) 1637 #define ASC_BOOTMD_SW_BOOT_MODE_LSB (4) 1638 #define ASC_BOOTMD_SW_BOOT_MODE_WIDTH (4) 1639 #define ASC_BOOTMD_SW_BOOT_MODE_MASK (((0x01UL << ASC_BOOTMD_SW_BOOT_MODE_WIDTH) - 1) << ASC_BOOTMD_SW_BOOT_MODE_LSB) 1640 aonsysctrl_bootmd_hw_boot_mode_getf(void)1641__STATIC_INLINE uint8_t aonsysctrl_bootmd_hw_boot_mode_getf(void) 1642 { 1643 return ((CS_AONSYSCTRL->BOOTMD & ASC_BOOTMD_HW_BOOT_MODE_MASK) >> ASC_BOOTMD_HW_BOOT_MODE_LSB); 1644 } 1645 aonsysctrl_bootmd_hw_boot_mode_setf(uint8_t boot_mode)1646__STATIC_INLINE void aonsysctrl_bootmd_hw_boot_mode_setf(uint8_t boot_mode) 1647 { 1648 uint32_t local_val = CS_AONSYSCTRL->BOOTMD & ~ASC_BOOTMD_HW_BOOT_MODE_MASK; 1649 CS_AONSYSCTRL->BOOTMD = local_val | ((boot_mode << ASC_BOOTMD_HW_BOOT_MODE_LSB) & ASC_BOOTMD_HW_BOOT_MODE_MASK); 1650 } 1651 aonsysctrl_bootmd_sw_boot_mode_getf(void)1652__STATIC_INLINE uint8_t aonsysctrl_bootmd_sw_boot_mode_getf(void) 1653 { 1654 return ((CS_AONSYSCTRL->BOOTMD & ASC_BOOTMD_SW_BOOT_MODE_MASK) >> ASC_BOOTMD_SW_BOOT_MODE_LSB); 1655 } 1656 aonsysctrl_bootmd_sw_boot_mode_setf(uint8_t boot_mode)1657__STATIC_INLINE void aonsysctrl_bootmd_sw_boot_mode_setf(uint8_t boot_mode) 1658 { 1659 uint32_t local_val = CS_AONSYSCTRL->BOOTMD & ~ASC_BOOTMD_SW_BOOT_MODE_MASK; 1660 CS_AONSYSCTRL->BOOTMD = local_val | ((boot_mode << ASC_BOOTMD_SW_BOOT_MODE_LSB) & ASC_BOOTMD_SW_BOOT_MODE_MASK); 1661 } 1662 1663 /** 1664 * Address Offset: 0x140 1665 * Register Name : ASC BTFW_CTRL 1666 */ 1667 1668 #define ASC_BTFWCTRL_STACK_TOP_LSB (0) 1669 #define ASC_BTFWCTRL_STACK_TOP_WIDTH (24) 1670 #define ASC_BTFWCTRL_STACK_TOP_MASK (((0x01UL << ASC_BTFWCTRL_STACK_TOP_WIDTH) - 1) << ASC_BTFWCTRL_STACK_TOP_LSB) 1671 #define ASC_BTFWCTRL_BTCORE_SWCTRL_LSB (24) 1672 #define ASC_BTFWCTRL_BTCORE_SWCTRL_WIDTH (2) 1673 #define ASC_BTFWCTRL_BTCORE_SWCTRL_MASK (((0x01UL << ASC_BTFWCTRL_BTCORE_SWCTRL_WIDTH) - 1) << ASC_BTFWCTRL_BTCORE_SWCTRL_LSB) 1674 #define ASC_BTFWCTRL_STACK_TOP_VALID_POS (31) 1675 #define ASC_BTFWCTRL_STACK_TOP_VALID_BIT (0x01UL << ASC_BTFWCTRL_STACK_TOP_VALID_POS) 1676 aonsysctrl_btfwctrl_stack_top_getf(void)1677__STATIC_INLINE uint32_t aonsysctrl_btfwctrl_stack_top_getf(void) 1678 { 1679 return ((CS_AONSYSCTRL->BTFWCTRL & ASC_BTFWCTRL_STACK_TOP_MASK) >> ASC_BTFWCTRL_STACK_TOP_LSB); 1680 } 1681 aonsysctrl_btfwctrl_stack_top_setf(uint32_t addr)1682__STATIC_INLINE void aonsysctrl_btfwctrl_stack_top_setf(uint32_t addr) 1683 { 1684 uint32_t local_val = CS_AONSYSCTRL->BTFWCTRL & ~ASC_BTFWCTRL_STACK_TOP_MASK; 1685 CS_AONSYSCTRL->BTFWCTRL = local_val | ((addr << ASC_BTFWCTRL_STACK_TOP_LSB) & ASC_BTFWCTRL_STACK_TOP_MASK) | ASC_BTFWCTRL_STACK_TOP_VALID_BIT; 1686 } 1687 aonsysctrl_btfwctrl_btcore_swctrl_getf(void)1688__STATIC_INLINE uint32_t aonsysctrl_btfwctrl_btcore_swctrl_getf(void) 1689 { 1690 return ((CS_AONSYSCTRL->BTFWCTRL & ASC_BTFWCTRL_BTCORE_SWCTRL_MASK) >> ASC_BTFWCTRL_BTCORE_SWCTRL_LSB); 1691 } 1692 aonsysctrl_btfwctrl_btcore_swctrl_setf(uint32_t addr)1693__STATIC_INLINE void aonsysctrl_btfwctrl_btcore_swctrl_setf(uint32_t addr) 1694 { 1695 uint32_t local_val = CS_AONSYSCTRL->BTFWCTRL & ~ASC_BTFWCTRL_BTCORE_SWCTRL_MASK; 1696 CS_AONSYSCTRL->BTFWCTRL = local_val | ((addr << ASC_BTFWCTRL_BTCORE_SWCTRL_LSB) & ASC_BTFWCTRL_BTCORE_SWCTRL_MASK); 1697 } 1698 1699 /** 1700 * Address Offset: 0x144 1701 * Register Name : ASC WIFIFW_CTRL 1702 */ 1703 1704 #define ASC_WIFIFWCTRL_STACK_TOP_LSB (0) 1705 #define ASC_WIFIFWCTRL_STACK_TOP_WIDTH (24) 1706 #define ASC_WIFIFWCTRL_STACK_TOP_MASK (((0x01UL << ASC_WIFIFWCTRL_STACK_TOP_WIDTH) - 1) << ASC_WIFIFWCTRL_STACK_TOP_LSB) 1707 #define ASC_WIFIFWCTRL_WIFICORE_SWCTRL_LSB (24) 1708 #define ASC_WIFIFWCTRL_WIFICORE_SWCTRL_WIDTH (2) 1709 #define ASC_WIFIFWCTRL_WIFICORE_SWCTRL_MASK (((0x01UL << ASC_WIFIFWCTRL_WIFICORE_SWCTRL_WIDTH) - 1) << ASC_WIFIFWCTRL_WIFICORE_SWCTRL_LSB) 1710 #define ASC_WIFIFWCTRL_STACK_TOP_VALID_POS (31) 1711 #define ASC_WIFIFWCTRL_STACK_TOP_VALID_BIT (0x01UL << ASC_WIFIFWCTRL_STACK_TOP_VALID_POS) 1712 aonsysctrl_wififwctrl_stack_top_getf(void)1713__STATIC_INLINE uint32_t aonsysctrl_wififwctrl_stack_top_getf(void) 1714 { 1715 return ((CS_AONSYSCTRL->WIFIFWCTRL & ASC_WIFIFWCTRL_STACK_TOP_MASK) >> ASC_WIFIFWCTRL_STACK_TOP_LSB); 1716 } 1717 aonsysctrl_wififwctrl_stack_top_setf(uint32_t addr)1718__STATIC_INLINE void aonsysctrl_wififwctrl_stack_top_setf(uint32_t addr) 1719 { 1720 uint32_t local_val = CS_AONSYSCTRL->WIFIFWCTRL & ~ASC_WIFIFWCTRL_STACK_TOP_MASK; 1721 CS_AONSYSCTRL->WIFIFWCTRL = local_val | ((addr << ASC_WIFIFWCTRL_STACK_TOP_LSB) & ASC_WIFIFWCTRL_STACK_TOP_MASK) | ASC_WIFIFWCTRL_STACK_TOP_VALID_BIT; 1722 } 1723 aonsysctrl_wififwctrl_wificore_swctrl_getf(void)1724__STATIC_INLINE uint32_t aonsysctrl_wififwctrl_wificore_swctrl_getf(void) 1725 { 1726 return ((CS_AONSYSCTRL->WIFIFWCTRL & ASC_WIFIFWCTRL_WIFICORE_SWCTRL_MASK) >> ASC_WIFIFWCTRL_WIFICORE_SWCTRL_LSB); 1727 } 1728 aonsysctrl_wififwctrl_wificore_swctrl_setf(uint32_t addr)1729__STATIC_INLINE void aonsysctrl_wififwctrl_wificore_swctrl_setf(uint32_t addr) 1730 { 1731 uint32_t local_val = CS_AONSYSCTRL->WIFIFWCTRL & ~ASC_WIFIFWCTRL_WIFICORE_SWCTRL_MASK; 1732 CS_AONSYSCTRL->WIFIFWCTRL = local_val | ((addr << ASC_WIFIFWCTRL_WIFICORE_SWCTRL_LSB) & ASC_WIFIFWCTRL_WIFICORE_SWCTRL_MASK); 1733 } 1734 1735 /** 1736 * Address Offset: 0x148 1737 * Register Name : ASC BOOT_ENTRY 1738 */ 1739 1740 #define ASC_BOOTENTRY_ADDR_LSB (0) 1741 #define ASC_BOOTENTRY_ADDR_WIDTH (28) 1742 #define ASC_BOOTENTRY_ADDR_MASK (((0x01UL << ASC_BOOTENTRY_ADDR_WIDTH) - 1) << ASC_BOOTENTRY_ADDR_LSB) 1743 #define ASC_BOOTENTRY_ADDR_VALID_POS (31) 1744 #define ASC_BOOTENTRY_ADDR_VALID_BIT (0x01UL << ASC_BOOTENTRY_ADDR_VALID_POS) 1745 aonsysctrl_bootentry_get(void)1746__STATIC_INLINE uint32_t aonsysctrl_bootentry_get(void) 1747 { 1748 return CS_AONSYSCTRL->BOOTENTRY; 1749 } 1750 aonsysctrl_bootentry_set(uint32_t entry)1751__STATIC_INLINE void aonsysctrl_bootentry_set(uint32_t entry) 1752 { 1753 CS_AONSYSCTRL->BOOTENTRY = entry; 1754 } 1755 1756 /** 1757 * Address Offset: 0x14C 1758 * Register Name : ASC BOOT_STACK 1759 */ 1760 1761 #define ASC_BOOTSTACK_ADDR_LSB (0) 1762 #define ASC_BOOTSTACK_ADDR_WIDTH (28) 1763 #define ASC_BOOTSTACK_ADDR_MASK (((0x01UL << ASC_BOOTSTACK_ADDR_WIDTH) - 1) << ASC_BOOTSTACK_ADDR_LSB) 1764 #define ASC_BOOTSTACK_ADDR_VALID_POS (31) 1765 #define ASC_BOOTSTACK_ADDR_VALID_BIT (0x01UL << ASC_BOOTSTACK_ADDR_VALID_POS) 1766 aonsysctrl_bootstack_get(void)1767__STATIC_INLINE uint32_t aonsysctrl_bootstack_get(void) 1768 { 1769 return CS_AONSYSCTRL->BOOTSTACK; 1770 } 1771 aonsysctrl_bootstack_set(uint32_t stack)1772__STATIC_INLINE void aonsysctrl_bootstack_set(uint32_t stack) 1773 { 1774 CS_AONSYSCTRL->BOOTSTACK = stack; 1775 } 1776 1777 /** 1778 * Address Offset: 0x150 1779 * Register Name : ASC HOST_TC_LSB 1780 */ 1781 aonsysctrl_hosttclsb_get(void)1782__STATIC_INLINE uint32_t aonsysctrl_hosttclsb_get(void) 1783 { 1784 return CS_AONSYSCTRL->HOSTTCLSB; 1785 } 1786 aonsysctrl_hosttclsb_set(uint32_t lsb)1787__STATIC_INLINE void aonsysctrl_hosttclsb_set(uint32_t lsb) 1788 { 1789 CS_AONSYSCTRL->HOSTTCLSB = lsb; 1790 } 1791 1792 /** 1793 * Address Offset: 0x154 1794 * Register Name : ASC HOST_TC_MSB 1795 */ 1796 aonsysctrl_hosttcmsb_get(void)1797__STATIC_INLINE uint32_t aonsysctrl_hosttcmsb_get(void) 1798 { 1799 return CS_AONSYSCTRL->HOSTTCMSB; 1800 } 1801 aonsysctrl_hosttcmsb_set(uint32_t msb)1802__STATIC_INLINE void aonsysctrl_hosttcmsb_set(uint32_t msb) 1803 { 1804 CS_AONSYSCTRL->HOSTTCMSB = msb; 1805 } 1806 1807 /** 1808 * Address Offset: 0x158 1809 * Register Name : ASC HOST_SYST 1810 */ 1811 aonsysctrl_hostsyst_get(void)1812__STATIC_INLINE uint32_t aonsysctrl_hostsyst_get(void) 1813 { 1814 return CS_AONSYSCTRL->HOSTSYST; 1815 } 1816 aonsysctrl_hostsyst_set(uint32_t syst)1817__STATIC_INLINE void aonsysctrl_hostsyst_set(uint32_t syst) 1818 { 1819 CS_AONSYSCTRL->HOSTSYST = syst; 1820 } 1821 1822 /** 1823 * Address Offset: 0x15C 1824 * Register Name : ASC BT_PWR_CTRL 1825 */ 1826 aonsysctrl_btpwrctrl_get(void)1827__STATIC_INLINE uint32_t aonsysctrl_btpwrctrl_get(void) 1828 { 1829 return CS_AONSYSCTRL->BTPWRCTRL; 1830 } 1831 aonsysctrl_btpwrctrl_set(uint32_t ctrl)1832__STATIC_INLINE void aonsysctrl_btpwrctrl_set(uint32_t ctrl) 1833 { 1834 CS_AONSYSCTRL->BTPWRCTRL = ctrl; 1835 } 1836 1837 /** 1838 * Address Offset: 0x004 1839 * Register Name : CSC CLKSEL 1840 */ 1841 1842 #define CSC_CLKSEL_FLASHCLK_POS (0) 1843 #define CSC_CLKSEL_FLASHCLK_BIT (0x01UL << CSC_CLKSEL_FLASHCLK_POS) 1844 #define CSC_CLKSEL_UART0CLK_POS (1) 1845 #define CSC_CLKSEL_UART0CLK_BIT (0x01UL << CSC_CLKSEL_UART0CLK_POS) 1846 #define CSC_CLKSEL_UART1CLK_POS (2) 1847 #define CSC_CLKSEL_UART1CLK_BIT (0x01UL << CSC_CLKSEL_UART1CLK_POS) 1848 #define CSC_CLKSEL_UART2CLK_POS (3) 1849 #define CSC_CLKSEL_UART2CLK_BIT (0x01UL << CSC_CLKSEL_UART2CLK_POS) 1850 #define CSC_CLKSEL_CAMERAREFCLK_POS (4) 1851 #define CSC_CLKSEL_CAMERAREFCLK_BIT (0x01UL << CSC_CLKSEL_CAMERAREFCLK_POS) 1852 #define CSC_CLKSEL_ASDMACLK_POS (5) 1853 #define CSC_CLKSEL_ASDMACLK_BIT (0x01UL << CSC_CLKSEL_ASDMACLK_POS) 1854 cpusysctrl_flash_clk_getb(void)1855__STATIC_INLINE uint8_t cpusysctrl_flash_clk_getb(void) 1856 { 1857 return (CS_CPUSYSCTRL->CLKSEL & CSC_CLKSEL_FLASHCLK_BIT) >> CSC_CLKSEL_FLASHCLK_POS; 1858 } 1859 cpusysctrl_flash_clk_setb(void)1860__STATIC_INLINE void cpusysctrl_flash_clk_setb(void) 1861 { 1862 CS_CPUSYSCTRL->CLKSEL |= CSC_CLKSEL_FLASHCLK_BIT; 1863 } 1864 cpusysctrl_flash_clk_clrb(void)1865__STATIC_INLINE void cpusysctrl_flash_clk_clrb(void) 1866 { 1867 CS_CPUSYSCTRL->CLKSEL &= ~CSC_CLKSEL_FLASHCLK_BIT; 1868 } 1869 cpusysctrl_uart0_clk_getb(void)1870__STATIC_INLINE uint8_t cpusysctrl_uart0_clk_getb(void) 1871 { 1872 return (CS_CPUSYSCTRL->CLKSEL & CSC_CLKSEL_UART0CLK_BIT) >> CSC_CLKSEL_UART0CLK_POS; 1873 } 1874 cpusysctrl_uart0_clk_setb(void)1875__STATIC_INLINE void cpusysctrl_uart0_clk_setb(void) 1876 { 1877 CS_CPUSYSCTRL->CLKSEL |= CSC_CLKSEL_UART0CLK_BIT; 1878 } 1879 cpusysctrl_uart0_clk_clrb(void)1880__STATIC_INLINE void cpusysctrl_uart0_clk_clrb(void) 1881 { 1882 CS_CPUSYSCTRL->CLKSEL &= ~CSC_CLKSEL_UART0CLK_BIT; 1883 } 1884 cpusysctrl_uart1_clk_getb(void)1885__STATIC_INLINE uint8_t cpusysctrl_uart1_clk_getb(void) 1886 { 1887 return (CS_CPUSYSCTRL->CLKSEL & CSC_CLKSEL_UART1CLK_BIT) >> CSC_CLKSEL_UART1CLK_POS; 1888 } 1889 cpusysctrl_uart1_clk_setb(void)1890__STATIC_INLINE void cpusysctrl_uart1_clk_setb(void) 1891 { 1892 CS_CPUSYSCTRL->CLKSEL |= CSC_CLKSEL_UART1CLK_BIT; 1893 } 1894 cpusysctrl_uart1_clk_clrb(void)1895__STATIC_INLINE void cpusysctrl_uart1_clk_clrb(void) 1896 { 1897 CS_CPUSYSCTRL->CLKSEL &= ~CSC_CLKSEL_UART1CLK_BIT; 1898 } 1899 cpusysctrl_uart2_clk_getb(void)1900__STATIC_INLINE uint8_t cpusysctrl_uart2_clk_getb(void) 1901 { 1902 return (CS_CPUSYSCTRL->CLKSEL & CSC_CLKSEL_UART2CLK_BIT) >> CSC_CLKSEL_UART2CLK_POS; 1903 } 1904 cpusysctrl_uart2_clk_setb(void)1905__STATIC_INLINE void cpusysctrl_uart2_clk_setb(void) 1906 { 1907 CS_CPUSYSCTRL->CLKSEL |= CSC_CLKSEL_UART2CLK_BIT; 1908 } 1909 cpusysctrl_uart2_clk_clrb(void)1910__STATIC_INLINE void cpusysctrl_uart2_clk_clrb(void) 1911 { 1912 CS_CPUSYSCTRL->CLKSEL &= ~CSC_CLKSEL_UART2CLK_BIT; 1913 } 1914 cpusysctrl_uart_clk_getb(int idx)1915__STATIC_INLINE uint8_t cpusysctrl_uart_clk_getb(int idx) 1916 { 1917 return (CS_CPUSYSCTRL->CLKSEL >> (CSC_CLKSEL_UART0CLK_POS + idx)) & 0x01U; 1918 } 1919 cpusysctrl_cameraref_clk_getb(void)1920__STATIC_INLINE uint8_t cpusysctrl_cameraref_clk_getb(void) 1921 { 1922 return (CS_CPUSYSCTRL->CLKSEL & CSC_CLKSEL_CAMERAREFCLK_BIT) >> CSC_CLKSEL_CAMERAREFCLK_POS; 1923 } 1924 cpusysctrl_cameraref_clk_setb(void)1925__STATIC_INLINE void cpusysctrl_cameraref_clk_setb(void) 1926 { 1927 CS_CPUSYSCTRL->CLKSEL |= CSC_CLKSEL_CAMERAREFCLK_BIT; 1928 } 1929 cpusysctrl_cameraref_clk_clrb(void)1930__STATIC_INLINE void cpusysctrl_cameraref_clk_clrb(void) 1931 { 1932 CS_CPUSYSCTRL->CLKSEL &= ~CSC_CLKSEL_CAMERAREFCLK_BIT; 1933 } 1934 cpusysctrl_asdma_clk_getb(void)1935__STATIC_INLINE uint8_t cpusysctrl_asdma_clk_getb(void) 1936 { 1937 return (CS_CPUSYSCTRL->CLKSEL & CSC_CLKSEL_ASDMACLK_BIT) >> CSC_CLKSEL_ASDMACLK_POS; 1938 } 1939 cpusysctrl_asdma_clk_setb(void)1940__STATIC_INLINE void cpusysctrl_asdma_clk_setb(void) 1941 { 1942 CS_CPUSYSCTRL->CLKSEL |= CSC_CLKSEL_ASDMACLK_BIT; 1943 } 1944 cpusysctrl_asdma_clk_clrb(void)1945__STATIC_INLINE void cpusysctrl_asdma_clk_clrb(void) 1946 { 1947 CS_CPUSYSCTRL->CLKSEL &= ~CSC_CLKSEL_ASDMACLK_BIT; 1948 } 1949 1950 /** 1951 * Address Offset: 0x008 1952 * Register Name : CSC HCLK_CTRL_MODE 1953 */ 1954 1955 #define CSC_HCLKCM_CPUP_MANUAL_POS (0) 1956 #define CSC_HCLKCM_CPUP_MANUAL_BIT (0x01UL << CSC_HCLKCM_CPUP_MANUAL_POS) 1957 #define CSC_HCLKCM_CPUP_GATED_MANUAL_POS (1) 1958 #define CSC_HCLKCM_CPUP_GATED_MANUAL_BIT (0x01UL << CSC_HCLKCM_CPUP_GATED_MANUAL_POS) 1959 #define CSC_HCLKCM_CPUS_MANUAL_POS (2) 1960 #define CSC_HCLKCM_CPUS_MANUAL_BIT (0x01UL << CSC_HCLKCM_CPUS_MANUAL_POS) 1961 #define CSC_HCLKCM_CPUS_GATED_MANUAL_POS (3) 1962 #define CSC_HCLKCM_CPUS_GATED_MANUAL_BIT (0x01UL << CSC_HCLKCM_CPUS_GATED_MANUAL_POS) 1963 #define CSC_HCLKCM_ROM_MANUAL_POS (4) 1964 #define CSC_HCLKCM_ROM_MANUAL_BIT (0x01UL << CSC_HCLKCM_ROM_MANUAL_POS) 1965 #define CSC_HCLKCM_RAM0_MANUAL_POS (5) 1966 #define CSC_HCLKCM_RAM0_MANUAL_BIT (0x01UL << CSC_HCLKCM_RAM0_MANUAL_POS) 1967 #define CSC_HCLKCM_RAM1_MANUAL_POS (6) 1968 #define CSC_HCLKCM_RAM1_MANUAL_BIT (0x01UL << CSC_HCLKCM_RAM1_MANUAL_POS) 1969 #define CSC_HCLKCM_RAM2_MANUAL_POS (7) 1970 #define CSC_HCLKCM_RAM2_MANUAL_BIT (0x01UL << CSC_HCLKCM_RAM2_MANUAL_POS) 1971 #define CSC_HCLKCM_RAM3_MANUAL_POS (8) 1972 #define CSC_HCLKCM_RAM3_MANUAL_BIT (0x01UL << CSC_HCLKCM_RAM3_MANUAL_POS) 1973 #define CSC_HCLKCM_RAM4_MANUAL_POS (9) 1974 #define CSC_HCLKCM_RAM4_MANUAL_BIT (0x01UL << CSC_HCLKCM_RAM4_MANUAL_POS) 1975 #define CSC_HCLKCM_SYS_MATRIX_MANUAL_POS (10) 1976 #define CSC_HCLKCM_SYS_MATRIX_MANUAL_BIT (0x01UL << CSC_HCLKCM_SYS_MATRIX_MANUAL_POS) 1977 #define CSC_HCLKCM_AHB0_MANUAL_POS (11) 1978 #define CSC_HCLKCM_AHB0_MANUAL_BIT (0x01UL << CSC_HCLKCM_AHB0_MANUAL_POS) 1979 #define CSC_HCLKCM_AHB1_MANUAL_POS (12) 1980 #define CSC_HCLKCM_AHB1_MANUAL_BIT (0x01UL << CSC_HCLKCM_AHB1_MANUAL_POS) 1981 #define CSC_HCLKCM_APB0_MANUAL_POS (13) 1982 #define CSC_HCLKCM_APB0_MANUAL_BIT (0x01UL << CSC_HCLKCM_APB0_MANUAL_POS) 1983 #define CSC_HCLKCM_EXMEM_BUS_MANUAL_POS (14) 1984 #define CSC_HCLKCM_EXMEM_BUS_MANUAL_BIT (0x01UL << CSC_HCLKCM_EXMEM_BUS_MANUAL_POS) 1985 #define CSC_HCLKCM_CACHE0_MANUAL_POS (15) 1986 #define CSC_HCLKCM_CACHE0_MANUAL_BIT (0x01UL << CSC_HCLKCM_CACHE0_MANUAL_POS) 1987 #define CSC_HCLKCM_CACHE1_MANUAL_POS (16) 1988 #define CSC_HCLKCM_CACHE1_MANUAL_BIT (0x01UL << CSC_HCLKCM_CACHE1_MANUAL_POS) 1989 #define CSC_HCLKCM_DMA_MANUAL_POS (17) 1990 #define CSC_HCLKCM_DMA_MANUAL_BIT (0x01UL << CSC_HCLKCM_DMA_MANUAL_POS) 1991 #define CSC_HCLKCM_FLASH_MANUAL_POS (18) 1992 #define CSC_HCLKCM_FLASH_MANUAL_BIT (0x01UL << CSC_HCLKCM_FLASH_MANUAL_POS) 1993 #define CSC_HCLKCM_PSRAM_ALWAYS_MANUAL_POS (19) 1994 #define CSC_HCLKCM_PSRAM_ALWAYS_MANUAL_BIT (0x01UL << CSC_HCLKCM_PSRAM_ALWAYS_MANUAL_POS) 1995 #define CSC_HCLKCM_PSRAM_MANUAL_POS (20) 1996 #define CSC_HCLKCM_PSRAM_MANUAL_BIT (0x01UL << CSC_HCLKCM_PSRAM_MANUAL_POS) 1997 #define CSC_HCLKCM_PSRAM_REG_MANUAL_POS (21) 1998 #define CSC_HCLKCM_PSRAM_REG_MANUAL_BIT (0x01UL << CSC_HCLKCM_PSRAM_REG_MANUAL_POS) 1999 #define CSC_HCLKCM_TRAP_MANUAL_POS (22) 2000 #define CSC_HCLKCM_TRAP_MANUAL_BIT (0x01UL << CSC_HCLKCM_TRAP_MANUAL_POS) 2001 #define CSC_HCLKCM_UART0_MANUAL_POS (23) 2002 #define CSC_HCLKCM_UART0_MANUAL_BIT (0x01UL << CSC_HCLKCM_UART0_MANUAL_POS) 2003 #define CSC_HCLKCM_UART1_MANUAL_POS (24) 2004 #define CSC_HCLKCM_UART1_MANUAL_BIT (0x01UL << CSC_HCLKCM_UART1_MANUAL_POS) 2005 #define CSC_HCLKCM_UART2_MANUAL_POS (25) 2006 #define CSC_HCLKCM_UART2_MANUAL_BIT (0x01UL << CSC_HCLKCM_UART2_MANUAL_POS) 2007 #define CSC_HCLKCM_USBC_MANUAL_POS (26) 2008 #define CSC_HCLKCM_USBC_MANUAL_BIT (0x01UL << CSC_HCLKCM_USBC_MANUAL_POS) 2009 #define CSC_HCLKCM_VPC_MANUAL_POS (27) 2010 #define CSC_HCLKCM_VPC_MANUAL_BIT (0x01UL << CSC_HCLKCM_VPC_MANUAL_POS) 2011 #define CSC_HCLKCM_MAILBOX_MANUAL_POS (28) 2012 #define CSC_HCLKCM_MAILBOX_MANUAL_BIT (0x01UL << CSC_HCLKCM_MAILBOX_MANUAL_POS) 2013 #define CSC_HCLKCM_ASDMA_MANUAL_POS (29) 2014 #define CSC_HCLKCM_ASDMA_MANUAL_BIT (0x01UL << CSC_HCLKCM_ASDMA_MANUAL_POS) 2015 #define CSC_HCLKCM_SDIO_MANUAL_POS (30) 2016 #define CSC_HCLKCM_SDIO_MANUAL_BIT (0x01UL << CSC_HCLKCM_SDIO_MANUAL_POS) 2017 #define CSC_HCLKCM_RAM5_MANUAL_POS (31) 2018 #define CSC_HCLKCM_RAM5_MANUAL_BIT (0x01UL << CSC_HCLKCM_RAM5_MANUAL_POS) 2019 cpusysctrl_hclkcm_get()2020__STATIC_INLINE uint32_t cpusysctrl_hclkcm_get() 2021 { 2022 return CS_CPUSYSCTRL->HCLKCM; 2023 } 2024 cpusysctrl_hclkcm_set(uint32_t manual_mode)2025__STATIC_INLINE void cpusysctrl_hclkcm_set(uint32_t manual_mode) 2026 { 2027 CS_CPUSYSCTRL->HCLKCM = manual_mode; 2028 } 2029 2030 /** 2031 * Address Offset: 0x00C 2032 * Register Name : CSC PCLK_CTRL_MODE 2033 */ 2034 2035 #define CSC_PCLKCM_CPU_SYSCTRL_MANUAL_POS (0) 2036 #define CSC_PCLKCM_CPU_SYSCTRL_MANUAL_BIT (0x01UL << CSC_PCLKCM_CPU_SYSCTRL_MANUAL_POS) 2037 #define CSC_PCLKCM_WDG0_MANUAL_POS (1) 2038 #define CSC_PCLKCM_WDG0_MANUAL_BIT (0x01UL << CSC_PCLKCM_WDG0_MANUAL_POS) 2039 #define CSC_PCLKCM_WDG1_MANUAL_POS (2) 2040 #define CSC_PCLKCM_WDG1_MANUAL_BIT (0x01UL << CSC_PCLKCM_WDG1_MANUAL_POS) 2041 #define CSC_PCLKCM_WDG2_MANUAL_POS (3) 2042 #define CSC_PCLKCM_WDG2_MANUAL_BIT (0x01UL << CSC_PCLKCM_WDG2_MANUAL_POS) 2043 #define CSC_PCLKCM_TIMER0_MANUAL_POS (4) 2044 #define CSC_PCLKCM_TIMER0_MANUAL_BIT (0x01UL << CSC_PCLKCM_TIMER0_MANUAL_POS) 2045 #define CSC_PCLKCM_TIMER1_MANUAL_POS (5) 2046 #define CSC_PCLKCM_TIMER1_MANUAL_BIT (0x01UL << CSC_PCLKCM_TIMER1_MANUAL_POS) 2047 #define CSC_PCLKCM_SPINLOCK_MANUAL_POS (6) 2048 #define CSC_PCLKCM_SPINLOCK_MANUAL_BIT (0x01UL << CSC_PCLKCM_SPINLOCK_MANUAL_POS) 2049 #define CSC_PCLKCM_SPI_MANUAL_POS (7) 2050 #define CSC_PCLKCM_SPI_MANUAL_BIT (0x01UL << CSC_PCLKCM_SPI_MANUAL_POS) 2051 #define CSC_PCLKCM_PWM_MANUAL_POS (8) 2052 #define CSC_PCLKCM_PWM_MANUAL_BIT (0x01UL << CSC_PCLKCM_PWM_MANUAL_POS) 2053 #define CSC_PCLKCM_I2CM_MANUAL_POS (9) 2054 #define CSC_PCLKCM_I2CM_MANUAL_BIT (0x01UL << CSC_PCLKCM_I2CM_MANUAL_POS) 2055 #define CSC_PCLKCM_JPEG_ENC_MANUAL_POS (10) 2056 #define CSC_PCLKCM_JPEG_ENC_MANUAL_BIT (0x01UL << CSC_PCLKCM_JPEG_ENC_MANUAL_POS) 2057 #define CSC_PCLKCM_TRNG_MANUAL_POS (11) 2058 #define CSC_PCLKCM_TRNG_MANUAL_BIT (0x01UL << CSC_PCLKCM_TRNG_MANUAL_POS) 2059 #define CSC_PCLKCM_WDG3_MANUAL_POS (12) 2060 #define CSC_PCLKCM_WDG3_MANUAL_BIT (0x01UL << CSC_PCLKCM_WDG3_MANUAL_POS) 2061 #define CSC_PCLKCM_ANALOG_REG0_MANUAL_POS (13) 2062 #define CSC_PCLKCM_ANALOG_REG0_MANUAL_BIT (0x01UL << CSC_PCLKCM_ANALOG_REG0_MANUAL_POS) 2063 #define CSC_PCLKCM_PROCESS_MON_MANUAL_POS (14) 2064 #define CSC_PCLKCM_PROCESS_MON_MANUAL_BIT (0x01UL << CSC_PCLKCM_PROCESS_MON_MANUAL_POS) 2065 cpusysctrl_pclkcm_get()2066__STATIC_INLINE uint32_t cpusysctrl_pclkcm_get() 2067 { 2068 return CS_CPUSYSCTRL->PCLKCM; 2069 } 2070 cpusysctrl_pclkcm_set(uint32_t manual_mode)2071__STATIC_INLINE void cpusysctrl_pclkcm_set(uint32_t manual_mode) 2072 { 2073 CS_CPUSYSCTRL->PCLKCM = manual_mode; 2074 } 2075 2076 /** 2077 * Address Offset: 0x010 2078 * Register Name : CSC OCLK_CTRL_MODE 2079 */ 2080 2081 #define CSC_OCLKCM_OPI_2X_ALWAYS_MANUAL_POS (0) 2082 #define CSC_OCLKCM_OPI_2X_ALWAYS_MANUAL_BIT (0x01UL << CSC_OCLKCM_OPI_2X_ALWAYS_MANUAL_POS) 2083 #define CSC_OCLKCM_OPI_2X_MANUAL_POS (1) 2084 #define CSC_OCLKCM_OPI_2X_MANUAL_BIT (0x01UL << CSC_OCLKCM_OPI_2X_MANUAL_POS) 2085 #define CSC_OCLKCM_SDMMC_MANUAL_POS (2) 2086 #define CSC_OCLKCM_SDMMC_MANUAL_BIT (0x01UL << CSC_OCLKCM_SDMMC_MANUAL_POS) 2087 #define CSC_OCLKCM_ASDMA_MANUAL_POS (3) 2088 #define CSC_OCLKCM_ASDMA_MANUAL_BIT (0x01UL << CSC_OCLKCM_ASDMA_MANUAL_POS) 2089 #define CSC_OCLKCM_FLASH_MANUAL_POS (4) 2090 #define CSC_OCLKCM_FLASH_MANUAL_BIT (0x01UL << CSC_OCLKCM_FLASH_MANUAL_POS) 2091 #define CSC_OCLKCM_TIMER00_MANUAL_POS (5) 2092 #define CSC_OCLKCM_TIMER00_MANUAL_BIT (0x01UL << CSC_OCLKCM_TIMER00_MANUAL_POS) 2093 #define CSC_OCLKCM_TIMER01_MANUAL_POS (6) 2094 #define CSC_OCLKCM_TIMER01_MANUAL_BIT (0x01UL << CSC_OCLKCM_TIMER01_MANUAL_POS) 2095 #define CSC_OCLKCM_TIMER10_MANUAL_POS (7) 2096 #define CSC_OCLKCM_TIMER10_MANUAL_BIT (0x01UL << CSC_OCLKCM_TIMER10_MANUAL_POS) 2097 #define CSC_OCLKCM_TIMER11_MANUAL_POS (8) 2098 #define CSC_OCLKCM_TIMER11_MANUAL_BIT (0x01UL << CSC_OCLKCM_TIMER11_MANUAL_POS) 2099 #define CSC_OCLKCM_SPI_MANUAL_POS (9) 2100 #define CSC_OCLKCM_SPI_MANUAL_BIT (0x01UL << CSC_OCLKCM_SPI_MANUAL_POS) 2101 #define CSC_OCLKCM_UART0_MANUAL_POS (10) 2102 #define CSC_OCLKCM_UART0_MANUAL_BIT (0x01UL << CSC_OCLKCM_UART0_MANUAL_POS) 2103 #define CSC_OCLKCM_UART1_MANUAL_POS (11) 2104 #define CSC_OCLKCM_UART1_MANUAL_BIT (0x01UL << CSC_OCLKCM_UART1_MANUAL_POS) 2105 #define CSC_OCLKCM_UART2_MANUAL_POS (12) 2106 #define CSC_OCLKCM_UART2_MANUAL_BIT (0x01UL << CSC_OCLKCM_UART2_MANUAL_POS) 2107 #define CSC_OCLKCM_ULPI_MANUAL_POS (13) 2108 #define CSC_OCLKCM_ULPI_MANUAL_BIT (0x01UL << CSC_OCLKCM_ULPI_MANUAL_POS) 2109 #define CSC_OCLKCM_SDIO_MANUAL_POS (14) 2110 #define CSC_OCLKCM_SDIO_MANUAL_BIT (0x01UL << CSC_OCLKCM_SDIO_MANUAL_POS) 2111 #define CSC_OCLKCM_PWM_MANUAL_POS (15) 2112 #define CSC_OCLKCM_PWM_MANUAL_BIT (0x01UL << CSC_OCLKCM_PWM_MANUAL_POS) 2113 #define CSC_OCLKCM_TIMER02_MANUAL_POS (16) 2114 #define CSC_OCLKCM_TIMER02_MANUAL_BIT (0x01UL << CSC_OCLKCM_TIMER02_MANUAL_POS) 2115 #define CSC_OCLKCM_TIMER12_MANUAL_POS (17) 2116 #define CSC_OCLKCM_TIMER12_MANUAL_BIT (0x01UL << CSC_OCLKCM_TIMER12_MANUAL_POS) 2117 #define CSC_OCLKCM_RTC_ALWAYS_MANUAL_POS (18) 2118 #define CSC_OCLKCM_RTC_ALWAYS_MANUAL_BIT (0x01UL << CSC_OCLKCM_RTC_ALWAYS_MANUAL_POS) 2119 #define CSC_OCLKCM_RTC_WDG0_MANUAL_POS (19) 2120 #define CSC_OCLKCM_RTC_WDG0_MANUAL_BIT (0x01UL << CSC_OCLKCM_RTC_WDG0_MANUAL_POS) 2121 #define CSC_OCLKCM_RTC_WDG1_MANUAL_POS (20) 2122 #define CSC_OCLKCM_RTC_WDG1_MANUAL_BIT (0x01UL << CSC_OCLKCM_RTC_WDG1_MANUAL_POS) 2123 #define CSC_OCLKCM_RTC_WDG2_MANUAL_POS (21) 2124 #define CSC_OCLKCM_RTC_WDG2_MANUAL_BIT (0x01UL << CSC_OCLKCM_RTC_WDG2_MANUAL_POS) 2125 #define CSC_OCLKCM_DDR_2X_MANUAL_POS (22) 2126 #define CSC_OCLKCM_DDR_2X_MANUAL_BIT (0x01UL << CSC_OCLKCM_DDR_2X_MANUAL_POS) 2127 #define CSC_OCLKCM_DDR_2X_ALWAYS_MANUAL_POS (23) 2128 #define CSC_OCLKCM_DDR_2X_ALWAYS_MANUAL_BIT (0x01UL << CSC_OCLKCM_DDR_2X_ALWAYS_MANUAL_POS) 2129 #define CSC_OCLKCM_CAMERA_REF_MANUAL_POS (24) 2130 #define CSC_OCLKCM_CAMERA_REF_MANUAL_BIT (0x01UL << CSC_OCLKCM_CAMERA_REF_MANUAL_POS) 2131 #define CSC_OCLKCM_AUDIO_PROC_MANUAL_POS (25) 2132 #define CSC_OCLKCM_AUDIO_PROC_MANUAL_BIT (0x01UL << CSC_OCLKCM_AUDIO_PROC_MANUAL_POS) 2133 #define CSC_OCLKCM_PROCESS_MON_MANUAL_POS (26) 2134 #define CSC_OCLKCM_PROCESS_MON_MANUAL_BIT (0x01UL << CSC_OCLKCM_PROCESS_MON_MANUAL_POS) 2135 #define CSC_OCLKCM_RTC_WDG3_MANUAL_POS (27) 2136 #define CSC_OCLKCM_RTC_WDG3_MANUAL_BIT (0x01UL << CSC_OCLKCM_RTC_WDG3_MANUAL_POS) 2137 #define CSC_OCLKCM_26M_ASDMA_MANUAL_POS (28) 2138 #define CSC_OCLKCM_26M_ASDMA_MANUAL_BIT (0x01UL << CSC_OCLKCM_26M_ASDMA_MANUAL_POS) 2139 #define CSC_OCLKCM_BCK0_MANUAL_POS (29) 2140 #define CSC_OCLKCM_BCK0_MANUAL_BIT (0x01UL << CSC_OCLKCM_BCK0_MANUAL_POS) 2141 #define CSC_OCLKCM_BCK1_MANUAL_POS (30) 2142 #define CSC_OCLKCM_BCK1_MANUAL_BIT (0x01UL << CSC_OCLKCM_BCK1_MANUAL_POS) 2143 #define CSC_OCLKCM_SPDIF_MANUAL_POS (31) 2144 #define CSC_OCLKCM_SPDIF_MANUAL_BIT (0x01UL << CSC_OCLKCM_SPDIF_MANUAL_POS) 2145 cpusysctrl_oclkcm_get()2146__STATIC_INLINE uint32_t cpusysctrl_oclkcm_get() 2147 { 2148 return CS_CPUSYSCTRL->OCLKCM; 2149 } 2150 cpusysctrl_oclkcm_set(uint32_t manual_mode)2151__STATIC_INLINE void cpusysctrl_oclkcm_set(uint32_t manual_mode) 2152 { 2153 CS_CPUSYSCTRL->OCLKCM = manual_mode; 2154 } 2155 2156 /** 2157 * Address Offset: 0x05C 2158 * Register Name : CSC CACHE_BYPASS 2159 */ 2160 2161 #define CSC_CACHEBP_BURST_INCR_ONLY_EN_POS (2) 2162 #define CSC_CACHEBP_BURST_INCR_ONLY_EN_BIT (0x01UL << CSC_CACHEBP_BURST_INCR_ONLY_EN_POS) 2163 cpusysctrl_cachebp_burst_incr_only_en_getb(void)2164__STATIC_INLINE uint8_t cpusysctrl_cachebp_burst_incr_only_en_getb(void) 2165 { 2166 return (CS_CPUSYSCTRL->CACHEBP & CSC_CACHEBP_BURST_INCR_ONLY_EN_BIT) >> CSC_CACHEBP_BURST_INCR_ONLY_EN_POS; 2167 } 2168 cpusysctrl_cachebp_burst_incr_only_en_setb(void)2169__STATIC_INLINE void cpusysctrl_cachebp_burst_incr_only_en_setb(void) 2170 { 2171 CS_CPUSYSCTRL->CACHEBP |= CSC_CACHEBP_BURST_INCR_ONLY_EN_BIT; 2172 } 2173 cpusysctrl_cachebp_burst_incr_only_en_clrb(void)2174__STATIC_INLINE void cpusysctrl_cachebp_burst_incr_only_en_clrb(void) 2175 { 2176 CS_CPUSYSCTRL->CACHEBP &= ~CSC_CACHEBP_BURST_INCR_ONLY_EN_BIT; 2177 } 2178 2179 /** 2180 * Address Offset: 0x060 2181 * Register Name : CSC HCLK1_CTRL_MODE 2182 */ 2183 2184 #define CSC_HCLK1CM_DSP_MANUAL_POS (0) 2185 #define CSC_HCLK1CM_DSP_MANUAL_BIT (0x01UL << CSC_HCLK1CM_DSP_MANUAL_POS) 2186 #define CSC_HCLK1CM_DSP_GATED_MANUAL_POS (1) 2187 #define CSC_HCLK1CM_DSP_GATED_MANUAL_BIT (0x01UL << CSC_HCLK1CM_DSP_GATED_MANUAL_POS) 2188 #define CSC_HCLK1CM_CAMERA_MANUAL_POS (2) 2189 #define CSC_HCLK1CM_CAMERA_MANUAL_BIT (0x01UL << CSC_HCLK1CM_CAMERA_MANUAL_POS) 2190 #define CSC_HCLK1CM_SPI_CAMERA_MANUAL_POS (3) 2191 #define CSC_HCLK1CM_SPI_CAMERA_MANUAL_BIT (0x01UL << CSC_HCLK1CM_SPI_CAMERA_MANUAL_POS) 2192 #define CSC_HCLK1CM_JPEG_ENC_MANUAL_POS (4) 2193 #define CSC_HCLK1CM_JPEG_ENC_MANUAL_BIT (0x01UL << CSC_HCLK1CM_JPEG_ENC_MANUAL_POS) 2194 #define CSC_HCLK1CM_BTROM_MANUAL_POS (5) 2195 #define CSC_HCLK1CM_BTROM_MANUAL_BIT (0x01UL << CSC_HCLK1CM_BTROM_MANUAL_POS) 2196 #define CSC_HCLK1CM_DSP_MATRIX_MANUAL_POS (6) 2197 #define CSC_HCLK1CM_DSP_MATRIX_MANUAL_BIT (0x01UL << CSC_HCLK1CM_DSP_MATRIX_MANUAL_POS) 2198 #define CSC_HCLK1CM_SRAM6_MANUAL_POS (7) 2199 #define CSC_HCLK1CM_SRAM6_MANUAL_BIT (0x01UL << CSC_HCLK1CM_SRAM6_MANUAL_POS) 2200 #define CSC_HCLK1CM_SDMMC_ALWAYS_MANUAL_POS (8) 2201 #define CSC_HCLK1CM_SDMMC_ALWAYS_MANUAL_BIT (0x01UL << CSC_HCLK1CM_SDMMC_ALWAYS_MANUAL_POS) 2202 #define CSC_HCLK1CM_SDMMC_MANUAL_POS (9) 2203 #define CSC_HCLK1CM_SDMMC_MANUAL_BIT (0x01UL << CSC_HCLK1CM_SDMMC_MANUAL_POS) 2204 #define CSC_HCLK1CM_CPUSB_MANUAL_POS (10) 2205 #define CSC_HCLK1CM_CPUSB_MANUAL_BIT (0x01UL << CSC_HCLK1CM_CPUSB_MANUAL_POS) 2206 #define CSC_HCLK1CM_CPUSB_GATED_MANUAL_POS (11) 2207 #define CSC_HCLK1CM_CPUSB_GATED_MANUAL_BIT (0x01UL << CSC_HCLK1CM_CPUSB_GATED_MANUAL_POS) 2208 #define CSC_HCLK1CM_SRAM5_LOW_MANUAL_POS (12) 2209 #define CSC_HCLK1CM_SRAM5_LOW_MANUAL_BIT (0x01UL << CSC_HCLK1CM_SRAM5_LOW_MANUAL_POS) 2210 #define CSC_HCLK1CM_SRAM5_HIGH_MANUAL_POS (13) 2211 #define CSC_HCLK1CM_SRAM5_HIGH_MANUAL_BIT (0x01UL << CSC_HCLK1CM_SRAM5_HIGH_MANUAL_POS) 2212 #define CSC_HCLK1CM_MM_MANUAL_POS (14) 2213 #define CSC_HCLK1CM_MM_MANUAL_BIT (0x01UL << CSC_HCLK1CM_MM_MANUAL_POS) 2214 cpusysctrl_hclk1cm_get()2215__STATIC_INLINE uint32_t cpusysctrl_hclk1cm_get() 2216 { 2217 return CS_CPUSYSCTRL->HCLK1CM; 2218 } 2219 cpusysctrl_hclk1cm_set(uint32_t manual_mode)2220__STATIC_INLINE void cpusysctrl_hclk1cm_set(uint32_t manual_mode) 2221 { 2222 CS_CPUSYSCTRL->HCLK1CM = manual_mode; 2223 } 2224 2225 /** 2226 * Address Offset: 0x07C 2227 * Register Name : CSC PSRAM_MODE_SEL 2228 */ 2229 2230 #define CSC_PSRMDSEL_UHSMD_POS (0) 2231 #define CSC_PSRMDSEL_UHSMD_BIT (0x01UL << CSC_PSRMDSEL_UHSMD_POS) 2232 cpusysctrl_psrmdsel_uhsmd_getb(void)2233__STATIC_INLINE uint8_t cpusysctrl_psrmdsel_uhsmd_getb(void) 2234 { 2235 return (CS_CPUSYSCTRL->PSRMDSEL & CSC_PSRMDSEL_UHSMD_BIT) >> CSC_PSRMDSEL_UHSMD_POS; 2236 } 2237 cpusysctrl_psrmdsel_uhsmd_setb(void)2238__STATIC_INLINE void cpusysctrl_psrmdsel_uhsmd_setb(void) 2239 { 2240 CS_CPUSYSCTRL->PSRMDSEL |= CSC_PSRMDSEL_UHSMD_BIT; 2241 } 2242 cpusysctrl_psrmdsel_uhsmd_clrb(void)2243__STATIC_INLINE void cpusysctrl_psrmdsel_uhsmd_clrb(void) 2244 { 2245 CS_CPUSYSCTRL->PSRMDSEL &= ~CSC_PSRMDSEL_UHSMD_BIT; 2246 } 2247 2248 /** 2249 * Address Offset: 0x084 2250 * Register Name : CSC PCLK_DIV 2251 */ 2252 2253 #define CSC_PCLKDIV_DENOM_LSB (0) 2254 #define CSC_PCLKDIV_DENOM_WIDTH (8) 2255 #define CSC_PCLKDIV_DENOM_MASK (((0x01UL << CSC_PCLKDIV_DENOM_WIDTH) - 1) << CSC_PCLKDIV_DENOM_LSB) 2256 #define CSC_PCLKDIV_UPDATE_POS (8) 2257 #define CSC_PCLKDIV_UPDATE_BIT (0x01UL << CSC_PCLKDIV_UPDATE_POS) 2258 cpusysctrl_pclkdiv_denom_getf(void)2259__STATIC_INLINE uint8_t cpusysctrl_pclkdiv_denom_getf(void) 2260 { 2261 return ((CS_CPUSYSCTRL->PCLKDIV & CSC_PCLKDIV_DENOM_MASK) >> CSC_PCLKDIV_DENOM_LSB); 2262 } 2263 cpusysctrl_pclkdiv_denom_setf(uint8_t div_denom)2264__STATIC_INLINE void cpusysctrl_pclkdiv_denom_setf(uint8_t div_denom) 2265 { 2266 uint32_t local_val = CS_CPUSYSCTRL->PCLKDIV & ~CSC_PCLKDIV_DENOM_MASK; 2267 CS_CPUSYSCTRL->PCLKDIV = local_val | ((div_denom << CSC_PCLKDIV_DENOM_LSB) & CSC_PCLKDIV_DENOM_MASK) | CSC_PCLKDIV_UPDATE_BIT; 2268 } 2269 2270 /** 2271 * Address Offset: 0x090 2272 * Register Name : CSC ULPI_CLK_DETECT 2273 */ 2274 2275 #define CSC_ULPICD_CLKDETTH_LSB (0) 2276 #define CSC_ULPICD_CLKDETTH_WIDTH (8) 2277 #define CSC_ULPICD_CLKDETTH_MASK (((0x01UL << CSC_ULPICD_CLKDETTH_WIDTH) - 1) << CSC_ULPICD_CLKDETTH_LSB) 2278 #define CSC_ULPICD_CLKDETEN_POS (8) 2279 #define CSC_ULPICD_CLKDETEN_BIT (0x01UL << CSC_ULPICD_CLKDETEN_POS) 2280 cpusysctrl_ulpicd_clkdetth_getf(void)2281__STATIC_INLINE uint8_t cpusysctrl_ulpicd_clkdetth_getf(void) 2282 { 2283 return ((CS_CPUSYSCTRL->ULPICD & CSC_ULPICD_CLKDETTH_MASK) >> CSC_ULPICD_CLKDETTH_LSB); 2284 } 2285 cpusysctrl_ulpicd_clkdetth_setf(uint8_t clkdet_th)2286__STATIC_INLINE void cpusysctrl_ulpicd_clkdetth_setf(uint8_t clkdet_th) 2287 { 2288 uint32_t local_val = CS_CPUSYSCTRL->ULPICD & ~CSC_ULPICD_CLKDETTH_MASK; 2289 CS_CPUSYSCTRL->ULPICD = local_val | ((clkdet_th << CSC_ULPICD_CLKDETTH_LSB) & CSC_ULPICD_CLKDETTH_MASK) | CSC_ULPICD_CLKDETEN_BIT; 2290 } 2291 2292 /** 2293 * Address Offset: 0x094 2294 * Register Name : CSC ULPI_CLK_STATUS 2295 */ 2296 2297 #define CSC_ULPICS_CLKST_POS (0) 2298 #define CSC_ULPICS_CLKST_BIT (0x01UL << CSC_ULPICS_CLKST_POS) 2299 cpusysctrl_ulpics_get(void)2300__STATIC_INLINE uint32_t cpusysctrl_ulpics_get(void) 2301 { 2302 return CS_CPUSYSCTRL->ULPICS; 2303 } 2304 cpusysctrl_ulpics_clkst_getf(void)2305__STATIC_INLINE uint8_t cpusysctrl_ulpics_clkst_getf(void) 2306 { 2307 return ((CS_CPUSYSCTRL->ULPICS & CSC_ULPICS_CLKST_BIT) >> CSC_ULPICS_CLKST_POS); 2308 } 2309 2310 /** 2311 * Address Offset: 0x100 2312 * Register Name : CSC HCLK_MANUAL_ENABLE (write 1 valid) 2313 */ 2314 2315 #define CSC_HCLKME_CPUP_EN_POS (0) 2316 #define CSC_HCLKME_CPUP_EN_BIT (0x01UL << CSC_HCLKME_CPUP_EN_POS) 2317 #define CSC_HCLKME_CPUP_GATED_EN_POS (1) 2318 #define CSC_HCLKME_CPUP_GATED_EN_BIT (0x01UL << CSC_HCLKME_CPUP_GATED_EN_POS) 2319 #define CSC_HCLKME_CPUS_EN_POS (2) 2320 #define CSC_HCLKME_CPUS_EN_BIT (0x01UL << CSC_HCLKME_CPUS_EN_POS) 2321 #define CSC_HCLKME_CPUS_GATED_EN_POS (3) 2322 #define CSC_HCLKME_CPUS_GATED_EN_BIT (0x01UL << CSC_HCLKME_CPUS_GATED_EN_POS) 2323 #define CSC_HCLKME_ROM_EN_POS (4) 2324 #define CSC_HCLKME_ROM_EN_BIT (0x01UL << CSC_HCLKME_ROM_EN_POS) 2325 #define CSC_HCLKME_RAM0_EN_POS (5) 2326 #define CSC_HCLKME_RAM0_EN_BIT (0x01UL << CSC_HCLKME_RAM0_EN_POS) 2327 #define CSC_HCLKME_RAM1_EN_POS (6) 2328 #define CSC_HCLKME_RAM1_EN_BIT (0x01UL << CSC_HCLKME_RAM1_EN_POS) 2329 #define CSC_HCLKME_RAM2_EN_POS (7) 2330 #define CSC_HCLKME_RAM2_EN_BIT (0x01UL << CSC_HCLKME_RAM2_EN_POS) 2331 #define CSC_HCLKME_RAM3_EN_POS (8) 2332 #define CSC_HCLKME_RAM3_EN_BIT (0x01UL << CSC_HCLKME_RAM3_EN_POS) 2333 #define CSC_HCLKME_RAM4_EN_POS (9) 2334 #define CSC_HCLKME_RAM4_EN_BIT (0x01UL << CSC_HCLKME_RAM4_EN_POS) 2335 #define CSC_HCLKME_SYS_MATRIX_EN_POS (10) 2336 #define CSC_HCLKME_SYS_MATRIX_EN_BIT (0x01UL << CSC_HCLKME_SYS_MATRIX_EN_POS) 2337 #define CSC_HCLKME_AHB0_EN_POS (11) 2338 #define CSC_HCLKME_AHB0_EN_BIT (0x01UL << CSC_HCLKME_AHB0_EN_POS) 2339 #define CSC_HCLKME_AHB1_EN_POS (12) 2340 #define CSC_HCLKME_AHB1_EN_BIT (0x01UL << CSC_HCLKME_AHB1_EN_POS) 2341 #define CSC_HCLKME_APB0_EN_POS (13) 2342 #define CSC_HCLKME_APB0_EN_BIT (0x01UL << CSC_HCLKME_APB0_EN_POS) 2343 #define CSC_HCLKME_EXMEM_BUS_EN_POS (14) 2344 #define CSC_HCLKME_EXMEM_BUS_EN_BIT (0x01UL << CSC_HCLKME_EXMEM_BUS_EN_POS) 2345 #define CSC_HCLKME_CACHE0_EN_POS (15) 2346 #define CSC_HCLKME_CACHE0_EN_BIT (0x01UL << CSC_HCLKME_CACHE0_EN_POS) 2347 #define CSC_HCLKME_CACHE1_EN_POS (16) 2348 #define CSC_HCLKME_CACHE1_EN_BIT (0x01UL << CSC_HCLKME_CACHE1_EN_POS) 2349 #define CSC_HCLKME_DMA_EN_POS (17) 2350 #define CSC_HCLKME_DMA_EN_BIT (0x01UL << CSC_HCLKME_DMA_EN_POS) 2351 #define CSC_HCLKME_FLASH_EN_POS (18) 2352 #define CSC_HCLKME_FLASH_EN_BIT (0x01UL << CSC_HCLKME_FLASH_EN_POS) 2353 #define CSC_HCLKME_PSRAM_ALWAYS_EN_POS (19) 2354 #define CSC_HCLKME_PSRAM_ALWAYS_EN_BIT (0x01UL << CSC_HCLKME_PSRAM_ALWAYS_EN_POS) 2355 #define CSC_HCLKME_PSRAM_EN_POS (20) 2356 #define CSC_HCLKME_PSRAM_EN_BIT (0x01UL << CSC_HCLKME_PSRAM_EN_POS) 2357 #define CSC_HCLKME_PSRAM_REG_EN_POS (21) 2358 #define CSC_HCLKME_PSRAM_REG_EN_BIT (0x01UL << CSC_HCLKME_PSRAM_REG_EN_POS) 2359 #define CSC_HCLKME_TRAP_EN_POS (22) 2360 #define CSC_HCLKME_TRAP_EN_BIT (0x01UL << CSC_HCLKME_TRAP_EN_POS) 2361 #define CSC_HCLKME_UART0_EN_POS (23) 2362 #define CSC_HCLKME_UART0_EN_BIT (0x01UL << CSC_HCLKME_UART0_EN_POS) 2363 #define CSC_HCLKME_UART1_EN_POS (24) 2364 #define CSC_HCLKME_UART1_EN_BIT (0x01UL << CSC_HCLKME_UART1_EN_POS) 2365 #define CSC_HCLKME_UART2_EN_POS (25) 2366 #define CSC_HCLKME_UART2_EN_BIT (0x01UL << CSC_HCLKME_UART2_EN_POS) 2367 #define CSC_HCLKME_USBC_EN_POS (26) 2368 #define CSC_HCLKME_USBC_EN_BIT (0x01UL << CSC_HCLKME_USBC_EN_POS) 2369 #define CSC_HCLKME_VPC_EN_POS (27) 2370 #define CSC_HCLKME_VPC_EN_BIT (0x01UL << CSC_HCLKME_VPC_EN_POS) 2371 #define CSC_HCLKME_MAILBOX_EN_POS (28) 2372 #define CSC_HCLKME_MAILBOX_EN_BIT (0x01UL << CSC_HCLKME_MAILBOX_EN_POS) 2373 #define CSC_HCLKME_ASDMA_EN_POS (29) 2374 #define CSC_HCLKME_ASDMA_EN_BIT (0x01UL << CSC_HCLKME_ASDMA_EN_POS) 2375 #define CSC_HCLKME_SDIO_EN_POS (30) 2376 #define CSC_HCLKME_SDIO_EN_BIT (0x01UL << CSC_HCLKME_SDIO_EN_POS) 2377 #define CSC_HCLKME_RAM5_EN_POS (31) 2378 #define CSC_HCLKME_RAM5_EN_BIT (0x01UL << CSC_HCLKME_RAM5_EN_POS) 2379 cpusysctrl_hclkme_get()2380__STATIC_INLINE uint32_t cpusysctrl_hclkme_get() 2381 { 2382 return CS_CPUSYSCTRL->HCLKME; 2383 } 2384 cpusysctrl_hclkme_set(uint32_t enable_bits)2385__STATIC_INLINE void cpusysctrl_hclkme_set(uint32_t enable_bits) 2386 { 2387 CS_CPUSYSCTRL->HCLKME = enable_bits; 2388 } 2389 2390 /** 2391 * Address Offset: 0x104 2392 * Register Name : CSC HCLK_MANUAL_DISABLE (write 1 valid) 2393 */ 2394 2395 #define CSC_HCLKMD_CPUP_DIS_POS (0) 2396 #define CSC_HCLKMD_CPUP_DIS_BIT (0x01UL << CSC_HCLKMD_CPUP_DIS_POS) 2397 #define CSC_HCLKMD_CPUP_GATED_DIS_POS (1) 2398 #define CSC_HCLKMD_CPUP_GATED_DIS_BIT (0x01UL << CSC_HCLKMD_CPUP_GATED_DIS_POS) 2399 #define CSC_HCLKMD_CPUS_DIS_POS (2) 2400 #define CSC_HCLKMD_CPUS_DIS_BIT (0x01UL << CSC_HCLKMD_CPUS_DIS_POS) 2401 #define CSC_HCLKMD_CPUS_GATED_DIS_POS (3) 2402 #define CSC_HCLKMD_CPUS_GATED_DIS_BIT (0x01UL << CSC_HCLKMD_CPUS_GATED_DIS_POS) 2403 #define CSC_HCLKMD_ROM_DIS_POS (4) 2404 #define CSC_HCLKMD_ROM_DIS_BIT (0x01UL << CSC_HCLKMD_ROM_DIS_POS) 2405 #define CSC_HCLKMD_RAM0_DIS_POS (5) 2406 #define CSC_HCLKMD_RAM0_DIS_BIT (0x01UL << CSC_HCLKMD_RAM0_DIS_POS) 2407 #define CSC_HCLKMD_RAM1_DIS_POS (6) 2408 #define CSC_HCLKMD_RAM1_DIS_BIT (0x01UL << CSC_HCLKMD_RAM1_DIS_POS) 2409 #define CSC_HCLKMD_RAM2_DIS_POS (7) 2410 #define CSC_HCLKMD_RAM2_DIS_BIT (0x01UL << CSC_HCLKMD_RAM2_DIS_POS) 2411 #define CSC_HCLKMD_RAM3_DIS_POS (8) 2412 #define CSC_HCLKMD_RAM3_DIS_BIT (0x01UL << CSC_HCLKMD_RAM3_DIS_POS) 2413 #define CSC_HCLKMD_RAM4_DIS_POS (9) 2414 #define CSC_HCLKMD_RAM4_DIS_BIT (0x01UL << CSC_HCLKMD_RAM4_DIS_POS) 2415 #define CSC_HCLKMD_SYS_MATRIX_DIS_POS (10) 2416 #define CSC_HCLKMD_SYS_MATRIX_DIS_BIT (0x01UL << CSC_HCLKMD_SYS_MATRIX_DIS_POS) 2417 #define CSC_HCLKMD_AHB0_DIS_POS (11) 2418 #define CSC_HCLKMD_AHB0_DIS_BIT (0x01UL << CSC_HCLKMD_AHB0_DIS_POS) 2419 #define CSC_HCLKMD_AHB1_DIS_POS (12) 2420 #define CSC_HCLKMD_AHB1_DIS_BIT (0x01UL << CSC_HCLKMD_AHB1_DIS_POS) 2421 #define CSC_HCLKMD_APB0_DIS_POS (13) 2422 #define CSC_HCLKMD_APB0_DIS_BIT (0x01UL << CSC_HCLKMD_APB0_DIS_POS) 2423 #define CSC_HCLKMD_EXMEM_BUS_DIS_POS (14) 2424 #define CSC_HCLKMD_EXMEM_BUS_DIS_BIT (0x01UL << CSC_HCLKMD_EXMEM_BUS_DIS_POS) 2425 #define CSC_HCLKMD_CACHE0_DIS_POS (15) 2426 #define CSC_HCLKMD_CACHE0_DIS_BIT (0x01UL << CSC_HCLKMD_CACHE0_DIS_POS) 2427 #define CSC_HCLKMD_CACHE1_DIS_POS (16) 2428 #define CSC_HCLKMD_CACHE1_DIS_BIT (0x01UL << CSC_HCLKMD_CACHE1_DIS_POS) 2429 #define CSC_HCLKMD_DMA_DIS_POS (17) 2430 #define CSC_HCLKMD_DMA_DIS_BIT (0x01UL << CSC_HCLKMD_DMA_DIS_POS) 2431 #define CSC_HCLKMD_FLASH_DIS_POS (18) 2432 #define CSC_HCLKMD_FLASH_DIS_BIT (0x01UL << CSC_HCLKMD_FLASH_DIS_POS) 2433 #define CSC_HCLKMD_PSRAM_ALWAYS_DIS_POS (19) 2434 #define CSC_HCLKMD_PSRAM_ALWAYS_DIS_BIT (0x01UL << CSC_HCLKMD_PSRAM_ALWAYS_DIS_POS) 2435 #define CSC_HCLKMD_PSRAM_DIS_POS (20) 2436 #define CSC_HCLKMD_PSRAM_DIS_BIT (0x01UL << CSC_HCLKMD_PSRAM_DIS_POS) 2437 #define CSC_HCLKMD_PSRAM_REG_DIS_POS (21) 2438 #define CSC_HCLKMD_PSRAM_REG_DIS_BIT (0x01UL << CSC_HCLKMD_PSRAM_REG_DIS_POS) 2439 #define CSC_HCLKMD_TRAP_DIS_POS (22) 2440 #define CSC_HCLKMD_TRAP_DIS_BIT (0x01UL << CSC_HCLKMD_TRAP_DIS_POS) 2441 #define CSC_HCLKMD_UART0_DIS_POS (23) 2442 #define CSC_HCLKMD_UART0_DIS_BIT (0x01UL << CSC_HCLKMD_UART0_DIS_POS) 2443 #define CSC_HCLKMD_UART1_DIS_POS (24) 2444 #define CSC_HCLKMD_UART1_DIS_BIT (0x01UL << CSC_HCLKMD_UART1_DIS_POS) 2445 #define CSC_HCLKMD_UART2_DIS_POS (25) 2446 #define CSC_HCLKMD_UART2_DIS_BIT (0x01UL << CSC_HCLKMD_UART2_DIS_POS) 2447 #define CSC_HCLKMD_USBC_DIS_POS (26) 2448 #define CSC_HCLKMD_USBC_DIS_BIT (0x01UL << CSC_HCLKMD_USBC_DIS_POS) 2449 #define CSC_HCLKMD_VPC_DIS_POS (27) 2450 #define CSC_HCLKMD_VPC_DIS_BIT (0x01UL << CSC_HCLKMD_VPC_DIS_POS) 2451 #define CSC_HCLKMD_MAILBOX_DIS_POS (28) 2452 #define CSC_HCLKMD_MAILBOX_DIS_BIT (0x01UL << CSC_HCLKMD_MAILBOX_DIS_POS) 2453 #define CSC_HCLKMD_ASDMA_DIS_POS (29) 2454 #define CSC_HCLKMD_ASDMA_DIS_BIT (0x01UL << CSC_HCLKMD_ASDMA_DIS_POS) 2455 #define CSC_HCLKMD_SDIO_DIS_POS (30) 2456 #define CSC_HCLKMD_SDIO_DIS_BIT (0x01UL << CSC_HCLKMD_SDIO_DIS_POS) 2457 #define CSC_HCLKMD_RAM5_DIS_POS (31) 2458 #define CSC_HCLKMD_RAM5_DIS_BIT (0x01UL << CSC_HCLKMD_RAM5_DIS_POS) 2459 cpusysctrl_hclkmd_get()2460__STATIC_INLINE uint32_t cpusysctrl_hclkmd_get() 2461 { 2462 return CS_CPUSYSCTRL->HCLKMD; 2463 } 2464 cpusysctrl_hclkmd_set(uint32_t disable_bits)2465__STATIC_INLINE void cpusysctrl_hclkmd_set(uint32_t disable_bits) 2466 { 2467 CS_CPUSYSCTRL->HCLKMD = disable_bits; 2468 } 2469 2470 /** 2471 * Address Offset: 0x108 2472 * Register Name : CSC PCLK_MANUAL_ENABLE (write 1 valid) 2473 */ 2474 2475 #define CSC_PCLKME_CPU_SYSCTRL_EN_POS (0) 2476 #define CSC_PCLKME_CPU_SYSCTRL_EN_BIT (0x01UL << CSC_PCLKME_CPU_SYSCTRL_EN_POS) 2477 #define CSC_PCLKME_WDG0_EN_POS (1) 2478 #define CSC_PCLKME_WDG0_EN_BIT (0x01UL << CSC_PCLKME_WDG0_EN_POS) 2479 #define CSC_PCLKME_WDG1_EN_POS (2) 2480 #define CSC_PCLKME_WDG1_EN_BIT (0x01UL << CSC_PCLKME_WDG1_EN_POS) 2481 #define CSC_PCLKME_WDG2_EN_POS (3) 2482 #define CSC_PCLKME_WDG2_EN_BIT (0x01UL << CSC_PCLKME_WDG2_EN_POS) 2483 #define CSC_PCLKME_TIMER0_EN_POS (4) 2484 #define CSC_PCLKME_TIMER0_EN_BIT (0x01UL << CSC_PCLKME_TIMER0_EN_POS) 2485 #define CSC_PCLKME_TIMER1_EN_POS (5) 2486 #define CSC_PCLKME_TIMER1_EN_BIT (0x01UL << CSC_PCLKME_TIMER1_EN_POS) 2487 #define CSC_PCLKME_SPINLOCK_EN_POS (6) 2488 #define CSC_PCLKME_SPINLOCK_EN_BIT (0x01UL << CSC_PCLKME_SPINLOCK_EN_POS) 2489 #define CSC_PCLKME_SPI_EN_POS (7) 2490 #define CSC_PCLKME_SPI_EN_BIT (0x01UL << CSC_PCLKME_SPI_EN_POS) 2491 #define CSC_PCLKME_PWM_EN_POS (8) 2492 #define CSC_PCLKME_PWM_EN_BIT (0x01UL << CSC_PCLKME_PWM_EN_POS) 2493 #define CSC_PCLKME_I2CM_EN_POS (9) 2494 #define CSC_PCLKME_I2CM_EN_BIT (0x01UL << CSC_PCLKME_I2CM_EN_POS) 2495 #define CSC_PCLKME_TRNG_EN_POS (10) 2496 #define CSC_PCLKME_TRNG_EN_BIT (0x01UL << CSC_PCLKME_TRNG_EN_POS) 2497 #define CSC_PCLKME_WDG3_EN_POS (11) 2498 #define CSC_PCLKME_WDG3_EN_BIT (0x01UL << CSC_PCLKME_WDG3_EN_POS) 2499 #define CSC_PCLKME_PROCESS_MON_EN_POS (12) 2500 #define CSC_PCLKME_PROCESS_MON_EN_BIT (0x01UL << CSC_PCLKME_PROCESS_MON_EN_POS) 2501 #define CSC_PCLKME_ANALOG_REG0_EN_POS (13) 2502 #define CSC_PCLKME_ANALOG_REG0_EN_BIT (0x01UL << CSC_PCLKME_ANALOG_REG0_EN_POS) 2503 cpusysctrl_pclkme_get()2504__STATIC_INLINE uint32_t cpusysctrl_pclkme_get() 2505 { 2506 return CS_CPUSYSCTRL->PCLKME; 2507 } 2508 cpusysctrl_pclkme_set(uint32_t enable_bits)2509__STATIC_INLINE void cpusysctrl_pclkme_set(uint32_t enable_bits) 2510 { 2511 CS_CPUSYSCTRL->PCLKME = enable_bits; 2512 } 2513 2514 /** 2515 * Address Offset: 0x10C 2516 * Register Name : CSC PCLK_MANUAL_DISABLE (write 1 valid) 2517 */ 2518 2519 #define CSC_PCLKMD_CPU_SYSCTRL_DIS_POS (0) 2520 #define CSC_PCLKMD_CPU_SYSCTRL_DIS_BIT (0x01UL << CSC_PCLKMD_CPU_SYSCTRL_DIS_POS) 2521 #define CSC_PCLKMD_WDG0_DIS_POS (1) 2522 #define CSC_PCLKMD_WDG0_DIS_BIT (0x01UL << CSC_PCLKMD_WDG0_DIS_POS) 2523 #define CSC_PCLKMD_WDG1_DIS_POS (2) 2524 #define CSC_PCLKMD_WDG1_DIS_BIT (0x01UL << CSC_PCLKMD_WDG1_DIS_POS) 2525 #define CSC_PCLKMD_WDG2_DIS_POS (3) 2526 #define CSC_PCLKMD_WDG2_DIS_BIT (0x01UL << CSC_PCLKMD_WDG2_DIS_POS) 2527 #define CSC_PCLKMD_TIMER0_DIS_POS (4) 2528 #define CSC_PCLKMD_TIMER0_DIS_BIT (0x01UL << CSC_PCLKMD_TIMER0_DIS_POS) 2529 #define CSC_PCLKMD_TIMER1_DIS_POS (5) 2530 #define CSC_PCLKMD_TIMER1_DIS_BIT (0x01UL << CSC_PCLKMD_TIMER1_DIS_POS) 2531 #define CSC_PCLKMD_SPINLOCK_DIS_POS (6) 2532 #define CSC_PCLKMD_SPINLOCK_DIS_BIT (0x01UL << CSC_PCLKMD_SPINLOCK_DIS_POS) 2533 #define CSC_PCLKMD_SPI_DIS_POS (7) 2534 #define CSC_PCLKMD_SPI_DIS_BIT (0x01UL << CSC_PCLKMD_SPI_DIS_POS) 2535 #define CSC_PCLKMD_PWM_DIS_POS (8) 2536 #define CSC_PCLKMD_PWM_DIS_BIT (0x01UL << CSC_PCLKMD_PWM_DIS_POS) 2537 #define CSC_PCLKMD_I2CM_DIS_POS (9) 2538 #define CSC_PCLKMD_I2CM_DIS_BIT (0x01UL << CSC_PCLKMD_I2CM_DIS_POS) 2539 #define CSC_PCLKMD_TRNG_DIS_POS (10) 2540 #define CSC_PCLKMD_TRNG_DIS_BIT (0x01UL << CSC_PCLKMD_TRNG_DIS_POS) 2541 #define CSC_PCLKMD_WDG3_DIS_POS (11) 2542 #define CSC_PCLKMD_WDG3_DIS_BIT (0x01UL << CSC_PCLKMD_WDG3_DIS_POS) 2543 #define CSC_PCLKMD_PROCESS_MON_DIS_POS (12) 2544 #define CSC_PCLKMD_PROCESS_MON_DIS_BIT (0x01UL << CSC_PCLKMD_PROCESS_MON_DIS_POS) 2545 #define CSC_PCLKMD_ANALOG_REG0_DIS_POS (13) 2546 #define CSC_PCLKMD_ANALOG_REG0_DIS_BIT (0x01UL << CSC_PCLKMD_ANALOG_REG0_DIS_POS) 2547 cpusysctrl_pclkmd_get()2548__STATIC_INLINE uint32_t cpusysctrl_pclkmd_get() 2549 { 2550 return CS_CPUSYSCTRL->PCLKMD; 2551 } 2552 cpusysctrl_pclkmd_set(uint32_t disable_bits)2553__STATIC_INLINE void cpusysctrl_pclkmd_set(uint32_t disable_bits) 2554 { 2555 CS_CPUSYSCTRL->PCLKMD = disable_bits; 2556 } 2557 2558 /** 2559 * Address Offset: 0x110 2560 * Register Name : CSC OCLK_MANUAL_ENABLE (write 1 valid) 2561 */ 2562 2563 #define CSC_OCLKME_OPI_2X_ALWAYS_EN_POS (0) 2564 #define CSC_OCLKME_OPI_2X_ALWAYS_EN_BIT (0x01UL << CSC_OCLKME_OPI_2X_ALWAYS_EN_POS) 2565 #define CSC_OCLKME_OPI_2X_EN_POS (1) 2566 #define CSC_OCLKME_OPI_2X_EN_BIT (0x01UL << CSC_OCLKME_OPI_2X_EN_POS) 2567 #define CSC_OCLKME_SDMMC_EN_POS (2) 2568 #define CSC_OCLKME_SDMMC_EN_BIT (0x01UL << CSC_OCLKME_SDMMC_EN_POS) 2569 #define CSC_OCLKME_ASDMA_EN_POS (3) 2570 #define CSC_OCLKME_ASDMA_EN_BIT (0x01UL << CSC_OCLKME_ASDMA_EN_POS) 2571 #define CSC_OCLKME_FLASH_EN_POS (4) 2572 #define CSC_OCLKME_FLASH_EN_BIT (0x01UL << CSC_OCLKME_FLASH_EN_POS) 2573 #define CSC_OCLKME_TIMER00_EN_POS (5) 2574 #define CSC_OCLKME_TIMER00_EN_BIT (0x01UL << CSC_OCLKME_TIMER00_EN_POS) 2575 #define CSC_OCLKME_TIMER01_EN_POS (6) 2576 #define CSC_OCLKME_TIMER01_EN_BIT (0x01UL << CSC_OCLKME_TIMER01_EN_POS) 2577 #define CSC_OCLKME_TIMER10_EN_POS (7) 2578 #define CSC_OCLKME_TIMER10_EN_BIT (0x01UL << CSC_OCLKME_TIMER10_EN_POS) 2579 #define CSC_OCLKME_TIMER11_EN_POS (8) 2580 #define CSC_OCLKME_TIMER11_EN_BIT (0x01UL << CSC_OCLKME_TIMER11_EN_POS) 2581 #define CSC_OCLKME_SPI_EN_POS (9) 2582 #define CSC_OCLKME_SPI_EN_BIT (0x01UL << CSC_OCLKME_SPI_EN_POS) 2583 #define CSC_OCLKME_UART0_EN_POS (10) 2584 #define CSC_OCLKME_UART0_EN_BIT (0x01UL << CSC_OCLKME_UART0_EN_POS) 2585 #define CSC_OCLKME_UART1_EN_POS (11) 2586 #define CSC_OCLKME_UART1_EN_BIT (0x01UL << CSC_OCLKME_UART1_EN_POS) 2587 #define CSC_OCLKME_UART2_EN_POS (12) 2588 #define CSC_OCLKME_UART2_EN_BIT (0x01UL << CSC_OCLKME_UART2_EN_POS) 2589 #define CSC_OCLKME_ULPI_EN_POS (13) 2590 #define CSC_OCLKME_ULPI_EN_BIT (0x01UL << CSC_OCLKME_ULPI_EN_POS) 2591 #define CSC_OCLKME_SDIO_EN_POS (14) 2592 #define CSC_OCLKME_SDIO_EN_BIT (0x01UL << CSC_OCLKME_SDIO_EN_POS) 2593 #define CSC_OCLKME_PWM_EN_POS (15) 2594 #define CSC_OCLKME_PWM_EN_BIT (0x01UL << CSC_OCLKME_PWM_EN_POS) 2595 #define CSC_OCLKME_TIMER02_EN_POS (16) 2596 #define CSC_OCLKME_TIMER02_EN_BIT (0x01UL << CSC_OCLKME_TIMER02_EN_POS) 2597 #define CSC_OCLKME_TIMER12_EN_POS (17) 2598 #define CSC_OCLKME_TIMER12_EN_BIT (0x01UL << CSC_OCLKME_TIMER12_EN_POS) 2599 #define CSC_OCLKME_RTC_ALWAYS_EN_POS (18) 2600 #define CSC_OCLKME_RTC_ALWAYS_EN_BIT (0x01UL << CSC_OCLKME_RTC_ALWAYS_EN_POS) 2601 #define CSC_OCLKME_RTC_WDG0_EN_POS (19) 2602 #define CSC_OCLKME_RTC_WDG0_EN_BIT (0x01UL << CSC_OCLKME_RTC_WDG0_EN_POS) 2603 #define CSC_OCLKME_RTC_WDG1_EN_POS (20) 2604 #define CSC_OCLKME_RTC_WDG1_EN_BIT (0x01UL << CSC_OCLKME_RTC_WDG1_EN_POS) 2605 #define CSC_OCLKME_RTC_WDG2_EN_POS (21) 2606 #define CSC_OCLKME_RTC_WDG2_EN_BIT (0x01UL << CSC_OCLKME_RTC_WDG2_EN_POS) 2607 #define CSC_OCLKME_DDR_2X_EN_POS (22) 2608 #define CSC_OCLKME_DDR_2X_EN_BIT (0x01UL << CSC_OCLKME_DDR_2X_EN_POS) 2609 #define CSC_OCLKME_DDR_2X_ALWAYS_EN_POS (23) 2610 #define CSC_OCLKME_DDR_2X_ALWAYS_EN_BIT (0x01UL << CSC_OCLKME_DDR_2X_ALWAYS_EN_POS) 2611 #define CSC_OCLKME_CAMERA_REF_EN_POS (24) 2612 #define CSC_OCLKME_CAMERA_REF_EN_BIT (0x01UL << CSC_OCLKME_CAMERA_REF_EN_POS) 2613 #define CSC_OCLKME_AUDIO_PROC_EN_POS (25) 2614 #define CSC_OCLKME_AUDIO_PROC_EN_BIT (0x01UL << CSC_OCLKME_AUDIO_PROC_EN_POS) 2615 #define CSC_OCLKME_RTC_WDG3_EN_POS (26) 2616 #define CSC_OCLKME_RTC_WDG3_EN_BIT (0x01UL << CSC_OCLKME_RTC_WDG3_EN_POS) 2617 #define CSC_OCLKME_PROCESS_MON_EN_POS (27) 2618 #define CSC_OCLKME_PROCESS_MON_EN_BIT (0x01UL << CSC_OCLKME_PROCESS_MON_EN_POS) 2619 #define CSC_OCLKME_26M_ASDMA_EN_POS (28) 2620 #define CSC_OCLKME_26M_ASDMA_EN_BIT (0x01UL << CSC_OCLKME_26M_ASDMA_EN_POS) 2621 #define CSC_OCLKME_BCK0_EN_POS (29) 2622 #define CSC_OCLKME_BCK0_EN_BIT (0x01UL << CSC_OCLKME_BCK0_EN_POS) 2623 #define CSC_OCLKME_BCK1_EN_POS (30) 2624 #define CSC_OCLKME_BCK1_EN_BIT (0x01UL << CSC_OCLKME_BCK1_EN_POS) 2625 #define CSC_OCLKME_SPDIF_EN_POS (31) 2626 #define CSC_OCLKME_SPDIF_EN_BIT (0x01UL << CSC_OCLKME_SPDIF_EN_POS) 2627 cpusysctrl_oclkme_get()2628__STATIC_INLINE uint32_t cpusysctrl_oclkme_get() 2629 { 2630 return CS_CPUSYSCTRL->OCLKME; 2631 } 2632 cpusysctrl_oclkme_set(uint32_t enable_bits)2633__STATIC_INLINE void cpusysctrl_oclkme_set(uint32_t enable_bits) 2634 { 2635 CS_CPUSYSCTRL->OCLKME = enable_bits; 2636 } 2637 2638 /** 2639 * Address Offset: 0x114 2640 * Register Name : CSC OCLK_MANUAL_DISABLE (write 1 valid) 2641 */ 2642 2643 #define CSC_OCLKMD_OPI_2X_ALWAYS_DIS_POS (0) 2644 #define CSC_OCLKMD_OPI_2X_ALWAYS_DIS_BIT (0x01UL << CSC_OCLKMD_OPI_2X_ALWAYS_DIS_POS) 2645 #define CSC_OCLKMD_OPI_2X_DIS_POS (1) 2646 #define CSC_OCLKMD_OPI_2X_DIS_BIT (0x01UL << CSC_OCLKMD_OPI_2X_DIS_POS) 2647 #define CSC_OCLKMD_SDMMC_DIS_POS (2) 2648 #define CSC_OCLKMD_SDMMC_DIS_BIT (0x01UL << CSC_OCLKMD_SDMMC_DIS_POS) 2649 #define CSC_OCLKMD_ASDMA_DIS_POS (3) 2650 #define CSC_OCLKMD_ASDMA_DIS_BIT (0x01UL << CSC_OCLKMD_ASDMA_DIS_POS) 2651 #define CSC_OCLKMD_FLASH_DIS_POS (4) 2652 #define CSC_OCLKMD_FLASH_DIS_BIT (0x01UL << CSC_OCLKMD_FLASH_DIS_POS) 2653 #define CSC_OCLKMD_TIMER00_DIS_POS (5) 2654 #define CSC_OCLKMD_TIMER00_DIS_BIT (0x01UL << CSC_OCLKMD_TIMER00_DIS_POS) 2655 #define CSC_OCLKMD_TIMER01_DIS_POS (6) 2656 #define CSC_OCLKMD_TIMER01_DIS_BIT (0x01UL << CSC_OCLKMD_TIMER01_DIS_POS) 2657 #define CSC_OCLKMD_TIMER10_DIS_POS (7) 2658 #define CSC_OCLKMD_TIMER10_DIS_BIT (0x01UL << CSC_OCLKMD_TIMER10_DIS_POS) 2659 #define CSC_OCLKMD_TIMER11_DIS_POS (8) 2660 #define CSC_OCLKMD_TIMER11_DIS_BIT (0x01UL << CSC_OCLKMD_TIMER11_DIS_POS) 2661 #define CSC_OCLKMD_SPI_DIS_POS (9) 2662 #define CSC_OCLKMD_SPI_DIS_BIT (0x01UL << CSC_OCLKMD_SPI_DIS_POS) 2663 #define CSC_OCLKMD_UART0_DIS_POS (10) 2664 #define CSC_OCLKMD_UART0_DIS_BIT (0x01UL << CSC_OCLKMD_UART0_DIS_POS) 2665 #define CSC_OCLKMD_UART1_DIS_POS (11) 2666 #define CSC_OCLKMD_UART1_DIS_BIT (0x01UL << CSC_OCLKMD_UART1_DIS_POS) 2667 #define CSC_OCLKMD_UART2_DIS_POS (12) 2668 #define CSC_OCLKMD_UART2_DIS_BIT (0x01UL << CSC_OCLKMD_UART2_DIS_POS) 2669 #define CSC_OCLKMD_ULPI_DIS_POS (13) 2670 #define CSC_OCLKMD_ULPI_DIS_BIT (0x01UL << CSC_OCLKMD_ULPI_DIS_POS) 2671 #define CSC_OCLKMD_SDIO_DIS_POS (14) 2672 #define CSC_OCLKMD_SDIO_DIS_BIT (0x01UL << CSC_OCLKMD_SDIO_DIS_POS) 2673 #define CSC_OCLKMD_PWM_DIS_POS (15) 2674 #define CSC_OCLKMD_PWM_DIS_BIT (0x01UL << CSC_OCLKMD_PWM_DIS_POS) 2675 #define CSC_OCLKMD_TIMER02_DIS_POS (16) 2676 #define CSC_OCLKMD_TIMER02_DIS_BIT (0x01UL << CSC_OCLKMD_TIMER02_DIS_POS) 2677 #define CSC_OCLKMD_TIMER12_DIS_POS (17) 2678 #define CSC_OCLKMD_TIMER12_DIS_BIT (0x01UL << CSC_OCLKMD_TIMER12_DIS_POS) 2679 #define CSC_OCLKMD_RTC_ALWAYS_DIS_POS (18) 2680 #define CSC_OCLKMD_RTC_ALWAYS_DIS_BIT (0x01UL << CSC_OCLKMD_RTC_ALWAYS_DIS_POS) 2681 #define CSC_OCLKMD_RTC_WDG0_DIS_POS (19) 2682 #define CSC_OCLKMD_RTC_WDG0_DIS_BIT (0x01UL << CSC_OCLKMD_RTC_WDG0_DIS_POS) 2683 #define CSC_OCLKMD_RTC_WDG1_DIS_POS (20) 2684 #define CSC_OCLKMD_RTC_WDG1_DIS_BIT (0x01UL << CSC_OCLKMD_RTC_WDG1_DIS_POS) 2685 #define CSC_OCLKMD_RTC_WDG2_DIS_POS (21) 2686 #define CSC_OCLKMD_RTC_WDG2_DIS_BIT (0x01UL << CSC_OCLKMD_RTC_WDG2_DIS_POS) 2687 #define CSC_OCLKMD_DDR_2X_DIS_POS (22) 2688 #define CSC_OCLKMD_DDR_2X_DIS_BIT (0x01UL << CSC_OCLKMD_DDR_2X_DIS_POS) 2689 #define CSC_OCLKMD_DDR_2X_ALWAYS_DIS_POS (23) 2690 #define CSC_OCLKMD_DDR_2X_ALWAYS_DIS_BIT (0x01UL << CSC_OCLKMD_DDR_2X_ALWAYS_DIS_POS) 2691 #define CSC_OCLKMD_CAMERA_REF_DIS_POS (24) 2692 #define CSC_OCLKMD_CAMERA_REF_DIS_BIT (0x01UL << CSC_OCLKMD_CAMERA_REF_DIS_POS) 2693 #define CSC_OCLKMD_AUDIO_PROC_DIS_POS (25) 2694 #define CSC_OCLKMD_AUDIO_PROC_DIS_BIT (0x01UL << CSC_OCLKMD_AUDIO_PROC_DIS_POS) 2695 #define CSC_OCLKMD_RTC_WDG3_DIS_POS (26) 2696 #define CSC_OCLKMD_RTC_WDG3_DIS_BIT (0x01UL << CSC_OCLKMD_RTC_WDG3_DIS_POS) 2697 #define CSC_OCLKMD_PROCESS_MON_DIS_POS (27) 2698 #define CSC_OCLKMD_PROCESS_MON_DIS_BIT (0x01UL << CSC_OCLKMD_PROCESS_MON_DIS_POS) 2699 #define CSC_OCLKMD_26M_ASDMA_DIS_POS (28) 2700 #define CSC_OCLKMD_26M_ASDMA_DIS_BIT (0x01UL << CSC_OCLKMD_26M_ASDMA_DIS_POS) 2701 #define CSC_OCLKMD_BCK0_DIS_POS (29) 2702 #define CSC_OCLKMD_BCK0_DIS_BIT (0x01UL << CSC_OCLKMD_BCK0_DIS_POS) 2703 #define CSC_OCLKMD_BCK1_DIS_POS (30) 2704 #define CSC_OCLKMD_BCK1_DIS_BIT (0x01UL << CSC_OCLKMD_BCK1_DIS_POS) 2705 #define CSC_OCLKMD_SPDIF_DIS_POS (31) 2706 #define CSC_OCLKMD_SPDIF_DIS_BIT (0x01UL << CSC_OCLKMD_SPDIF_DIS_POS) 2707 cpusysctrl_oclkmd_get()2708__STATIC_INLINE uint32_t cpusysctrl_oclkmd_get() 2709 { 2710 return CS_CPUSYSCTRL->OCLKMD; 2711 } 2712 cpusysctrl_oclkmd_set(uint32_t disable_bits)2713__STATIC_INLINE void cpusysctrl_oclkmd_set(uint32_t disable_bits) 2714 { 2715 CS_CPUSYSCTRL->OCLKMD = disable_bits; 2716 } 2717 2718 /** 2719 * Address Offset: 0x118 2720 * Register Name : CSC HCLK_SOFT_RESETn_SET (write 1 valid) 2721 */ 2722 2723 #define CSC_HCLKRS_CPUPSET_POS (0) 2724 #define CSC_HCLKRS_CPUPSET_BIT (0x01UL << CSC_HCLKRS_CPUPSET_POS) 2725 #define CSC_HCLKRS_ROMSET_POS (2) 2726 #define CSC_HCLKRS_ROMSET_BIT (0x01UL << CSC_HCLKRS_ROMSET_POS) 2727 #define CSC_HCLKRS_SRAM0SET_POS (3) 2728 #define CSC_HCLKRS_SRAM0SET_BIT (0x01UL << CSC_HCLKRS_SRAM0SET_POS) 2729 #define CSC_HCLKRS_SRAM1SET_POS (4) 2730 #define CSC_HCLKRS_SRAM1SET_BIT (0x01UL << CSC_HCLKRS_SRAM1SET_POS) 2731 #define CSC_HCLKRS_SRAM2SET_POS (5) 2732 #define CSC_HCLKRS_SRAM2SET_BIT (0x01UL << CSC_HCLKRS_SRAM2SET_POS) 2733 #define CSC_HCLKRS_SRAM3SET_POS (6) 2734 #define CSC_HCLKRS_SRAM3SET_BIT (0x01UL << CSC_HCLKRS_SRAM3SET_POS) 2735 #define CSC_HCLKRS_SRAM4SET_POS (7) 2736 #define CSC_HCLKRS_SRAM4SET_BIT (0x01UL << CSC_HCLKRS_SRAM4SET_POS) 2737 #define CSC_HCLKRS_SRAM5SET_POS (8) 2738 #define CSC_HCLKRS_SRAM5SET_BIT (0x01UL << CSC_HCLKRS_SRAM5SET_POS) 2739 #define CSC_HCLKRS_AHB0DECSET_POS (9) 2740 #define CSC_HCLKRS_AHB0DECSET_BIT (0x01UL << CSC_HCLKRS_AHB0DECSET_POS) 2741 #define CSC_HCLKRS_AHB1DECSET_POS (10) 2742 #define CSC_HCLKRS_AHB1DECSET_BIT (0x01UL << CSC_HCLKRS_AHB1DECSET_POS) 2743 #define CSC_HCLKRS_APB0SET_POS (11) 2744 #define CSC_HCLKRS_APB0SET_BIT (0x01UL << CSC_HCLKRS_APB0SET_POS) 2745 #define CSC_HCLKRS_FLASHSET_POS (12) 2746 #define CSC_HCLKRS_FLASHSET_BIT (0x01UL << CSC_HCLKRS_FLASHSET_POS) 2747 #define CSC_HCLKRS_DMASET_POS (13) 2748 #define CSC_HCLKRS_DMASET_BIT (0x01UL << CSC_HCLKRS_DMASET_POS) 2749 #define CSC_HCLKRS_EXMEMBUSSET_POS (14) 2750 #define CSC_HCLKRS_EXMEMBUSSET_BIT (0x01UL << CSC_HCLKRS_EXMEMBUSSET_POS) 2751 #define CSC_HCLKRS_CACHE0SET_POS (15) 2752 #define CSC_HCLKRS_CACHE0SET_BIT (0x01UL << CSC_HCLKRS_CACHE0SET_POS) 2753 #define CSC_HCLKRS_CACHE1SET_POS (16) 2754 #define CSC_HCLKRS_CACHE1SET_BIT (0x01UL << CSC_HCLKRS_CACHE1SET_POS) 2755 #define CSC_HCLKRS_PSRAMSET_POS (17) 2756 #define CSC_HCLKRS_PSRAMSET_BIT (0x01UL << CSC_HCLKRS_PSRAMSET_POS) 2757 #define CSC_HCLKRS_PSRAMREGSET_POS (18) 2758 #define CSC_HCLKRS_PSRAMREGSET_BIT (0x01UL << CSC_HCLKRS_PSRAMREGSET_POS) 2759 #define CSC_HCLKRS_TRAPSET_POS (19) 2760 #define CSC_HCLKRS_TRAPSET_BIT (0x01UL << CSC_HCLKRS_TRAPSET_POS) 2761 #define CSC_HCLKRS_UART0SET_POS (20) 2762 #define CSC_HCLKRS_UART0SET_BIT (0x01UL << CSC_HCLKRS_UART0SET_POS) 2763 #define CSC_HCLKRS_UART1SET_POS (21) 2764 #define CSC_HCLKRS_UART1SET_BIT (0x01UL << CSC_HCLKRS_UART1SET_POS) 2765 #define CSC_HCLKRS_UART2SET_POS (22) 2766 #define CSC_HCLKRS_UART2SET_BIT (0x01UL << CSC_HCLKRS_UART2SET_POS) 2767 #define CSC_HCLKRS_USBCSET_POS (23) 2768 #define CSC_HCLKRS_USBCSET_BIT (0x01UL << CSC_HCLKRS_USBCSET_POS) 2769 #define CSC_HCLKRS_VPCSET_POS (24) 2770 #define CSC_HCLKRS_VPCSET_BIT (0x01UL << CSC_HCLKRS_VPCSET_POS) 2771 #define CSC_HCLKRS_MAILBOXSET_POS (25) 2772 #define CSC_HCLKRS_MAILBOXSET_BIT (0x01UL << CSC_HCLKRS_MAILBOXSET_POS) 2773 #define CSC_HCLKRS_ASDMASET_POS (26) 2774 #define CSC_HCLKRS_ASDMASET_BIT (0x01UL << CSC_HCLKRS_ASDMASET_POS) 2775 #define CSC_HCLKRS_SDIOSET_POS (27) 2776 #define CSC_HCLKRS_SDIOSET_BIT (0x01UL << CSC_HCLKRS_SDIOSET_POS) 2777 #define CSC_HCLKRS_CAMERASET_POS (29) 2778 #define CSC_HCLKRS_CAMERASET_BIT (0x01UL << CSC_HCLKRS_CAMERASET_POS) 2779 #define CSC_HCLKRS_SRAM6SET_POS (30) 2780 #define CSC_HCLKRS_SRAM6SET_BIT (0x01UL << CSC_HCLKRS_SRAM6SET_POS) 2781 #define CSC_HCLKRS_JPEGENCSET_POS (31) 2782 #define CSC_HCLKRS_JPEGENCSET_BIT (0x01UL << CSC_HCLKRS_JPEGENCSET_POS) 2783 cpusysctrl_hclkrs_get()2784__STATIC_INLINE uint32_t cpusysctrl_hclkrs_get() 2785 { 2786 return CS_CPUSYSCTRL->HCLKRS; 2787 } 2788 cpusysctrl_hclkrs_set(uint32_t reset_bits)2789__STATIC_INLINE void cpusysctrl_hclkrs_set(uint32_t reset_bits) 2790 { 2791 CS_CPUSYSCTRL->HCLKRS = reset_bits; 2792 } 2793 cpusysctrl_hclkrs_cpupset_getb(void)2794__STATIC_INLINE uint8_t cpusysctrl_hclkrs_cpupset_getb(void) 2795 { 2796 return (CS_CPUSYSCTRL->HCLKRS & CSC_HCLKRS_CPUPSET_BIT) >> CSC_HCLKRS_CPUPSET_POS; 2797 } 2798 cpusysctrl_hclkrs_cpupset_setb(void)2799__STATIC_INLINE void cpusysctrl_hclkrs_cpupset_setb(void) 2800 { 2801 CS_CPUSYSCTRL->HCLKRS = CSC_HCLKRS_CPUPSET_BIT; 2802 } 2803 cpusysctrl_hclkrs_romset_getb(void)2804__STATIC_INLINE uint8_t cpusysctrl_hclkrs_romset_getb(void) 2805 { 2806 return (CS_CPUSYSCTRL->HCLKRS & CSC_HCLKRS_ROMSET_BIT) >> CSC_HCLKRS_ROMSET_POS; 2807 } 2808 cpusysctrl_hclkrs_romset_setb(void)2809__STATIC_INLINE void cpusysctrl_hclkrs_romset_setb(void) 2810 { 2811 CS_CPUSYSCTRL->HCLKRS = CSC_HCLKRS_ROMSET_BIT; 2812 } 2813 cpusysctrl_hclkrs_sram0set_getb(void)2814__STATIC_INLINE uint8_t cpusysctrl_hclkrs_sram0set_getb(void) 2815 { 2816 return (CS_CPUSYSCTRL->HCLKRS & CSC_HCLKRS_SRAM0SET_BIT) >> CSC_HCLKRS_SRAM0SET_POS; 2817 } 2818 cpusysctrl_hclkrs_sram0set_setb(void)2819__STATIC_INLINE void cpusysctrl_hclkrs_sram0set_setb(void) 2820 { 2821 CS_CPUSYSCTRL->HCLKRS = CSC_HCLKRS_SRAM0SET_BIT; 2822 } 2823 cpusysctrl_hclkrs_sram1set_getb(void)2824__STATIC_INLINE uint8_t cpusysctrl_hclkrs_sram1set_getb(void) 2825 { 2826 return (CS_CPUSYSCTRL->HCLKRS & CSC_HCLKRS_SRAM1SET_BIT) >> CSC_HCLKRS_SRAM1SET_POS; 2827 } 2828 cpusysctrl_hclkrs_sram1set_setb(void)2829__STATIC_INLINE void cpusysctrl_hclkrs_sram1set_setb(void) 2830 { 2831 CS_CPUSYSCTRL->HCLKRS = CSC_HCLKRS_SRAM1SET_BIT; 2832 } 2833 cpusysctrl_hclkrs_sram2set_getb(void)2834__STATIC_INLINE uint8_t cpusysctrl_hclkrs_sram2set_getb(void) 2835 { 2836 return (CS_CPUSYSCTRL->HCLKRS & CSC_HCLKRS_SRAM2SET_BIT) >> CSC_HCLKRS_SRAM2SET_POS; 2837 } 2838 cpusysctrl_hclkrs_sram2set_setb(void)2839__STATIC_INLINE void cpusysctrl_hclkrs_sram2set_setb(void) 2840 { 2841 CS_CPUSYSCTRL->HCLKRS = CSC_HCLKRS_SRAM2SET_BIT; 2842 } 2843 cpusysctrl_hclkrs_sram3set_getb(void)2844__STATIC_INLINE uint8_t cpusysctrl_hclkrs_sram3set_getb(void) 2845 { 2846 return (CS_CPUSYSCTRL->HCLKRS & CSC_HCLKRS_SRAM3SET_BIT) >> CSC_HCLKRS_SRAM3SET_POS; 2847 } 2848 cpusysctrl_hclkrs_sram3set_setb(void)2849__STATIC_INLINE void cpusysctrl_hclkrs_sram3set_setb(void) 2850 { 2851 CS_CPUSYSCTRL->HCLKRS = CSC_HCLKRS_SRAM3SET_BIT; 2852 } 2853 cpusysctrl_hclkrs_sram4set_getb(void)2854__STATIC_INLINE uint8_t cpusysctrl_hclkrs_sram4set_getb(void) 2855 { 2856 return (CS_CPUSYSCTRL->HCLKRS & CSC_HCLKRS_SRAM4SET_BIT) >> CSC_HCLKRS_SRAM4SET_POS; 2857 } 2858 cpusysctrl_hclkrs_sram4set_setb(void)2859__STATIC_INLINE void cpusysctrl_hclkrs_sram4set_setb(void) 2860 { 2861 CS_CPUSYSCTRL->HCLKRS = CSC_HCLKRS_SRAM4SET_BIT; 2862 } 2863 cpusysctrl_hclkrs_sram5set_getb(void)2864__STATIC_INLINE uint8_t cpusysctrl_hclkrs_sram5set_getb(void) 2865 { 2866 return (CS_CPUSYSCTRL->HCLKRS & CSC_HCLKRS_SRAM5SET_BIT) >> CSC_HCLKRS_SRAM5SET_POS; 2867 } 2868 cpusysctrl_hclkrs_sram5set_setb(void)2869__STATIC_INLINE void cpusysctrl_hclkrs_sram5set_setb(void) 2870 { 2871 CS_CPUSYSCTRL->HCLKRS = CSC_HCLKRS_SRAM5SET_BIT; 2872 } 2873 cpusysctrl_hclkrs_ahb0decset_getb(void)2874__STATIC_INLINE uint8_t cpusysctrl_hclkrs_ahb0decset_getb(void) 2875 { 2876 return (CS_CPUSYSCTRL->HCLKRS & CSC_HCLKRS_AHB0DECSET_BIT) >> CSC_HCLKRS_AHB0DECSET_POS; 2877 } 2878 cpusysctrl_hclkrs_ahb0decset_setb(void)2879__STATIC_INLINE void cpusysctrl_hclkrs_ahb0decset_setb(void) 2880 { 2881 CS_CPUSYSCTRL->HCLKRS = CSC_HCLKRS_AHB0DECSET_BIT; 2882 } 2883 cpusysctrl_hclkrs_ahb1decset_getb(void)2884__STATIC_INLINE uint8_t cpusysctrl_hclkrs_ahb1decset_getb(void) 2885 { 2886 return (CS_CPUSYSCTRL->HCLKRS & CSC_HCLKRS_AHB1DECSET_BIT) >> CSC_HCLKRS_AHB1DECSET_POS; 2887 } 2888 cpusysctrl_hclkrs_ahb1decset_setb(void)2889__STATIC_INLINE void cpusysctrl_hclkrs_ahb1decset_setb(void) 2890 { 2891 CS_CPUSYSCTRL->HCLKRS = CSC_HCLKRS_AHB1DECSET_BIT; 2892 } 2893 cpusysctrl_hclkrs_apb0set_getb(void)2894__STATIC_INLINE uint8_t cpusysctrl_hclkrs_apb0set_getb(void) 2895 { 2896 return (CS_CPUSYSCTRL->HCLKRS & CSC_HCLKRS_APB0SET_BIT) >> CSC_HCLKRS_APB0SET_POS; 2897 } 2898 cpusysctrl_hclkrs_apb0set_setb(void)2899__STATIC_INLINE void cpusysctrl_hclkrs_apb0set_setb(void) 2900 { 2901 CS_CPUSYSCTRL->HCLKRS = CSC_HCLKRS_APB0SET_BIT; 2902 } 2903 cpusysctrl_hclkrs_flashset_getb(void)2904__STATIC_INLINE uint8_t cpusysctrl_hclkrs_flashset_getb(void) 2905 { 2906 return (CS_CPUSYSCTRL->HCLKRS & CSC_HCLKRS_FLASHSET_BIT) >> CSC_HCLKRS_FLASHSET_POS; 2907 } 2908 cpusysctrl_hclkrs_flashset_setb(void)2909__STATIC_INLINE void cpusysctrl_hclkrs_flashset_setb(void) 2910 { 2911 CS_CPUSYSCTRL->HCLKRS = CSC_HCLKRS_FLASHSET_BIT; 2912 } 2913 cpusysctrl_hclkrs_dmaset_getb(void)2914__STATIC_INLINE uint8_t cpusysctrl_hclkrs_dmaset_getb(void) 2915 { 2916 return (CS_CPUSYSCTRL->HCLKRS & CSC_HCLKRS_DMASET_BIT) >> CSC_HCLKRS_DMASET_POS; 2917 } 2918 cpusysctrl_hclkrs_dmaset_setb(void)2919__STATIC_INLINE void cpusysctrl_hclkrs_dmaset_setb(void) 2920 { 2921 CS_CPUSYSCTRL->HCLKRS = CSC_HCLKRS_DMASET_BIT; 2922 } 2923 cpusysctrl_hclkrs_exmembusset_getb(void)2924__STATIC_INLINE uint8_t cpusysctrl_hclkrs_exmembusset_getb(void) 2925 { 2926 return (CS_CPUSYSCTRL->HCLKRS & CSC_HCLKRS_EXMEMBUSSET_BIT) >> CSC_HCLKRS_EXMEMBUSSET_POS; 2927 } 2928 cpusysctrl_hclkrs_exmembusset_setb(void)2929__STATIC_INLINE void cpusysctrl_hclkrs_exmembusset_setb(void) 2930 { 2931 CS_CPUSYSCTRL->HCLKRS = CSC_HCLKRS_EXMEMBUSSET_BIT; 2932 } 2933 cpusysctrl_hclkrs_cache0set_getb(void)2934__STATIC_INLINE uint8_t cpusysctrl_hclkrs_cache0set_getb(void) 2935 { 2936 return (CS_CPUSYSCTRL->HCLKRS & CSC_HCLKRS_CACHE0SET_BIT) >> CSC_HCLKRS_CACHE0SET_POS; 2937 } 2938 cpusysctrl_hclkrs_cache0set_setb(void)2939__STATIC_INLINE void cpusysctrl_hclkrs_cache0set_setb(void) 2940 { 2941 CS_CPUSYSCTRL->HCLKRS = CSC_HCLKRS_CACHE0SET_BIT; 2942 } 2943 cpusysctrl_hclkrs_cache1set_getb(void)2944__STATIC_INLINE uint8_t cpusysctrl_hclkrs_cache1set_getb(void) 2945 { 2946 return (CS_CPUSYSCTRL->HCLKRS & CSC_HCLKRS_CACHE1SET_BIT) >> CSC_HCLKRS_CACHE1SET_POS; 2947 } 2948 cpusysctrl_hclkrs_cache1set_setb(void)2949__STATIC_INLINE void cpusysctrl_hclkrs_cache1set_setb(void) 2950 { 2951 CS_CPUSYSCTRL->HCLKRS = CSC_HCLKRS_CACHE1SET_BIT; 2952 } 2953 cpusysctrl_hclkrs_psramset_getb(void)2954__STATIC_INLINE uint8_t cpusysctrl_hclkrs_psramset_getb(void) 2955 { 2956 return (CS_CPUSYSCTRL->HCLKRS & CSC_HCLKRS_PSRAMSET_BIT) >> CSC_HCLKRS_PSRAMSET_POS; 2957 } 2958 cpusysctrl_hclkrs_psramset_setb(void)2959__STATIC_INLINE void cpusysctrl_hclkrs_psramset_setb(void) 2960 { 2961 CS_CPUSYSCTRL->HCLKRS = CSC_HCLKRS_PSRAMSET_BIT; 2962 } 2963 cpusysctrl_hclkrs_psramregset_getb(void)2964__STATIC_INLINE uint8_t cpusysctrl_hclkrs_psramregset_getb(void) 2965 { 2966 return (CS_CPUSYSCTRL->HCLKRS & CSC_HCLKRS_PSRAMREGSET_BIT) >> CSC_HCLKRS_PSRAMREGSET_POS; 2967 } 2968 cpusysctrl_hclkrs_psramregset_setb(void)2969__STATIC_INLINE void cpusysctrl_hclkrs_psramregset_setb(void) 2970 { 2971 CS_CPUSYSCTRL->HCLKRS = CSC_HCLKRS_PSRAMREGSET_BIT; 2972 } 2973 cpusysctrl_hclkrs_trapset_getb(void)2974__STATIC_INLINE uint8_t cpusysctrl_hclkrs_trapset_getb(void) 2975 { 2976 return (CS_CPUSYSCTRL->HCLKRS & CSC_HCLKRS_TRAPSET_BIT) >> CSC_HCLKRS_TRAPSET_POS; 2977 } 2978 cpusysctrl_hclkrs_trapset_setb(void)2979__STATIC_INLINE void cpusysctrl_hclkrs_trapset_setb(void) 2980 { 2981 CS_CPUSYSCTRL->HCLKRS = CSC_HCLKRS_TRAPSET_BIT; 2982 } 2983 cpusysctrl_hclkrs_uart0set_getb(void)2984__STATIC_INLINE uint8_t cpusysctrl_hclkrs_uart0set_getb(void) 2985 { 2986 return (CS_CPUSYSCTRL->HCLKRS & CSC_HCLKRS_UART0SET_BIT) >> CSC_HCLKRS_UART0SET_POS; 2987 } 2988 cpusysctrl_hclkrs_uart0set_setb(void)2989__STATIC_INLINE void cpusysctrl_hclkrs_uart0set_setb(void) 2990 { 2991 CS_CPUSYSCTRL->HCLKRS = CSC_HCLKRS_UART0SET_BIT; 2992 } 2993 cpusysctrl_hclkrs_uart1set_getb(void)2994__STATIC_INLINE uint8_t cpusysctrl_hclkrs_uart1set_getb(void) 2995 { 2996 return (CS_CPUSYSCTRL->HCLKRS & CSC_HCLKRS_UART1SET_BIT) >> CSC_HCLKRS_UART1SET_POS; 2997 } 2998 cpusysctrl_hclkrs_uart1set_setb(void)2999__STATIC_INLINE void cpusysctrl_hclkrs_uart1set_setb(void) 3000 { 3001 CS_CPUSYSCTRL->HCLKRS = CSC_HCLKRS_UART1SET_BIT; 3002 } 3003 cpusysctrl_hclkrs_uart2set_getb(void)3004__STATIC_INLINE uint8_t cpusysctrl_hclkrs_uart2set_getb(void) 3005 { 3006 return (CS_CPUSYSCTRL->HCLKRS & CSC_HCLKRS_UART2SET_BIT) >> CSC_HCLKRS_UART2SET_POS; 3007 } 3008 cpusysctrl_hclkrs_uart2set_setb(void)3009__STATIC_INLINE void cpusysctrl_hclkrs_uart2set_setb(void) 3010 { 3011 CS_CPUSYSCTRL->HCLKRS = CSC_HCLKRS_UART2SET_BIT; 3012 } 3013 cpusysctrl_hclkrs_usbcset_getb(void)3014__STATIC_INLINE uint8_t cpusysctrl_hclkrs_usbcset_getb(void) 3015 { 3016 return (CS_CPUSYSCTRL->HCLKRS & CSC_HCLKRS_USBCSET_BIT) >> CSC_HCLKRS_USBCSET_POS; 3017 } 3018 cpusysctrl_hclkrs_usbcset_setb(void)3019__STATIC_INLINE void cpusysctrl_hclkrs_usbcset_setb(void) 3020 { 3021 CS_CPUSYSCTRL->HCLKRS = CSC_HCLKRS_USBCSET_BIT; 3022 } 3023 cpusysctrl_hclkrs_vpcset_getb(void)3024__STATIC_INLINE uint8_t cpusysctrl_hclkrs_vpcset_getb(void) 3025 { 3026 return (CS_CPUSYSCTRL->HCLKRS & CSC_HCLKRS_VPCSET_BIT) >> CSC_HCLKRS_VPCSET_POS; 3027 } 3028 cpusysctrl_hclkrs_vpcset_setb(void)3029__STATIC_INLINE void cpusysctrl_hclkrs_vpcset_setb(void) 3030 { 3031 CS_CPUSYSCTRL->HCLKRS = CSC_HCLKRS_VPCSET_BIT; 3032 } 3033 cpusysctrl_hclkrs_mailboxset_getb(void)3034__STATIC_INLINE uint8_t cpusysctrl_hclkrs_mailboxset_getb(void) 3035 { 3036 return (CS_CPUSYSCTRL->HCLKRS & CSC_HCLKRS_MAILBOXSET_BIT) >> CSC_HCLKRS_MAILBOXSET_POS; 3037 } 3038 cpusysctrl_hclkrs_mailboxset_setb(void)3039__STATIC_INLINE void cpusysctrl_hclkrs_mailboxset_setb(void) 3040 { 3041 CS_CPUSYSCTRL->HCLKRS = CSC_HCLKRS_MAILBOXSET_BIT; 3042 } 3043 cpusysctrl_hclkrs_asdmaset_getb(void)3044__STATIC_INLINE uint8_t cpusysctrl_hclkrs_asdmaset_getb(void) 3045 { 3046 return (CS_CPUSYSCTRL->HCLKRS & CSC_HCLKRS_ASDMASET_BIT) >> CSC_HCLKRS_ASDMASET_POS; 3047 } 3048 cpusysctrl_hclkrs_asdmaset_setb(void)3049__STATIC_INLINE void cpusysctrl_hclkrs_asdmaset_setb(void) 3050 { 3051 CS_CPUSYSCTRL->HCLKRS = CSC_HCLKRS_ASDMASET_BIT; 3052 } 3053 cpusysctrl_hclkrs_sdioset_getb(void)3054__STATIC_INLINE uint8_t cpusysctrl_hclkrs_sdioset_getb(void) 3055 { 3056 return (CS_CPUSYSCTRL->HCLKRS & CSC_HCLKRS_SDIOSET_BIT) >> CSC_HCLKRS_SDIOSET_POS; 3057 } 3058 cpusysctrl_hclkrs_sdioset_setb(void)3059__STATIC_INLINE void cpusysctrl_hclkrs_sdioset_setb(void) 3060 { 3061 CS_CPUSYSCTRL->HCLKRS = CSC_HCLKRS_SDIOSET_BIT; 3062 } 3063 cpusysctrl_hclkrs_cameraset_getb(void)3064__STATIC_INLINE uint8_t cpusysctrl_hclkrs_cameraset_getb(void) 3065 { 3066 return (CS_CPUSYSCTRL->HCLKRS & CSC_HCLKRS_CAMERASET_BIT) >> CSC_HCLKRS_CAMERASET_POS; 3067 } 3068 cpusysctrl_hclkrs_cameraset_setb(void)3069__STATIC_INLINE void cpusysctrl_hclkrs_cameraset_setb(void) 3070 { 3071 CS_CPUSYSCTRL->HCLKRS = CSC_HCLKRS_CAMERASET_BIT; 3072 } 3073 cpusysctrl_hclkrs_sram6set_getb(void)3074__STATIC_INLINE uint8_t cpusysctrl_hclkrs_sram6set_getb(void) 3075 { 3076 return (CS_CPUSYSCTRL->HCLKRS & CSC_HCLKRS_SRAM6SET_BIT) >> CSC_HCLKRS_SRAM6SET_POS; 3077 } 3078 cpusysctrl_hclkrs_sram6set_setb(void)3079__STATIC_INLINE void cpusysctrl_hclkrs_sram6set_setb(void) 3080 { 3081 CS_CPUSYSCTRL->HCLKRS = CSC_HCLKRS_SRAM6SET_BIT; 3082 } 3083 cpusysctrl_hclkrs_jpegencset_getb(void)3084__STATIC_INLINE uint8_t cpusysctrl_hclkrs_jpegencset_getb(void) 3085 { 3086 return (CS_CPUSYSCTRL->HCLKRS & CSC_HCLKRS_JPEGENCSET_BIT) >> CSC_HCLKRS_JPEGENCSET_POS; 3087 } 3088 cpusysctrl_hclkrs_jpegencset_setb(void)3089__STATIC_INLINE void cpusysctrl_hclkrs_jpegencset_setb(void) 3090 { 3091 CS_CPUSYSCTRL->HCLKRS = CSC_HCLKRS_JPEGENCSET_BIT; 3092 } 3093 3094 /** 3095 * Address Offset: 0x11C 3096 * Register Name : CSC HCLK_SOFT_RESETn_CLEAR (write 1 valid) 3097 */ 3098 3099 #define CSC_HCLKRC_CPUPCLR_POS (0) 3100 #define CSC_HCLKRC_CPUPCLR_BIT (0x01UL << CSC_HCLKRC_CPUPCLR_POS) 3101 #define CSC_HCLKRC_ROMCLR_POS (2) 3102 #define CSC_HCLKRC_ROMCLR_BIT (0x01UL << CSC_HCLKRC_ROMCLR_POS) 3103 #define CSC_HCLKRC_SRAM0CLR_POS (3) 3104 #define CSC_HCLKRC_SRAM0CLR_BIT (0x01UL << CSC_HCLKRC_SRAM0CLR_POS) 3105 #define CSC_HCLKRC_SRAM1CLR_POS (4) 3106 #define CSC_HCLKRC_SRAM1CLR_BIT (0x01UL << CSC_HCLKRC_SRAM1CLR_POS) 3107 #define CSC_HCLKRC_SRAM2CLR_POS (5) 3108 #define CSC_HCLKRC_SRAM2CLR_BIT (0x01UL << CSC_HCLKRC_SRAM2CLR_POS) 3109 #define CSC_HCLKRC_SRAM3CLR_POS (6) 3110 #define CSC_HCLKRC_SRAM3CLR_BIT (0x01UL << CSC_HCLKRC_SRAM3CLR_POS) 3111 #define CSC_HCLKRC_SRAM4CLR_POS (7) 3112 #define CSC_HCLKRC_SRAM4CLR_BIT (0x01UL << CSC_HCLKRC_SRAM4CLR_POS) 3113 #define CSC_HCLKRC_SRAM5CLR_POS (8) 3114 #define CSC_HCLKRC_SRAM5CLR_BIT (0x01UL << CSC_HCLKRC_SRAM5CLR_POS) 3115 #define CSC_HCLKRC_AHB0DECCLR_POS (9) 3116 #define CSC_HCLKRC_AHB0DECCLR_BIT (0x01UL << CSC_HCLKRC_AHB0DECCLR_POS) 3117 #define CSC_HCLKRC_AHB1DECCLR_POS (10) 3118 #define CSC_HCLKRC_AHB1DECCLR_BIT (0x01UL << CSC_HCLKRC_AHB1DECCLR_POS) 3119 #define CSC_HCLKRC_APB0CLR_POS (11) 3120 #define CSC_HCLKRC_APB0CLR_BIT (0x01UL << CSC_HCLKRC_APB0CLR_POS) 3121 #define CSC_HCLKRC_FLASHCLR_POS (12) 3122 #define CSC_HCLKRC_FLASHCLR_BIT (0x01UL << CSC_HCLKRC_FLASHCLR_POS) 3123 #define CSC_HCLKRC_DMACLR_POS (13) 3124 #define CSC_HCLKRC_DMACLR_BIT (0x01UL << CSC_HCLKRC_DMACLR_POS) 3125 #define CSC_HCLKRC_EXMEMBUSCLR_POS (14) 3126 #define CSC_HCLKRC_EXMEMBUSCLR_BIT (0x01UL << CSC_HCLKRC_EXMEMBUSCLR_POS) 3127 #define CSC_HCLKRC_CACHE0CLR_POS (15) 3128 #define CSC_HCLKRC_CACHE0CLR_BIT (0x01UL << CSC_HCLKRC_CACHE0CLR_POS) 3129 #define CSC_HCLKRC_CACHE1CLR_POS (16) 3130 #define CSC_HCLKRC_CACHE1CLR_BIT (0x01UL << CSC_HCLKRC_CACHE1CLR_POS) 3131 #define CSC_HCLKRC_PSRAMCLR_POS (17) 3132 #define CSC_HCLKRC_PSRAMCLR_BIT (0x01UL << CSC_HCLKRC_PSRAMCLR_POS) 3133 #define CSC_HCLKRC_PSRAMREGCLR_POS (18) 3134 #define CSC_HCLKRC_PSRAMREGCLR_BIT (0x01UL << CSC_HCLKRC_PSRAMREGCLR_POS) 3135 #define CSC_HCLKRC_TRAPCLR_POS (19) 3136 #define CSC_HCLKRC_TRAPCLR_BIT (0x01UL << CSC_HCLKRC_TRAPCLR_POS) 3137 #define CSC_HCLKRC_UART0CLR_POS (20) 3138 #define CSC_HCLKRC_UART0CLR_BIT (0x01UL << CSC_HCLKRC_UART0CLR_POS) 3139 #define CSC_HCLKRC_UART1CLR_POS (21) 3140 #define CSC_HCLKRC_UART1CLR_BIT (0x01UL << CSC_HCLKRC_UART1CLR_POS) 3141 #define CSC_HCLKRC_UART2CLR_POS (22) 3142 #define CSC_HCLKRC_UART2CLR_BIT (0x01UL << CSC_HCLKRC_UART2CLR_POS) 3143 #define CSC_HCLKRC_USBCCLR_POS (23) 3144 #define CSC_HCLKRC_USBCCLR_BIT (0x01UL << CSC_HCLKRC_USBCCLR_POS) 3145 #define CSC_HCLKRC_VPCCLR_POS (24) 3146 #define CSC_HCLKRC_VPCCLR_BIT (0x01UL << CSC_HCLKRC_VPCCLR_POS) 3147 #define CSC_HCLKRC_MAILBOXCLR_POS (25) 3148 #define CSC_HCLKRC_MAILBOXCLR_BIT (0x01UL << CSC_HCLKRC_MAILBOXCLR_POS) 3149 #define CSC_HCLKRC_ASDMACLR_POS (26) 3150 #define CSC_HCLKRC_ASDMACLR_BIT (0x01UL << CSC_HCLKRC_ASDMACLR_POS) 3151 #define CSC_HCLKRC_SDIOCLR_POS (27) 3152 #define CSC_HCLKRC_SDIOCLR_BIT (0x01UL << CSC_HCLKRC_SDIOCLR_POS) 3153 #define CSC_HCLKRC_CAMERACLR_POS (29) 3154 #define CSC_HCLKRC_CAMERACLR_BIT (0x01UL << CSC_HCLKRC_CAMERACLR_POS) 3155 #define CSC_HCLKRC_SRAM6CLR_POS (30) 3156 #define CSC_HCLKRC_SRAM6CLR_BIT (0x01UL << CSC_HCLKRC_SRAM6CLR_POS) 3157 #define CSC_HCLKRC_JPEGENCCLR_POS (31) 3158 #define CSC_HCLKRC_JPEGENCCLR_BIT (0x01UL << CSC_HCLKRC_JPEGENCCLR_POS) 3159 cpusysctrl_hclkrc_get()3160__STATIC_INLINE uint32_t cpusysctrl_hclkrc_get() 3161 { 3162 return CS_CPUSYSCTRL->HCLKRC; 3163 } 3164 cpusysctrl_hclkrc_set(uint32_t reset_bits)3165__STATIC_INLINE void cpusysctrl_hclkrc_set(uint32_t reset_bits) 3166 { 3167 CS_CPUSYSCTRL->HCLKRC = reset_bits; 3168 } 3169 cpusysctrl_hclkrc_cpupclr_getb(void)3170__STATIC_INLINE uint8_t cpusysctrl_hclkrc_cpupclr_getb(void) 3171 { 3172 return (CS_CPUSYSCTRL->HCLKRC & CSC_HCLKRC_CPUPCLR_BIT) >> CSC_HCLKRC_CPUPCLR_POS; 3173 } 3174 cpusysctrl_hclkrc_cpupclr_setb(void)3175__STATIC_INLINE void cpusysctrl_hclkrc_cpupclr_setb(void) 3176 { 3177 CS_CPUSYSCTRL->HCLKRC = CSC_HCLKRC_CPUPCLR_BIT; 3178 } 3179 cpusysctrl_hclkrc_romclr_getb(void)3180__STATIC_INLINE uint8_t cpusysctrl_hclkrc_romclr_getb(void) 3181 { 3182 return (CS_CPUSYSCTRL->HCLKRC & CSC_HCLKRC_ROMCLR_BIT) >> CSC_HCLKRC_ROMCLR_POS; 3183 } 3184 cpusysctrl_hclkrc_romclr_setb(void)3185__STATIC_INLINE void cpusysctrl_hclkrc_romclr_setb(void) 3186 { 3187 CS_CPUSYSCTRL->HCLKRC = CSC_HCLKRC_ROMCLR_BIT; 3188 } 3189 cpusysctrl_hclkrc_sram0clr_getb(void)3190__STATIC_INLINE uint8_t cpusysctrl_hclkrc_sram0clr_getb(void) 3191 { 3192 return (CS_CPUSYSCTRL->HCLKRC & CSC_HCLKRC_SRAM0CLR_BIT) >> CSC_HCLKRC_SRAM0CLR_POS; 3193 } 3194 cpusysctrl_hclkrc_sram0clr_setb(void)3195__STATIC_INLINE void cpusysctrl_hclkrc_sram0clr_setb(void) 3196 { 3197 CS_CPUSYSCTRL->HCLKRC = CSC_HCLKRC_SRAM0CLR_BIT; 3198 } 3199 cpusysctrl_hclkrc_sram1clr_getb(void)3200__STATIC_INLINE uint8_t cpusysctrl_hclkrc_sram1clr_getb(void) 3201 { 3202 return (CS_CPUSYSCTRL->HCLKRC & CSC_HCLKRC_SRAM1CLR_BIT) >> CSC_HCLKRC_SRAM1CLR_POS; 3203 } 3204 cpusysctrl_hclkrc_sram1clr_setb(void)3205__STATIC_INLINE void cpusysctrl_hclkrc_sram1clr_setb(void) 3206 { 3207 CS_CPUSYSCTRL->HCLKRC = CSC_HCLKRC_SRAM1CLR_BIT; 3208 } 3209 cpusysctrl_hclkrc_sram2clr_getb(void)3210__STATIC_INLINE uint8_t cpusysctrl_hclkrc_sram2clr_getb(void) 3211 { 3212 return (CS_CPUSYSCTRL->HCLKRC & CSC_HCLKRC_SRAM2CLR_BIT) >> CSC_HCLKRC_SRAM2CLR_POS; 3213 } 3214 cpusysctrl_hclkrc_sram2clr_setb(void)3215__STATIC_INLINE void cpusysctrl_hclkrc_sram2clr_setb(void) 3216 { 3217 CS_CPUSYSCTRL->HCLKRC = CSC_HCLKRC_SRAM2CLR_BIT; 3218 } 3219 cpusysctrl_hclkrc_sram3clr_getb(void)3220__STATIC_INLINE uint8_t cpusysctrl_hclkrc_sram3clr_getb(void) 3221 { 3222 return (CS_CPUSYSCTRL->HCLKRC & CSC_HCLKRC_SRAM3CLR_BIT) >> CSC_HCLKRC_SRAM3CLR_POS; 3223 } 3224 cpusysctrl_hclkrc_sram3clr_setb(void)3225__STATIC_INLINE void cpusysctrl_hclkrc_sram3clr_setb(void) 3226 { 3227 CS_CPUSYSCTRL->HCLKRC = CSC_HCLKRC_SRAM3CLR_BIT; 3228 } 3229 cpusysctrl_hclkrc_sram4clr_getb(void)3230__STATIC_INLINE uint8_t cpusysctrl_hclkrc_sram4clr_getb(void) 3231 { 3232 return (CS_CPUSYSCTRL->HCLKRC & CSC_HCLKRC_SRAM4CLR_BIT) >> CSC_HCLKRC_SRAM4CLR_POS; 3233 } 3234 cpusysctrl_hclkrc_sram4clr_setb(void)3235__STATIC_INLINE void cpusysctrl_hclkrc_sram4clr_setb(void) 3236 { 3237 CS_CPUSYSCTRL->HCLKRC = CSC_HCLKRC_SRAM4CLR_BIT; 3238 } 3239 cpusysctrl_hclkrc_sram5clr_getb(void)3240__STATIC_INLINE uint8_t cpusysctrl_hclkrc_sram5clr_getb(void) 3241 { 3242 return (CS_CPUSYSCTRL->HCLKRC & CSC_HCLKRC_SRAM5CLR_BIT) >> CSC_HCLKRC_SRAM5CLR_POS; 3243 } 3244 cpusysctrl_hclkrc_sram5clr_setb(void)3245__STATIC_INLINE void cpusysctrl_hclkrc_sram5clr_setb(void) 3246 { 3247 CS_CPUSYSCTRL->HCLKRC = CSC_HCLKRC_SRAM5CLR_BIT; 3248 } 3249 cpusysctrl_hclkrc_ahb0decclr_getb(void)3250__STATIC_INLINE uint8_t cpusysctrl_hclkrc_ahb0decclr_getb(void) 3251 { 3252 return (CS_CPUSYSCTRL->HCLKRC & CSC_HCLKRC_AHB0DECCLR_BIT) >> CSC_HCLKRC_AHB0DECCLR_POS; 3253 } 3254 cpusysctrl_hclkrc_ahb0decclr_setb(void)3255__STATIC_INLINE void cpusysctrl_hclkrc_ahb0decclr_setb(void) 3256 { 3257 CS_CPUSYSCTRL->HCLKRC = CSC_HCLKRC_AHB0DECCLR_BIT; 3258 } 3259 cpusysctrl_hclkrc_ahb1decclr_getb(void)3260__STATIC_INLINE uint8_t cpusysctrl_hclkrc_ahb1decclr_getb(void) 3261 { 3262 return (CS_CPUSYSCTRL->HCLKRC & CSC_HCLKRC_AHB1DECCLR_BIT) >> CSC_HCLKRC_AHB1DECCLR_POS; 3263 } 3264 cpusysctrl_hclkrc_ahb1decclr_setb(void)3265__STATIC_INLINE void cpusysctrl_hclkrc_ahb1decclr_setb(void) 3266 { 3267 CS_CPUSYSCTRL->HCLKRC = CSC_HCLKRC_AHB1DECCLR_BIT; 3268 } 3269 cpusysctrl_hclkrc_apb0clr_getb(void)3270__STATIC_INLINE uint8_t cpusysctrl_hclkrc_apb0clr_getb(void) 3271 { 3272 return (CS_CPUSYSCTRL->HCLKRC & CSC_HCLKRC_APB0CLR_BIT) >> CSC_HCLKRC_APB0CLR_POS; 3273 } 3274 cpusysctrl_hclkrc_apb0clr_setb(void)3275__STATIC_INLINE void cpusysctrl_hclkrc_apb0clr_setb(void) 3276 { 3277 CS_CPUSYSCTRL->HCLKRC = CSC_HCLKRC_APB0CLR_BIT; 3278 } 3279 cpusysctrl_hclkrc_flashclr_getb(void)3280__STATIC_INLINE uint8_t cpusysctrl_hclkrc_flashclr_getb(void) 3281 { 3282 return (CS_CPUSYSCTRL->HCLKRC & CSC_HCLKRC_FLASHCLR_BIT) >> CSC_HCLKRC_FLASHCLR_POS; 3283 } 3284 cpusysctrl_hclkrc_flashclr_setb(void)3285__STATIC_INLINE void cpusysctrl_hclkrc_flashclr_setb(void) 3286 { 3287 CS_CPUSYSCTRL->HCLKRC = CSC_HCLKRC_FLASHCLR_BIT; 3288 } 3289 cpusysctrl_hclkrc_dmaclr_getb(void)3290__STATIC_INLINE uint8_t cpusysctrl_hclkrc_dmaclr_getb(void) 3291 { 3292 return (CS_CPUSYSCTRL->HCLKRC & CSC_HCLKRC_DMACLR_BIT) >> CSC_HCLKRC_DMACLR_POS; 3293 } 3294 cpusysctrl_hclkrc_dmaclr_setb(void)3295__STATIC_INLINE void cpusysctrl_hclkrc_dmaclr_setb(void) 3296 { 3297 CS_CPUSYSCTRL->HCLKRC = CSC_HCLKRC_DMACLR_BIT; 3298 } 3299 cpusysctrl_hclkrc_exmembusclr_getb(void)3300__STATIC_INLINE uint8_t cpusysctrl_hclkrc_exmembusclr_getb(void) 3301 { 3302 return (CS_CPUSYSCTRL->HCLKRC & CSC_HCLKRC_EXMEMBUSCLR_BIT) >> CSC_HCLKRC_EXMEMBUSCLR_POS; 3303 } 3304 cpusysctrl_hclkrc_exmembusclr_setb(void)3305__STATIC_INLINE void cpusysctrl_hclkrc_exmembusclr_setb(void) 3306 { 3307 CS_CPUSYSCTRL->HCLKRC = CSC_HCLKRC_EXMEMBUSCLR_BIT; 3308 } 3309 cpusysctrl_hclkrc_cache0clr_getb(void)3310__STATIC_INLINE uint8_t cpusysctrl_hclkrc_cache0clr_getb(void) 3311 { 3312 return (CS_CPUSYSCTRL->HCLKRC & CSC_HCLKRC_CACHE0CLR_BIT) >> CSC_HCLKRC_CACHE0CLR_POS; 3313 } 3314 cpusysctrl_hclkrc_cache0clr_setb(void)3315__STATIC_INLINE void cpusysctrl_hclkrc_cache0clr_setb(void) 3316 { 3317 CS_CPUSYSCTRL->HCLKRC = CSC_HCLKRC_CACHE0CLR_BIT; 3318 } 3319 cpusysctrl_hclkrc_cache1clr_getb(void)3320__STATIC_INLINE uint8_t cpusysctrl_hclkrc_cache1clr_getb(void) 3321 { 3322 return (CS_CPUSYSCTRL->HCLKRC & CSC_HCLKRC_CACHE1CLR_BIT) >> CSC_HCLKRC_CACHE1CLR_POS; 3323 } 3324 cpusysctrl_hclkrc_cache1clr_setb(void)3325__STATIC_INLINE void cpusysctrl_hclkrc_cache1clr_setb(void) 3326 { 3327 CS_CPUSYSCTRL->HCLKRC = CSC_HCLKRC_CACHE1CLR_BIT; 3328 } 3329 cpusysctrl_hclkrc_psramclr_getb(void)3330__STATIC_INLINE uint8_t cpusysctrl_hclkrc_psramclr_getb(void) 3331 { 3332 return (CS_CPUSYSCTRL->HCLKRC & CSC_HCLKRC_PSRAMCLR_BIT) >> CSC_HCLKRC_PSRAMCLR_POS; 3333 } 3334 cpusysctrl_hclkrc_psramclr_setb(void)3335__STATIC_INLINE void cpusysctrl_hclkrc_psramclr_setb(void) 3336 { 3337 CS_CPUSYSCTRL->HCLKRC = CSC_HCLKRC_PSRAMCLR_BIT; 3338 } 3339 cpusysctrl_hclkrc_psramregclr_getb(void)3340__STATIC_INLINE uint8_t cpusysctrl_hclkrc_psramregclr_getb(void) 3341 { 3342 return (CS_CPUSYSCTRL->HCLKRC & CSC_HCLKRC_PSRAMREGCLR_BIT) >> CSC_HCLKRC_PSRAMREGCLR_POS; 3343 } 3344 cpusysctrl_hclkrc_psramregclr_setb(void)3345__STATIC_INLINE void cpusysctrl_hclkrc_psramregclr_setb(void) 3346 { 3347 CS_CPUSYSCTRL->HCLKRC = CSC_HCLKRC_PSRAMREGCLR_BIT; 3348 } 3349 cpusysctrl_hclkrc_trapclr_getb(void)3350__STATIC_INLINE uint8_t cpusysctrl_hclkrc_trapclr_getb(void) 3351 { 3352 return (CS_CPUSYSCTRL->HCLKRC & CSC_HCLKRC_TRAPCLR_BIT) >> CSC_HCLKRC_TRAPCLR_POS; 3353 } 3354 cpusysctrl_hclkrc_trapclr_setb(void)3355__STATIC_INLINE void cpusysctrl_hclkrc_trapclr_setb(void) 3356 { 3357 CS_CPUSYSCTRL->HCLKRC = CSC_HCLKRC_TRAPCLR_BIT; 3358 } 3359 cpusysctrl_hclkrc_uart0clr_getb(void)3360__STATIC_INLINE uint8_t cpusysctrl_hclkrc_uart0clr_getb(void) 3361 { 3362 return (CS_CPUSYSCTRL->HCLKRC & CSC_HCLKRC_UART0CLR_BIT) >> CSC_HCLKRC_UART0CLR_POS; 3363 } 3364 cpusysctrl_hclkrc_uart0clr_setb(void)3365__STATIC_INLINE void cpusysctrl_hclkrc_uart0clr_setb(void) 3366 { 3367 CS_CPUSYSCTRL->HCLKRC = CSC_HCLKRC_UART0CLR_BIT; 3368 } 3369 cpusysctrl_hclkrc_uart1clr_getb(void)3370__STATIC_INLINE uint8_t cpusysctrl_hclkrc_uart1clr_getb(void) 3371 { 3372 return (CS_CPUSYSCTRL->HCLKRC & CSC_HCLKRC_UART1CLR_BIT) >> CSC_HCLKRC_UART1CLR_POS; 3373 } 3374 cpusysctrl_hclkrc_uart1clr_setb(void)3375__STATIC_INLINE void cpusysctrl_hclkrc_uart1clr_setb(void) 3376 { 3377 CS_CPUSYSCTRL->HCLKRC = CSC_HCLKRC_UART1CLR_BIT; 3378 } 3379 cpusysctrl_hclkrc_uart2clr_getb(void)3380__STATIC_INLINE uint8_t cpusysctrl_hclkrc_uart2clr_getb(void) 3381 { 3382 return (CS_CPUSYSCTRL->HCLKRC & CSC_HCLKRC_UART2CLR_BIT) >> CSC_HCLKRC_UART2CLR_POS; 3383 } 3384 cpusysctrl_hclkrc_uart2clr_setb(void)3385__STATIC_INLINE void cpusysctrl_hclkrc_uart2clr_setb(void) 3386 { 3387 CS_CPUSYSCTRL->HCLKRC = CSC_HCLKRC_UART2CLR_BIT; 3388 } 3389 cpusysctrl_hclkrc_usbcclr_getb(void)3390__STATIC_INLINE uint8_t cpusysctrl_hclkrc_usbcclr_getb(void) 3391 { 3392 return (CS_CPUSYSCTRL->HCLKRC & CSC_HCLKRC_USBCCLR_BIT) >> CSC_HCLKRC_USBCCLR_POS; 3393 } 3394 cpusysctrl_hclkrc_usbcclr_setb(void)3395__STATIC_INLINE void cpusysctrl_hclkrc_usbcclr_setb(void) 3396 { 3397 CS_CPUSYSCTRL->HCLKRC = CSC_HCLKRC_USBCCLR_BIT; 3398 } 3399 cpusysctrl_hclkrc_vpcclr_getb(void)3400__STATIC_INLINE uint8_t cpusysctrl_hclkrc_vpcclr_getb(void) 3401 { 3402 return (CS_CPUSYSCTRL->HCLKRC & CSC_HCLKRC_VPCCLR_BIT) >> CSC_HCLKRC_VPCCLR_POS; 3403 } 3404 cpusysctrl_hclkrc_vpcclr_setb(void)3405__STATIC_INLINE void cpusysctrl_hclkrc_vpcclr_setb(void) 3406 { 3407 CS_CPUSYSCTRL->HCLKRC = CSC_HCLKRC_VPCCLR_BIT; 3408 } 3409 cpusysctrl_hclkrc_mailboxclr_getb(void)3410__STATIC_INLINE uint8_t cpusysctrl_hclkrc_mailboxclr_getb(void) 3411 { 3412 return (CS_CPUSYSCTRL->HCLKRC & CSC_HCLKRC_MAILBOXCLR_BIT) >> CSC_HCLKRC_MAILBOXCLR_POS; 3413 } 3414 cpusysctrl_hclkrc_mailboxclr_setb(void)3415__STATIC_INLINE void cpusysctrl_hclkrc_mailboxclr_setb(void) 3416 { 3417 CS_CPUSYSCTRL->HCLKRC = CSC_HCLKRC_MAILBOXCLR_BIT; 3418 } 3419 cpusysctrl_hclkrc_asdmaclr_getb(void)3420__STATIC_INLINE uint8_t cpusysctrl_hclkrc_asdmaclr_getb(void) 3421 { 3422 return (CS_CPUSYSCTRL->HCLKRC & CSC_HCLKRC_ASDMACLR_BIT) >> CSC_HCLKRC_ASDMACLR_POS; 3423 } 3424 cpusysctrl_hclkrc_asdmaclr_setb(void)3425__STATIC_INLINE void cpusysctrl_hclkrc_asdmaclr_setb(void) 3426 { 3427 CS_CPUSYSCTRL->HCLKRC = CSC_HCLKRC_ASDMACLR_BIT; 3428 } 3429 cpusysctrl_hclkrc_sdioclr_getb(void)3430__STATIC_INLINE uint8_t cpusysctrl_hclkrc_sdioclr_getb(void) 3431 { 3432 return (CS_CPUSYSCTRL->HCLKRC & CSC_HCLKRC_SDIOCLR_BIT) >> CSC_HCLKRC_SDIOCLR_POS; 3433 } 3434 cpusysctrl_hclkrc_sdioclr_setb(void)3435__STATIC_INLINE void cpusysctrl_hclkrc_sdioclr_setb(void) 3436 { 3437 CS_CPUSYSCTRL->HCLKRC = CSC_HCLKRC_SDIOCLR_BIT; 3438 } 3439 cpusysctrl_hclkrc_cameraclr_getb(void)3440__STATIC_INLINE uint8_t cpusysctrl_hclkrc_cameraclr_getb(void) 3441 { 3442 return (CS_CPUSYSCTRL->HCLKRC & CSC_HCLKRC_CAMERACLR_BIT) >> CSC_HCLKRC_CAMERACLR_POS; 3443 } 3444 cpusysctrl_hclkrc_cameraclr_setb(void)3445__STATIC_INLINE void cpusysctrl_hclkrc_cameraclr_setb(void) 3446 { 3447 CS_CPUSYSCTRL->HCLKRC = CSC_HCLKRC_CAMERACLR_BIT; 3448 } 3449 cpusysctrl_hclkrc_sram6clr_getb(void)3450__STATIC_INLINE uint8_t cpusysctrl_hclkrc_sram6clr_getb(void) 3451 { 3452 return (CS_CPUSYSCTRL->HCLKRC & CSC_HCLKRC_SRAM6CLR_BIT) >> CSC_HCLKRC_SRAM6CLR_POS; 3453 } 3454 cpusysctrl_hclkrc_sram6clr_setb(void)3455__STATIC_INLINE void cpusysctrl_hclkrc_sram6clr_setb(void) 3456 { 3457 CS_CPUSYSCTRL->HCLKRC = CSC_HCLKRC_SRAM6CLR_BIT; 3458 } 3459 cpusysctrl_hclkrc_jpegencclr_getb(void)3460__STATIC_INLINE uint8_t cpusysctrl_hclkrc_jpegencclr_getb(void) 3461 { 3462 return (CS_CPUSYSCTRL->HCLKRC & CSC_HCLKRC_JPEGENCCLR_BIT) >> CSC_HCLKRC_JPEGENCCLR_POS; 3463 } 3464 cpusysctrl_hclkrc_jpegencclr_setb(void)3465__STATIC_INLINE void cpusysctrl_hclkrc_jpegencclr_setb(void) 3466 { 3467 CS_CPUSYSCTRL->HCLKRC = CSC_HCLKRC_JPEGENCCLR_BIT; 3468 } 3469 3470 /** 3471 * Address Offset: 0x120 3472 * Register Name : CSC PCLK_SOFT_RESETn_SET (write 1 valid) 3473 */ 3474 3475 #define CSC_PCLKRS_CPUSYSCTRLSET_POS (0) 3476 #define CSC_PCLKRS_CPUSYSCTRLSET_BIT (0x01UL << CSC_PCLKRS_CPUSYSCTRLSET_POS) 3477 cpusysctrl_pclkrs_get()3478__STATIC_INLINE uint32_t cpusysctrl_pclkrs_get() 3479 { 3480 return CS_CPUSYSCTRL->PCLKRS; 3481 } 3482 cpusysctrl_pclkrs_set(uint32_t reset_bits)3483__STATIC_INLINE void cpusysctrl_pclkrs_set(uint32_t reset_bits) 3484 { 3485 CS_CPUSYSCTRL->PCLKRS = reset_bits; 3486 } 3487 cpusysctrl_pclkrs_cpusysctrlset_getb(void)3488__STATIC_INLINE uint8_t cpusysctrl_pclkrs_cpusysctrlset_getb(void) 3489 { 3490 return (CS_CPUSYSCTRL->PCLKRS & CSC_PCLKRS_CPUSYSCTRLSET_BIT) >> CSC_PCLKRS_CPUSYSCTRLSET_POS; 3491 } 3492 cpusysctrl_pclkrs_cpusysctrlset_setb(void)3493__STATIC_INLINE void cpusysctrl_pclkrs_cpusysctrlset_setb(void) 3494 { 3495 CS_CPUSYSCTRL->PCLKRS = CSC_PCLKRS_CPUSYSCTRLSET_BIT; 3496 } 3497 3498 /** 3499 * Address Offset: 0x124 3500 * Register Name : CSC PCLK_SOFT_RESETn_CLEAR (write 1 valid) 3501 */ 3502 3503 #define CSC_PCLKRC_CPUSYSCTRLCLR_POS (0) 3504 #define CSC_PCLKRC_CPUSYSCTRLCLR_BIT (0x01UL << CSC_PCLKRC_CPUSYSCTRLCLR_POS) 3505 cpusysctrl_pclkrc_get()3506__STATIC_INLINE uint32_t cpusysctrl_pclkrc_get() 3507 { 3508 return CS_CPUSYSCTRL->PCLKRC; 3509 } 3510 cpusysctrl_pclkrc_set(uint32_t reset_bits)3511__STATIC_INLINE void cpusysctrl_pclkrc_set(uint32_t reset_bits) 3512 { 3513 CS_CPUSYSCTRL->PCLKRC = reset_bits; 3514 } 3515 cpusysctrl_pclkrc_cpusysctrlclr_getb(void)3516__STATIC_INLINE uint8_t cpusysctrl_pclkrc_cpusysctrlclr_getb(void) 3517 { 3518 return (CS_CPUSYSCTRL->PCLKRC & CSC_PCLKRC_CPUSYSCTRLCLR_BIT) >> CSC_PCLKRC_CPUSYSCTRLCLR_POS; 3519 } 3520 cpusysctrl_pclkrc_cpusysctrlclr_setb(void)3521__STATIC_INLINE void cpusysctrl_pclkrc_cpusysctrlclr_setb(void) 3522 { 3523 CS_CPUSYSCTRL->PCLKRC = CSC_PCLKRC_CPUSYSCTRLCLR_BIT; 3524 } 3525 3526 /** 3527 * Address Offset: 0x128 3528 * Register Name : CSC OTHERS_SOFT_RESETn_SET (write 1 valid) 3529 */ 3530 3531 #define CSC_OCLKRS_SDIOSET_POS (0) 3532 #define CSC_OCLKRS_SDIOSET_BIT (0x01UL << CSC_OCLKRS_SDIOSET_POS) 3533 #define CSC_OCLKRS_ASDMASET_POS (1) 3534 #define CSC_OCLKRS_ASDMASET_BIT (0x01UL << CSC_OCLKRS_ASDMASET_POS) 3535 #define CSC_OCLKRS_ULPISET_POS (10) 3536 #define CSC_OCLKRS_ULPISET_BIT (0x01UL << CSC_OCLKRS_ULPISET_POS) 3537 cpusysctrl_oclkrs_get()3538__STATIC_INLINE uint32_t cpusysctrl_oclkrs_get() 3539 { 3540 return CS_CPUSYSCTRL->OCLKRS; 3541 } 3542 cpusysctrl_oclkrs_set(uint32_t reset_bits)3543__STATIC_INLINE void cpusysctrl_oclkrs_set(uint32_t reset_bits) 3544 { 3545 CS_CPUSYSCTRL->OCLKRS = reset_bits; 3546 } 3547 cpusysctrl_oclkrs_sdioset_getb(void)3548__STATIC_INLINE uint8_t cpusysctrl_oclkrs_sdioset_getb(void) 3549 { 3550 return (CS_CPUSYSCTRL->OCLKRS & CSC_OCLKRS_SDIOSET_BIT) >> CSC_OCLKRS_SDIOSET_POS; 3551 } 3552 cpusysctrl_oclkrs_sdioset_setb(void)3553__STATIC_INLINE void cpusysctrl_oclkrs_sdioset_setb(void) 3554 { 3555 CS_CPUSYSCTRL->OCLKRS = CSC_OCLKRS_SDIOSET_BIT; 3556 } 3557 cpusysctrl_oclkrs_asdmaset_getb(void)3558__STATIC_INLINE uint8_t cpusysctrl_oclkrs_asdmaset_getb(void) 3559 { 3560 return (CS_CPUSYSCTRL->OCLKRS & CSC_OCLKRS_ASDMASET_BIT) >> CSC_OCLKRS_ASDMASET_POS; 3561 } 3562 cpusysctrl_oclkrs_asdmaset_setb(void)3563__STATIC_INLINE void cpusysctrl_oclkrs_asdmaset_setb(void) 3564 { 3565 CS_CPUSYSCTRL->OCLKRS = CSC_OCLKRS_ASDMASET_BIT; 3566 } 3567 cpusysctrl_oclkrs_ulpiset_getb(void)3568__STATIC_INLINE uint8_t cpusysctrl_oclkrs_ulpiset_getb(void) 3569 { 3570 return (CS_CPUSYSCTRL->OCLKRS & CSC_OCLKRS_ULPISET_BIT) >> CSC_OCLKRS_ULPISET_POS; 3571 } 3572 cpusysctrl_oclkrs_ulpiset_setb(void)3573__STATIC_INLINE void cpusysctrl_oclkrs_ulpiset_setb(void) 3574 { 3575 CS_CPUSYSCTRL->OCLKRS = CSC_OCLKRS_ULPISET_BIT; 3576 } 3577 3578 /** 3579 * Address Offset: 0x12C 3580 * Register Name : CSC OTHERS_SOFT_RESETn_CLEAR (write 1 valid) 3581 */ 3582 3583 #define CSC_OCLKRC_SDIOCLR_POS (0) 3584 #define CSC_OCLKRC_SDIOCLR_BIT (0x01UL << CSC_OCLKRC_SDIOCLR_POS) 3585 #define CSC_OCLKRC_ASDMACLR_POS (1) 3586 #define CSC_OCLKRC_ASDMACLR_BIT (0x01UL << CSC_OCLKRC_ASDMACLR_POS) 3587 #define CSC_OCLKRC_ULPICLR_POS (10) 3588 #define CSC_OCLKRC_ULPICLR_BIT (0x01UL << CSC_OCLKRC_ULPICLR_POS) 3589 cpusysctrl_oclkrc_get()3590__STATIC_INLINE uint32_t cpusysctrl_oclkrc_get() 3591 { 3592 return CS_CPUSYSCTRL->OCLKRC; 3593 } 3594 cpusysctrl_oclkrc_set(uint32_t reset_bits)3595__STATIC_INLINE void cpusysctrl_oclkrc_set(uint32_t reset_bits) 3596 { 3597 CS_CPUSYSCTRL->OCLKRC = reset_bits; 3598 } 3599 cpusysctrl_oclkrc_sdioclr_getb(void)3600__STATIC_INLINE uint8_t cpusysctrl_oclkrc_sdioclr_getb(void) 3601 { 3602 return (CS_CPUSYSCTRL->OCLKRC & CSC_OCLKRC_SDIOCLR_BIT) >> CSC_OCLKRC_SDIOCLR_POS; 3603 } 3604 cpusysctrl_oclkrc_sdioclr_setb(void)3605__STATIC_INLINE void cpusysctrl_oclkrc_sdioclr_setb(void) 3606 { 3607 CS_CPUSYSCTRL->OCLKRC = CSC_OCLKRC_SDIOCLR_BIT; 3608 } 3609 cpusysctrl_oclkrc_asdmaclr_getb(void)3610__STATIC_INLINE uint8_t cpusysctrl_oclkrc_asdmaclr_getb(void) 3611 { 3612 return (CS_CPUSYSCTRL->OCLKRC & CSC_OCLKRC_ASDMACLR_BIT) >> CSC_OCLKRC_ASDMACLR_POS; 3613 } 3614 cpusysctrl_oclkrc_asdmaclr_setb(void)3615__STATIC_INLINE void cpusysctrl_oclkrc_asdmaclr_setb(void) 3616 { 3617 CS_CPUSYSCTRL->OCLKRC = CSC_OCLKRC_ASDMACLR_BIT; 3618 } 3619 cpusysctrl_oclkrc_ulpiclr_getb(void)3620__STATIC_INLINE uint8_t cpusysctrl_oclkrc_ulpiclr_getb(void) 3621 { 3622 return (CS_CPUSYSCTRL->OCLKRC & CSC_OCLKRC_ULPICLR_BIT) >> CSC_OCLKRC_ULPICLR_POS; 3623 } 3624 cpusysctrl_oclkrc_ulpiclr_setb(void)3625__STATIC_INLINE void cpusysctrl_oclkrc_ulpiclr_setb(void) 3626 { 3627 CS_CPUSYSCTRL->OCLKRC = CSC_OCLKRC_ULPICLR_BIT; 3628 } 3629 3630 /** 3631 * Address Offset: 0x130 3632 * Register Name : CSC HCLK1_MANUAL_ENABLE (write 1 valid) 3633 */ 3634 3635 #define CSC_HCLK1ME_DSP_EN_POS (0) 3636 #define CSC_HCLK1ME_DSP_EN_BIT (0x01UL << CSC_HCLK1ME_DSP_EN_POS) 3637 #define CSC_HCLK1ME_DSP_GATED_EN_POS (1) 3638 #define CSC_HCLK1ME_DSP_GATED_EN_BIT (0x01UL << CSC_HCLK1ME_DSP_GATED_EN_POS) 3639 #define CSC_HCLK1ME_CAMERA_EN_POS (2) 3640 #define CSC_HCLK1ME_CAMERA_EN_BIT (0x01UL << CSC_HCLK1ME_CAMERA_EN_POS) 3641 #define CSC_HCLK1ME_SPI_CAMERA_EN_POS (3) 3642 #define CSC_HCLK1ME_SPI_CAMERA_EN_BIT (0x01UL << CSC_HCLK1ME_SPI_CAMERA_EN_POS) 3643 #define CSC_HCLK1ME_JPEG_ENC_EN_POS (4) 3644 #define CSC_HCLK1ME_JPEG_ENC_EN_BIT (0x01UL << CSC_HCLK1ME_JPEG_ENC_EN_POS) 3645 #define CSC_HCLK1ME_BTROM_EN_POS (5) 3646 #define CSC_HCLK1ME_BTROM_EN_BIT (0x01UL << CSC_HCLK1ME_BTROM_EN_POS) 3647 #define CSC_HCLK1ME_DSP_MATRIX_EN_POS (6) 3648 #define CSC_HCLK1ME_DSP_MATRIX_EN_BIT (0x01UL << CSC_HCLK1ME_DSP_MATRIX_EN_POS) 3649 #define CSC_HCLK1ME_SRAM6_EN_POS (7) 3650 #define CSC_HCLK1ME_SRAM6_EN_BIT (0x01UL << CSC_HCLK1ME_SRAM6_EN_POS) 3651 #define CSC_HCLK1ME_SDMMC_ALWAYS_EN_POS (8) 3652 #define CSC_HCLK1ME_SDMMC_ALWAYS_EN_BIT (0x01UL << CSC_HCLK1ME_SDMMC_ALWAYS_EN_POS) 3653 #define CSC_HCLK1ME_SDMMC_EN_POS (9) 3654 #define CSC_HCLK1ME_SDMMC_EN_BIT (0x01UL << CSC_HCLK1ME_SDMMC_EN_POS) 3655 #define CSC_HCLK1ME_CPUSB_EN_POS (10) 3656 #define CSC_HCLK1ME_CPUSB_EN_BIT (0x01UL << CSC_HCLK1ME_CPUSB_EN_POS) 3657 #define CSC_HCLK1ME_CPUSB_GATED_EN_POS (11) 3658 #define CSC_HCLK1ME_CPUSB_GATED_EN_BIT (0x01UL << CSC_HCLK1ME_CPUSB_GATED_EN_POS) 3659 #define CSC_HCLK1ME_SRAM5_LOW_EN_POS (12) 3660 #define CSC_HCLK1ME_SRAM5_LOW_EN_BIT (0x01UL << CSC_HCLK1ME_SRAM5_LOW_EN_POS) 3661 #define CSC_HCLK1ME_SRAM5_HIGH_EN_POS (13) 3662 #define CSC_HCLK1ME_SRAM5_HIGH_EN_BIT (0x01UL << CSC_HCLK1ME_SRAM5_HIGH_EN_POS) 3663 #define CSC_HCLK1ME_MM_EN_POS (14) 3664 #define CSC_HCLK1ME_MM_EN_BIT (0x01UL << CSC_HCLK1ME_MM_EN_POS) 3665 cpusysctrl_hclk1me_get()3666__STATIC_INLINE uint32_t cpusysctrl_hclk1me_get() 3667 { 3668 return CS_CPUSYSCTRL->HCLK1ME; 3669 } 3670 cpusysctrl_hclk1me_set(uint32_t enable_bits)3671__STATIC_INLINE void cpusysctrl_hclk1me_set(uint32_t enable_bits) 3672 { 3673 CS_CPUSYSCTRL->HCLK1ME = enable_bits; 3674 } 3675 3676 /** 3677 * Address Offset: 0x134 3678 * Register Name : CSC HCLK1_MANUAL_DISABLE (write 1 valid) 3679 */ 3680 3681 #define CSC_HCLK1MD_DSP_DIS_POS (0) 3682 #define CSC_HCLK1MD_DSP_DIS_BIT (0x01UL << CSC_HCLK1MD_DSP_DIS_POS) 3683 #define CSC_HCLK1MD_DSP_GATED_DIS_POS (1) 3684 #define CSC_HCLK1MD_DSP_GATED_DIS_BIT (0x01UL << CSC_HCLK1MD_DSP_GATED_DIS_POS) 3685 #define CSC_HCLK1MD_CAMERA_DIS_POS (2) 3686 #define CSC_HCLK1MD_CAMERA_DIS_BIT (0x01UL << CSC_HCLK1MD_CAMERA_DIS_POS) 3687 #define CSC_HCLK1MD_SPI_CAMERA_DIS_POS (3) 3688 #define CSC_HCLK1MD_SPI_CAMERA_DIS_BIT (0x01UL << CSC_HCLK1MD_SPI_CAMERA_DIS_POS) 3689 #define CSC_HCLK1MD_JPEG_ENC_DIS_POS (4) 3690 #define CSC_HCLK1MD_JPEG_ENC_DIS_BIT (0x01UL << CSC_HCLK1MD_JPEG_ENC_DIS_POS) 3691 #define CSC_HCLK1MD_BTROM_DIS_POS (5) 3692 #define CSC_HCLK1MD_BTROM_DIS_BIT (0x01UL << CSC_HCLK1MD_BTROM_DIS_POS) 3693 #define CSC_HCLK1MD_DSP_MATRIX_DIS_POS (6) 3694 #define CSC_HCLK1MD_DSP_MATRIX_DIS_BIT (0x01UL << CSC_HCLK1MD_DSP_MATRIX_DIS_POS) 3695 #define CSC_HCLK1MD_SRAM6_DIS_POS (7) 3696 #define CSC_HCLK1MD_SRAM6_DIS_BIT (0x01UL << CSC_HCLK1MD_SRAM6_DIS_POS) 3697 #define CSC_HCLK1MD_SDMMC_ALWAYS_DIS_POS (8) 3698 #define CSC_HCLK1MD_SDMMC_ALWAYS_DIS_BIT (0x01UL << CSC_HCLK1MD_SDMMC_ALWAYS_DIS_POS) 3699 #define CSC_HCLK1MD_SDMMC_DIS_POS (9) 3700 #define CSC_HCLK1MD_SDMMC_DIS_BIT (0x01UL << CSC_HCLK1MD_SDMMC_DIS_POS) 3701 #define CSC_HCLK1MD_CPUSB_DIS_POS (10) 3702 #define CSC_HCLK1MD_CPUSB_DIS_BIT (0x01UL << CSC_HCLK1MD_CPUSB_DIS_POS) 3703 #define CSC_HCLK1MD_CPUSB_GATED_DIS_POS (11) 3704 #define CSC_HCLK1MD_CPUSB_GATED_DIS_BIT (0x01UL << CSC_HCLK1MD_CPUSB_GATED_DIS_POS) 3705 #define CSC_HCLK1MD_SRAM5_LOW_DIS_POS (12) 3706 #define CSC_HCLK1MD_SRAM5_LOW_DIS_BIT (0x01UL << CSC_HCLK1MD_SRAM5_LOW_DIS_POS) 3707 #define CSC_HCLK1MD_SRAM5_HIGH_DIS_POS (13) 3708 #define CSC_HCLK1MD_SRAM5_HIGH_DIS_BIT (0x01UL << CSC_HCLK1MD_SRAM5_HIGH_DIS_POS) 3709 #define CSC_HCLK1MD_MM_DIS_POS (14) 3710 #define CSC_HCLK1MD_MM_DIS_BIT (0x01UL << CSC_HCLK1MD_MM_DIS_POS) 3711 cpusysctrl_hclk1md_get()3712__STATIC_INLINE uint32_t cpusysctrl_hclk1md_get() 3713 { 3714 return CS_CPUSYSCTRL->HCLK1MD; 3715 } 3716 cpusysctrl_hclk1md_set(uint32_t disable_bits)3717__STATIC_INLINE void cpusysctrl_hclk1md_set(uint32_t disable_bits) 3718 { 3719 CS_CPUSYSCTRL->HCLK1MD = disable_bits; 3720 } 3721 3722 /** 3723 * Address Offset: 0x000 3724 * Register Name : PC CPUSYS 3725 */ 3726 3727 #define PC_CPUSYS_AWAKE_SRC_LSB (0) 3728 #define PC_CPUSYS_AWAKE_SRC_WIDTH (10) 3729 #define PC_CPUSYS_AWAKE_SRC_MASK (((0x01UL << PC_CPUSYS_AWAKE_SRC_WIDTH) - 1) << PC_CPUSYS_AWAKE_SRC_LSB) 3730 #define PC_CPUSYS_SLEEP_SRC_LSB (10) 3731 #define PC_CPUSYS_SLEEP_SRC_WIDTH (2) 3732 #define PC_CPUSYS_SLEEP_SRC_MASK (((0x01UL << PC_CPUSYS_SLEEP_SRC_WIDTH) - 1) << PC_CPUSYS_SLEEP_SRC_LSB) 3733 #define PC_CPUSYS_SLEEP_SRC_WIFI_POS (10) 3734 #define PC_CPUSYS_SLEEP_SRC_WIFI_BIT (0x01UL << PC_CPUSYS_SLEEP_SRC_WIFI_POS) 3735 #define PC_CPUSYS_SLEEP_SRC_BT_POS (11) 3736 #define PC_CPUSYS_SLEEP_SRC_BT_BIT (0x01UL << PC_CPUSYS_SLEEP_SRC_BT_POS) 3737 #define PC_CPUSYS_SLEEP_SOFT_REQ_POS (12) 3738 #define PC_CPUSYS_SLEEP_SOFT_REQ_BIT (0x01UL << PC_CPUSYS_SLEEP_SOFT_REQ_POS) 3739 #define PC_CPUSYS_SLEEP_REQVLDCLR_POS (13) 3740 #define PC_CPUSYS_SLEEP_REQVLDCLR_BIT (0x01UL << PC_CPUSYS_SLEEP_REQVLDCLR_POS) 3741 #define PC_CPUSYS_HWEN_PON_POS (15) 3742 #define PC_CPUSYS_HWEN_PON_BIT (0x01UL << PC_CPUSYS_HWEN_PON_POS) 3743 #define PC_CPUSYS_HWEN_POFF_POS (16) 3744 #define PC_CPUSYS_HWEN_POFF_BIT (0x01UL << PC_CPUSYS_HWEN_POFF_POS) 3745 #define PC_CPUSYS_PON_POS (17) 3746 #define PC_CPUSYS_PON_BIT (0x01UL << PC_CPUSYS_PON_POS) 3747 #define PC_CPUSYS_POFF_POS (18) 3748 #define PC_CPUSYS_POFF_BIT (0x01UL << PC_CPUSYS_POFF_POS) 3749 #define PC_CPUSYS_PWRSYS_TMR_POFF_POS (19) 3750 #define PC_CPUSYS_PWRSYS_TMR_POFF_BIT (0x01UL << PC_CPUSYS_PWRSYS_TMR_POFF_POS) 3751 #define PC_CPUSYS_PWRSYS_PON_POS (20) 3752 #define PC_CPUSYS_PWRSYS_PON_BIT (0x01UL << PC_CPUSYS_PWRSYS_PON_POS) 3753 #define PC_CPUSYS_PWRSYS_POFF_POS (21) 3754 #define PC_CPUSYS_PWRSYS_POFF_BIT (0x01UL << PC_CPUSYS_PWRSYS_POFF_POS) 3755 #define PC_CPUSYS_AWAKE_SOFT_REQ_POS (22) 3756 #define PC_CPUSYS_AWAKE_SOFT_REQ_BIT (0x01UL << PC_CPUSYS_AWAKE_SOFT_REQ_POS) 3757 #define PC_CPUSYS_AWAKE_REQVLDCLR_POS (23) 3758 #define PC_CPUSYS_AWAKE_REQVLDCLR_BIT (0x01UL << PC_CPUSYS_AWAKE_REQVLDCLR_POS) 3759 pwrctrl_cpusys_get(void)3760__STATIC_INLINE uint32_t pwrctrl_cpusys_get(void) 3761 { 3762 return CS_PWRCTRL->CPUSYS; 3763 } 3764 pwrctrl_cpusys_set(uint32_t reg_val)3765__STATIC_INLINE void pwrctrl_cpusys_set(uint32_t reg_val) 3766 { 3767 CS_PWRCTRL->CPUSYS = reg_val; 3768 } 3769 pwrctrl_cpusys_awake_src_getf(void)3770__STATIC_INLINE uint16_t pwrctrl_cpusys_awake_src_getf(void) 3771 { 3772 return ((CS_PWRCTRL->CPUSYS & PC_CPUSYS_AWAKE_SRC_MASK) >> PC_CPUSYS_AWAKE_SRC_LSB); 3773 } 3774 pwrctrl_cpusys_awake_src_setf(uint16_t awake_src)3775__STATIC_INLINE void pwrctrl_cpusys_awake_src_setf(uint16_t awake_src) 3776 { 3777 uint32_t local_val = CS_PWRCTRL->CPUSYS & ~PC_CPUSYS_AWAKE_SRC_MASK; 3778 CS_PWRCTRL->CPUSYS = local_val | ((awake_src << PC_CPUSYS_AWAKE_SRC_LSB) & PC_CPUSYS_AWAKE_SRC_MASK); 3779 } 3780 pwrctrl_cpusys_sleep_src_getf(void)3781__STATIC_INLINE uint16_t pwrctrl_cpusys_sleep_src_getf(void) 3782 { 3783 return ((CS_PWRCTRL->CPUSYS & PC_CPUSYS_SLEEP_SRC_MASK) >> PC_CPUSYS_SLEEP_SRC_LSB); 3784 } 3785 pwrctrl_cpusys_sleep_src_setf(uint16_t awake_src)3786__STATIC_INLINE void pwrctrl_cpusys_sleep_src_setf(uint16_t awake_src) 3787 { 3788 uint32_t local_val = CS_PWRCTRL->CPUSYS & ~PC_CPUSYS_SLEEP_SRC_MASK; 3789 CS_PWRCTRL->CPUSYS = local_val | ((awake_src << PC_CPUSYS_SLEEP_SRC_LSB) & PC_CPUSYS_SLEEP_SRC_MASK); 3790 } 3791 pwrctrl_cpusys_sleep_src_wifi_getb(void)3792__STATIC_INLINE uint8_t pwrctrl_cpusys_sleep_src_wifi_getb(void) 3793 { 3794 return (CS_PWRCTRL->CPUSYS & PC_CPUSYS_SLEEP_SRC_WIFI_BIT) >> PC_CPUSYS_SLEEP_SRC_WIFI_POS; 3795 } 3796 pwrctrl_cpusys_sleep_src_wifi_setb(void)3797__STATIC_INLINE void pwrctrl_cpusys_sleep_src_wifi_setb(void) 3798 { 3799 CS_PWRCTRL->CPUSYS |= PC_CPUSYS_SLEEP_SRC_WIFI_BIT; 3800 } 3801 pwrctrl_cpusys_sleep_src_wifi_clrb(void)3802__STATIC_INLINE void pwrctrl_cpusys_sleep_src_wifi_clrb(void) 3803 { 3804 CS_PWRCTRL->CPUSYS &= ~PC_CPUSYS_SLEEP_SRC_WIFI_BIT; 3805 } 3806 pwrctrl_cpusys_sleep_src_bt_getb(void)3807__STATIC_INLINE uint8_t pwrctrl_cpusys_sleep_src_bt_getb(void) 3808 { 3809 return (CS_PWRCTRL->CPUSYS & PC_CPUSYS_SLEEP_SRC_BT_BIT) >> PC_CPUSYS_SLEEP_SRC_BT_POS; 3810 } 3811 pwrctrl_cpusys_sleep_src_bt_setb(void)3812__STATIC_INLINE void pwrctrl_cpusys_sleep_src_bt_setb(void) 3813 { 3814 CS_PWRCTRL->CPUSYS |= PC_CPUSYS_SLEEP_SRC_BT_BIT; 3815 } 3816 pwrctrl_cpusys_sleep_src_bt_clrb(void)3817__STATIC_INLINE void pwrctrl_cpusys_sleep_src_bt_clrb(void) 3818 { 3819 CS_PWRCTRL->CPUSYS &= ~PC_CPUSYS_SLEEP_SRC_BT_BIT; 3820 } 3821 pwrctrl_cpusys_sleep_soft_req_getb(void)3822__STATIC_INLINE uint8_t pwrctrl_cpusys_sleep_soft_req_getb(void) 3823 { 3824 return (CS_PWRCTRL->CPUSYS & PC_CPUSYS_SLEEP_SOFT_REQ_BIT) >> PC_CPUSYS_SLEEP_SOFT_REQ_POS; 3825 } 3826 pwrctrl_cpusys_sleep_soft_req_setb(void)3827__STATIC_INLINE void pwrctrl_cpusys_sleep_soft_req_setb(void) 3828 { 3829 CS_PWRCTRL->CPUSYS |= PC_CPUSYS_SLEEP_SOFT_REQ_BIT; 3830 } 3831 pwrctrl_cpusys_sleep_req_vld_clr_getb(void)3832__STATIC_INLINE uint8_t pwrctrl_cpusys_sleep_req_vld_clr_getb(void) 3833 { 3834 return (CS_PWRCTRL->CPUSYS & PC_CPUSYS_SLEEP_REQVLDCLR_BIT) >> PC_CPUSYS_SLEEP_REQVLDCLR_POS; 3835 } 3836 pwrctrl_cpusys_sleep_req_vld_clr_setb(void)3837__STATIC_INLINE void pwrctrl_cpusys_sleep_req_vld_clr_setb(void) 3838 { 3839 CS_PWRCTRL->CPUSYS |= PC_CPUSYS_SLEEP_REQVLDCLR_BIT; 3840 } 3841 pwrctrl_cpusys_hwen_pon_getb(void)3842__STATIC_INLINE uint8_t pwrctrl_cpusys_hwen_pon_getb(void) 3843 { 3844 return (CS_PWRCTRL->CPUSYS & PC_CPUSYS_HWEN_PON_BIT) >> PC_CPUSYS_HWEN_PON_POS; 3845 } 3846 pwrctrl_cpusys_hwen_pon_setb(void)3847__STATIC_INLINE void pwrctrl_cpusys_hwen_pon_setb(void) 3848 { 3849 CS_PWRCTRL->CPUSYS |= PC_CPUSYS_HWEN_PON_BIT; 3850 } 3851 pwrctrl_cpusys_hwen_pon_clrb(void)3852__STATIC_INLINE void pwrctrl_cpusys_hwen_pon_clrb(void) 3853 { 3854 CS_PWRCTRL->CPUSYS &= ~PC_CPUSYS_HWEN_PON_BIT; 3855 } 3856 pwrctrl_cpusys_hwen_poff_getb(void)3857__STATIC_INLINE uint8_t pwrctrl_cpusys_hwen_poff_getb(void) 3858 { 3859 return (CS_PWRCTRL->CPUSYS & PC_CPUSYS_HWEN_POFF_BIT) >> PC_CPUSYS_HWEN_POFF_POS; 3860 } 3861 pwrctrl_cpusys_hwen_poff_setb(void)3862__STATIC_INLINE void pwrctrl_cpusys_hwen_poff_setb(void) 3863 { 3864 CS_PWRCTRL->CPUSYS |= PC_CPUSYS_HWEN_POFF_BIT; 3865 } 3866 pwrctrl_cpusys_hwen_poff_clrb(void)3867__STATIC_INLINE void pwrctrl_cpusys_hwen_poff_clrb(void) 3868 { 3869 CS_PWRCTRL->CPUSYS &= ~PC_CPUSYS_HWEN_POFF_BIT; 3870 } 3871 pwrctrl_cpusys_pon_getb(void)3872__STATIC_INLINE uint8_t pwrctrl_cpusys_pon_getb(void) 3873 { 3874 return (CS_PWRCTRL->CPUSYS & PC_CPUSYS_PON_BIT) >> PC_CPUSYS_PON_POS; 3875 } 3876 pwrctrl_cpusys_pon_setb(void)3877__STATIC_INLINE void pwrctrl_cpusys_pon_setb(void) 3878 { 3879 CS_PWRCTRL->CPUSYS |= PC_CPUSYS_PON_BIT; 3880 } 3881 pwrctrl_cpusys_pon_clrb(void)3882__STATIC_INLINE void pwrctrl_cpusys_pon_clrb(void) 3883 { 3884 CS_PWRCTRL->CPUSYS &= ~PC_CPUSYS_PON_BIT; 3885 } 3886 pwrctrl_cpusys_poff_getb(void)3887__STATIC_INLINE uint8_t pwrctrl_cpusys_poff_getb(void) 3888 { 3889 return (CS_PWRCTRL->CPUSYS & PC_CPUSYS_POFF_BIT) >> PC_CPUSYS_POFF_POS; 3890 } 3891 pwrctrl_cpusys_poff_setb(void)3892__STATIC_INLINE void pwrctrl_cpusys_poff_setb(void) 3893 { 3894 CS_PWRCTRL->CPUSYS |= PC_CPUSYS_POFF_BIT; 3895 } 3896 pwrctrl_cpusys_poff_clrb(void)3897__STATIC_INLINE void pwrctrl_cpusys_poff_clrb(void) 3898 { 3899 CS_PWRCTRL->CPUSYS &= ~PC_CPUSYS_POFF_BIT; 3900 } 3901 pwrctrl_cpusys_pwrsys_timer_poff_getb(void)3902__STATIC_INLINE uint8_t pwrctrl_cpusys_pwrsys_timer_poff_getb(void) 3903 { 3904 return (CS_PWRCTRL->CPUSYS & PC_CPUSYS_PWRSYS_TMR_POFF_BIT) >> PC_CPUSYS_PWRSYS_TMR_POFF_POS; 3905 } 3906 pwrctrl_cpusys_pwrsys_timer_poff_setb(void)3907__STATIC_INLINE void pwrctrl_cpusys_pwrsys_timer_poff_setb(void) 3908 { 3909 CS_PWRCTRL->CPUSYS |= PC_CPUSYS_PWRSYS_TMR_POFF_BIT; 3910 } 3911 pwrctrl_cpusys_pwrsys_timer_poff_clrb(void)3912__STATIC_INLINE void pwrctrl_cpusys_pwrsys_timer_poff_clrb(void) 3913 { 3914 CS_PWRCTRL->CPUSYS &= ~PC_CPUSYS_PWRSYS_TMR_POFF_BIT; 3915 } 3916 pwrctrl_cpusys_pwrsys_pon_getb(void)3917__STATIC_INLINE uint8_t pwrctrl_cpusys_pwrsys_pon_getb(void) 3918 { 3919 return (CS_PWRCTRL->CPUSYS & PC_CPUSYS_PWRSYS_PON_BIT) >> PC_CPUSYS_PWRSYS_PON_POS; 3920 } 3921 pwrctrl_cpusys_pwrsys_pon_setb(void)3922__STATIC_INLINE void pwrctrl_cpusys_pwrsys_pon_setb(void) 3923 { 3924 CS_PWRCTRL->CPUSYS |= PC_CPUSYS_PWRSYS_PON_BIT; 3925 } 3926 pwrctrl_cpusys_pwrsys_pon_clrb(void)3927__STATIC_INLINE void pwrctrl_cpusys_pwrsys_pon_clrb(void) 3928 { 3929 CS_PWRCTRL->CPUSYS &= ~PC_CPUSYS_PWRSYS_PON_BIT; 3930 } 3931 pwrctrl_cpusys_pwrsys_poff_getb(void)3932__STATIC_INLINE uint8_t pwrctrl_cpusys_pwrsys_poff_getb(void) 3933 { 3934 return (CS_PWRCTRL->CPUSYS & PC_CPUSYS_PWRSYS_POFF_BIT) >> PC_CPUSYS_PWRSYS_POFF_POS; 3935 } 3936 pwrctrl_cpusys_pwrsys_poff_setb(void)3937__STATIC_INLINE void pwrctrl_cpusys_pwrsys_poff_setb(void) 3938 { 3939 CS_PWRCTRL->CPUSYS |= PC_CPUSYS_PWRSYS_POFF_BIT; 3940 } 3941 pwrctrl_cpusys_pwrsys_poff_clrb(void)3942__STATIC_INLINE void pwrctrl_cpusys_pwrsys_poff_clrb(void) 3943 { 3944 CS_PWRCTRL->CPUSYS &= ~PC_CPUSYS_PWRSYS_POFF_BIT; 3945 } 3946 pwrctrl_cpusys_awake_soft_req_getb(void)3947__STATIC_INLINE uint8_t pwrctrl_cpusys_awake_soft_req_getb(void) 3948 { 3949 return (CS_PWRCTRL->CPUSYS & PC_CPUSYS_AWAKE_SOFT_REQ_BIT) >> PC_CPUSYS_AWAKE_SOFT_REQ_POS; 3950 } 3951 pwrctrl_cpusys_awake_soft_req_setb(void)3952__STATIC_INLINE void pwrctrl_cpusys_awake_soft_req_setb(void) 3953 { 3954 CS_PWRCTRL->CPUSYS |= PC_CPUSYS_AWAKE_SOFT_REQ_BIT; 3955 } 3956 pwrctrl_cpusys_awake_req_vld_clr_getb(void)3957__STATIC_INLINE uint8_t pwrctrl_cpusys_awake_req_vld_clr_getb(void) 3958 { 3959 return (CS_PWRCTRL->CPUSYS & PC_CPUSYS_AWAKE_REQVLDCLR_BIT) >> PC_CPUSYS_AWAKE_REQVLDCLR_POS; 3960 } 3961 pwrctrl_cpusys_awake_req_vld_clr_setb(void)3962__STATIC_INLINE void pwrctrl_cpusys_awake_req_vld_clr_setb(void) 3963 { 3964 CS_PWRCTRL->CPUSYS |= PC_CPUSYS_AWAKE_REQVLDCLR_BIT; 3965 } 3966 3967 /** 3968 * Address Offset: 0x004 3969 * Register Name : PC BTCORE 3970 */ 3971 3972 #define PC_BTCORE_AWAKE_SRC_LSB (0) 3973 #define PC_BTCORE_AWAKE_SRC_WIDTH (10) 3974 #define PC_BTCORE_AWAKE_SRC_MASK (((0x01UL << PC_BTCORE_AWAKE_SRC_WIDTH) - 1) << PC_BTCORE_AWAKE_SRC_LSB) 3975 #define PC_BTCORE_SLEEP_SRC_LSB (10) 3976 #define PC_BTCORE_SLEEP_SRC_WIDTH (2) 3977 #define PC_BTCORE_SLEEP_SRC_MASK (((0x01UL << PC_BTCORE_SLEEP_SRC_WIDTH) - 1) << PC_BTCORE_SLEEP_SRC_LSB) 3978 #define PC_BTCORE_SLEEP_SRC_WIFI_POS (10) 3979 #define PC_BTCORE_SLEEP_SRC_WIFI_BIT (0x01UL << PC_BTCORE_SLEEP_SRC_WIFI_POS) 3980 #define PC_BTCORE_SLEEP_SRC_BT_POS (11) 3981 #define PC_BTCORE_SLEEP_SRC_BT_BIT (0x01UL << PC_BTCORE_SLEEP_SRC_BT_POS) 3982 #define PC_BTCORE_SLEEP_SOFT_REQ_POS (12) 3983 #define PC_BTCORE_SLEEP_SOFT_REQ_BIT (0x01UL << PC_BTCORE_SLEEP_SOFT_REQ_POS) 3984 #define PC_BTCORE_SLEEP_REQVLDCLR_POS (13) 3985 #define PC_BTCORE_SLEEP_REQVLDCLR_BIT (0x01UL << PC_BTCORE_SLEEP_REQVLDCLR_POS) 3986 #define PC_BTCORE_HWEN_PON_POS (15) 3987 #define PC_BTCORE_HWEN_PON_BIT (0x01UL << PC_BTCORE_HWEN_PON_POS) 3988 #define PC_BTCORE_HWEN_POFF_POS (16) 3989 #define PC_BTCORE_HWEN_POFF_BIT (0x01UL << PC_BTCORE_HWEN_POFF_POS) 3990 #define PC_BTCORE_PON_POS (17) 3991 #define PC_BTCORE_PON_BIT (0x01UL << PC_BTCORE_PON_POS) 3992 #define PC_BTCORE_POFF_POS (18) 3993 #define PC_BTCORE_POFF_BIT (0x01UL << PC_BTCORE_POFF_POS) 3994 #define PC_BTCORE_PWRSYS_TMR_POFF_POS (19) 3995 #define PC_BTCORE_PWRSYS_TMR_POFF_BIT (0x01UL << PC_BTCORE_PWRSYS_TMR_POFF_POS) 3996 #define PC_BTCORE_PWRSYS_PON_POS (20) 3997 #define PC_BTCORE_PWRSYS_PON_BIT (0x01UL << PC_BTCORE_PWRSYS_PON_POS) 3998 #define PC_BTCORE_PWRSYS_POFF_POS (21) 3999 #define PC_BTCORE_PWRSYS_POFF_BIT (0x01UL << PC_BTCORE_PWRSYS_POFF_POS) 4000 #define PC_BTCORE_AWAKE_SOFT_REQ_POS (22) 4001 #define PC_BTCORE_AWAKE_SOFT_REQ_BIT (0x01UL << PC_BTCORE_AWAKE_SOFT_REQ_POS) 4002 #define PC_BTCORE_AWAKE_REQVLDCLR_POS (23) 4003 #define PC_BTCORE_AWAKE_REQVLDCLR_BIT (0x01UL << PC_BTCORE_AWAKE_REQVLDCLR_POS) 4004 #define PC_BTCORE_AWAKE_SOFTREQBT_POS (24) 4005 #define PC_BTCORE_AWAKE_SOFTREQBT_BIT (0x01UL << PC_BTCORE_AWAKE_SOFTREQBT_POS) 4006 pwrctrl_btcore_get(void)4007__STATIC_INLINE uint32_t pwrctrl_btcore_get(void) 4008 { 4009 return CS_PWRCTRL->BTCORE; 4010 } 4011 pwrctrl_btcore_set(uint32_t reg_val)4012__STATIC_INLINE void pwrctrl_btcore_set(uint32_t reg_val) 4013 { 4014 CS_PWRCTRL->BTCORE = reg_val; 4015 } 4016 pwrctrl_btcore_awake_src_getf(void)4017__STATIC_INLINE uint16_t pwrctrl_btcore_awake_src_getf(void) 4018 { 4019 return ((CS_PWRCTRL->BTCORE & PC_BTCORE_AWAKE_SRC_MASK) >> PC_BTCORE_AWAKE_SRC_LSB); 4020 } 4021 pwrctrl_btcore_awake_src_setf(uint16_t awake_src)4022__STATIC_INLINE void pwrctrl_btcore_awake_src_setf(uint16_t awake_src) 4023 { 4024 uint32_t local_val = CS_PWRCTRL->BTCORE & ~PC_BTCORE_AWAKE_SRC_MASK; 4025 CS_PWRCTRL->BTCORE = local_val | ((awake_src << PC_BTCORE_AWAKE_SRC_LSB) & PC_BTCORE_AWAKE_SRC_MASK); 4026 } 4027 pwrctrl_btcore_sleep_src_getf(void)4028__STATIC_INLINE uint16_t pwrctrl_btcore_sleep_src_getf(void) 4029 { 4030 return ((CS_PWRCTRL->BTCORE & PC_BTCORE_SLEEP_SRC_MASK) >> PC_BTCORE_SLEEP_SRC_LSB); 4031 } 4032 pwrctrl_btcore_sleep_src_setf(uint16_t awake_src)4033__STATIC_INLINE void pwrctrl_btcore_sleep_src_setf(uint16_t awake_src) 4034 { 4035 uint32_t local_val = CS_PWRCTRL->BTCORE & ~PC_BTCORE_SLEEP_SRC_MASK; 4036 CS_PWRCTRL->BTCORE = local_val | ((awake_src << PC_BTCORE_SLEEP_SRC_LSB) & PC_BTCORE_SLEEP_SRC_MASK); 4037 } 4038 pwrctrl_btcore_sleep_src_wifi_getb(void)4039__STATIC_INLINE uint8_t pwrctrl_btcore_sleep_src_wifi_getb(void) 4040 { 4041 return (CS_PWRCTRL->BTCORE & PC_BTCORE_SLEEP_SRC_WIFI_BIT) >> PC_BTCORE_SLEEP_SRC_WIFI_POS; 4042 } 4043 pwrctrl_btcore_sleep_src_wifi_setb(void)4044__STATIC_INLINE void pwrctrl_btcore_sleep_src_wifi_setb(void) 4045 { 4046 CS_PWRCTRL->BTCORE |= PC_BTCORE_SLEEP_SRC_WIFI_BIT; 4047 } 4048 pwrctrl_btcore_sleep_src_wifi_clrb(void)4049__STATIC_INLINE void pwrctrl_btcore_sleep_src_wifi_clrb(void) 4050 { 4051 CS_PWRCTRL->BTCORE &= ~PC_BTCORE_SLEEP_SRC_WIFI_BIT; 4052 } 4053 pwrctrl_btcore_sleep_src_bt_getb(void)4054__STATIC_INLINE uint8_t pwrctrl_btcore_sleep_src_bt_getb(void) 4055 { 4056 return (CS_PWRCTRL->BTCORE & PC_BTCORE_SLEEP_SRC_BT_BIT) >> PC_BTCORE_SLEEP_SRC_BT_POS; 4057 } 4058 pwrctrl_btcore_sleep_src_bt_setb(void)4059__STATIC_INLINE void pwrctrl_btcore_sleep_src_bt_setb(void) 4060 { 4061 CS_PWRCTRL->BTCORE |= PC_BTCORE_SLEEP_SRC_BT_BIT; 4062 } 4063 pwrctrl_btcore_sleep_src_bt_clrb(void)4064__STATIC_INLINE void pwrctrl_btcore_sleep_src_bt_clrb(void) 4065 { 4066 CS_PWRCTRL->BTCORE &= ~PC_BTCORE_SLEEP_SRC_BT_BIT; 4067 } 4068 pwrctrl_btcore_sleep_soft_req_getb(void)4069__STATIC_INLINE uint8_t pwrctrl_btcore_sleep_soft_req_getb(void) 4070 { 4071 return (CS_PWRCTRL->BTCORE & PC_BTCORE_SLEEP_SOFT_REQ_BIT) >> PC_BTCORE_SLEEP_SOFT_REQ_POS; 4072 } 4073 pwrctrl_btcore_sleep_soft_req_setb(void)4074__STATIC_INLINE void pwrctrl_btcore_sleep_soft_req_setb(void) 4075 { 4076 CS_PWRCTRL->BTCORE |= PC_BTCORE_SLEEP_SOFT_REQ_BIT; 4077 } 4078 pwrctrl_btcore_sleep_req_vld_clr_getb(void)4079__STATIC_INLINE uint8_t pwrctrl_btcore_sleep_req_vld_clr_getb(void) 4080 { 4081 return (CS_PWRCTRL->BTCORE & PC_BTCORE_SLEEP_REQVLDCLR_BIT) >> PC_BTCORE_SLEEP_REQVLDCLR_POS; 4082 } 4083 pwrctrl_btcore_sleep_req_vld_clr_setb(void)4084__STATIC_INLINE void pwrctrl_btcore_sleep_req_vld_clr_setb(void) 4085 { 4086 CS_PWRCTRL->BTCORE |= PC_BTCORE_SLEEP_REQVLDCLR_BIT; 4087 } 4088 pwrctrl_btcore_hwen_pon_getb(void)4089__STATIC_INLINE uint8_t pwrctrl_btcore_hwen_pon_getb(void) 4090 { 4091 return (CS_PWRCTRL->BTCORE & PC_BTCORE_HWEN_PON_BIT) >> PC_BTCORE_HWEN_PON_POS; 4092 } 4093 pwrctrl_btcore_hwen_pon_setb(void)4094__STATIC_INLINE void pwrctrl_btcore_hwen_pon_setb(void) 4095 { 4096 CS_PWRCTRL->BTCORE |= PC_BTCORE_HWEN_PON_BIT; 4097 } 4098 pwrctrl_btcore_hwen_pon_clrb(void)4099__STATIC_INLINE void pwrctrl_btcore_hwen_pon_clrb(void) 4100 { 4101 CS_PWRCTRL->BTCORE &= ~PC_BTCORE_HWEN_PON_BIT; 4102 } 4103 pwrctrl_btcore_hwen_poff_getb(void)4104__STATIC_INLINE uint8_t pwrctrl_btcore_hwen_poff_getb(void) 4105 { 4106 return (CS_PWRCTRL->BTCORE & PC_BTCORE_HWEN_POFF_BIT) >> PC_BTCORE_HWEN_POFF_POS; 4107 } 4108 pwrctrl_btcore_hwen_poff_setb(void)4109__STATIC_INLINE void pwrctrl_btcore_hwen_poff_setb(void) 4110 { 4111 CS_PWRCTRL->BTCORE |= PC_BTCORE_HWEN_POFF_BIT; 4112 } 4113 pwrctrl_btcore_hwen_poff_clrb(void)4114__STATIC_INLINE void pwrctrl_btcore_hwen_poff_clrb(void) 4115 { 4116 CS_PWRCTRL->BTCORE &= ~PC_BTCORE_HWEN_POFF_BIT; 4117 } 4118 pwrctrl_btcore_pon_getb(void)4119__STATIC_INLINE uint8_t pwrctrl_btcore_pon_getb(void) 4120 { 4121 return (CS_PWRCTRL->BTCORE & PC_BTCORE_PON_BIT) >> PC_BTCORE_PON_POS; 4122 } 4123 pwrctrl_btcore_pon_setb(void)4124__STATIC_INLINE void pwrctrl_btcore_pon_setb(void) 4125 { 4126 CS_PWRCTRL->BTCORE |= PC_BTCORE_PON_BIT; 4127 } 4128 pwrctrl_btcore_pon_clrb(void)4129__STATIC_INLINE void pwrctrl_btcore_pon_clrb(void) 4130 { 4131 CS_PWRCTRL->BTCORE &= ~PC_BTCORE_PON_BIT; 4132 } 4133 pwrctrl_btcore_poff_getb(void)4134__STATIC_INLINE uint8_t pwrctrl_btcore_poff_getb(void) 4135 { 4136 return (CS_PWRCTRL->BTCORE & PC_BTCORE_POFF_BIT) >> PC_BTCORE_POFF_POS; 4137 } 4138 pwrctrl_btcore_poff_setb(void)4139__STATIC_INLINE void pwrctrl_btcore_poff_setb(void) 4140 { 4141 CS_PWRCTRL->BTCORE |= PC_BTCORE_POFF_BIT; 4142 } 4143 pwrctrl_btcore_poff_clrb(void)4144__STATIC_INLINE void pwrctrl_btcore_poff_clrb(void) 4145 { 4146 CS_PWRCTRL->BTCORE &= ~PC_BTCORE_POFF_BIT; 4147 } 4148 pwrctrl_btcore_pwrsys_timer_poff_getb(void)4149__STATIC_INLINE uint8_t pwrctrl_btcore_pwrsys_timer_poff_getb(void) 4150 { 4151 return (CS_PWRCTRL->BTCORE & PC_BTCORE_PWRSYS_TMR_POFF_BIT) >> PC_BTCORE_PWRSYS_TMR_POFF_POS; 4152 } 4153 pwrctrl_btcore_pwrsys_timer_poff_setb(void)4154__STATIC_INLINE void pwrctrl_btcore_pwrsys_timer_poff_setb(void) 4155 { 4156 CS_PWRCTRL->BTCORE |= PC_BTCORE_PWRSYS_TMR_POFF_BIT; 4157 } 4158 pwrctrl_btcore_pwrsys_timer_poff_clrb(void)4159__STATIC_INLINE void pwrctrl_btcore_pwrsys_timer_poff_clrb(void) 4160 { 4161 CS_PWRCTRL->BTCORE &= ~PC_BTCORE_PWRSYS_TMR_POFF_BIT; 4162 } 4163 pwrctrl_btcore_pwrsys_pon_getb(void)4164__STATIC_INLINE uint8_t pwrctrl_btcore_pwrsys_pon_getb(void) 4165 { 4166 return (CS_PWRCTRL->BTCORE & PC_BTCORE_PWRSYS_PON_BIT) >> PC_BTCORE_PWRSYS_PON_POS; 4167 } 4168 pwrctrl_btcore_pwrsys_pon_setb(void)4169__STATIC_INLINE void pwrctrl_btcore_pwrsys_pon_setb(void) 4170 { 4171 CS_PWRCTRL->BTCORE |= PC_BTCORE_PWRSYS_PON_BIT; 4172 } 4173 pwrctrl_btcore_pwrsys_pon_clrb(void)4174__STATIC_INLINE void pwrctrl_btcore_pwrsys_pon_clrb(void) 4175 { 4176 CS_PWRCTRL->BTCORE &= ~PC_BTCORE_PWRSYS_PON_BIT; 4177 } 4178 pwrctrl_btcore_pwrsys_poff_getb(void)4179__STATIC_INLINE uint8_t pwrctrl_btcore_pwrsys_poff_getb(void) 4180 { 4181 return (CS_PWRCTRL->BTCORE & PC_BTCORE_PWRSYS_POFF_BIT) >> PC_BTCORE_PWRSYS_POFF_POS; 4182 } 4183 pwrctrl_btcore_pwrsys_poff_setb(void)4184__STATIC_INLINE void pwrctrl_btcore_pwrsys_poff_setb(void) 4185 { 4186 CS_PWRCTRL->BTCORE |= PC_BTCORE_PWRSYS_POFF_BIT; 4187 } 4188 pwrctrl_btcore_pwrsys_poff_clrb(void)4189__STATIC_INLINE void pwrctrl_btcore_pwrsys_poff_clrb(void) 4190 { 4191 CS_PWRCTRL->BTCORE &= ~PC_BTCORE_PWRSYS_POFF_BIT; 4192 } 4193 pwrctrl_btcore_awake_soft_req_getb(void)4194__STATIC_INLINE uint8_t pwrctrl_btcore_awake_soft_req_getb(void) 4195 { 4196 return (CS_PWRCTRL->BTCORE & PC_BTCORE_AWAKE_SOFT_REQ_BIT) >> PC_BTCORE_AWAKE_SOFT_REQ_POS; 4197 } 4198 pwrctrl_btcore_awake_soft_req_setb(void)4199__STATIC_INLINE void pwrctrl_btcore_awake_soft_req_setb(void) 4200 { 4201 CS_PWRCTRL->BTCORE |= PC_BTCORE_AWAKE_SOFT_REQ_BIT; 4202 } 4203 pwrctrl_btcore_awake_req_vld_clr_getb(void)4204__STATIC_INLINE uint8_t pwrctrl_btcore_awake_req_vld_clr_getb(void) 4205 { 4206 return (CS_PWRCTRL->BTCORE & PC_BTCORE_AWAKE_REQVLDCLR_BIT) >> PC_BTCORE_AWAKE_REQVLDCLR_POS; 4207 } 4208 pwrctrl_btcore_awake_req_vld_clr_setb(void)4209__STATIC_INLINE void pwrctrl_btcore_awake_req_vld_clr_setb(void) 4210 { 4211 CS_PWRCTRL->BTCORE |= PC_BTCORE_AWAKE_REQVLDCLR_BIT; 4212 } 4213 pwrctrl_btcore_awake_soft_req_to_bt_getb(void)4214__STATIC_INLINE uint8_t pwrctrl_btcore_awake_soft_req_to_bt_getb(void) 4215 { 4216 return (CS_PWRCTRL->BTCORE & PC_BTCORE_AWAKE_SOFTREQBT_BIT) >> PC_BTCORE_AWAKE_SOFTREQBT_POS; 4217 } 4218 pwrctrl_btcore_awake_soft_req_to_bt_setb(void)4219__STATIC_INLINE void pwrctrl_btcore_awake_soft_req_to_bt_setb(void) 4220 { 4221 CS_PWRCTRL->BTCORE |= PC_BTCORE_AWAKE_SOFTREQBT_BIT; 4222 } 4223 pwrctrl_btcore_awake_soft_req_to_bt_clrb(void)4224__STATIC_INLINE void pwrctrl_btcore_awake_soft_req_to_bt_clrb(void) 4225 { 4226 CS_PWRCTRL->BTCORE &= ~PC_BTCORE_AWAKE_SOFTREQBT_BIT; 4227 } 4228 4229 /** 4230 * Address Offset: 0x008 4231 * Register Name : PC WIFICORE 4232 */ 4233 4234 #define PC_WIFICORE_AWAKE_SRC_LSB (0) 4235 #define PC_WIFICORE_AWAKE_SRC_WIDTH (10) 4236 #define PC_WIFICORE_AWAKE_SRC_MASK (((0x01UL << PC_WIFICORE_AWAKE_SRC_WIDTH) - 1) << PC_WIFICORE_AWAKE_SRC_LSB) 4237 #define PC_WIFICORE_SLEEP_SRC_LSB (10) 4238 #define PC_WIFICORE_SLEEP_SRC_WIDTH (2) 4239 #define PC_WIFICORE_SLEEP_SRC_MASK (((0x01UL << PC_WIFICORE_SLEEP_SRC_WIDTH) - 1) << PC_WIFICORE_SLEEP_SRC_LSB) 4240 #define PC_WIFICORE_SLEEP_SRC_WIFI_POS (10) 4241 #define PC_WIFICORE_SLEEP_SRC_WIFI_BIT (0x01UL << PC_WIFICORE_SLEEP_SRC_WIFI_POS) 4242 #define PC_WIFICORE_SLEEP_SRC_BT_POS (11) 4243 #define PC_WIFICORE_SLEEP_SRC_BT_BIT (0x01UL << PC_WIFICORE_SLEEP_SRC_BT_POS) 4244 #define PC_WIFICORE_SLEEP_SOFT_REQ_POS (12) 4245 #define PC_WIFICORE_SLEEP_SOFT_REQ_BIT (0x01UL << PC_WIFICORE_SLEEP_SOFT_REQ_POS) 4246 #define PC_WIFICORE_SLEEP_REQVLDCLR_POS (13) 4247 #define PC_WIFICORE_SLEEP_REQVLDCLR_BIT (0x01UL << PC_WIFICORE_SLEEP_REQVLDCLR_POS) 4248 #define PC_WIFICORE_HWEN_PON_POS (15) 4249 #define PC_WIFICORE_HWEN_PON_BIT (0x01UL << PC_WIFICORE_HWEN_PON_POS) 4250 #define PC_WIFICORE_HWEN_POFF_POS (16) 4251 #define PC_WIFICORE_HWEN_POFF_BIT (0x01UL << PC_WIFICORE_HWEN_POFF_POS) 4252 #define PC_WIFICORE_PON_POS (17) 4253 #define PC_WIFICORE_PON_BIT (0x01UL << PC_WIFICORE_PON_POS) 4254 #define PC_WIFICORE_POFF_POS (18) 4255 #define PC_WIFICORE_POFF_BIT (0x01UL << PC_WIFICORE_POFF_POS) 4256 #define PC_WIFICORE_PWRSYS_TMR_POFF_POS (19) 4257 #define PC_WIFICORE_PWRSYS_TMR_POFF_BIT (0x01UL << PC_WIFICORE_PWRSYS_TMR_POFF_POS) 4258 #define PC_WIFICORE_PWRSYS_PON_POS (20) 4259 #define PC_WIFICORE_PWRSYS_PON_BIT (0x01UL << PC_WIFICORE_PWRSYS_PON_POS) 4260 #define PC_WIFICORE_PWRSYS_POFF_POS (21) 4261 #define PC_WIFICORE_PWRSYS_POFF_BIT (0x01UL << PC_WIFICORE_PWRSYS_POFF_POS) 4262 #define PC_WIFICORE_AWAKE_SOFT_REQ_POS (22) 4263 #define PC_WIFICORE_AWAKE_SOFT_REQ_BIT (0x01UL << PC_WIFICORE_AWAKE_SOFT_REQ_POS) 4264 #define PC_WIFICORE_AWAKE_REQVLDCLR_POS (23) 4265 #define PC_WIFICORE_AWAKE_REQVLDCLR_BIT (0x01UL << PC_WIFICORE_AWAKE_REQVLDCLR_POS) 4266 #define PC_WIFICORE_AWAKE_SOFTREQWF_POS (24) 4267 #define PC_WIFICORE_AWAKE_SOFTREQWF_BIT (0x01UL << PC_WIFICORE_AWAKE_SOFTREQWF_POS) 4268 pwrctrl_wificore_get(void)4269__STATIC_INLINE uint32_t pwrctrl_wificore_get(void) 4270 { 4271 return CS_PWRCTRL->WIFICORE; 4272 } 4273 pwrctrl_wificore_set(uint32_t reg_val)4274__STATIC_INLINE void pwrctrl_wificore_set(uint32_t reg_val) 4275 { 4276 CS_PWRCTRL->WIFICORE = reg_val; 4277 } 4278 pwrctrl_wificore_awake_src_getf(void)4279__STATIC_INLINE uint16_t pwrctrl_wificore_awake_src_getf(void) 4280 { 4281 return ((CS_PWRCTRL->WIFICORE & PC_WIFICORE_AWAKE_SRC_MASK) >> PC_WIFICORE_AWAKE_SRC_LSB); 4282 } 4283 pwrctrl_wificore_awake_src_setf(uint16_t awake_src)4284__STATIC_INLINE void pwrctrl_wificore_awake_src_setf(uint16_t awake_src) 4285 { 4286 uint32_t local_val = CS_PWRCTRL->WIFICORE & ~PC_WIFICORE_AWAKE_SRC_MASK; 4287 CS_PWRCTRL->WIFICORE = local_val | ((awake_src << PC_WIFICORE_AWAKE_SRC_LSB) & PC_WIFICORE_AWAKE_SRC_MASK); 4288 } 4289 pwrctrl_wificore_sleep_src_getf(void)4290__STATIC_INLINE uint16_t pwrctrl_wificore_sleep_src_getf(void) 4291 { 4292 return ((CS_PWRCTRL->WIFICORE & PC_WIFICORE_SLEEP_SRC_MASK) >> PC_WIFICORE_SLEEP_SRC_LSB); 4293 } 4294 pwrctrl_wificore_sleep_src_setf(uint16_t awake_src)4295__STATIC_INLINE void pwrctrl_wificore_sleep_src_setf(uint16_t awake_src) 4296 { 4297 uint32_t local_val = CS_PWRCTRL->WIFICORE & ~PC_WIFICORE_SLEEP_SRC_MASK; 4298 CS_PWRCTRL->WIFICORE = local_val | ((awake_src << PC_WIFICORE_SLEEP_SRC_LSB) & PC_WIFICORE_SLEEP_SRC_MASK); 4299 } 4300 pwrctrl_wificore_sleep_src_wifi_getb(void)4301__STATIC_INLINE uint8_t pwrctrl_wificore_sleep_src_wifi_getb(void) 4302 { 4303 return (CS_PWRCTRL->WIFICORE & PC_WIFICORE_SLEEP_SRC_WIFI_BIT) >> PC_WIFICORE_SLEEP_SRC_WIFI_POS; 4304 } 4305 pwrctrl_wificore_sleep_src_wifi_setb(void)4306__STATIC_INLINE void pwrctrl_wificore_sleep_src_wifi_setb(void) 4307 { 4308 CS_PWRCTRL->WIFICORE |= PC_WIFICORE_SLEEP_SRC_WIFI_BIT; 4309 } 4310 pwrctrl_wificore_sleep_src_wifi_clrb(void)4311__STATIC_INLINE void pwrctrl_wificore_sleep_src_wifi_clrb(void) 4312 { 4313 CS_PWRCTRL->WIFICORE &= ~PC_WIFICORE_SLEEP_SRC_WIFI_BIT; 4314 } 4315 pwrctrl_wificore_sleep_src_bt_getb(void)4316__STATIC_INLINE uint8_t pwrctrl_wificore_sleep_src_bt_getb(void) 4317 { 4318 return (CS_PWRCTRL->WIFICORE & PC_WIFICORE_SLEEP_SRC_BT_BIT) >> PC_WIFICORE_SLEEP_SRC_BT_POS; 4319 } 4320 pwrctrl_wificore_sleep_src_bt_setb(void)4321__STATIC_INLINE void pwrctrl_wificore_sleep_src_bt_setb(void) 4322 { 4323 CS_PWRCTRL->WIFICORE |= PC_WIFICORE_SLEEP_SRC_BT_BIT; 4324 } 4325 pwrctrl_wificore_sleep_src_bt_clrb(void)4326__STATIC_INLINE void pwrctrl_wificore_sleep_src_bt_clrb(void) 4327 { 4328 CS_PWRCTRL->WIFICORE &= ~PC_WIFICORE_SLEEP_SRC_BT_BIT; 4329 } 4330 pwrctrl_wificore_sleep_soft_req_getb(void)4331__STATIC_INLINE uint8_t pwrctrl_wificore_sleep_soft_req_getb(void) 4332 { 4333 return (CS_PWRCTRL->WIFICORE & PC_WIFICORE_SLEEP_SOFT_REQ_BIT) >> PC_WIFICORE_SLEEP_SOFT_REQ_POS; 4334 } 4335 pwrctrl_wificore_sleep_soft_req_setb(void)4336__STATIC_INLINE void pwrctrl_wificore_sleep_soft_req_setb(void) 4337 { 4338 CS_PWRCTRL->WIFICORE |= PC_WIFICORE_SLEEP_SOFT_REQ_BIT; 4339 } 4340 pwrctrl_wificore_sleep_req_vld_clr_getb(void)4341__STATIC_INLINE uint8_t pwrctrl_wificore_sleep_req_vld_clr_getb(void) 4342 { 4343 return (CS_PWRCTRL->WIFICORE & PC_WIFICORE_SLEEP_REQVLDCLR_BIT) >> PC_WIFICORE_SLEEP_REQVLDCLR_POS; 4344 } 4345 pwrctrl_wificore_sleep_req_vld_clr_setb(void)4346__STATIC_INLINE void pwrctrl_wificore_sleep_req_vld_clr_setb(void) 4347 { 4348 CS_PWRCTRL->WIFICORE |= PC_WIFICORE_SLEEP_REQVLDCLR_BIT; 4349 } 4350 pwrctrl_wificore_hwen_pon_getb(void)4351__STATIC_INLINE uint8_t pwrctrl_wificore_hwen_pon_getb(void) 4352 { 4353 return (CS_PWRCTRL->WIFICORE & PC_WIFICORE_HWEN_PON_BIT) >> PC_WIFICORE_HWEN_PON_POS; 4354 } 4355 pwrctrl_wificore_hwen_pon_setb(void)4356__STATIC_INLINE void pwrctrl_wificore_hwen_pon_setb(void) 4357 { 4358 CS_PWRCTRL->WIFICORE |= PC_WIFICORE_HWEN_PON_BIT; 4359 } 4360 pwrctrl_wificore_hwen_pon_clrb(void)4361__STATIC_INLINE void pwrctrl_wificore_hwen_pon_clrb(void) 4362 { 4363 CS_PWRCTRL->WIFICORE &= ~PC_WIFICORE_HWEN_PON_BIT; 4364 } 4365 pwrctrl_wificore_hwen_poff_getb(void)4366__STATIC_INLINE uint8_t pwrctrl_wificore_hwen_poff_getb(void) 4367 { 4368 return (CS_PWRCTRL->WIFICORE & PC_WIFICORE_HWEN_POFF_BIT) >> PC_WIFICORE_HWEN_POFF_POS; 4369 } 4370 pwrctrl_wificore_hwen_poff_setb(void)4371__STATIC_INLINE void pwrctrl_wificore_hwen_poff_setb(void) 4372 { 4373 CS_PWRCTRL->WIFICORE |= PC_WIFICORE_HWEN_POFF_BIT; 4374 } 4375 pwrctrl_wificore_hwen_poff_clrb(void)4376__STATIC_INLINE void pwrctrl_wificore_hwen_poff_clrb(void) 4377 { 4378 CS_PWRCTRL->WIFICORE &= ~PC_WIFICORE_HWEN_POFF_BIT; 4379 } 4380 pwrctrl_wificore_pon_getb(void)4381__STATIC_INLINE uint8_t pwrctrl_wificore_pon_getb(void) 4382 { 4383 return (CS_PWRCTRL->WIFICORE & PC_WIFICORE_PON_BIT) >> PC_WIFICORE_PON_POS; 4384 } 4385 pwrctrl_wificore_pon_setb(void)4386__STATIC_INLINE void pwrctrl_wificore_pon_setb(void) 4387 { 4388 CS_PWRCTRL->WIFICORE |= PC_WIFICORE_PON_BIT; 4389 } 4390 pwrctrl_wificore_pon_clrb(void)4391__STATIC_INLINE void pwrctrl_wificore_pon_clrb(void) 4392 { 4393 CS_PWRCTRL->WIFICORE &= ~PC_WIFICORE_PON_BIT; 4394 } 4395 pwrctrl_wificore_poff_getb(void)4396__STATIC_INLINE uint8_t pwrctrl_wificore_poff_getb(void) 4397 { 4398 return (CS_PWRCTRL->WIFICORE & PC_WIFICORE_POFF_BIT) >> PC_WIFICORE_POFF_POS; 4399 } 4400 pwrctrl_wificore_poff_setb(void)4401__STATIC_INLINE void pwrctrl_wificore_poff_setb(void) 4402 { 4403 CS_PWRCTRL->WIFICORE |= PC_WIFICORE_POFF_BIT; 4404 } 4405 pwrctrl_wificore_poff_clrb(void)4406__STATIC_INLINE void pwrctrl_wificore_poff_clrb(void) 4407 { 4408 CS_PWRCTRL->WIFICORE &= ~PC_WIFICORE_POFF_BIT; 4409 } 4410 pwrctrl_wificore_pwrsys_timer_poff_getb(void)4411__STATIC_INLINE uint8_t pwrctrl_wificore_pwrsys_timer_poff_getb(void) 4412 { 4413 return (CS_PWRCTRL->WIFICORE & PC_WIFICORE_PWRSYS_TMR_POFF_BIT) >> PC_WIFICORE_PWRSYS_TMR_POFF_POS; 4414 } 4415 pwrctrl_wificore_pwrsys_timer_poff_setb(void)4416__STATIC_INLINE void pwrctrl_wificore_pwrsys_timer_poff_setb(void) 4417 { 4418 CS_PWRCTRL->WIFICORE |= PC_WIFICORE_PWRSYS_TMR_POFF_BIT; 4419 } 4420 pwrctrl_wificore_pwrsys_timer_poff_clrb(void)4421__STATIC_INLINE void pwrctrl_wificore_pwrsys_timer_poff_clrb(void) 4422 { 4423 CS_PWRCTRL->WIFICORE &= ~PC_WIFICORE_PWRSYS_TMR_POFF_BIT; 4424 } 4425 pwrctrl_wificore_pwrsys_pon_getb(void)4426__STATIC_INLINE uint8_t pwrctrl_wificore_pwrsys_pon_getb(void) 4427 { 4428 return (CS_PWRCTRL->WIFICORE & PC_WIFICORE_PWRSYS_PON_BIT) >> PC_WIFICORE_PWRSYS_PON_POS; 4429 } 4430 pwrctrl_wificore_pwrsys_pon_setb(void)4431__STATIC_INLINE void pwrctrl_wificore_pwrsys_pon_setb(void) 4432 { 4433 CS_PWRCTRL->WIFICORE |= PC_WIFICORE_PWRSYS_PON_BIT; 4434 } 4435 pwrctrl_wificore_pwrsys_pon_clrb(void)4436__STATIC_INLINE void pwrctrl_wificore_pwrsys_pon_clrb(void) 4437 { 4438 CS_PWRCTRL->WIFICORE &= ~PC_WIFICORE_PWRSYS_PON_BIT; 4439 } 4440 pwrctrl_wificore_pwrsys_poff_getb(void)4441__STATIC_INLINE uint8_t pwrctrl_wificore_pwrsys_poff_getb(void) 4442 { 4443 return (CS_PWRCTRL->WIFICORE & PC_WIFICORE_PWRSYS_POFF_BIT) >> PC_WIFICORE_PWRSYS_POFF_POS; 4444 } 4445 pwrctrl_wificore_pwrsys_poff_setb(void)4446__STATIC_INLINE void pwrctrl_wificore_pwrsys_poff_setb(void) 4447 { 4448 CS_PWRCTRL->WIFICORE |= PC_WIFICORE_PWRSYS_POFF_BIT; 4449 } 4450 pwrctrl_wificore_pwrsys_poff_clrb(void)4451__STATIC_INLINE void pwrctrl_wificore_pwrsys_poff_clrb(void) 4452 { 4453 CS_PWRCTRL->WIFICORE &= ~PC_WIFICORE_PWRSYS_POFF_BIT; 4454 } 4455 pwrctrl_wificore_awake_soft_req_getb(void)4456__STATIC_INLINE uint8_t pwrctrl_wificore_awake_soft_req_getb(void) 4457 { 4458 return (CS_PWRCTRL->WIFICORE & PC_WIFICORE_AWAKE_SOFT_REQ_BIT) >> PC_WIFICORE_AWAKE_SOFT_REQ_POS; 4459 } 4460 pwrctrl_wificore_awake_soft_req_setb(void)4461__STATIC_INLINE void pwrctrl_wificore_awake_soft_req_setb(void) 4462 { 4463 CS_PWRCTRL->WIFICORE |= PC_WIFICORE_AWAKE_SOFT_REQ_BIT; 4464 } 4465 pwrctrl_wificore_awake_req_vld_clr_getb(void)4466__STATIC_INLINE uint8_t pwrctrl_wificore_awake_req_vld_clr_getb(void) 4467 { 4468 return (CS_PWRCTRL->WIFICORE & PC_WIFICORE_AWAKE_REQVLDCLR_BIT) >> PC_WIFICORE_AWAKE_REQVLDCLR_POS; 4469 } 4470 pwrctrl_wificore_awake_req_vld_clr_setb(void)4471__STATIC_INLINE void pwrctrl_wificore_awake_req_vld_clr_setb(void) 4472 { 4473 CS_PWRCTRL->WIFICORE |= PC_WIFICORE_AWAKE_REQVLDCLR_BIT; 4474 } 4475 pwrctrl_wificore_awake_soft_req_to_wifi_getb(void)4476__STATIC_INLINE uint8_t pwrctrl_wificore_awake_soft_req_to_wifi_getb(void) 4477 { 4478 return (CS_PWRCTRL->WIFICORE & PC_WIFICORE_AWAKE_SOFTREQWF_BIT) >> PC_WIFICORE_AWAKE_SOFTREQWF_POS; 4479 } 4480 pwrctrl_wificore_awake_soft_req_to_wifi_setb(void)4481__STATIC_INLINE void pwrctrl_wificore_awake_soft_req_to_wifi_setb(void) 4482 { 4483 CS_PWRCTRL->WIFICORE |= PC_WIFICORE_AWAKE_SOFTREQWF_BIT; 4484 } 4485 pwrctrl_wificore_awake_soft_req_to_wifi_clrb(void)4486__STATIC_INLINE void pwrctrl_wificore_awake_soft_req_to_wifi_clrb(void) 4487 { 4488 CS_PWRCTRL->WIFICORE &= ~PC_WIFICORE_AWAKE_SOFTREQWF_BIT; 4489 } 4490 4491 /** 4492 * Address Offset: 0x010 4493 * Register Name : PC PWRSYS CTRL 4494 */ 4495 4496 #define PC_PWRSYS_DEJITTER_LSB (0) 4497 #define PC_PWRSYS_DEJITTER_WIDTH (16) 4498 #define PC_PWRSYS_DEJITTER_MASK (((0x01UL << PC_PWRSYS_DEJITTER_WIDTH) - 1) << PC_PWRSYS_DEJITTER_LSB) 4499 #define PC_PWRSYS_PON_SOFT_POS (16) 4500 #define PC_PWRSYS_PON_SOFT_BIT (0x01UL << PC_PWRSYS_PON_SOFT_POS) 4501 #define PC_PWRSYS_PON_SOFT_EN_POS (17) 4502 #define PC_PWRSYS_PON_SOFT_EN_BIT (0x01UL << PC_PWRSYS_PON_SOFT_EN_POS) 4503 #define PC_PWRSYS_PU_PLL_SOFT_POS (18) 4504 #define PC_PWRSYS_PU_PLL_SOFT_BIT (0x01UL << PC_PWRSYS_PU_PLL_SOFT_POS) 4505 #define PC_PWRSYS_PU_PLL_SOFT_EN_POS (19) 4506 #define PC_PWRSYS_PU_PLL_SOFT_EN_BIT (0x01UL << PC_PWRSYS_PU_PLL_SOFT_EN_POS) 4507 #define PC_PWRSYS_CHIP_SLP_SOFT_POS (20) 4508 #define PC_PWRSYS_CHIP_SLP_SOFT_BIT (0x01UL << PC_PWRSYS_CHIP_SLP_SOFT_POS) 4509 #define PC_PWRSYS_CHIP_SLP_SOFT_EN_POS (21) 4510 #define PC_PWRSYS_CHIP_SLP_SOFT_EN_BIT (0x01UL << PC_PWRSYS_CHIP_SLP_SOFT_EN_POS) 4511 #define PC_PWRSYS_CG_PLL_SOFT_POS (22) 4512 #define PC_PWRSYS_CG_PLL_SOFT_BIT (0x01UL << PC_PWRSYS_CG_PLL_SOFT_POS) 4513 #define PC_PWRSYS_CG_PLL_SOFT_EN_POS (23) 4514 #define PC_PWRSYS_CG_PLL_SOFT_EN_BIT (0x01UL << PC_PWRSYS_CG_PLL_SOFT_EN_POS) 4515 #define PC_PWRSYS_CLK32K52M_SEL_SOFT_POS (24) 4516 #define PC_PWRSYS_CLK32K52M_SEL_SOFT_BIT (0x01UL << PC_PWRSYS_CLK32K52M_SEL_SOFT_POS) 4517 #define PC_PWRSYS_CLK32K52M_SEL_SOFT_EN_POS (25) 4518 #define PC_PWRSYS_CLK32K52M_SEL_SOFT_EN_BIT (0x01UL << PC_PWRSYS_CLK32K52M_SEL_SOFT_EN_POS) 4519 #define PC_PWRSYS_CLK32K52M_SW_EN_POS (26) 4520 #define PC_PWRSYS_CLK32K52M_SW_EN_BIT (0x01UL << PC_PWRSYS_CLK32K52M_SW_EN_POS) 4521 #define PC_PWRSYS_POFF_HW_EN_POS (27) 4522 #define PC_PWRSYS_POFF_HW_EN_BIT (0x01UL << PC_PWRSYS_POFF_HW_EN_POS) 4523 #define PC_PWRSYS_XTAL_PD_EN_POS (28) 4524 #define PC_PWRSYS_XTAL_PD_EN_BIT (0x01UL << PC_PWRSYS_XTAL_PD_EN_POS) 4525 #define PC_PWRSYS_PU_XTAL_SOFT_POS (29) 4526 #define PC_PWRSYS_PU_XTAL_SOFT_BIT (0x01UL << PC_PWRSYS_PU_XTAL_SOFT_POS) 4527 #define PC_PWRSYS_PU_XTAL_SOFT_EN_POS (30) 4528 #define PC_PWRSYS_PU_XTAL_SOFT_EN_BIT (0x01UL << PC_PWRSYS_PU_XTAL_SOFT_EN_POS) 4529 #define PC_PWRSYS_CHIP_SLP_HW_EN_POS (31) 4530 #define PC_PWRSYS_CHIP_SLP_HW_EN_BIT (0x01UL << PC_PWRSYS_CHIP_SLP_HW_EN_POS) 4531 pwrctrl_pwrsys_chip_slp_hw_en_getb(void)4532__STATIC_INLINE uint8_t pwrctrl_pwrsys_chip_slp_hw_en_getb(void) 4533 { 4534 return (CS_PWRCTRL->PWRSYS & PC_PWRSYS_CHIP_SLP_HW_EN_BIT) >> PC_PWRSYS_CHIP_SLP_HW_EN_POS; 4535 } 4536 pwrctrl_pwrsys_chip_slp_hw_en_setb(void)4537__STATIC_INLINE void pwrctrl_pwrsys_chip_slp_hw_en_setb(void) 4538 { 4539 CS_PWRCTRL->PWRSYS |= PC_PWRSYS_CHIP_SLP_HW_EN_BIT; 4540 } 4541 pwrctrl_pwrsys_chip_slp_hw_en_clrb(void)4542__STATIC_INLINE void pwrctrl_pwrsys_chip_slp_hw_en_clrb(void) 4543 { 4544 CS_PWRCTRL->PWRSYS &= ~PC_PWRSYS_CHIP_SLP_HW_EN_BIT; 4545 } 4546 4547 /** 4548 * Address Offset: 0x01C 4549 * Register Name : PC CTRL DELAY1 4550 */ 4551 4552 #define PC_CTRLDLY1_PRE_DELAY_LSB (0) 4553 #define PC_CTRLDLY1_PRE_DELAY_WIDTH (16) 4554 #define PC_CTRLDLY1_PRE_DELAY_MASK (((0x01UL << PC_CTRLDLY1_PRE_DELAY_WIDTH) - 1) << PC_CTRLDLY1_PRE_DELAY_LSB) 4555 #define PC_CTRLDLY1_DELAY_LSB (16) 4556 #define PC_CTRLDLY1_DELAY_WIDTH (16) 4557 #define PC_CTRLDLY1_DELAY_MASK (((0x01UL << PC_CTRLDLY1_DELAY_WIDTH) - 1) << PC_CTRLDLY1_DELAY_LSB) 4558 pwrctrl_ctrldly1_pre_delay_getf(void)4559__STATIC_INLINE uint16_t pwrctrl_ctrldly1_pre_delay_getf(void) 4560 { 4561 return ((CS_PWRCTRL->CTRLDLY[0] & PC_CTRLDLY1_PRE_DELAY_MASK) >> PC_CTRLDLY1_PRE_DELAY_LSB); 4562 } 4563 pwrctrl_ctrldly1_pre_delay_setf(uint16_t delay)4564__STATIC_INLINE void pwrctrl_ctrldly1_pre_delay_setf(uint16_t delay) 4565 { 4566 uint32_t local_val = CS_PWRCTRL->CTRLDLY[0] & ~PC_CTRLDLY1_PRE_DELAY_MASK; 4567 CS_PWRCTRL->CTRLDLY[0] = local_val | ((delay << PC_CTRLDLY1_PRE_DELAY_LSB) & PC_CTRLDLY1_PRE_DELAY_MASK); 4568 } 4569 pwrctrl_ctrldly1_delay_getf(void)4570__STATIC_INLINE uint16_t pwrctrl_ctrldly1_delay_getf(void) 4571 { 4572 return ((CS_PWRCTRL->CTRLDLY[0] & PC_CTRLDLY1_DELAY_MASK) >> PC_CTRLDLY1_DELAY_LSB); 4573 } 4574 pwrctrl_ctrldly1_delay_setf(uint16_t delay)4575__STATIC_INLINE void pwrctrl_ctrldly1_delay_setf(uint16_t delay) 4576 { 4577 uint32_t local_val = CS_PWRCTRL->CTRLDLY[0] & ~PC_CTRLDLY1_DELAY_MASK; 4578 CS_PWRCTRL->CTRLDLY[0] = local_val | ((delay << PC_CTRLDLY1_DELAY_LSB) & PC_CTRLDLY1_DELAY_MASK); 4579 } 4580 4581 /** 4582 * Address Offset: 0x020 4583 * Register Name : PC CTRL DELAY2 4584 */ 4585 4586 #define PC_CTRLDLY2_STATE_DELAY_LSB (0) 4587 #define PC_CTRLDLY2_STATE_DELAY_WIDTH (8) 4588 #define PC_CTRLDLY2_STATE_DELAY_MASK (((0x01UL << PC_CTRLDLY2_STATE_DELAY_WIDTH) - 1) << PC_CTRLDLY2_STATE_DELAY_LSB) 4589 #define PC_CTRLDLY2_XTAL_CLOSE_DELAY_LSB (8) 4590 #define PC_CTRLDLY2_XTAL_CLOSE_DELAY_WIDTH (8) 4591 #define PC_CTRLDLY2_XTAL_CLOSE_DELAY_MASK (((0x01UL << PC_CTRLDLY2_XTAL_CLOSE_DELAY_WIDTH) - 1) << PC_CTRLDLY2_XTAL_CLOSE_DELAY_LSB) 4592 #define PC_CTRLDLY2_XTAL_OPEN_DELAY_LSB (16) 4593 #define PC_CTRLDLY2_XTAL_OPEN_DELAY_WIDTH (8) 4594 #define PC_CTRLDLY2_XTAL_OPEN_DELAY_MASK (((0x01UL << PC_CTRLDLY2_XTAL_OPEN_DELAY_WIDTH) - 1) << PC_CTRLDLY2_XTAL_OPEN_DELAY_LSB) 4595 #define PC_CTRLDLY2_PUPD_XTAL_DELAY_LSB (24) 4596 #define PC_CTRLDLY2_PUPD_XTAL_DELAY_WIDTH (8) 4597 #define PC_CTRLDLY2_PUPD_XTAL_DELAY_MASK (((0x01UL << PC_CTRLDLY2_PUPD_XTAL_DELAY_WIDTH) - 1) << PC_CTRLDLY2_PUPD_XTAL_DELAY_LSB) 4598 pwrctrl_ctrldly2_state_delay_getf(void)4599__STATIC_INLINE uint8_t pwrctrl_ctrldly2_state_delay_getf(void) 4600 { 4601 return ((CS_PWRCTRL->CTRLDLY[1] & PC_CTRLDLY2_STATE_DELAY_MASK) >> PC_CTRLDLY2_STATE_DELAY_LSB); 4602 } 4603 pwrctrl_ctrldly2_state_delay_setf(uint8_t delay)4604__STATIC_INLINE void pwrctrl_ctrldly2_state_delay_setf(uint8_t delay) 4605 { 4606 uint32_t local_val = CS_PWRCTRL->CTRLDLY[1] & ~PC_CTRLDLY2_STATE_DELAY_MASK; 4607 CS_PWRCTRL->CTRLDLY[1] = local_val | ((delay << PC_CTRLDLY2_STATE_DELAY_LSB) & PC_CTRLDLY2_STATE_DELAY_MASK); 4608 } 4609 pwrctrl_ctrldly2_xtal_close_delay_getf(void)4610__STATIC_INLINE uint8_t pwrctrl_ctrldly2_xtal_close_delay_getf(void) 4611 { 4612 return ((CS_PWRCTRL->CTRLDLY[1] & PC_CTRLDLY2_XTAL_CLOSE_DELAY_MASK) >> PC_CTRLDLY2_XTAL_CLOSE_DELAY_LSB); 4613 } 4614 pwrctrl_ctrldly2_xtal_close_delay_setf(uint8_t delay)4615__STATIC_INLINE void pwrctrl_ctrldly2_xtal_close_delay_setf(uint8_t delay) 4616 { 4617 uint32_t local_val = CS_PWRCTRL->CTRLDLY[1] & ~PC_CTRLDLY2_XTAL_CLOSE_DELAY_MASK; 4618 CS_PWRCTRL->CTRLDLY[1] = local_val | ((delay << PC_CTRLDLY2_XTAL_CLOSE_DELAY_LSB) & PC_CTRLDLY2_XTAL_CLOSE_DELAY_MASK); 4619 } 4620 pwrctrl_ctrldly2_xtal_open_delay_getf(void)4621__STATIC_INLINE uint8_t pwrctrl_ctrldly2_xtal_open_delay_getf(void) 4622 { 4623 return ((CS_PWRCTRL->CTRLDLY[1] & PC_CTRLDLY2_XTAL_OPEN_DELAY_MASK) >> PC_CTRLDLY2_XTAL_OPEN_DELAY_LSB); 4624 } 4625 pwrctrl_ctrldly2_xtal_open_delay_setf(uint8_t delay)4626__STATIC_INLINE void pwrctrl_ctrldly2_xtal_open_delay_setf(uint8_t delay) 4627 { 4628 uint32_t local_val = CS_PWRCTRL->CTRLDLY[1] & ~PC_CTRLDLY2_XTAL_OPEN_DELAY_MASK; 4629 CS_PWRCTRL->CTRLDLY[1] = local_val | ((delay << PC_CTRLDLY2_XTAL_OPEN_DELAY_LSB) & PC_CTRLDLY2_XTAL_OPEN_DELAY_MASK); 4630 } 4631 pwrctrl_ctrldly2_pupd_xtal_delay_getf(void)4632__STATIC_INLINE uint8_t pwrctrl_ctrldly2_pupd_xtal_delay_getf(void) 4633 { 4634 return ((CS_PWRCTRL->CTRLDLY[1] & PC_CTRLDLY2_PUPD_XTAL_DELAY_MASK) >> PC_CTRLDLY2_PUPD_XTAL_DELAY_LSB); 4635 } 4636 pwrctrl_ctrldly2_pupd_xtal_delay_setf(uint8_t delay)4637__STATIC_INLINE void pwrctrl_ctrldly2_pupd_xtal_delay_setf(uint8_t delay) 4638 { 4639 uint32_t local_val = CS_PWRCTRL->CTRLDLY[1] & ~PC_CTRLDLY2_PUPD_XTAL_DELAY_MASK; 4640 CS_PWRCTRL->CTRLDLY[1] = local_val | ((delay << PC_CTRLDLY2_PUPD_XTAL_DELAY_LSB) & PC_CTRLDLY2_PUPD_XTAL_DELAY_MASK); 4641 } 4642 4643 /** 4644 * Address Offset: 0x024 4645 * Register Name : PC SYS DELAY1 4646 */ 4647 4648 #define PC_SYSDLY1_DP_OPEN_DELAY_LSB (0) 4649 #define PC_SYSDLY1_DP_OPEN_DELAY_WIDTH (8) 4650 #define PC_SYSDLY1_DP_OPEN_DELAY_MASK (((0x01UL << PC_SYSDLY1_DP_OPEN_DELAY_WIDTH) - 1) << PC_SYSDLY1_DP_OPEN_DELAY_LSB) 4651 #define PC_SYSDLY1_DP_CLOSE_DELAY_LSB (8) 4652 #define PC_SYSDLY1_DP_CLOSE_DELAY_WIDTH (8) 4653 #define PC_SYSDLY1_DP_CLOSE_DELAY_MASK (((0x01UL << PC_SYSDLY1_DP_CLOSE_DELAY_WIDTH) - 1) << PC_SYSDLY1_DP_CLOSE_DELAY_LSB) 4654 #define PC_SYSDLY1_CG_OPEN_DELAY_LSB (16) 4655 #define PC_SYSDLY1_CG_OPEN_DELAY_WIDTH (8) 4656 #define PC_SYSDLY1_CG_OPEN_DELAY_MASK (((0x01UL << PC_SYSDLY1_CG_OPEN_DELAY_WIDTH) - 1) << PC_SYSDLY1_CG_OPEN_DELAY_LSB) 4657 #define PC_SYSDLY1_CG_CLOSE_DELAY_LSB (24) 4658 #define PC_SYSDLY1_CG_CLOSE_DELAY_WIDTH (8) 4659 #define PC_SYSDLY1_CG_CLOSE_DELAY_MASK (((0x01UL << PC_SYSDLY1_CG_CLOSE_DELAY_WIDTH) - 1) << PC_SYSDLY1_CG_CLOSE_DELAY_LSB) 4660 pwrctrl_sysdly1_dp_open_delay_getf(void)4661__STATIC_INLINE uint8_t pwrctrl_sysdly1_dp_open_delay_getf(void) 4662 { 4663 return ((CS_PWRCTRL->SYSDLY[0] & PC_SYSDLY1_DP_OPEN_DELAY_MASK) >> PC_SYSDLY1_DP_OPEN_DELAY_LSB); 4664 } 4665 pwrctrl_sysdly1_dp_open_delay_setf(uint8_t delay)4666__STATIC_INLINE void pwrctrl_sysdly1_dp_open_delay_setf(uint8_t delay) 4667 { 4668 uint32_t local_val = CS_PWRCTRL->SYSDLY[0] & ~PC_SYSDLY1_DP_OPEN_DELAY_MASK; 4669 CS_PWRCTRL->SYSDLY[0] = local_val | ((delay << PC_SYSDLY1_DP_OPEN_DELAY_LSB) & PC_SYSDLY1_DP_OPEN_DELAY_MASK); 4670 } 4671 pwrctrl_sysdly1_dp_close_delay_getf(void)4672__STATIC_INLINE uint8_t pwrctrl_sysdly1_dp_close_delay_getf(void) 4673 { 4674 return ((CS_PWRCTRL->SYSDLY[0] & PC_SYSDLY1_DP_CLOSE_DELAY_MASK) >> PC_SYSDLY1_DP_CLOSE_DELAY_LSB); 4675 } 4676 pwrctrl_sysdly1_dp_close_delay_setf(uint8_t delay)4677__STATIC_INLINE void pwrctrl_sysdly1_dp_close_delay_setf(uint8_t delay) 4678 { 4679 uint32_t local_val = CS_PWRCTRL->SYSDLY[0] & ~PC_SYSDLY1_DP_CLOSE_DELAY_MASK; 4680 CS_PWRCTRL->SYSDLY[0] = local_val | ((delay << PC_SYSDLY1_DP_CLOSE_DELAY_LSB) & PC_SYSDLY1_DP_CLOSE_DELAY_MASK); 4681 } 4682 pwrctrl_sysdly1_cg_open_delay_getf(void)4683__STATIC_INLINE uint8_t pwrctrl_sysdly1_cg_open_delay_getf(void) 4684 { 4685 return ((CS_PWRCTRL->SYSDLY[0] & PC_SYSDLY1_CG_OPEN_DELAY_MASK) >> PC_SYSDLY1_CG_OPEN_DELAY_LSB); 4686 } 4687 pwrctrl_sysdly1_cg_open_delay_setf(uint8_t delay)4688__STATIC_INLINE void pwrctrl_sysdly1_cg_open_delay_setf(uint8_t delay) 4689 { 4690 uint32_t local_val = CS_PWRCTRL->SYSDLY[0] & ~PC_SYSDLY1_CG_OPEN_DELAY_MASK; 4691 CS_PWRCTRL->SYSDLY[0] = local_val | ((delay << PC_SYSDLY1_CG_OPEN_DELAY_LSB) & PC_SYSDLY1_CG_OPEN_DELAY_MASK); 4692 } 4693 pwrctrl_sysdly1_cg_close_delay_getf(void)4694__STATIC_INLINE uint8_t pwrctrl_sysdly1_cg_close_delay_getf(void) 4695 { 4696 return ((CS_PWRCTRL->SYSDLY[0] & PC_SYSDLY1_CG_CLOSE_DELAY_MASK) >> PC_SYSDLY1_CG_CLOSE_DELAY_LSB); 4697 } 4698 pwrctrl_sysdly1_cg_close_delay_setf(uint8_t delay)4699__STATIC_INLINE void pwrctrl_sysdly1_cg_close_delay_setf(uint8_t delay) 4700 { 4701 uint32_t local_val = CS_PWRCTRL->SYSDLY[0] & ~PC_SYSDLY1_CG_CLOSE_DELAY_MASK; 4702 CS_PWRCTRL->SYSDLY[0] = local_val | ((delay << PC_SYSDLY1_CG_CLOSE_DELAY_LSB) & PC_SYSDLY1_CG_CLOSE_DELAY_MASK); 4703 } 4704 4705 /** 4706 * Address Offset: 0x028 4707 * Register Name : PC SYS DELAY2 4708 */ 4709 4710 #define PC_SYSDLY2_PWR_OPEN_DELAY_LSB (0) 4711 #define PC_SYSDLY2_PWR_OPEN_DELAY_WIDTH (8) 4712 #define PC_SYSDLY2_PWR_OPEN_DELAY_MASK (((0x01UL << PC_SYSDLY2_PWR_OPEN_DELAY_WIDTH) - 1) << PC_SYSDLY2_PWR_OPEN_DELAY_LSB) 4713 #define PC_SYSDLY2_PWR_CLOSE_DELAY_LSB (8) 4714 #define PC_SYSDLY2_PWR_CLOSE_DELAY_WIDTH (8) 4715 #define PC_SYSDLY2_PWR_CLOSE_DELAY_MASK (((0x01UL << PC_SYSDLY2_PWR_CLOSE_DELAY_WIDTH) - 1) << PC_SYSDLY2_PWR_CLOSE_DELAY_LSB) 4716 #define PC_SYSDLY2_PLL_OPEN_DELAY_LSB (16) 4717 #define PC_SYSDLY2_PLL_OPEN_DELAY_WIDTH (8) 4718 #define PC_SYSDLY2_PLL_OPEN_DELAY_MASK (((0x01UL << PC_SYSDLY2_PLL_OPEN_DELAY_WIDTH) - 1) << PC_SYSDLY2_PLL_OPEN_DELAY_LSB) 4719 #define PC_SYSDLY2_PLL_CLOSE_DELAY_LSB (24) 4720 #define PC_SYSDLY2_PLL_CLOSE_DELAY_WIDTH (8) 4721 #define PC_SYSDLY2_PLL_CLOSE_DELAY_MASK (((0x01UL << PC_SYSDLY2_PLL_CLOSE_DELAY_WIDTH) - 1) << PC_SYSDLY2_PLL_CLOSE_DELAY_LSB) 4722 pwrctrl_sysdly2_pwr_open_delay_getf(void)4723__STATIC_INLINE uint8_t pwrctrl_sysdly2_pwr_open_delay_getf(void) 4724 { 4725 return ((CS_PWRCTRL->SYSDLY[1] & PC_SYSDLY2_PWR_OPEN_DELAY_MASK) >> PC_SYSDLY2_PWR_OPEN_DELAY_LSB); 4726 } 4727 pwrctrl_sysdly2_pwr_open_delay_setf(uint8_t delay)4728__STATIC_INLINE void pwrctrl_sysdly2_pwr_open_delay_setf(uint8_t delay) 4729 { 4730 uint32_t local_val = CS_PWRCTRL->SYSDLY[1] & ~PC_SYSDLY2_PWR_OPEN_DELAY_MASK; 4731 CS_PWRCTRL->SYSDLY[1] = local_val | ((delay << PC_SYSDLY2_PWR_OPEN_DELAY_LSB) & PC_SYSDLY2_PWR_OPEN_DELAY_MASK); 4732 } 4733 pwrctrl_sysdly2_pwr_close_delay_getf(void)4734__STATIC_INLINE uint8_t pwrctrl_sysdly2_pwr_close_delay_getf(void) 4735 { 4736 return ((CS_PWRCTRL->SYSDLY[1] & PC_SYSDLY2_PWR_CLOSE_DELAY_MASK) >> PC_SYSDLY2_PWR_CLOSE_DELAY_LSB); 4737 } 4738 pwrctrl_sysdly2_pwr_close_delay_setf(uint8_t delay)4739__STATIC_INLINE void pwrctrl_sysdly2_pwr_close_delay_setf(uint8_t delay) 4740 { 4741 uint32_t local_val = CS_PWRCTRL->SYSDLY[1] & ~PC_SYSDLY2_PWR_CLOSE_DELAY_MASK; 4742 CS_PWRCTRL->SYSDLY[1] = local_val | ((delay << PC_SYSDLY2_PWR_CLOSE_DELAY_LSB) & PC_SYSDLY2_PWR_CLOSE_DELAY_MASK); 4743 } 4744 pwrctrl_sysdly2_pll_open_delay_getf(void)4745__STATIC_INLINE uint8_t pwrctrl_sysdly2_pll_open_delay_getf(void) 4746 { 4747 return ((CS_PWRCTRL->SYSDLY[1] & PC_SYSDLY2_PLL_OPEN_DELAY_MASK) >> PC_SYSDLY2_PLL_OPEN_DELAY_LSB); 4748 } 4749 pwrctrl_sysdly2_pll_open_delay_setf(uint8_t delay)4750__STATIC_INLINE void pwrctrl_sysdly2_pll_open_delay_setf(uint8_t delay) 4751 { 4752 uint32_t local_val = CS_PWRCTRL->SYSDLY[1] & ~PC_SYSDLY2_PLL_OPEN_DELAY_MASK; 4753 CS_PWRCTRL->SYSDLY[1] = local_val | ((delay << PC_SYSDLY2_PLL_OPEN_DELAY_LSB) & PC_SYSDLY2_PLL_OPEN_DELAY_MASK); 4754 } 4755 pwrctrl_sysdly2_pll_close_delay_getf(void)4756__STATIC_INLINE uint8_t pwrctrl_sysdly2_pll_close_delay_getf(void) 4757 { 4758 return ((CS_PWRCTRL->SYSDLY[1] & PC_SYSDLY2_PLL_CLOSE_DELAY_MASK) >> PC_SYSDLY2_PLL_CLOSE_DELAY_LSB); 4759 } 4760 pwrctrl_sysdly2_pll_close_delay_setf(uint8_t delay)4761__STATIC_INLINE void pwrctrl_sysdly2_pll_close_delay_setf(uint8_t delay) 4762 { 4763 uint32_t local_val = CS_PWRCTRL->SYSDLY[1] & ~PC_SYSDLY2_PLL_CLOSE_DELAY_MASK; 4764 CS_PWRCTRL->SYSDLY[1] = local_val | ((delay << PC_SYSDLY2_PLL_CLOSE_DELAY_LSB) & PC_SYSDLY2_PLL_CLOSE_DELAY_MASK); 4765 } 4766 4767 /** 4768 * Address Offset: 0x030 4769 * Register Name : PC STATE1 4770 */ 4771 4772 #define PC_STATE1_PONSTAB_WIFICORE_POS (1) 4773 #define PC_STATE1_PONSTAB_WIFICORE_BIT (0x01UL << PC_STATE1_PONSTAB_WIFICORE_POS) 4774 #define PC_STATE1_PONSTAB_BTCORE_POS (2) 4775 #define PC_STATE1_PONSTAB_BTCORE_BIT (0x01UL << PC_STATE1_PONSTAB_BTCORE_POS) 4776 #define PC_STATE1_PONSTAB_CPUSYS_POS (3) 4777 #define PC_STATE1_PONSTAB_CPUSYS_BIT (0x01UL << PC_STATE1_PONSTAB_CPUSYS_POS) 4778 #define PC_STATE1_POFFSTAB_WIFICORE_POS (5) 4779 #define PC_STATE1_POFFSTAB_WIFICORE_BIT (0x01UL << PC_STATE1_POFFSTAB_WIFICORE_POS) 4780 #define PC_STATE1_POFFSTAB_BTCORE_POS (6) 4781 #define PC_STATE1_POFFSTAB_BTCORE_BIT (0x01UL << PC_STATE1_POFFSTAB_BTCORE_POS) 4782 #define PC_STATE1_POFFSTAB_CPUSYS_POS (7) 4783 #define PC_STATE1_POFFSTAB_CPUSYS_BIT (0x01UL << PC_STATE1_POFFSTAB_CPUSYS_POS) 4784 #define PC_STATE1_STATE_WIFICORE_LSB (8) 4785 #define PC_STATE1_STATE_WIFICORE_WIDTH (4) 4786 #define PC_STATE1_STATE_WIFICORE_MASK (((0x01UL << PC_STATE1_STATE_WIFICORE_WIDTH) - 1) << PC_STATE1_STATE_WIFICORE_LSB) 4787 #define PC_STATE1_STATE_BTCORE_LSB (12) 4788 #define PC_STATE1_STATE_BTCORE_WIDTH (4) 4789 #define PC_STATE1_STATE_BTCORE_MASK (((0x01UL << PC_STATE1_STATE_BTCORE_WIDTH) - 1) << PC_STATE1_STATE_BTCORE_LSB) 4790 #define PC_STATE1_STATE_CPUSYS_LSB (16) 4791 #define PC_STATE1_STATE_CPUSYS_WIDTH (4) 4792 #define PC_STATE1_STATE_CPUSYS_MASK (((0x01UL << PC_STATE1_STATE_CPUSYS_WIDTH) - 1) << PC_STATE1_STATE_CPUSYS_LSB) 4793 #define PC_STATE1_CURSTATE_WIFICORE_LSB (20) 4794 #define PC_STATE1_CURSTATE_WIFICORE_WIDTH (2) 4795 #define PC_STATE1_CURSTATE_WIFICORE_MASK (((0x01UL << PC_STATE1_CURSTATE_WIFICORE_WIDTH) - 1) << PC_STATE1_CURSTATE_WIFICORE_LSB) 4796 #define PC_STATE1_CURSTATE_BTCORE_LSB (22) 4797 #define PC_STATE1_CURSTATE_BTCORE_WIDTH (2) 4798 #define PC_STATE1_CURSTATE_BTCORE_MASK (((0x01UL << PC_STATE1_CURSTATE_BTCORE_WIDTH) - 1) << PC_STATE1_CURSTATE_BTCORE_LSB) 4799 #define PC_STATE1_CURSTATE_CPUSYS_LSB (24) 4800 #define PC_STATE1_CURSTATE_CPUSYS_WIDTH (2) 4801 #define PC_STATE1_CURSTATE_CPUSYS_MASK (((0x01UL << PC_STATE1_CURSTATE_CPUSYS_WIDTH) - 1) << PC_STATE1_CURSTATE_CPUSYS_LSB) 4802 #define PC_STATE1_CURSTATE_PWRSYS_LSB (26) 4803 #define PC_STATE1_CURSTATE_PWRSYS_WIDTH (4) 4804 #define PC_STATE1_CURSTATE_PWRSYS_MASK (((0x01UL << PC_STATE1_CURSTATE_PWRSYS_WIDTH) - 1) << PC_STATE1_CURSTATE_PWRSYS_LSB) 4805 #define PC_STATE1_CURSTATE_VCORESYS_LSB (30) 4806 #define PC_STATE1_CURSTATE_VCORESYS_WIDTH (2) 4807 #define PC_STATE1_CURSTATE_VCORESYS_MASK (((0x01UL << PC_STATE1_CURSTATE_VCORESYS_WIDTH) - 1) << PC_STATE1_CURSTATE_VCORESYS_LSB) 4808 pwrctrl_state1_pon_stable_wificore_getb(void)4809__STATIC_INLINE uint8_t pwrctrl_state1_pon_stable_wificore_getb(void) 4810 { 4811 return (CS_PWRCTRL->STATE[0] & PC_STATE1_PONSTAB_WIFICORE_BIT) >> PC_STATE1_PONSTAB_WIFICORE_POS; 4812 } 4813 pwrctrl_state1_pon_stable_btcore_getb(void)4814__STATIC_INLINE uint8_t pwrctrl_state1_pon_stable_btcore_getb(void) 4815 { 4816 return (CS_PWRCTRL->STATE[0] & PC_STATE1_PONSTAB_BTCORE_BIT) >> PC_STATE1_PONSTAB_BTCORE_POS; 4817 } 4818 pwrctrl_state1_pon_stable_cpusys_getb(void)4819__STATIC_INLINE uint8_t pwrctrl_state1_pon_stable_cpusys_getb(void) 4820 { 4821 return (CS_PWRCTRL->STATE[0] & PC_STATE1_PONSTAB_CPUSYS_BIT) >> PC_STATE1_PONSTAB_CPUSYS_POS; 4822 } 4823 pwrctrl_state1_poff_stable_wificore_getb(void)4824__STATIC_INLINE uint8_t pwrctrl_state1_poff_stable_wificore_getb(void) 4825 { 4826 return (CS_PWRCTRL->STATE[0] & PC_STATE1_POFFSTAB_WIFICORE_BIT) >> PC_STATE1_POFFSTAB_WIFICORE_POS; 4827 } 4828 pwrctrl_state1_poff_stable_btcore_getb(void)4829__STATIC_INLINE uint8_t pwrctrl_state1_poff_stable_btcore_getb(void) 4830 { 4831 return (CS_PWRCTRL->STATE[0] & PC_STATE1_POFFSTAB_BTCORE_BIT) >> PC_STATE1_POFFSTAB_BTCORE_POS; 4832 } 4833 pwrctrl_state1_poff_stable_cpusys_getb(void)4834__STATIC_INLINE uint8_t pwrctrl_state1_poff_stable_cpusys_getb(void) 4835 { 4836 return (CS_PWRCTRL->STATE[0] & PC_STATE1_POFFSTAB_CPUSYS_BIT) >> PC_STATE1_POFFSTAB_CPUSYS_POS; 4837 } 4838 pwrctrl_state1_state_wificore_getf(void)4839__STATIC_INLINE uint8_t pwrctrl_state1_state_wificore_getf(void) 4840 { 4841 return ((CS_PWRCTRL->STATE[0] & PC_STATE1_STATE_WIFICORE_MASK) >> PC_STATE1_STATE_WIFICORE_LSB); 4842 } 4843 pwrctrl_state1_state_btcore_getf(void)4844__STATIC_INLINE uint8_t pwrctrl_state1_state_btcore_getf(void) 4845 { 4846 return ((CS_PWRCTRL->STATE[0] & PC_STATE1_STATE_BTCORE_MASK) >> PC_STATE1_STATE_BTCORE_LSB); 4847 } 4848 pwrctrl_state1_state_cpusys_getf(void)4849__STATIC_INLINE uint8_t pwrctrl_state1_state_cpusys_getf(void) 4850 { 4851 return ((CS_PWRCTRL->STATE[0] & PC_STATE1_STATE_CPUSYS_MASK) >> PC_STATE1_STATE_CPUSYS_LSB); 4852 } 4853 pwrctrl_state1_curstate_wificore_getf(void)4854__STATIC_INLINE uint8_t pwrctrl_state1_curstate_wificore_getf(void) 4855 { 4856 return ((CS_PWRCTRL->STATE[0] & PC_STATE1_CURSTATE_WIFICORE_MASK) >> PC_STATE1_CURSTATE_WIFICORE_LSB); 4857 } 4858 pwrctrl_state1_curstate_btcore_getf(void)4859__STATIC_INLINE uint8_t pwrctrl_state1_curstate_btcore_getf(void) 4860 { 4861 return ((CS_PWRCTRL->STATE[0] & PC_STATE1_CURSTATE_BTCORE_MASK) >> PC_STATE1_CURSTATE_BTCORE_LSB); 4862 } 4863 pwrctrl_state1_curstate_cpusys_getf(void)4864__STATIC_INLINE uint8_t pwrctrl_state1_curstate_cpusys_getf(void) 4865 { 4866 return ((CS_PWRCTRL->STATE[0] & PC_STATE1_CURSTATE_CPUSYS_MASK) >> PC_STATE1_CURSTATE_CPUSYS_LSB); 4867 } 4868 pwrctrl_state1_curstate_pwrsys_getf(void)4869__STATIC_INLINE uint8_t pwrctrl_state1_curstate_pwrsys_getf(void) 4870 { 4871 return ((CS_PWRCTRL->STATE[0] & PC_STATE1_CURSTATE_PWRSYS_MASK) >> PC_STATE1_CURSTATE_PWRSYS_LSB); 4872 } 4873 pwrctrl_state1_curstate_vcoresys_getf(void)4874__STATIC_INLINE uint8_t pwrctrl_state1_curstate_vcoresys_getf(void) 4875 { 4876 return ((CS_PWRCTRL->STATE[0] & PC_STATE1_CURSTATE_VCORESYS_MASK) >> PC_STATE1_CURSTATE_VCORESYS_LSB); 4877 } 4878 4879 /** 4880 * Address Offset: 0x034 4881 * Register Name : PC STATE2 4882 */ 4883 4884 #define PC_STATE2_PONSTAB_VCORESYS_POS (0) 4885 #define PC_STATE2_PONSTAB_VCORESYS_BIT (0x01UL << PC_STATE2_PONSTAB_VCORESYS_POS) 4886 #define PC_STATE2_PONSTAB_AONRAM1_POS (1) 4887 #define PC_STATE2_PONSTAB_AONRAM1_BIT (0x01UL << PC_STATE2_PONSTAB_AONRAM1_POS) 4888 #define PC_STATE2_PONSTAB_AONRAM2_POS (2) 4889 #define PC_STATE2_PONSTAB_AONRAM2_BIT (0x01UL << PC_STATE2_PONSTAB_AONRAM2_POS) 4890 #define PC_STATE2_PONSTAB_MMSYS_POS (3) 4891 #define PC_STATE2_PONSTAB_MMSYS_BIT (0x01UL << PC_STATE2_PONSTAB_MMSYS_POS) 4892 #define PC_STATE2_POFFSTAB_VCORESYS_POS (4) 4893 #define PC_STATE2_POFFSTAB_VCORESYS_BIT (0x01UL << PC_STATE2_POFFSTAB_VCORESYS_POS) 4894 #define PC_STATE2_POFFSTAB_AONRAM1_POS (5) 4895 #define PC_STATE2_POFFSTAB_AONRAM1_BIT (0x01UL << PC_STATE2_POFFSTAB_AONRAM1_POS) 4896 #define PC_STATE2_POFFSTAB_AONRAM2_POS (6) 4897 #define PC_STATE2_POFFSTAB_AONRAM2_BIT (0x01UL << PC_STATE2_POFFSTAB_AONRAM2_POS) 4898 #define PC_STATE2_POFFSTAB_MMSYS_POS (7) 4899 #define PC_STATE2_POFFSTAB_MMSYS_BIT (0x01UL << PC_STATE2_POFFSTAB_MMSYS_POS) 4900 #define PC_STATE2_STATE_AONRAM1_LSB (8) 4901 #define PC_STATE2_STATE_AONRAM1_WIDTH (4) 4902 #define PC_STATE2_STATE_AONRAM1_MASK (((0x01UL << PC_STATE2_STATE_AONRAM1_WIDTH) - 1) << PC_STATE2_STATE_AONRAM1_LSB) 4903 #define PC_STATE2_STATE_AONRAM2_LSB (12) 4904 #define PC_STATE2_STATE_AONRAM2_WIDTH (4) 4905 #define PC_STATE2_STATE_AONRAM2_MASK (((0x01UL << PC_STATE2_STATE_AONRAM2_WIDTH) - 1) << PC_STATE2_STATE_AONRAM2_LSB) 4906 #define PC_STATE2_STATE_MMSYS_LSB (16) 4907 #define PC_STATE2_STATE_MMSYS_WIDTH (4) 4908 #define PC_STATE2_STATE_MMSYS_MASK (((0x01UL << PC_STATE2_STATE_MMSYS_WIDTH) - 1) << PC_STATE2_STATE_MMSYS_LSB) 4909 #define PC_STATE2_STATE_VCORESYS_LSB (20) 4910 #define PC_STATE2_STATE_VCORESYS_WIDTH (4) 4911 #define PC_STATE2_STATE_VCORESYS_MASK (((0x01UL << PC_STATE2_STATE_VCORESYS_WIDTH) - 1) << PC_STATE2_STATE_VCORESYS_LSB) 4912 pwrctrl_state2_pon_stable_vcoresys_getb(void)4913__STATIC_INLINE uint8_t pwrctrl_state2_pon_stable_vcoresys_getb(void) 4914 { 4915 return (CS_PWRCTRL->STATE[1] & PC_STATE2_PONSTAB_VCORESYS_BIT) >> PC_STATE2_PONSTAB_VCORESYS_POS; 4916 } 4917 pwrctrl_state2_pon_stable_aonram1_getb(void)4918__STATIC_INLINE uint8_t pwrctrl_state2_pon_stable_aonram1_getb(void) 4919 { 4920 return (CS_PWRCTRL->STATE[1] & PC_STATE2_PONSTAB_AONRAM1_BIT) >> PC_STATE2_PONSTAB_AONRAM1_POS; 4921 } 4922 pwrctrl_state2_pon_stable_aonram2_getb(void)4923__STATIC_INLINE uint8_t pwrctrl_state2_pon_stable_aonram2_getb(void) 4924 { 4925 return (CS_PWRCTRL->STATE[1] & PC_STATE2_PONSTAB_AONRAM2_BIT) >> PC_STATE2_PONSTAB_AONRAM2_POS; 4926 } 4927 pwrctrl_state2_pon_stable_mmsys_getb(void)4928__STATIC_INLINE uint8_t pwrctrl_state2_pon_stable_mmsys_getb(void) 4929 { 4930 return (CS_PWRCTRL->STATE[1] & PC_STATE2_PONSTAB_MMSYS_BIT) >> PC_STATE2_PONSTAB_MMSYS_POS; 4931 } 4932 pwrctrl_state2_poff_stable_vcoresys_getb(void)4933__STATIC_INLINE uint8_t pwrctrl_state2_poff_stable_vcoresys_getb(void) 4934 { 4935 return (CS_PWRCTRL->STATE[1] & PC_STATE2_POFFSTAB_VCORESYS_BIT) >> PC_STATE2_POFFSTAB_VCORESYS_POS; 4936 } 4937 pwrctrl_state2_poff_stable_aonram1_getb(void)4938__STATIC_INLINE uint8_t pwrctrl_state2_poff_stable_aonram1_getb(void) 4939 { 4940 return (CS_PWRCTRL->STATE[1] & PC_STATE2_POFFSTAB_AONRAM1_BIT) >> PC_STATE2_POFFSTAB_AONRAM1_POS; 4941 } 4942 pwrctrl_state2_poff_stable_aonram2_getb(void)4943__STATIC_INLINE uint8_t pwrctrl_state2_poff_stable_aonram2_getb(void) 4944 { 4945 return (CS_PWRCTRL->STATE[1] & PC_STATE2_POFFSTAB_AONRAM2_BIT) >> PC_STATE2_POFFSTAB_AONRAM2_POS; 4946 } 4947 pwrctrl_state2_poff_stable_mmsys_getb(void)4948__STATIC_INLINE uint8_t pwrctrl_state2_poff_stable_mmsys_getb(void) 4949 { 4950 return (CS_PWRCTRL->STATE[1] & PC_STATE2_POFFSTAB_MMSYS_BIT) >> PC_STATE2_POFFSTAB_MMSYS_POS; 4951 } 4952 pwrctrl_state2_state_aonram1_getf(void)4953__STATIC_INLINE uint8_t pwrctrl_state2_state_aonram1_getf(void) 4954 { 4955 return ((CS_PWRCTRL->STATE[1] & PC_STATE2_STATE_AONRAM1_MASK) >> PC_STATE2_STATE_AONRAM1_LSB); 4956 } 4957 pwrctrl_state2_state_aonram2_getf(void)4958__STATIC_INLINE uint8_t pwrctrl_state2_state_aonram2_getf(void) 4959 { 4960 return ((CS_PWRCTRL->STATE[1] & PC_STATE2_STATE_AONRAM2_MASK) >> PC_STATE2_STATE_AONRAM2_LSB); 4961 } 4962 pwrctrl_state2_state_mmsys_getf(void)4963__STATIC_INLINE uint8_t pwrctrl_state2_state_mmsys_getf(void) 4964 { 4965 return ((CS_PWRCTRL->STATE[1] & PC_STATE2_STATE_MMSYS_MASK) >> PC_STATE2_STATE_MMSYS_LSB); 4966 } 4967 pwrctrl_state2_state_vcoresys_getf(void)4968__STATIC_INLINE uint8_t pwrctrl_state2_state_vcoresys_getf(void) 4969 { 4970 return ((CS_PWRCTRL->STATE[1] & PC_STATE2_STATE_VCORESYS_MASK) >> PC_STATE2_STATE_VCORESYS_LSB); 4971 } 4972 4973 /** 4974 * Address Offset: 0x038 4975 * Register Name : PC SOFTMD1 4976 */ 4977 4978 #define PC_SOFTMD1_CPUSYS_PWRCTRL_SOFT_LSB (0) 4979 #define PC_SOFTMD1_CPUSYS_PWRCTRL_SOFT_WIDTH (6) 4980 #define PC_SOFTMD1_CPUSYS_PWRCTRL_SOFT_MASK (((0x01UL << PC_SOFTMD1_CPUSYS_PWRCTRL_SOFT_WIDTH) - 1) << PC_SOFTMD1_CPUSYS_PWRCTRL_SOFT_LSB) 4981 #define PC_SOFTMD1_BTCORE_PWRCTRL_SOFT_LSB (6) 4982 #define PC_SOFTMD1_BTCORE_PWRCTRL_SOFT_WIDTH (6) 4983 #define PC_SOFTMD1_BTCORE_PWRCTRL_SOFT_MASK (((0x01UL << PC_SOFTMD1_BTCORE_PWRCTRL_SOFT_WIDTH) - 1) << PC_SOFTMD1_BTCORE_PWRCTRL_SOFT_LSB) 4984 #define PC_SOFTMD1_WIFICORE_PWRCTRL_SOFT_LSB (12) 4985 #define PC_SOFTMD1_WIFICORE_PWRCTRL_SOFT_WIDTH (6) 4986 #define PC_SOFTMD1_WIFICORE_PWRCTRL_SOFT_MASK (((0x01UL << PC_SOFTMD1_WIFICORE_PWRCTRL_SOFT_WIDTH) - 1) << PC_SOFTMD1_WIFICORE_PWRCTRL_SOFT_LSB) 4987 #define PC_SOFTMD1_AONRAM1_PWRCTRL_SOFT_LSB (18) 4988 #define PC_SOFTMD1_AONRAM1_PWRCTRL_SOFT_WIDTH (6) 4989 #define PC_SOFTMD1_AONRAM1_PWRCTRL_SOFT_MASK (((0x01UL << PC_SOFTMD1_AONRAM1_PWRCTRL_SOFT_WIDTH) - 1) << PC_SOFTMD1_AONRAM1_PWRCTRL_SOFT_LSB) 4990 #define PC_SOFTMD1_AONRAM2_PWRCTRL_SOFT_LSB (24) 4991 #define PC_SOFTMD1_AONRAM2_PWRCTRL_SOFT_WIDTH (6) 4992 #define PC_SOFTMD1_AONRAM2_PWRCTRL_SOFT_MASK (((0x01UL << PC_SOFTMD1_AONRAM2_PWRCTRL_SOFT_WIDTH) - 1) << PC_SOFTMD1_AONRAM2_PWRCTRL_SOFT_LSB) 4993 pwrctrl_softmd1_cpusys_pwrctrl_soft_getf(void)4994__STATIC_INLINE uint8_t pwrctrl_softmd1_cpusys_pwrctrl_soft_getf(void) 4995 { 4996 return ((CS_PWRCTRL->SOFTMD1 & PC_SOFTMD1_CPUSYS_PWRCTRL_SOFT_MASK) >> PC_SOFTMD1_CPUSYS_PWRCTRL_SOFT_LSB); 4997 } 4998 pwrctrl_softmd1_cpusys_pwrctrl_soft_setf(uint8_t pwrctrl_soft)4999__STATIC_INLINE void pwrctrl_softmd1_cpusys_pwrctrl_soft_setf(uint8_t pwrctrl_soft) 5000 { 5001 uint32_t local_val = CS_PWRCTRL->SOFTMD1 & ~PC_SOFTMD1_CPUSYS_PWRCTRL_SOFT_MASK; 5002 CS_PWRCTRL->SOFTMD1 = local_val | ((pwrctrl_soft << PC_SOFTMD1_CPUSYS_PWRCTRL_SOFT_LSB) & PC_SOFTMD1_CPUSYS_PWRCTRL_SOFT_MASK); 5003 } 5004 pwrctrl_softmd1_btcore_pwrctrl_soft_getf(void)5005__STATIC_INLINE uint8_t pwrctrl_softmd1_btcore_pwrctrl_soft_getf(void) 5006 { 5007 return ((CS_PWRCTRL->SOFTMD1 & PC_SOFTMD1_BTCORE_PWRCTRL_SOFT_MASK) >> PC_SOFTMD1_BTCORE_PWRCTRL_SOFT_LSB); 5008 } 5009 pwrctrl_softmd1_btcore_pwrctrl_soft_setf(uint8_t pwrctrl_soft)5010__STATIC_INLINE void pwrctrl_softmd1_btcore_pwrctrl_soft_setf(uint8_t pwrctrl_soft) 5011 { 5012 uint32_t local_val = CS_PWRCTRL->SOFTMD1 & ~PC_SOFTMD1_BTCORE_PWRCTRL_SOFT_MASK; 5013 CS_PWRCTRL->SOFTMD1 = local_val | ((pwrctrl_soft << PC_SOFTMD1_BTCORE_PWRCTRL_SOFT_LSB) & PC_SOFTMD1_BTCORE_PWRCTRL_SOFT_MASK); 5014 } 5015 pwrctrl_softmd1_wificore_pwrctrl_soft_getf(void)5016__STATIC_INLINE uint8_t pwrctrl_softmd1_wificore_pwrctrl_soft_getf(void) 5017 { 5018 return ((CS_PWRCTRL->SOFTMD1 & PC_SOFTMD1_WIFICORE_PWRCTRL_SOFT_MASK) >> PC_SOFTMD1_WIFICORE_PWRCTRL_SOFT_LSB); 5019 } 5020 pwrctrl_softmd1_wificore_pwrctrl_soft_setf(uint8_t pwrctrl_soft)5021__STATIC_INLINE void pwrctrl_softmd1_wificore_pwrctrl_soft_setf(uint8_t pwrctrl_soft) 5022 { 5023 uint32_t local_val = CS_PWRCTRL->SOFTMD1 & ~PC_SOFTMD1_WIFICORE_PWRCTRL_SOFT_MASK; 5024 CS_PWRCTRL->SOFTMD1 = local_val | ((pwrctrl_soft << PC_SOFTMD1_WIFICORE_PWRCTRL_SOFT_LSB) & PC_SOFTMD1_WIFICORE_PWRCTRL_SOFT_MASK); 5025 } 5026 pwrctrl_softmd1_aonram1_pwrctrl_soft_getf(void)5027__STATIC_INLINE uint8_t pwrctrl_softmd1_aonram1_pwrctrl_soft_getf(void) 5028 { 5029 return ((CS_PWRCTRL->SOFTMD1 & PC_SOFTMD1_AONRAM1_PWRCTRL_SOFT_MASK) >> PC_SOFTMD1_AONRAM1_PWRCTRL_SOFT_LSB); 5030 } 5031 pwrctrl_softmd1_aonram1_pwrctrl_soft_setf(uint8_t pwrctrl_soft)5032__STATIC_INLINE void pwrctrl_softmd1_aonram1_pwrctrl_soft_setf(uint8_t pwrctrl_soft) 5033 { 5034 uint32_t local_val = CS_PWRCTRL->SOFTMD1 & ~PC_SOFTMD1_AONRAM1_PWRCTRL_SOFT_MASK; 5035 CS_PWRCTRL->SOFTMD1 = local_val | ((pwrctrl_soft << PC_SOFTMD1_AONRAM1_PWRCTRL_SOFT_LSB) & PC_SOFTMD1_AONRAM1_PWRCTRL_SOFT_MASK); 5036 } 5037 pwrctrl_softmd1_aonram2_pwrctrl_soft_getf(void)5038__STATIC_INLINE uint8_t pwrctrl_softmd1_aonram2_pwrctrl_soft_getf(void) 5039 { 5040 return ((CS_PWRCTRL->SOFTMD1 & PC_SOFTMD1_AONRAM2_PWRCTRL_SOFT_MASK) >> PC_SOFTMD1_AONRAM2_PWRCTRL_SOFT_LSB); 5041 } 5042 pwrctrl_softmd1_aonram2_pwrctrl_soft_setf(uint8_t pwrctrl_soft)5043__STATIC_INLINE void pwrctrl_softmd1_aonram2_pwrctrl_soft_setf(uint8_t pwrctrl_soft) 5044 { 5045 uint32_t local_val = CS_PWRCTRL->SOFTMD1 & ~PC_SOFTMD1_AONRAM2_PWRCTRL_SOFT_MASK; 5046 CS_PWRCTRL->SOFTMD1 = local_val | ((pwrctrl_soft << PC_SOFTMD1_AONRAM2_PWRCTRL_SOFT_LSB) & PC_SOFTMD1_AONRAM2_PWRCTRL_SOFT_MASK); 5047 } 5048 5049 /** 5050 * Address Offset: 0x044 5051 * Register Name : PC IRQCTRL 5052 */ 5053 5054 #define PC_IRQCTRL_CLR_AWAKE_STATE_WIFI_POS (0) 5055 #define PC_IRQCTRL_CLR_AWAKE_STATE_WIFI_BIT (0x01UL << PC_IRQCTRL_CLR_AWAKE_STATE_WIFI_POS) 5056 #define PC_IRQCTRL_CLR_AWAKE_STATE_BT_POS (1) 5057 #define PC_IRQCTRL_CLR_AWAKE_STATE_BT_BIT (0x01UL << PC_IRQCTRL_CLR_AWAKE_STATE_BT_POS) 5058 #define PC_IRQCTRL_CLR_AWAKE_STATE_GPIO_POS (2) 5059 #define PC_IRQCTRL_CLR_AWAKE_STATE_GPIO_BIT (0x01UL << PC_IRQCTRL_CLR_AWAKE_STATE_GPIO_POS) 5060 #define PC_IRQCTRL_CLR_AWAKE_STATE_TMR2_POS (3) 5061 #define PC_IRQCTRL_CLR_AWAKE_STATE_TMR2_BIT (0x01UL << PC_IRQCTRL_CLR_AWAKE_STATE_TMR2_POS) 5062 #define PC_IRQCTRL_CLR_AWAKE_STATE_C0_POS (4) 5063 #define PC_IRQCTRL_CLR_AWAKE_STATE_C0_BIT (0x01UL << PC_IRQCTRL_CLR_AWAKE_STATE_C0_POS) 5064 #define PC_IRQCTRL_CLR_AWAKE_STATE_C1_POS (5) 5065 #define PC_IRQCTRL_CLR_AWAKE_STATE_C1_BIT (0x01UL << PC_IRQCTRL_CLR_AWAKE_STATE_C1_POS) 5066 #define PC_IRQCTRL_CLR_AWAKE_STATE_BTCPU_POS (6) 5067 #define PC_IRQCTRL_CLR_AWAKE_STATE_BTCPU_BIT (0x01UL << PC_IRQCTRL_CLR_AWAKE_STATE_BTCPU_POS) 5068 #define PC_IRQCTRL_CLR_AWAKE_STATE_WIFICPU_POS (7) 5069 #define PC_IRQCTRL_CLR_AWAKE_STATE_WIFICPU_BIT (0x01UL << PC_IRQCTRL_CLR_AWAKE_STATE_WIFICPU_POS) 5070 #define PC_IRQCTRL_CLR_AWAKE_STATE_PMIC_POS (8) 5071 #define PC_IRQCTRL_CLR_AWAKE_STATE_PMIC_BIT (0x01UL << PC_IRQCTRL_CLR_AWAKE_STATE_PMIC_POS) 5072 #define PC_IRQCTRL_CLR_SLEEP_STATE_DIGTOP_POS (10) 5073 #define PC_IRQCTRL_CLR_SLEEP_STATE_DIGTOP_BIT (0x01UL << PC_IRQCTRL_CLR_SLEEP_STATE_DIGTOP_POS) 5074 #define PC_IRQCTRL_CLR_SLEEP_STATE_CPUSYS_POS (11) 5075 #define PC_IRQCTRL_CLR_SLEEP_STATE_CPUSYS_BIT (0x01UL << PC_IRQCTRL_CLR_SLEEP_STATE_CPUSYS_POS) 5076 #define PC_IRQCTRL_CLR_SLEEP_STATE_BTSYS_POS (12) 5077 #define PC_IRQCTRL_CLR_SLEEP_STATE_BTSYS_BIT (0x01UL << PC_IRQCTRL_CLR_SLEEP_STATE_BTSYS_POS) 5078 #define PC_IRQCTRL_CLR_SLEEP_STATE_WIFISYS_POS (13) 5079 #define PC_IRQCTRL_CLR_SLEEP_STATE_WIFISYS_BIT (0x01UL << PC_IRQCTRL_CLR_SLEEP_STATE_WIFISYS_POS) 5080 #define PC_IRQCTRL_MSK_AWAKE_STATE_WIFI_POS (16) 5081 #define PC_IRQCTRL_MSK_AWAKE_STATE_WIFI_BIT (0x01UL << PC_IRQCTRL_MSK_AWAKE_STATE_WIFI_POS) 5082 #define PC_IRQCTRL_MSK_AWAKE_STATE_BT_POS (17) 5083 #define PC_IRQCTRL_MSK_AWAKE_STATE_BT_BIT (0x01UL << PC_IRQCTRL_MSK_AWAKE_STATE_BT_POS) 5084 #define PC_IRQCTRL_MSK_AWAKE_STATE_GPIO_POS (18) 5085 #define PC_IRQCTRL_MSK_AWAKE_STATE_GPIO_BIT (0x01UL << PC_IRQCTRL_MSK_AWAKE_STATE_GPIO_POS) 5086 #define PC_IRQCTRL_MSK_AWAKE_STATE_TMR2_POS (19) 5087 #define PC_IRQCTRL_MSK_AWAKE_STATE_TMR2_BIT (0x01UL << PC_IRQCTRL_MSK_AWAKE_STATE_TMR2_POS) 5088 #define PC_IRQCTRL_MSK_AWAKE_STATE_C0_POS (20) 5089 #define PC_IRQCTRL_MSK_AWAKE_STATE_C0_BIT (0x01UL << PC_IRQCTRL_MSK_AWAKE_STATE_C0_POS) 5090 #define PC_IRQCTRL_MSK_AWAKE_STATE_C1_POS (21) 5091 #define PC_IRQCTRL_MSK_AWAKE_STATE_C1_BIT (0x01UL << PC_IRQCTRL_MSK_AWAKE_STATE_C1_POS) 5092 #define PC_IRQCTRL_MSK_AWAKE_STATE_BTCPU_POS (22) 5093 #define PC_IRQCTRL_MSK_AWAKE_STATE_BTCPU_BIT (0x01UL << PC_IRQCTRL_MSK_AWAKE_STATE_BTCPU_POS) 5094 #define PC_IRQCTRL_MSK_AWAKE_STATE_WIFICPU_POS (23) 5095 #define PC_IRQCTRL_MSK_AWAKE_STATE_WIFICPU_BIT (0x01UL << PC_IRQCTRL_MSK_AWAKE_STATE_WIFICPU_POS) 5096 #define PC_IRQCTRL_MSK_AWAKE_STATE_PMIC_POS (24) 5097 #define PC_IRQCTRL_MSK_AWAKE_STATE_PMIC_BIT (0x01UL << PC_IRQCTRL_MSK_AWAKE_STATE_PMIC_POS) 5098 #define PC_IRQCTRL_MSK_SLEEP_STATE_DIGTOP_POS (26) 5099 #define PC_IRQCTRL_MSK_SLEEP_STATE_DIGTOP_BIT (0x01UL << PC_IRQCTRL_MSK_SLEEP_STATE_DIGTOP_POS) 5100 #define PC_IRQCTRL_MSK_SLEEP_STATE_CPUSYS_POS (27) 5101 #define PC_IRQCTRL_MSK_SLEEP_STATE_CPUSYS_BIT (0x01UL << PC_IRQCTRL_MSK_SLEEP_STATE_CPUSYS_POS) 5102 #define PC_IRQCTRL_MSK_SLEEP_STATE_BTSYS_POS (28) 5103 #define PC_IRQCTRL_MSK_SLEEP_STATE_BTSYS_BIT (0x01UL << PC_IRQCTRL_MSK_SLEEP_STATE_BTSYS_POS) 5104 #define PC_IRQCTRL_MSK_SLEEP_STATE_WIFISYS_POS (29) 5105 #define PC_IRQCTRL_MSK_SLEEP_STATE_WIFISYS_BIT (0x01UL << PC_IRQCTRL_MSK_SLEEP_STATE_WIFISYS_POS) 5106 #define PC_IRQCTRL_PWR_CTRL_IRQ_EN_POS (31) 5107 #define PC_IRQCTRL_PWR_CTRL_IRQ_EN_BIT (0x01UL << PC_IRQCTRL_PWR_CTRL_IRQ_EN_POS) 5108 pwrctrl_irqctrl_get(void)5109__STATIC_INLINE uint32_t pwrctrl_irqctrl_get(void) 5110 { 5111 return CS_PWRCTRL->IRQCTRL; 5112 } 5113 pwrctrl_irqctrl_set(uint32_t reg_val)5114__STATIC_INLINE void pwrctrl_irqctrl_set(uint32_t reg_val) 5115 { 5116 CS_PWRCTRL->IRQCTRL = reg_val; 5117 } 5118 5119 /** 5120 * Address Offset: 0x048 5121 * Register Name : PC IRQSTATUS 5122 */ 5123 5124 #define PC_IRQSTATUS_RAW_AWAKE_STATE_WIFI_POS (0) 5125 #define PC_IRQSTATUS_RAW_AWAKE_STATE_WIFI_BIT (0x01UL << PC_IRQSTATUS_RAW_AWAKE_STATE_WIFI_POS) 5126 #define PC_IRQSTATUS_RAW_AWAKE_STATE_BT_POS (1) 5127 #define PC_IRQSTATUS_RAW_AWAKE_STATE_BT_BIT (0x01UL << PC_IRQSTATUS_RAW_AWAKE_STATE_BT_POS) 5128 #define PC_IRQSTATUS_RAW_AWAKE_STATE_GPIO_POS (2) 5129 #define PC_IRQSTATUS_RAW_AWAKE_STATE_GPIO_BIT (0x01UL << PC_IRQSTATUS_RAW_AWAKE_STATE_GPIO_POS) 5130 #define PC_IRQSTATUS_RAW_AWAKE_STATE_TMR2_POS (3) 5131 #define PC_IRQSTATUS_RAW_AWAKE_STATE_TMR2_BIT (0x01UL << PC_IRQSTATUS_RAW_AWAKE_STATE_TMR2_POS) 5132 #define PC_IRQSTATUS_RAW_AWAKE_STATE_C0_POS (4) 5133 #define PC_IRQSTATUS_RAW_AWAKE_STATE_C0_BIT (0x01UL << PC_IRQSTATUS_RAW_AWAKE_STATE_C0_POS) 5134 #define PC_IRQSTATUS_RAW_AWAKE_STATE_C1_POS (5) 5135 #define PC_IRQSTATUS_RAW_AWAKE_STATE_C1_BIT (0x01UL << PC_IRQSTATUS_RAW_AWAKE_STATE_C1_POS) 5136 #define PC_IRQSTATUS_RAW_AWAKE_STATE_BTCPU_POS (6) 5137 #define PC_IRQSTATUS_RAW_AWAKE_STATE_BTCPU_BIT (0x01UL << PC_IRQSTATUS_RAW_AWAKE_STATE_BTCPU_POS) 5138 #define PC_IRQSTATUS_RAW_AWAKE_STATE_WIFICPU_POS (7) 5139 #define PC_IRQSTATUS_RAW_AWAKE_STATE_WIFICPU_BIT (0x01UL << PC_IRQSTATUS_RAW_AWAKE_STATE_WIFICPU_POS) 5140 #define PC_IRQSTATUS_RAW_AWAKE_STATE_PMIC_POS (8) 5141 #define PC_IRQSTATUS_RAW_AWAKE_STATE_PMIC_BIT (0x01UL << PC_IRQSTATUS_RAW_AWAKE_STATE_PMIC_POS) 5142 #define PC_IRQSTATUS_RAW_SLEEP_STATE_DIGTOP_POS (10) 5143 #define PC_IRQSTATUS_RAW_SLEEP_STATE_DIGTOP_BIT (0x01UL << PC_IRQSTATUS_RAW_SLEEP_STATE_DIGTOP_POS) 5144 #define PC_IRQSTATUS_RAW_SLEEP_STATE_CPUSYS_POS (11) 5145 #define PC_IRQSTATUS_RAW_SLEEP_STATE_CPUSYS_BIT (0x01UL << PC_IRQSTATUS_RAW_SLEEP_STATE_CPUSYS_POS) 5146 #define PC_IRQSTATUS_RAW_SLEEP_STATE_BTSYS_POS (12) 5147 #define PC_IRQSTATUS_RAW_SLEEP_STATE_BTSYS_BIT (0x01UL << PC_IRQSTATUS_RAW_SLEEP_STATE_BTSYS_POS) 5148 #define PC_IRQSTATUS_RAW_SLEEP_STATE_WIFISYS_POS (13) 5149 #define PC_IRQSTATUS_RAW_SLEEP_STATE_WIFISYS_BIT (0x01UL << PC_IRQSTATUS_RAW_SLEEP_STATE_WIFISYS_POS) 5150 #define PC_IRQSTATUS_RAW_AWAKE_STATUS_VCORESYS_POS (14) 5151 #define PC_IRQSTATUS_RAW_AWAKE_STATUS_VCORESYS_BIT (0x01UL << PC_IRQSTATUS_RAW_AWAKE_STATUS_VCORESYS_POS) 5152 #define PC_IRQSTATUS_RAW_AWAKE_STATUS_CPUSYS_POS (15) 5153 #define PC_IRQSTATUS_RAW_AWAKE_STATUS_CPUSYS_BIT (0x01UL << PC_IRQSTATUS_RAW_AWAKE_STATUS_CPUSYS_POS) 5154 #define PC_IRQSTATUS_MSK_AWAKE_STATE_WIFI_POS (16) 5155 #define PC_IRQSTATUS_MSK_AWAKE_STATE_WIFI_BIT (0x01UL << PC_IRQSTATUS_MSK_AWAKE_STATE_WIFI_POS) 5156 #define PC_IRQSTATUS_MSK_AWAKE_STATE_BT_POS (17) 5157 #define PC_IRQSTATUS_MSK_AWAKE_STATE_BT_BIT (0x01UL << PC_IRQSTATUS_MSK_AWAKE_STATE_BT_POS) 5158 #define PC_IRQSTATUS_MSK_AWAKE_STATE_GPIO_POS (18) 5159 #define PC_IRQSTATUS_MSK_AWAKE_STATE_GPIO_BIT (0x01UL << PC_IRQSTATUS_MSK_AWAKE_STATE_GPIO_POS) 5160 #define PC_IRQSTATUS_MSK_AWAKE_STATE_TMR2_POS (19) 5161 #define PC_IRQSTATUS_MSK_AWAKE_STATE_TMR2_BIT (0x01UL << PC_IRQSTATUS_MSK_AWAKE_STATE_TMR2_POS) 5162 #define PC_IRQSTATUS_MSK_AWAKE_STATE_C0_POS (20) 5163 #define PC_IRQSTATUS_MSK_AWAKE_STATE_C0_BIT (0x01UL << PC_IRQSTATUS_MSK_AWAKE_STATE_C0_POS) 5164 #define PC_IRQSTATUS_MSK_AWAKE_STATE_C1_POS (21) 5165 #define PC_IRQSTATUS_MSK_AWAKE_STATE_C1_BIT (0x01UL << PC_IRQSTATUS_MSK_AWAKE_STATE_C1_POS) 5166 #define PC_IRQSTATUS_MSK_AWAKE_STATE_BTCPU_POS (22) 5167 #define PC_IRQSTATUS_MSK_AWAKE_STATE_BTCPU_BIT (0x01UL << PC_IRQSTATUS_MSK_AWAKE_STATE_BTCPU_POS) 5168 #define PC_IRQSTATUS_MSK_AWAKE_STATE_WIFICPU_POS (23) 5169 #define PC_IRQSTATUS_MSK_AWAKE_STATE_WIFICPU_BIT (0x01UL << PC_IRQSTATUS_MSK_AWAKE_STATE_WIFICPU_POS) 5170 #define PC_IRQSTATUS_MSK_AWAKE_STATE_PMIC_POS (24) 5171 #define PC_IRQSTATUS_MSK_AWAKE_STATE_PMIC_BIT (0x01UL << PC_IRQSTATUS_MSK_AWAKE_STATE_PMIC_POS) 5172 #define PC_IRQSTATUS_MSK_SLEEP_STATE_DIGTOP_POS (26) 5173 #define PC_IRQSTATUS_MSK_SLEEP_STATE_DIGTOP_BIT (0x01UL << PC_IRQSTATUS_MSK_SLEEP_STATE_DIGTOP_POS) 5174 #define PC_IRQSTATUS_MSK_SLEEP_STATE_CPUSYS_POS (27) 5175 #define PC_IRQSTATUS_MSK_SLEEP_STATE_CPUSYS_BIT (0x01UL << PC_IRQSTATUS_MSK_SLEEP_STATE_CPUSYS_POS) 5176 #define PC_IRQSTATUS_MSK_SLEEP_STATE_BTSYS_POS (28) 5177 #define PC_IRQSTATUS_MSK_SLEEP_STATE_BTSYS_BIT (0x01UL << PC_IRQSTATUS_MSK_SLEEP_STATE_BTSYS_POS) 5178 #define PC_IRQSTATUS_MSK_SLEEP_STATE_WIFISYS_POS (29) 5179 #define PC_IRQSTATUS_MSK_SLEEP_STATE_WIFISYS_BIT (0x01UL << PC_IRQSTATUS_MSK_SLEEP_STATE_WIFISYS_POS) 5180 #define PC_IRQSTATUS_RAW_AWAKE_STATUS_BTCORE_POS (30) 5181 #define PC_IRQSTATUS_RAW_AWAKE_STATUS_BTCORE_BIT (0x01UL << PC_IRQSTATUS_RAW_AWAKE_STATUS_BTCORE_POS) 5182 #define PC_IRQSTATUS_RAW_AWAKE_STATUS_WIFICORE_POS (31) 5183 #define PC_IRQSTATUS_RAW_AWAKE_STATUS_WIFICORE_BIT (0x01UL << PC_IRQSTATUS_RAW_AWAKE_STATUS_WIFICORE_POS) 5184 pwrctrl_irqstatus_get(void)5185__STATIC_INLINE uint32_t pwrctrl_irqstatus_get(void) 5186 { 5187 return CS_PWRCTRL->IRQSTATUS; 5188 } 5189 pwrctrl_irqstatus_set(uint32_t reg_val)5190__STATIC_INLINE void pwrctrl_irqstatus_set(uint32_t reg_val) 5191 { 5192 CS_PWRCTRL->IRQSTATUS = reg_val; 5193 } 5194 5195 /** 5196 * Address Offset: 0x04C 5197 * Register Name : PC MMSYS 5198 */ 5199 5200 #define PC_MMSYS_PON_POS (17) 5201 #define PC_MMSYS_PON_BIT (0x01UL << PC_MMSYS_PON_POS) 5202 #define PC_MMSYS_POFF_POS (18) 5203 #define PC_MMSYS_POFF_BIT (0x01UL << PC_MMSYS_POFF_POS) 5204 pwrctrl_mmsys_pon_getb(void)5205__STATIC_INLINE uint8_t pwrctrl_mmsys_pon_getb(void) 5206 { 5207 return (CS_PWRCTRL->MMSYS & PC_MMSYS_PON_BIT) >> PC_MMSYS_PON_POS; 5208 } 5209 pwrctrl_mmsys_pon_setb(void)5210__STATIC_INLINE void pwrctrl_mmsys_pon_setb(void) 5211 { 5212 CS_PWRCTRL->MMSYS |= PC_MMSYS_PON_BIT; 5213 } 5214 pwrctrl_mmsys_pon_clrb(void)5215__STATIC_INLINE void pwrctrl_mmsys_pon_clrb(void) 5216 { 5217 CS_PWRCTRL->MMSYS &= ~PC_MMSYS_PON_BIT; 5218 } 5219 pwrctrl_mmsys_poff_getb(void)5220__STATIC_INLINE uint8_t pwrctrl_mmsys_poff_getb(void) 5221 { 5222 return (CS_PWRCTRL->MMSYS & PC_MMSYS_POFF_BIT) >> PC_MMSYS_POFF_POS; 5223 } 5224 pwrctrl_mmsys_poff_setb(void)5225__STATIC_INLINE void pwrctrl_mmsys_poff_setb(void) 5226 { 5227 CS_PWRCTRL->MMSYS |= PC_MMSYS_POFF_BIT; 5228 } 5229 pwrctrl_mmsys_poff_clrb(void)5230__STATIC_INLINE void pwrctrl_mmsys_poff_clrb(void) 5231 { 5232 CS_PWRCTRL->MMSYS &= ~PC_MMSYS_POFF_BIT; 5233 } 5234 5235 /** 5236 * Address Offset: 0x050 5237 * Register Name : PC SOFTMD2 5238 */ 5239 5240 #define PC_SOFTMD2_MMSYS_PWRCTRL_SOFT_LSB (0) 5241 #define PC_SOFTMD2_MMSYS_PWRCTRL_SOFT_WIDTH (6) 5242 #define PC_SOFTMD2_MMSYS_PWRCTRL_SOFT_MASK (((0x01UL << PC_SOFTMD2_MMSYS_PWRCTRL_SOFT_WIDTH) - 1) << PC_SOFTMD2_MMSYS_PWRCTRL_SOFT_LSB) 5243 #define PC_SOFTMD2_VCORESYS_PWRCTRL_SOFT_LSB (6) 5244 #define PC_SOFTMD2_VCORESYS_PWRCTRL_SOFT_WIDTH (6) 5245 #define PC_SOFTMD2_VCORESYS_PWRCTRL_SOFT_MASK (((0x01UL << PC_SOFTMD2_VCORESYS_PWRCTRL_SOFT_WIDTH) - 1) << PC_SOFTMD2_VCORESYS_PWRCTRL_SOFT_LSB) 5246 #define PC_SOFTMD2_SLP_MODE_SEL_AONRAM1_POS (12) 5247 #define PC_SOFTMD2_SLP_MODE_SEL_AONRAM1_BIT (0x01UL << PC_SOFTMD2_SLP_MODE_SEL_AONRAM1_POS) 5248 #define PC_SOFTMD2_SLP_MODE_SEL_AONRAM2_POS (13) 5249 #define PC_SOFTMD2_SLP_MODE_SEL_AONRAM2_BIT (0x01UL << PC_SOFTMD2_SLP_MODE_SEL_AONRAM2_POS) 5250 #define PC_SOFTMD2_SLP_MODE_SEL_BTCORE_POS (14) 5251 #define PC_SOFTMD2_SLP_MODE_SEL_BTCORE_BIT (0x01UL << PC_SOFTMD2_SLP_MODE_SEL_BTCORE_POS) 5252 #define PC_SOFTMD2_SLP_MODE_SEL_CPUSYS_POS (15) 5253 #define PC_SOFTMD2_SLP_MODE_SEL_CPUSYS_BIT (0x01UL << PC_SOFTMD2_SLP_MODE_SEL_CPUSYS_POS) 5254 #define PC_SOFTMD2_SLP_MODE_SEL_MMSYS_POS (16) 5255 #define PC_SOFTMD2_SLP_MODE_SEL_MMSYS_BIT (0x01UL << PC_SOFTMD2_SLP_MODE_SEL_MMSYS_POS) 5256 #define PC_SOFTMD2_SLP_MODE_SEL_VCORESYS_POS (17) 5257 #define PC_SOFTMD2_SLP_MODE_SEL_VCORESYS_BIT (0x01UL << PC_SOFTMD2_SLP_MODE_SEL_VCORESYS_POS) 5258 #define PC_SOFTMD2_SLP_MODE_SEL_WIFICORE_POS (18) 5259 #define PC_SOFTMD2_SLP_MODE_SEL_WIFICORE_BIT (0x01UL << PC_SOFTMD2_SLP_MODE_SEL_WIFICORE_POS) 5260 pwrctrl_softmd2_mmsys_pwrctrl_soft_getf(void)5261__STATIC_INLINE uint8_t pwrctrl_softmd2_mmsys_pwrctrl_soft_getf(void) 5262 { 5263 return ((CS_PWRCTRL->SOFTMD2 & PC_SOFTMD2_MMSYS_PWRCTRL_SOFT_MASK) >> PC_SOFTMD2_MMSYS_PWRCTRL_SOFT_LSB); 5264 } 5265 pwrctrl_softmd2_mmsys_pwrctrl_soft_setf(uint8_t pwrctrl_soft)5266__STATIC_INLINE void pwrctrl_softmd2_mmsys_pwrctrl_soft_setf(uint8_t pwrctrl_soft) 5267 { 5268 uint32_t local_val = CS_PWRCTRL->SOFTMD2 & ~PC_SOFTMD2_MMSYS_PWRCTRL_SOFT_MASK; 5269 CS_PWRCTRL->SOFTMD2 = local_val | ((pwrctrl_soft << PC_SOFTMD2_MMSYS_PWRCTRL_SOFT_LSB) & PC_SOFTMD2_MMSYS_PWRCTRL_SOFT_MASK); 5270 } 5271 pwrctrl_softmd2_vcoresys_pwrctrl_soft_getf(void)5272__STATIC_INLINE uint8_t pwrctrl_softmd2_vcoresys_pwrctrl_soft_getf(void) 5273 { 5274 return ((CS_PWRCTRL->SOFTMD2 & PC_SOFTMD2_VCORESYS_PWRCTRL_SOFT_MASK) >> PC_SOFTMD2_VCORESYS_PWRCTRL_SOFT_LSB); 5275 } 5276 pwrctrl_softmd2_vcoresys_pwrctrl_soft_setf(uint8_t pwrctrl_soft)5277__STATIC_INLINE void pwrctrl_softmd2_vcoresys_pwrctrl_soft_setf(uint8_t pwrctrl_soft) 5278 { 5279 uint32_t local_val = CS_PWRCTRL->SOFTMD2 & ~PC_SOFTMD2_VCORESYS_PWRCTRL_SOFT_MASK; 5280 CS_PWRCTRL->SOFTMD2 = local_val | ((pwrctrl_soft << PC_SOFTMD2_VCORESYS_PWRCTRL_SOFT_LSB) & PC_SOFTMD2_VCORESYS_PWRCTRL_SOFT_MASK); 5281 } 5282 pwrctrl_softmd2_slp_mode_sel_aonram1_getb(void)5283__STATIC_INLINE uint8_t pwrctrl_softmd2_slp_mode_sel_aonram1_getb(void) 5284 { 5285 return (CS_PWRCTRL->SOFTMD2 & PC_SOFTMD2_SLP_MODE_SEL_AONRAM1_BIT) >> PC_SOFTMD2_SLP_MODE_SEL_AONRAM1_POS; 5286 } 5287 pwrctrl_softmd2_slp_mode_sel_aonram1_setb(void)5288__STATIC_INLINE void pwrctrl_softmd2_slp_mode_sel_aonram1_setb(void) 5289 { 5290 CS_PWRCTRL->SOFTMD2 |= PC_SOFTMD2_SLP_MODE_SEL_AONRAM1_BIT; 5291 } 5292 pwrctrl_softmd2_slp_mode_sel_aonram1_clrb(void)5293__STATIC_INLINE void pwrctrl_softmd2_slp_mode_sel_aonram1_clrb(void) 5294 { 5295 CS_PWRCTRL->SOFTMD2 &= ~PC_SOFTMD2_SLP_MODE_SEL_AONRAM1_BIT; 5296 } 5297 pwrctrl_softmd2_slp_mode_sel_aonram2_getb(void)5298__STATIC_INLINE uint8_t pwrctrl_softmd2_slp_mode_sel_aonram2_getb(void) 5299 { 5300 return (CS_PWRCTRL->SOFTMD2 & PC_SOFTMD2_SLP_MODE_SEL_AONRAM2_BIT) >> PC_SOFTMD2_SLP_MODE_SEL_AONRAM2_POS; 5301 } 5302 pwrctrl_softmd2_slp_mode_sel_aonram2_setb(void)5303__STATIC_INLINE void pwrctrl_softmd2_slp_mode_sel_aonram2_setb(void) 5304 { 5305 CS_PWRCTRL->SOFTMD2 |= PC_SOFTMD2_SLP_MODE_SEL_AONRAM2_BIT; 5306 } 5307 pwrctrl_softmd2_slp_mode_sel_aonram2_clrb(void)5308__STATIC_INLINE void pwrctrl_softmd2_slp_mode_sel_aonram2_clrb(void) 5309 { 5310 CS_PWRCTRL->SOFTMD2 &= ~PC_SOFTMD2_SLP_MODE_SEL_AONRAM2_BIT; 5311 } 5312 pwrctrl_softmd2_slp_mode_sel_btcore_getb(void)5313__STATIC_INLINE uint8_t pwrctrl_softmd2_slp_mode_sel_btcore_getb(void) 5314 { 5315 return (CS_PWRCTRL->SOFTMD2 & PC_SOFTMD2_SLP_MODE_SEL_BTCORE_BIT) >> PC_SOFTMD2_SLP_MODE_SEL_BTCORE_POS; 5316 } 5317 pwrctrl_softmd2_slp_mode_sel_btcore_setb(void)5318__STATIC_INLINE void pwrctrl_softmd2_slp_mode_sel_btcore_setb(void) 5319 { 5320 CS_PWRCTRL->SOFTMD2 |= PC_SOFTMD2_SLP_MODE_SEL_BTCORE_BIT; 5321 } 5322 pwrctrl_softmd2_slp_mode_sel_btcore_clrb(void)5323__STATIC_INLINE void pwrctrl_softmd2_slp_mode_sel_btcore_clrb(void) 5324 { 5325 CS_PWRCTRL->SOFTMD2 &= ~PC_SOFTMD2_SLP_MODE_SEL_BTCORE_BIT; 5326 } 5327 pwrctrl_softmd2_slp_mode_sel_cpusys_getb(void)5328__STATIC_INLINE uint8_t pwrctrl_softmd2_slp_mode_sel_cpusys_getb(void) 5329 { 5330 return (CS_PWRCTRL->SOFTMD2 & PC_SOFTMD2_SLP_MODE_SEL_CPUSYS_BIT) >> PC_SOFTMD2_SLP_MODE_SEL_CPUSYS_POS; 5331 } 5332 pwrctrl_softmd2_slp_mode_sel_cpusys_setb(void)5333__STATIC_INLINE void pwrctrl_softmd2_slp_mode_sel_cpusys_setb(void) 5334 { 5335 CS_PWRCTRL->SOFTMD2 |= PC_SOFTMD2_SLP_MODE_SEL_CPUSYS_BIT; 5336 } 5337 pwrctrl_softmd2_slp_mode_sel_cpusys_clrb(void)5338__STATIC_INLINE void pwrctrl_softmd2_slp_mode_sel_cpusys_clrb(void) 5339 { 5340 CS_PWRCTRL->SOFTMD2 &= ~PC_SOFTMD2_SLP_MODE_SEL_CPUSYS_BIT; 5341 } 5342 pwrctrl_softmd2_slp_mode_sel_mmsys_getb(void)5343__STATIC_INLINE uint8_t pwrctrl_softmd2_slp_mode_sel_mmsys_getb(void) 5344 { 5345 return (CS_PWRCTRL->SOFTMD2 & PC_SOFTMD2_SLP_MODE_SEL_MMSYS_BIT) >> PC_SOFTMD2_SLP_MODE_SEL_MMSYS_POS; 5346 } 5347 pwrctrl_softmd2_slp_mode_sel_mmsys_setb(void)5348__STATIC_INLINE void pwrctrl_softmd2_slp_mode_sel_mmsys_setb(void) 5349 { 5350 CS_PWRCTRL->SOFTMD2 |= PC_SOFTMD2_SLP_MODE_SEL_MMSYS_BIT; 5351 } 5352 pwrctrl_softmd2_slp_mode_sel_mmsys_clrb(void)5353__STATIC_INLINE void pwrctrl_softmd2_slp_mode_sel_mmsys_clrb(void) 5354 { 5355 CS_PWRCTRL->SOFTMD2 &= ~PC_SOFTMD2_SLP_MODE_SEL_MMSYS_BIT; 5356 } 5357 pwrctrl_softmd2_slp_mode_sel_vcoresys_getb(void)5358__STATIC_INLINE uint8_t pwrctrl_softmd2_slp_mode_sel_vcoresys_getb(void) 5359 { 5360 return (CS_PWRCTRL->SOFTMD2 & PC_SOFTMD2_SLP_MODE_SEL_VCORESYS_BIT) >> PC_SOFTMD2_SLP_MODE_SEL_VCORESYS_POS; 5361 } 5362 pwrctrl_softmd2_slp_mode_sel_vcoresys_setb(void)5363__STATIC_INLINE void pwrctrl_softmd2_slp_mode_sel_vcoresys_setb(void) 5364 { 5365 CS_PWRCTRL->SOFTMD2 |= PC_SOFTMD2_SLP_MODE_SEL_VCORESYS_BIT; 5366 } 5367 pwrctrl_softmd2_slp_mode_sel_vcoresys_clrb(void)5368__STATIC_INLINE void pwrctrl_softmd2_slp_mode_sel_vcoresys_clrb(void) 5369 { 5370 CS_PWRCTRL->SOFTMD2 &= ~PC_SOFTMD2_SLP_MODE_SEL_VCORESYS_BIT; 5371 } 5372 pwrctrl_softmd2_slp_mode_sel_wificore_getb(void)5373__STATIC_INLINE uint8_t pwrctrl_softmd2_slp_mode_sel_wificore_getb(void) 5374 { 5375 return (CS_PWRCTRL->SOFTMD2 & PC_SOFTMD2_SLP_MODE_SEL_WIFICORE_BIT) >> PC_SOFTMD2_SLP_MODE_SEL_WIFICORE_POS; 5376 } 5377 pwrctrl_softmd2_slp_mode_sel_wificore_setb(void)5378__STATIC_INLINE void pwrctrl_softmd2_slp_mode_sel_wificore_setb(void) 5379 { 5380 CS_PWRCTRL->SOFTMD2 |= PC_SOFTMD2_SLP_MODE_SEL_WIFICORE_BIT; 5381 } 5382 pwrctrl_softmd2_slp_mode_sel_wificore_clrb(void)5383__STATIC_INLINE void pwrctrl_softmd2_slp_mode_sel_wificore_clrb(void) 5384 { 5385 CS_PWRCTRL->SOFTMD2 &= ~PC_SOFTMD2_SLP_MODE_SEL_WIFICORE_BIT; 5386 } 5387 5388 /** 5389 * Address Offset: 0x054 5390 * Register Name : PC VCORESYS 5391 */ 5392 5393 #define PC_VCORESYS_AWAKE_SRC_LSB (0) 5394 #define PC_VCORESYS_AWAKE_SRC_WIDTH (10) 5395 #define PC_VCORESYS_AWAKE_SRC_MASK (((0x01UL << PC_VCORESYS_AWAKE_SRC_WIDTH) - 1) << PC_VCORESYS_AWAKE_SRC_LSB) 5396 #define PC_VCORESYS_SLEEP_SRC_LSB (10) 5397 #define PC_VCORESYS_SLEEP_SRC_WIDTH (2) 5398 #define PC_VCORESYS_SLEEP_SRC_MASK (((0x01UL << PC_VCORESYS_SLEEP_SRC_WIDTH) - 1) << PC_VCORESYS_SLEEP_SRC_LSB) 5399 #define PC_VCORESYS_SLEEP_SRC_WIFI_POS (10) 5400 #define PC_VCORESYS_SLEEP_SRC_WIFI_BIT (0x01UL << PC_VCORESYS_SLEEP_SRC_WIFI_POS) 5401 #define PC_VCORESYS_SLEEP_SRC_BT_POS (11) 5402 #define PC_VCORESYS_SLEEP_SRC_BT_BIT (0x01UL << PC_VCORESYS_SLEEP_SRC_BT_POS) 5403 #define PC_VCORESYS_SLEEP_SOFT_REQ_POS (12) 5404 #define PC_VCORESYS_SLEEP_SOFT_REQ_BIT (0x01UL << PC_VCORESYS_SLEEP_SOFT_REQ_POS) 5405 #define PC_VCORESYS_SLEEP_REQVLDCLR_POS (13) 5406 #define PC_VCORESYS_SLEEP_REQVLDCLR_BIT (0x01UL << PC_VCORESYS_SLEEP_REQVLDCLR_POS) 5407 #define PC_VCORESYS_HWEN_PON_POS (15) 5408 #define PC_VCORESYS_HWEN_PON_BIT (0x01UL << PC_VCORESYS_HWEN_PON_POS) 5409 #define PC_VCORESYS_HWEN_POFF_POS (16) 5410 #define PC_VCORESYS_HWEN_POFF_BIT (0x01UL << PC_VCORESYS_HWEN_POFF_POS) 5411 #define PC_VCORESYS_PON_POS (17) 5412 #define PC_VCORESYS_PON_BIT (0x01UL << PC_VCORESYS_PON_POS) 5413 #define PC_VCORESYS_POFF_POS (18) 5414 #define PC_VCORESYS_POFF_BIT (0x01UL << PC_VCORESYS_POFF_POS) 5415 #define PC_VCORESYS_PWRSYS_TMR_POFF_POS (19) 5416 #define PC_VCORESYS_PWRSYS_TMR_POFF_BIT (0x01UL << PC_VCORESYS_PWRSYS_TMR_POFF_POS) 5417 #define PC_VCORESYS_PWRSYS_PON_POS (20) 5418 #define PC_VCORESYS_PWRSYS_PON_BIT (0x01UL << PC_VCORESYS_PWRSYS_PON_POS) 5419 #define PC_VCORESYS_PWRSYS_POFF_POS (21) 5420 #define PC_VCORESYS_PWRSYS_POFF_BIT (0x01UL << PC_VCORESYS_PWRSYS_POFF_POS) 5421 #define PC_VCORESYS_AWAKE_SOFT_REQ_POS (22) 5422 #define PC_VCORESYS_AWAKE_SOFT_REQ_BIT (0x01UL << PC_VCORESYS_AWAKE_SOFT_REQ_POS) 5423 #define PC_VCORESYS_AWAKE_REQVLDCLR_POS (23) 5424 #define PC_VCORESYS_AWAKE_REQVLDCLR_BIT (0x01UL << PC_VCORESYS_AWAKE_REQVLDCLR_POS) 5425 pwrctrl_vcoresys_get(void)5426__STATIC_INLINE uint32_t pwrctrl_vcoresys_get(void) 5427 { 5428 return CS_PWRCTRL->VCORESYS; 5429 } 5430 pwrctrl_vcoresys_set(uint32_t reg_val)5431__STATIC_INLINE void pwrctrl_vcoresys_set(uint32_t reg_val) 5432 { 5433 CS_PWRCTRL->VCORESYS = reg_val; 5434 } 5435 pwrctrl_vcoresys_awake_src_getf(void)5436__STATIC_INLINE uint16_t pwrctrl_vcoresys_awake_src_getf(void) 5437 { 5438 return ((CS_PWRCTRL->VCORESYS & PC_VCORESYS_AWAKE_SRC_MASK) >> PC_VCORESYS_AWAKE_SRC_LSB); 5439 } 5440 pwrctrl_vcoresys_awake_src_setf(uint16_t awake_src)5441__STATIC_INLINE void pwrctrl_vcoresys_awake_src_setf(uint16_t awake_src) 5442 { 5443 uint32_t local_val = CS_PWRCTRL->VCORESYS & ~PC_VCORESYS_AWAKE_SRC_MASK; 5444 CS_PWRCTRL->VCORESYS = local_val | ((awake_src << PC_VCORESYS_AWAKE_SRC_LSB) & PC_VCORESYS_AWAKE_SRC_MASK); 5445 } 5446 pwrctrl_vcoresys_sleep_src_getf(void)5447__STATIC_INLINE uint16_t pwrctrl_vcoresys_sleep_src_getf(void) 5448 { 5449 return ((CS_PWRCTRL->VCORESYS & PC_VCORESYS_SLEEP_SRC_MASK) >> PC_VCORESYS_SLEEP_SRC_LSB); 5450 } 5451 pwrctrl_vcoresys_sleep_src_setf(uint16_t awake_src)5452__STATIC_INLINE void pwrctrl_vcoresys_sleep_src_setf(uint16_t awake_src) 5453 { 5454 uint32_t local_val = CS_PWRCTRL->VCORESYS & ~PC_VCORESYS_SLEEP_SRC_MASK; 5455 CS_PWRCTRL->VCORESYS = local_val | ((awake_src << PC_VCORESYS_SLEEP_SRC_LSB) & PC_VCORESYS_SLEEP_SRC_MASK); 5456 } 5457 pwrctrl_vcoresys_sleep_src_wifi_getb(void)5458__STATIC_INLINE uint8_t pwrctrl_vcoresys_sleep_src_wifi_getb(void) 5459 { 5460 return (CS_PWRCTRL->VCORESYS & PC_VCORESYS_SLEEP_SRC_WIFI_BIT) >> PC_VCORESYS_SLEEP_SRC_WIFI_POS; 5461 } 5462 pwrctrl_vcoresys_sleep_src_wifi_setb(void)5463__STATIC_INLINE void pwrctrl_vcoresys_sleep_src_wifi_setb(void) 5464 { 5465 CS_PWRCTRL->VCORESYS |= PC_VCORESYS_SLEEP_SRC_WIFI_BIT; 5466 } 5467 pwrctrl_vcoresys_sleep_src_wifi_clrb(void)5468__STATIC_INLINE void pwrctrl_vcoresys_sleep_src_wifi_clrb(void) 5469 { 5470 CS_PWRCTRL->VCORESYS &= ~PC_VCORESYS_SLEEP_SRC_WIFI_BIT; 5471 } 5472 pwrctrl_vcoresys_sleep_src_bt_getb(void)5473__STATIC_INLINE uint8_t pwrctrl_vcoresys_sleep_src_bt_getb(void) 5474 { 5475 return (CS_PWRCTRL->VCORESYS & PC_VCORESYS_SLEEP_SRC_BT_BIT) >> PC_VCORESYS_SLEEP_SRC_BT_POS; 5476 } 5477 pwrctrl_vcoresys_sleep_src_bt_setb(void)5478__STATIC_INLINE void pwrctrl_vcoresys_sleep_src_bt_setb(void) 5479 { 5480 CS_PWRCTRL->VCORESYS |= PC_VCORESYS_SLEEP_SRC_BT_BIT; 5481 } 5482 pwrctrl_vcoresys_sleep_src_bt_clrb(void)5483__STATIC_INLINE void pwrctrl_vcoresys_sleep_src_bt_clrb(void) 5484 { 5485 CS_PWRCTRL->VCORESYS &= ~PC_VCORESYS_SLEEP_SRC_BT_BIT; 5486 } 5487 pwrctrl_vcoresys_sleep_soft_req_getb(void)5488__STATIC_INLINE uint8_t pwrctrl_vcoresys_sleep_soft_req_getb(void) 5489 { 5490 return (CS_PWRCTRL->VCORESYS & PC_VCORESYS_SLEEP_SOFT_REQ_BIT) >> PC_VCORESYS_SLEEP_SOFT_REQ_POS; 5491 } 5492 pwrctrl_vcoresys_sleep_soft_req_setb(void)5493__STATIC_INLINE void pwrctrl_vcoresys_sleep_soft_req_setb(void) 5494 { 5495 CS_PWRCTRL->VCORESYS |= PC_VCORESYS_SLEEP_SOFT_REQ_BIT; 5496 } 5497 pwrctrl_vcoresys_sleep_req_vld_clr_getb(void)5498__STATIC_INLINE uint8_t pwrctrl_vcoresys_sleep_req_vld_clr_getb(void) 5499 { 5500 return (CS_PWRCTRL->VCORESYS & PC_VCORESYS_SLEEP_REQVLDCLR_BIT) >> PC_VCORESYS_SLEEP_REQVLDCLR_POS; 5501 } 5502 pwrctrl_vcoresys_sleep_req_vld_clr_setb(void)5503__STATIC_INLINE void pwrctrl_vcoresys_sleep_req_vld_clr_setb(void) 5504 { 5505 CS_PWRCTRL->VCORESYS |= PC_VCORESYS_SLEEP_REQVLDCLR_BIT; 5506 } 5507 pwrctrl_vcoresys_hwen_pon_getb(void)5508__STATIC_INLINE uint8_t pwrctrl_vcoresys_hwen_pon_getb(void) 5509 { 5510 return (CS_PWRCTRL->VCORESYS & PC_VCORESYS_HWEN_PON_BIT) >> PC_VCORESYS_HWEN_PON_POS; 5511 } 5512 pwrctrl_vcoresys_hwen_pon_setb(void)5513__STATIC_INLINE void pwrctrl_vcoresys_hwen_pon_setb(void) 5514 { 5515 CS_PWRCTRL->VCORESYS |= PC_VCORESYS_HWEN_PON_BIT; 5516 } 5517 pwrctrl_vcoresys_hwen_pon_clrb(void)5518__STATIC_INLINE void pwrctrl_vcoresys_hwen_pon_clrb(void) 5519 { 5520 CS_PWRCTRL->VCORESYS &= ~PC_VCORESYS_HWEN_PON_BIT; 5521 } 5522 pwrctrl_vcoresys_hwen_poff_getb(void)5523__STATIC_INLINE uint8_t pwrctrl_vcoresys_hwen_poff_getb(void) 5524 { 5525 return (CS_PWRCTRL->VCORESYS & PC_VCORESYS_HWEN_POFF_BIT) >> PC_VCORESYS_HWEN_POFF_POS; 5526 } 5527 pwrctrl_vcoresys_hwen_poff_setb(void)5528__STATIC_INLINE void pwrctrl_vcoresys_hwen_poff_setb(void) 5529 { 5530 CS_PWRCTRL->VCORESYS |= PC_VCORESYS_HWEN_POFF_BIT; 5531 } 5532 pwrctrl_vcoresys_hwen_poff_clrb(void)5533__STATIC_INLINE void pwrctrl_vcoresys_hwen_poff_clrb(void) 5534 { 5535 CS_PWRCTRL->VCORESYS &= ~PC_VCORESYS_HWEN_POFF_BIT; 5536 } 5537 pwrctrl_vcoresys_pon_getb(void)5538__STATIC_INLINE uint8_t pwrctrl_vcoresys_pon_getb(void) 5539 { 5540 return (CS_PWRCTRL->VCORESYS & PC_VCORESYS_PON_BIT) >> PC_VCORESYS_PON_POS; 5541 } 5542 pwrctrl_vcoresys_pon_setb(void)5543__STATIC_INLINE void pwrctrl_vcoresys_pon_setb(void) 5544 { 5545 CS_PWRCTRL->VCORESYS |= PC_VCORESYS_PON_BIT; 5546 } 5547 pwrctrl_vcoresys_pon_clrb(void)5548__STATIC_INLINE void pwrctrl_vcoresys_pon_clrb(void) 5549 { 5550 CS_PWRCTRL->VCORESYS &= ~PC_VCORESYS_PON_BIT; 5551 } 5552 pwrctrl_vcoresys_poff_getb(void)5553__STATIC_INLINE uint8_t pwrctrl_vcoresys_poff_getb(void) 5554 { 5555 return (CS_PWRCTRL->VCORESYS & PC_VCORESYS_POFF_BIT) >> PC_VCORESYS_POFF_POS; 5556 } 5557 pwrctrl_vcoresys_poff_setb(void)5558__STATIC_INLINE void pwrctrl_vcoresys_poff_setb(void) 5559 { 5560 CS_PWRCTRL->VCORESYS |= PC_VCORESYS_POFF_BIT; 5561 } 5562 pwrctrl_vcoresys_poff_clrb(void)5563__STATIC_INLINE void pwrctrl_vcoresys_poff_clrb(void) 5564 { 5565 CS_PWRCTRL->VCORESYS &= ~PC_VCORESYS_POFF_BIT; 5566 } 5567 pwrctrl_vcoresys_pwrsys_timer_poff_getb(void)5568__STATIC_INLINE uint8_t pwrctrl_vcoresys_pwrsys_timer_poff_getb(void) 5569 { 5570 return (CS_PWRCTRL->VCORESYS & PC_VCORESYS_PWRSYS_TMR_POFF_BIT) >> PC_VCORESYS_PWRSYS_TMR_POFF_POS; 5571 } 5572 pwrctrl_vcoresys_pwrsys_timer_poff_setb(void)5573__STATIC_INLINE void pwrctrl_vcoresys_pwrsys_timer_poff_setb(void) 5574 { 5575 CS_PWRCTRL->VCORESYS |= PC_VCORESYS_PWRSYS_TMR_POFF_BIT; 5576 } 5577 pwrctrl_vcoresys_pwrsys_timer_poff_clrb(void)5578__STATIC_INLINE void pwrctrl_vcoresys_pwrsys_timer_poff_clrb(void) 5579 { 5580 CS_PWRCTRL->VCORESYS &= ~PC_VCORESYS_PWRSYS_TMR_POFF_BIT; 5581 } 5582 pwrctrl_vcoresys_pwrsys_pon_getb(void)5583__STATIC_INLINE uint8_t pwrctrl_vcoresys_pwrsys_pon_getb(void) 5584 { 5585 return (CS_PWRCTRL->VCORESYS & PC_VCORESYS_PWRSYS_PON_BIT) >> PC_VCORESYS_PWRSYS_PON_POS; 5586 } 5587 pwrctrl_vcoresys_pwrsys_pon_setb(void)5588__STATIC_INLINE void pwrctrl_vcoresys_pwrsys_pon_setb(void) 5589 { 5590 CS_PWRCTRL->VCORESYS |= PC_VCORESYS_PWRSYS_PON_BIT; 5591 } 5592 pwrctrl_vcoresys_pwrsys_pon_clrb(void)5593__STATIC_INLINE void pwrctrl_vcoresys_pwrsys_pon_clrb(void) 5594 { 5595 CS_PWRCTRL->VCORESYS &= ~PC_VCORESYS_PWRSYS_PON_BIT; 5596 } 5597 pwrctrl_vcoresys_pwrsys_poff_getb(void)5598__STATIC_INLINE uint8_t pwrctrl_vcoresys_pwrsys_poff_getb(void) 5599 { 5600 return (CS_PWRCTRL->VCORESYS & PC_VCORESYS_PWRSYS_POFF_BIT) >> PC_VCORESYS_PWRSYS_POFF_POS; 5601 } 5602 pwrctrl_vcoresys_pwrsys_poff_setb(void)5603__STATIC_INLINE void pwrctrl_vcoresys_pwrsys_poff_setb(void) 5604 { 5605 CS_PWRCTRL->VCORESYS |= PC_VCORESYS_PWRSYS_POFF_BIT; 5606 } 5607 pwrctrl_vcoresys_pwrsys_poff_clrb(void)5608__STATIC_INLINE void pwrctrl_vcoresys_pwrsys_poff_clrb(void) 5609 { 5610 CS_PWRCTRL->VCORESYS &= ~PC_VCORESYS_PWRSYS_POFF_BIT; 5611 } 5612 pwrctrl_vcoresys_awake_soft_req_getb(void)5613__STATIC_INLINE uint8_t pwrctrl_vcoresys_awake_soft_req_getb(void) 5614 { 5615 return (CS_PWRCTRL->VCORESYS & PC_VCORESYS_AWAKE_SOFT_REQ_BIT) >> PC_VCORESYS_AWAKE_SOFT_REQ_POS; 5616 } 5617 pwrctrl_vcoresys_awake_soft_req_setb(void)5618__STATIC_INLINE void pwrctrl_vcoresys_awake_soft_req_setb(void) 5619 { 5620 CS_PWRCTRL->VCORESYS |= PC_VCORESYS_AWAKE_SOFT_REQ_BIT; 5621 } 5622 pwrctrl_vcoresys_awake_req_vld_clr_getb(void)5623__STATIC_INLINE uint8_t pwrctrl_vcoresys_awake_req_vld_clr_getb(void) 5624 { 5625 return (CS_PWRCTRL->VCORESYS & PC_VCORESYS_AWAKE_REQVLDCLR_BIT) >> PC_VCORESYS_AWAKE_REQVLDCLR_POS; 5626 } 5627 pwrctrl_vcoresys_awake_req_vld_clr_setb(void)5628__STATIC_INLINE void pwrctrl_vcoresys_awake_req_vld_clr_setb(void) 5629 { 5630 CS_PWRCTRL->VCORESYS |= PC_VCORESYS_AWAKE_REQVLDCLR_BIT; 5631 } 5632 5633 /** 5634 * Address Offset: 0x05C 5635 * Register Name : PC PWRMD 5636 */ 5637 5638 #define PC_PWRMD_CPUSYS_SW_RECORD_LSB (0) 5639 #define PC_PWRMD_CPUSYS_SW_RECORD_WIDTH (2) 5640 #define PC_PWRMD_CPUSYS_SW_RECORD_MASK (((0x01UL << PC_PWRMD_CPUSYS_SW_RECORD_WIDTH) - 1) << PC_PWRMD_CPUSYS_SW_RECORD_LSB) 5641 #define PC_PWRMD_FLASH_SMPLDLY_LSB (2) 5642 #define PC_PWRMD_FLASH_SMPLDLY_WIDTH (3) 5643 #define PC_PWRMD_FLASH_SMPLDLY_MASK (((0x01UL << PC_PWRMD_FLASH_SMPLDLY_WIDTH) - 1) << PC_PWRMD_FLASH_SMPLDLY_LSB) 5644 #define PC_PWRMD_FLASH_CLKSEL_FAST_POS (5) 5645 #define PC_PWRMD_FLASH_CLKSEL_FAST_BIT (0x01UL << PC_PWRMD_FLASH_CLKSEL_FAST_POS) 5646 #define PC_PWRMD_FLASH_CLKDIV_LSB (6) 5647 #define PC_PWRMD_FLASH_CLKDIV_WIDTH (8) 5648 #define PC_PWRMD_FLASH_CLKDIV_MASK (((0x01UL << PC_PWRMD_FLASH_CLKDIV_WIDTH) - 1) << PC_PWRMD_FLASH_CLKDIV_LSB) 5649 #define PC_PWRMD_UPDATE_POS (31) 5650 #define PC_PWRMD_UPDATE_BIT (0x01UL << PC_PWRMD_UPDATE_POS) 5651 pwrctrl_pwrmd_cpusys_sw_record_getf(void)5652__STATIC_INLINE uint32_t pwrctrl_pwrmd_cpusys_sw_record_getf(void) 5653 { 5654 return ((CS_PWRCTRL->PWRMD & PC_PWRMD_CPUSYS_SW_RECORD_MASK) >> PC_PWRMD_CPUSYS_SW_RECORD_LSB); 5655 } 5656 pwrctrl_pwrmd_cpusys_sw_record_setf(uint32_t mode)5657__STATIC_INLINE void pwrctrl_pwrmd_cpusys_sw_record_setf(uint32_t mode) 5658 { 5659 uint32_t local_val = CS_PWRCTRL->PWRMD & ~PC_PWRMD_CPUSYS_SW_RECORD_MASK; 5660 CS_PWRCTRL->PWRMD = local_val | ((mode << PC_PWRMD_CPUSYS_SW_RECORD_LSB) & PC_PWRMD_CPUSYS_SW_RECORD_MASK) | PC_PWRMD_UPDATE_BIT; 5661 } 5662 pwrctrl_pwrmd_flash_clksel_fast_getb(void)5663__STATIC_INLINE uint8_t pwrctrl_pwrmd_flash_clksel_fast_getb(void) 5664 { 5665 return (CS_PWRCTRL->PWRMD & PC_PWRMD_FLASH_CLKSEL_FAST_BIT) >> PC_PWRMD_FLASH_CLKSEL_FAST_POS; 5666 } 5667 pwrctrl_pwrmd_flash_clksel_fast_setb(void)5668__STATIC_INLINE void pwrctrl_pwrmd_flash_clksel_fast_setb(void) 5669 { 5670 CS_PWRCTRL->PWRMD |= PC_PWRMD_FLASH_CLKSEL_FAST_BIT; 5671 } 5672 pwrctrl_pwrmd_flash_clksel_fast_clrb(void)5673__STATIC_INLINE void pwrctrl_pwrmd_flash_clksel_fast_clrb(void) 5674 { 5675 CS_PWRCTRL->PWRMD &= ~PC_PWRMD_FLASH_CLKSEL_FAST_BIT; 5676 } 5677 pwrctrl_pwrmd_flash_clkdiv_smpldly_getf(void)5678__STATIC_INLINE uint32_t pwrctrl_pwrmd_flash_clkdiv_smpldly_getf(void) 5679 { 5680 return ((CS_PWRCTRL->PWRMD & (PC_PWRMD_FLASH_CLKDIV_MASK | PC_PWRMD_FLASH_SMPLDLY_MASK)) >> PC_PWRMD_FLASH_SMPLDLY_LSB); 5681 } 5682 pwrctrl_pwrmd_flash_clkdiv_smpldly_setf(uint32_t div_dly)5683__STATIC_INLINE void pwrctrl_pwrmd_flash_clkdiv_smpldly_setf(uint32_t div_dly) 5684 { 5685 uint32_t local_val = CS_PWRCTRL->PWRMD & ~(PC_PWRMD_FLASH_CLKDIV_MASK | PC_PWRMD_FLASH_SMPLDLY_MASK); 5686 CS_PWRCTRL->PWRMD = local_val | ((div_dly << PC_PWRMD_FLASH_SMPLDLY_LSB) & (PC_PWRMD_FLASH_CLKDIV_MASK | PC_PWRMD_FLASH_SMPLDLY_MASK)); 5687 } 5688 5689 #endif // _REG_SYSCTRL_H_ 5690