1 /* 2 * Copyright (c) 2021 Chipsea Technologies (Shenzhen) Corp., Ltd. All rights reserved. 3 * Licensed under the Apache License, Version 2.0 (the "License"); 4 * you may not use this file except in compliance with the License. 5 * You may obtain a copy of the License at 6 * 7 * http://www.apache.org/licenses/LICENSE-2.0 8 * 9 * Unless required by applicable law or agreed to in writing, software 10 * distributed under the License is distributed on an "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 * See the License for the specific language governing permissions and 13 * limitations under the License. 14 */ 15 /** 16 **************************************************************************************** 17 * 18 * @file sysctrl_api.h 19 * 20 * @brief SYSCTRL utility functions 21 * 22 **************************************************************************************** 23 */ 24 25 #ifndef _SYSCTRL_API_H_ 26 #define _SYSCTRL_API_H_ 27 28 /* 29 * INCLUDE FILES 30 **************************************************************************************** 31 */ 32 #include "reg_sysctrl.h" 33 34 #define DEF_CLK_FREQUENCY_52M ( 52000000UL) 35 #define DEF_CLK_FREQUENCY_26M ( 26000000UL) 36 #define SYS_CLK_FREQUENCY_40M ( 40000000UL) 37 38 enum { 39 SYS_FCLK = 0, 40 SYS_HCLK, 41 SYS_PCLK, 42 PER_UART0, 43 PER_UART1, 44 PER_UART2, 45 PER_PSRAM, 46 PER_FLASH, 47 PER_PWM, 48 }; 49 50 enum { 51 CLK_CFG_D480S240P120F120 = 0, 52 CLK_CFG_D480S240P120F80, 53 CLK_CFG_D480S240P120F60, 54 CLK_CFG_D480S240P60F120, 55 CLK_CFG_D480S240P60F80, 56 CLK_CFG_D480S240P60F60, 57 CLK_CFG_D240S240P120F120, 58 CLK_CFG_D240S240P120F60, 59 CLK_CFG_D240S240P60F60, 60 CLK_CFG_D240S120P60F120, 61 CLK_CFG_D240S120P60F60, 62 CLK_CFG_D240S120P30F60, 63 CLK_CFG_D120S120P60F60, 64 CLK_CFG_D120S120P30F60, 65 CLK_CFG_D80S80P40F40, 66 CLK_CFG_D52S52P26F26, 67 CLK_CFG_MAX, 68 }; 69 70 enum { 71 PLL_CFG_OFF = 0, 72 PLL_CFG_320, 73 PLL_CFG_480, 74 PLL_CFG_320_480, 75 }; 76 77 /* 78 * cpu_sys pwr_ctrl_mode 79 * 1) set by host idle task 80 * 2) get by fw/host other task 81 */ 82 enum { 83 CPU_SYS_POWER_ON_RESET = 0x00, 84 CPU_SYS_CLOCK_GATE = 0x01, 85 CPU_SYS_POWER_DOWN = 0x02, 86 CPU_SYS_HIBERNATE = 0x03 87 }; 88 89 /* 90 * wifi_core sw_ctrl_mode 91 * 1) set by fw/aon 92 * 2) get by fw/aon 93 */ 94 enum { 95 WIFI_CORE_CONTROLLED_BY_FW = 0x00, 96 WIFI_CORE_RELEASED_BY_FW = 0x01, 97 WIFI_CORE_CONTROLLED_BY_AON = 0x02, 98 WIFI_CORE_RELEASED_BY_AON = 0x03 99 }; 100 101 /* 102 * bt_core sw_ctrl_mode 103 * 1) set by fw/aon 104 * 2) get by fw/aon 105 */ 106 enum { 107 BT_CORE_CONTROLLED_BY_FW = 0x00, 108 BT_CORE_RELEASED_BY_FW = 0x01, 109 BT_CORE_CONTROLLED_BY_AON = 0x02, 110 BT_CORE_RELEASED_BY_AON = 0x03 111 }; 112 113 enum { 114 PWRCTRL_POWERUP = 0, 115 PWRCTRL_POWERDOWN, 116 }; 117 118 /** 119 * get HCLK/PCLK/PER_CLK 120 */ 121 uint32_t sysctrl_clock_get(int sys_per); 122 123 /** 124 * cfg DSP_CLK/SYS_CLK/PERI_CLK/FLSH_CLK 125 */ 126 void sysctrl_clock_cfg(int cfg); 127 128 /** 129 * cfg pll 130 */ 131 void sysctrl_pll_cfg(int cfg); 132 133 /** 134 * set wifi power up/down 135 */ 136 void pwrctrl_wifi_set(int ctrl); 137 138 /** 139 * set mmsys power up/down 140 */ 141 void pwrctrl_mmsys_set(int ctrl); 142 143 #endif /* _SYSCTRL_API_H_ */ 144