1 // Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
2 //
3 // Licensed under the Apache License, Version 2.0 (the "License");
4 // you may not use this file except in compliance with the License.
5 // You may obtain a copy of the License at
6 //
7 // http://www.apache.org/licenses/LICENSE-2.0
8 //
9 // Unless required by applicable law or agreed to in writing, software
10 // distributed under the License is distributed on an "AS IS" BASIS,
11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 // See the License for the specific language governing permissions and
13 // limitations under the License.
14
15 #include <stdarg.h>
16 #include "sdkconfig.h"
17 #include "esp_flash.h"
18 #include "esp_attr.h"
19
20 #include "esp_rom_sys.h"
21 #if CONFIG_IDF_TARGET_ESP32
22 #include "esp32/rom/cache.h"
23 #elif CONFIG_IDF_TARGET_ESP32S2
24 #include "esp32s2/rom/cache.h"
25 #elif CONFIG_IDF_TARGET_ESP32S3
26 #include "esp32s3/rom/ets_sys.h"
27 #include "esp32s3/rom/cache.h"
28 #elif CONFIG_IDF_TARGET_ESP32C3
29 #include "esp32c3/rom/ets_sys.h"
30 #include "esp32c3/rom/cache.h"
31 #endif
32
33 #include "esp_attr.h"
34
35 #if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
36 typedef struct {
37 uint32_t icache_autoload;
38 uint32_t dcache_autoload;
39 } spi_noos_arg_t;
40
41 static DRAM_ATTR spi_noos_arg_t spi_arg = { 0 };
42 #elif CONFIG_IDF_TARGET_ESP32C3
43 typedef struct {
44 uint32_t icache_autoload;
45 } spi_noos_arg_t;
46
47 static DRAM_ATTR spi_noos_arg_t spi_arg = { 0 };
48 #endif
49
start(void * arg)50 static IRAM_ATTR esp_err_t start(void *arg)
51 {
52 #if CONFIG_IDF_TARGET_ESP32
53 Cache_Read_Disable(0);
54 Cache_Read_Disable(1);
55 #elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
56 spi_noos_arg_t *spi_arg = arg;
57 spi_arg->icache_autoload = Cache_Suspend_ICache();
58 spi_arg->dcache_autoload = Cache_Suspend_DCache();
59 #elif CONFIG_IDF_TARGET_ESP32C3
60 spi_noos_arg_t *spi_arg = arg;
61 spi_arg->icache_autoload = Cache_Suspend_ICache();
62 #endif
63 return ESP_OK;
64 }
65
end(void * arg)66 static IRAM_ATTR esp_err_t end(void *arg)
67 {
68 #if CONFIG_IDF_TARGET_ESP32
69 Cache_Flush(0);
70 Cache_Flush(1);
71 Cache_Read_Enable(0);
72 Cache_Read_Enable(1);
73 #elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
74 spi_noos_arg_t *spi_arg = arg;
75 Cache_Invalidate_ICache_All();
76 Cache_Resume_ICache(spi_arg->icache_autoload);
77 Cache_Resume_DCache(spi_arg->dcache_autoload);
78 #elif CONFIG_IDF_TARGET_ESP32C3
79 spi_noos_arg_t *spi_arg = arg;
80 Cache_Invalidate_ICache_All();
81 Cache_Resume_ICache(spi_arg->icache_autoload);
82 #endif
83 return ESP_OK;
84 }
85
delay_us(void * arg,uint32_t us)86 static IRAM_ATTR esp_err_t delay_us(void *arg, uint32_t us)
87 {
88 esp_rom_delay_us(us);
89 return ESP_OK;
90 }
91
92 // Currently when the os is not up yet, the caller is supposed to call esp_flash APIs with proper
93 // buffers.
get_temp_buffer_not_supported(void * arg,size_t reqest_size,size_t * out_size)94 IRAM_ATTR void* get_temp_buffer_not_supported(void* arg, size_t reqest_size, size_t* out_size)
95 {
96 return NULL;
97 }
98
99 const DRAM_ATTR esp_flash_os_functions_t esp_flash_noos_functions = {
100 .start = start,
101 .end = end,
102 .delay_us = delay_us,
103 .region_protected = NULL,
104 /* the caller is supposed to call esp_flash_read/esp_flash_write APIs with buffers in DRAM */
105 .get_temp_buffer = NULL,
106 .release_temp_buffer = NULL,
107 .yield = NULL,
108 };
109
esp_flash_app_disable_os_functions(esp_flash_t * chip)110 esp_err_t IRAM_ATTR esp_flash_app_disable_os_functions(esp_flash_t* chip)
111 {
112 chip->os_func = &esp_flash_noos_functions;
113
114 #if !CONFIG_IDF_TARGET_ESP32
115 chip->os_func_data = &spi_arg;
116 #endif
117
118 return ESP_OK;
119 }
120