1 // Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 15 #ifndef ERI_H 16 #define ERI_H 17 18 #include <stdint.h> 19 20 /* 21 The ERI is a bus internal to each Xtensa core. It connects, amongst others, to the debug interface, where it 22 allows reading/writing the same registers as available over JTAG. 23 */ 24 25 26 /** 27 * @brief Perform an ERI read 28 * @param addr : ERI register to read from 29 * 30 * @return Value read 31 */ 32 uint32_t eri_read(int addr); 33 34 35 /** 36 * @brief Perform an ERI write 37 * @param addr : ERI register to write to 38 * @param data : Value to write 39 * 40 * @return Value read 41 */ 42 void eri_write(int addr, uint32_t data); 43 44 45 #endif 46