1 /* 2 * Copyright (c) 2023 HPMicro 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 */ 7 8 /* 9 * Note: 10 * PY and PZ IOs: if any SOC pin function needs to be routed to these IOs, 11 * besides of IOC, PIOC/BIOC needs to be configured SOC_GPIO_X_xx, so that 12 * expected SoC function can be enabled on these IOs. 13 * 14 */ 15 #include "board.h" 16 #include "pinmux.h" 17 init_xtal_pins(void)18void init_xtal_pins(void) 19 { 20 /* Package QFN32 should be set PA30 and PA31 pins as analog type to enable xtal. */ 21 /* 22 * HPM_IOC->PAD[IOC_PAD_PA30].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; 23 * HPM_IOC->PAD[IOC_PAD_PA31].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; 24 */ 25 } 26 init_py_pins_as_pgpio(void)27void init_py_pins_as_pgpio(void) 28 { 29 /* Set PY00-PY05 default function to PGPIO */ 30 HPM_PIOC->PAD[IOC_PAD_PY00].FUNC_CTL = IOC_PY00_FUNC_CTL_PGPIO_Y_00; 31 HPM_PIOC->PAD[IOC_PAD_PY01].FUNC_CTL = IOC_PY01_FUNC_CTL_PGPIO_Y_01; 32 HPM_PIOC->PAD[IOC_PAD_PY02].FUNC_CTL = IOC_PY02_FUNC_CTL_PGPIO_Y_02; 33 HPM_PIOC->PAD[IOC_PAD_PY03].FUNC_CTL = IOC_PY03_FUNC_CTL_PGPIO_Y_03; 34 HPM_PIOC->PAD[IOC_PAD_PY04].FUNC_CTL = IOC_PY04_FUNC_CTL_PGPIO_Y_04; 35 HPM_PIOC->PAD[IOC_PAD_PY05].FUNC_CTL = IOC_PY05_FUNC_CTL_PGPIO_Y_05; 36 } 37 init_uart_pins(UART_Type * ptr)38void init_uart_pins(UART_Type *ptr) 39 { 40 if (ptr == HPM_UART0) { 41 HPM_IOC->PAD[IOC_PAD_PA00].FUNC_CTL = IOC_PA00_FUNC_CTL_UART0_TXD; 42 HPM_IOC->PAD[IOC_PAD_PA01].FUNC_CTL = IOC_PA01_FUNC_CTL_UART0_RXD; 43 } else if (ptr == HPM_UART2) { 44 HPM_IOC->PAD[IOC_PAD_PB08].FUNC_CTL = IOC_PB08_FUNC_CTL_UART2_TXD; 45 HPM_IOC->PAD[IOC_PAD_PB09].FUNC_CTL = IOC_PB09_FUNC_CTL_UART2_RXD; 46 HPM_IOC->PAD[IOC_PAD_PB10].FUNC_CTL = IOC_PB10_FUNC_CTL_UART2_DE; 47 } else { 48 ; 49 } 50 } 51 init_i2c_pins(I2C_Type * ptr)52void init_i2c_pins(I2C_Type *ptr) 53 { 54 if (ptr == HPM_I2C0) { 55 HPM_IOC->PAD[IOC_PAD_PB02].FUNC_CTL = IOC_PB02_FUNC_CTL_I2C0_SCL | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; 56 HPM_IOC->PAD[IOC_PAD_PB03].FUNC_CTL = IOC_PB03_FUNC_CTL_I2C0_SDA | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; 57 HPM_IOC->PAD[IOC_PAD_PB02].PAD_CTL = IOC_PAD_PAD_CTL_OD_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); 58 HPM_IOC->PAD[IOC_PAD_PB03].PAD_CTL = IOC_PAD_PAD_CTL_OD_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); 59 } else if (ptr == HPM_I2C1) { 60 HPM_IOC->PAD[IOC_PAD_PB06].FUNC_CTL = IOC_PB06_FUNC_CTL_I2C1_SDA | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; 61 HPM_IOC->PAD[IOC_PAD_PB07].FUNC_CTL = IOC_PB07_FUNC_CTL_I2C1_SCL | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; 62 HPM_IOC->PAD[IOC_PAD_PB06].PAD_CTL = IOC_PAD_PAD_CTL_OD_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); 63 HPM_IOC->PAD[IOC_PAD_PB07].PAD_CTL = IOC_PAD_PAD_CTL_OD_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); 64 } else { 65 ; 66 } 67 } 68 init_gpio_pins(void)69void init_gpio_pins(void) 70 { 71 /* configure pad setting: pull enable and pull up, schmitt trigger enable */ 72 /* enable schmitt trigger to eliminate jitter of pin used as button */ 73 74 /* Button */ 75 uint32_t pad_ctl = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1) | IOC_PAD_PAD_CTL_HYS_SET(1); 76 HPM_IOC->PAD[IOC_PAD_PA09].FUNC_CTL = IOC_PA09_FUNC_CTL_GPIO_A_09; 77 HPM_IOC->PAD[IOC_PAD_PA09].PAD_CTL = pad_ctl; 78 } 79 init_spi_pins(SPI_Type * ptr)80void init_spi_pins(SPI_Type *ptr) 81 { 82 if (ptr == HPM_SPI1) { 83 HPM_IOC->PAD[IOC_PAD_PA25].FUNC_CTL = IOC_PA25_FUNC_CTL_SPI1_CS_1; 84 HPM_IOC->PAD[IOC_PAD_PA26].FUNC_CTL = IOC_PA26_FUNC_CTL_SPI1_CS_0; 85 HPM_IOC->PAD[IOC_PAD_PA27].FUNC_CTL = IOC_PA27_FUNC_CTL_SPI1_SCLK | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1); 86 HPM_IOC->PAD[IOC_PAD_PA28].FUNC_CTL = IOC_PA28_FUNC_CTL_SPI1_MISO; 87 HPM_IOC->PAD[IOC_PAD_PA29].FUNC_CTL = IOC_PA29_FUNC_CTL_SPI1_MOSI; 88 } 89 } 90 init_spi_pins_with_gpio_as_cs(SPI_Type * ptr)91void init_spi_pins_with_gpio_as_cs(SPI_Type *ptr) 92 { 93 if (ptr == HPM_SPI1) { 94 HPM_IOC->PAD[IOC_PAD_PA25].FUNC_CTL = IOC_PA25_FUNC_CTL_GPIO_A_25; 95 HPM_IOC->PAD[IOC_PAD_PA26].FUNC_CTL = IOC_PA26_FUNC_CTL_GPIO_A_26; 96 HPM_IOC->PAD[IOC_PAD_PA27].FUNC_CTL = IOC_PA27_FUNC_CTL_SPI1_SCLK | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1); 97 HPM_IOC->PAD[IOC_PAD_PA28].FUNC_CTL = IOC_PA28_FUNC_CTL_SPI1_MISO; 98 HPM_IOC->PAD[IOC_PAD_PA29].FUNC_CTL = IOC_PA29_FUNC_CTL_SPI1_MOSI; 99 } 100 } 101 102 init_gptmr_pins(GPTMR_Type * ptr)103void init_gptmr_pins(GPTMR_Type *ptr) 104 { 105 if (ptr == HPM_GPTMR0) { 106 HPM_IOC->PAD[IOC_PAD_PB06].FUNC_CTL = IOC_PB06_FUNC_CTL_GPTMR0_CAPT_0; 107 HPM_IOC->PAD[IOC_PAD_PB07].FUNC_CTL = IOC_PB07_FUNC_CTL_GPTMR0_COMP_0; 108 HPM_IOC->PAD[IOC_PAD_PB08].FUNC_CTL = IOC_PB08_FUNC_CTL_GPTMR0_COMP_1; 109 } 110 } 111 init_hall_trgm_pins(void)112void init_hall_trgm_pins(void) 113 { 114 init_qeiv2_uvw_pins(HPM_QEI1); 115 } 116 init_qei_trgm_pins(void)117void init_qei_trgm_pins(void) 118 { 119 init_qeiv2_ab_pins(HPM_QEI1); 120 } 121 init_butn_pins(void)122void init_butn_pins(void) 123 { 124 /* configure pad setting: pull enable and pull up, schmitt trigger enable */ 125 /* enable schmitt trigger to eliminate jitter of pin used as button */ 126 127 /* Button */ 128 uint32_t pad_ctl = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1) | IOC_PAD_PAD_CTL_HYS_SET(1); 129 HPM_IOC->PAD[IOC_PAD_PA09].FUNC_CTL = IOC_PA09_FUNC_CTL_GPIO_A_09; 130 HPM_IOC->PAD[IOC_PAD_PA09].PAD_CTL = pad_ctl; 131 } 132 init_acmp_pins(void)133void init_acmp_pins(void) 134 { 135 /* configure to ACMP_COMP_1(ALT16) function */ 136 HPM_IOC->PAD[IOC_PAD_PB09].FUNC_CTL = IOC_PB09_FUNC_CTL_ACMP_COMP_1; 137 /* configure to CMP1_INN4 function */ 138 HPM_IOC->PAD[IOC_PAD_PB11].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; 139 } 140 init_pwm_pins(PWM_Type * ptr)141void init_pwm_pins(PWM_Type *ptr) 142 { 143 if (ptr == HPM_PWM0) { 144 HPM_IOC->PAD[IOC_PAD_PA26].FUNC_CTL = IOC_PA26_FUNC_CTL_PWM0_P_2; 145 HPM_IOC->PAD[IOC_PAD_PA27].FUNC_CTL = IOC_PA27_FUNC_CTL_PWM0_P_3; 146 HPM_IOC->PAD[IOC_PAD_PA28].FUNC_CTL = IOC_PA28_FUNC_CTL_PWM0_P_4; 147 HPM_IOC->PAD[IOC_PAD_PA29].FUNC_CTL = IOC_PA29_FUNC_CTL_PWM0_P_5; 148 HPM_IOC->PAD[IOC_PAD_PA30].FUNC_CTL = IOC_PA30_FUNC_CTL_PWM0_P_6; 149 HPM_IOC->PAD[IOC_PAD_PA31].FUNC_CTL = IOC_PA31_FUNC_CTL_PWM0_P_7; 150 } 151 } 152 init_adc_pins(void)153void init_adc_pins(void) 154 { 155 HPM_IOC->PAD[IOC_PAD_PB00].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; /* ADC Test: ADC0.15/ADC1.15 */ 156 HPM_IOC->PAD[IOC_PAD_PB01].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; /* ADC_BUS: ADC0.14/ADC1.14 */ 157 HPM_IOC->PAD[IOC_PAD_PB08].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; /* ADC_A: ADC0.11/ADC1.11 */ 158 HPM_IOC->PAD[IOC_PAD_PB09].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; /* ADC_B: ADC0.1 /ADC1.1 */ 159 HPM_IOC->PAD[IOC_PAD_PB10].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; /* ADC_C: ADC0.2 /ADC1.2 */ 160 HPM_IOC->PAD[IOC_PAD_PB11].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; /* ADC_D: ADC0.3 /ADC1.3 */ 161 HPM_IOC->PAD[IOC_PAD_PB12].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; /* ADC_IW: ADC0.4 /ADC1.4 */ 162 HPM_IOC->PAD[IOC_PAD_PB13].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; /* ADC_IU: ADC0.5 /ADC1.5 */ 163 HPM_IOC->PAD[IOC_PAD_PB14].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; /* ADC_IV: ADC0.6 /ADC1.6 */ 164 HPM_IOC->PAD[IOC_PAD_PB15].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; /* Board ID: ADC0.7 /ADC1.7 */ 165 } 166 init_adc_bldc_pins(void)167void init_adc_bldc_pins(void) 168 { 169 HPM_IOC->PAD[IOC_PAD_PB13].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; /* ADC_IU: ADC0.5 /ADC1.5 */ 170 HPM_IOC->PAD[IOC_PAD_PB14].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; /* ADC_IV: ADC0.6 /ADC1.6 */ 171 } 172 init_adc_qeiv2_pins(void)173void init_adc_qeiv2_pins(void) 174 { 175 HPM_IOC->PAD[IOC_PAD_PB12].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; /* ADC_IW: ADC0.4 /ADC1.4 */ 176 HPM_IOC->PAD[IOC_PAD_PB13].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; /* ADC_IU: ADC0.5 /ADC1.5 */ 177 } 178 init_usb_pins(void)179void init_usb_pins(void) 180 { 181 /* Package QFN48 and LQFP64 should be set PA24 and PA25 pins as analog type to enable USB_P and USB_N. */ 182 /* 183 * HPM_IOC->PAD[IOC_PAD_PA24].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; 184 * HPM_IOC->PAD[IOC_PAD_PA25].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; 185 */ 186 187 /* Package QFN32 should be set PA26 and PA27 pins as analog type to enable USB_P and USB_N. */ 188 /* 189 * HPM_IOC->PAD[IOC_PAD_PA26].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; 190 * HPM_IOC->PAD[IOC_PAD_PA27].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; 191 */ 192 193 /* USB0_ID */ 194 HPM_IOC->PAD[IOC_PAD_PY00].FUNC_CTL = IOC_PY00_FUNC_CTL_USB0_ID; 195 /* USB0_OC */ 196 HPM_IOC->PAD[IOC_PAD_PY01].FUNC_CTL = IOC_PY01_FUNC_CTL_USB0_OC; 197 /* USB0_PWR */ 198 HPM_IOC->PAD[IOC_PAD_PY02].FUNC_CTL = IOC_PY02_FUNC_CTL_USB0_PWR; 199 200 /* PY port IO needs to configure PIOC as well */ 201 HPM_PIOC->PAD[IOC_PAD_PY00].FUNC_CTL = IOC_PY00_FUNC_CTL_SOC_GPIO_Y_00; 202 HPM_PIOC->PAD[IOC_PAD_PY01].FUNC_CTL = IOC_PY01_FUNC_CTL_SOC_GPIO_Y_01; 203 HPM_PIOC->PAD[IOC_PAD_PY02].FUNC_CTL = IOC_PY02_FUNC_CTL_SOC_GPIO_Y_02; 204 } 205 init_can_pins(MCAN_Type * ptr)206void init_can_pins(MCAN_Type *ptr) 207 { 208 if (ptr == HPM_MCAN3) { 209 HPM_IOC->PAD[IOC_PAD_PY04].FUNC_CTL = IOC_PY04_FUNC_CTL_CAN3_RXD; 210 HPM_IOC->PAD[IOC_PAD_PY05].FUNC_CTL = IOC_PY05_FUNC_CTL_CAN3_TXD; 211 /* PY port IO needs to configure PIOC as well */ 212 HPM_PIOC->PAD[IOC_PAD_PY04].FUNC_CTL = IOC_PY04_FUNC_CTL_SOC_GPIO_Y_04; 213 HPM_PIOC->PAD[IOC_PAD_PY05].FUNC_CTL = IOC_PY05_FUNC_CTL_SOC_GPIO_Y_05; 214 } 215 } 216 init_led_pins_as_gpio(void)217void init_led_pins_as_gpio(void) 218 { 219 HPM_IOC->PAD[IOC_PAD_PA23].FUNC_CTL = IOC_PA23_FUNC_CTL_GPIO_A_23; 220 } 221 init_led_pins_as_pwm(void)222void init_led_pins_as_pwm(void) 223 { 224 HPM_IOC->PAD[IOC_PAD_PA23].FUNC_CTL = IOC_PA23_FUNC_CTL_TRGM0_P_03; 225 } 226 init_dac_pins(DAC_Type * ptr)227void init_dac_pins(DAC_Type *ptr) 228 { 229 if (ptr == HPM_DAC0) { 230 HPM_IOC->PAD[IOC_PAD_PB08].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; /* DAC0.OUT */ 231 } else if (ptr == HPM_DAC1) { 232 HPM_IOC->PAD[IOC_PAD_PB09].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; /* DAC1.OUT */ 233 } 234 } 235 init_lin_pins(LINV2_Type * ptr)236void init_lin_pins(LINV2_Type *ptr) 237 { 238 /** enable open drain and pull up */ 239 uint32_t pad_ctl = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1) | IOC_PAD_PAD_CTL_OD_SET(1); 240 if (ptr == HPM_LIN3) { 241 HPM_IOC->PAD[IOC_PAD_PA13].FUNC_CTL = IOC_PA13_FUNC_CTL_LIN3_TREN; 242 HPM_IOC->PAD[IOC_PAD_PA13].PAD_CTL = pad_ctl; 243 HPM_IOC->PAD[IOC_PAD_PA14].FUNC_CTL = IOC_PA14_FUNC_CTL_LIN3_RXD; 244 HPM_IOC->PAD[IOC_PAD_PA14].PAD_CTL = pad_ctl; 245 HPM_IOC->PAD[IOC_PAD_PA15].FUNC_CTL = IOC_PA15_FUNC_CTL_LIN3_TXD; 246 HPM_IOC->PAD[IOC_PAD_PA15].PAD_CTL = pad_ctl; 247 } 248 /* Enable 12V */ 249 HPM_IOC->PAD[IOC_PAD_PA24].FUNC_CTL = IOC_PA24_FUNC_CTL_GPIO_A_24; 250 } 251 init_plb_pins(void)252void init_plb_pins(void) 253 { 254 HPM_IOC->PAD[IOC_PAD_PA26].FUNC_CTL = IOC_PA26_FUNC_CTL_TRGM0_P_02; 255 } 256 init_qeo_pins(QEO_Type * ptr)257void init_qeo_pins(QEO_Type *ptr) 258 { 259 if (ptr == HPM_QEO0) { 260 HPM_IOC->PAD[IOC_PAD_PA20].FUNC_CTL = IOC_PA20_FUNC_CTL_QEO0_A; 261 HPM_IOC->PAD[IOC_PAD_PA21].FUNC_CTL = IOC_PA21_FUNC_CTL_QEO0_B; 262 HPM_IOC->PAD[IOC_PAD_PA22].FUNC_CTL = IOC_PA22_FUNC_CTL_QEO0_Z; 263 } 264 } 265 init_sei_pins(SEI_Type * ptr,uint8_t sei_ctrl_idx)266void init_sei_pins(SEI_Type *ptr, uint8_t sei_ctrl_idx) 267 { 268 if (ptr == HPM_SEI) { 269 if (sei_ctrl_idx == SEI_CTRL_1) { 270 HPM_IOC->PAD[IOC_PAD_PA16].FUNC_CTL = IOC_PA16_FUNC_CTL_SEI1_DE; 271 HPM_IOC->PAD[IOC_PAD_PA17].FUNC_CTL = IOC_PA17_FUNC_CTL_SEI1_CK; 272 HPM_IOC->PAD[IOC_PAD_PA18].FUNC_CTL = IOC_PA18_FUNC_CTL_SEI1_TX; 273 HPM_IOC->PAD[IOC_PAD_PA19].FUNC_CTL = IOC_PA19_FUNC_CTL_SEI1_RX; 274 } 275 } 276 } 277 init_rdc_pin(void)278void init_rdc_pin(void) 279 { 280 HPM_IOC->PAD[IOC_PAD_PA28].FUNC_CTL = IOC_PA28_FUNC_CTL_RDC0_EXC_P; 281 HPM_IOC->PAD[IOC_PAD_PB13].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; 282 HPM_IOC->PAD[IOC_PAD_PB14].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; 283 284 /*The GPIO is designed for debug */ 285 #ifdef RDC_SAMPLE_TEST_GPIO_OUTPUT 286 HPM_IOC->PAD[IOC_PAD_PB04].FUNC_CTL = IOC_PB04_FUNC_CTL_TRGM0_P_00; 287 #endif 288 } 289 init_qeiv2_uvw_pins(QEIV2_Type * ptr)290void init_qeiv2_uvw_pins(QEIV2_Type *ptr) 291 { 292 if (ptr == HPM_QEI1) { 293 HPM_IOC->PAD[IOC_PAD_PA10].FUNC_CTL = IOC_PA10_FUNC_CTL_QEI1_A; 294 HPM_IOC->PAD[IOC_PAD_PA11].FUNC_CTL = IOC_PA11_FUNC_CTL_QEI1_B; 295 HPM_IOC->PAD[IOC_PAD_PA12].FUNC_CTL = IOC_PA12_FUNC_CTL_QEI1_Z; 296 } 297 } 298 init_qeiv2_ab_pins(QEIV2_Type * ptr)299void init_qeiv2_ab_pins(QEIV2_Type *ptr) 300 { 301 if (ptr == HPM_QEI1) { 302 HPM_IOC->PAD[IOC_PAD_PA10].FUNC_CTL = IOC_PA10_FUNC_CTL_QEI1_A; 303 HPM_IOC->PAD[IOC_PAD_PA11].FUNC_CTL = IOC_PA11_FUNC_CTL_QEI1_B; 304 } 305 } 306 init_qeiv2_abz_pins(QEIV2_Type * ptr)307void init_qeiv2_abz_pins(QEIV2_Type *ptr) 308 { 309 if (ptr == HPM_QEI1) { 310 HPM_IOC->PAD[IOC_PAD_PA10].FUNC_CTL = IOC_PA10_FUNC_CTL_QEI1_A; 311 HPM_IOC->PAD[IOC_PAD_PA11].FUNC_CTL = IOC_PA11_FUNC_CTL_QEI1_B; 312 HPM_IOC->PAD[IOC_PAD_PA12].FUNC_CTL = IOC_PA12_FUNC_CTL_QEI1_Z; 313 } 314 } 315 init_opamp_pins(void)316void init_opamp_pins(void) 317 { 318 HPM_IOC->PAD[IOC_PAD_PB00].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; 319 HPM_IOC->PAD[IOC_PAD_PB04].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; 320 } 321