1 /*
2 * Copyright (c) 2023 HPMicro
3 * SPDX-License-Identifier: BSD-3-Clause
4 *
5 */
6
7 #include "board.h"
8 #include "hpm_uart_drv.h"
9 #include "hpm_sdk_version.h"
10 #include "hpm_gptmr_drv.h"
11 #include "hpm_gpio_drv.h"
12 #include "hpm_usb_drv.h"
13 #include "hpm_clock_drv.h"
14 #include "hpm_pllctlv2_drv.h"
15 #include "hpm_i2c_drv.h"
16 #include "hpm_pcfg_drv.h"
17
18 static board_timer_cb timer_cb;
19
20 /**
21 * @brief FLASH configuration option definitions:
22 * option[0]:
23 * [31:16] 0xfcf9 - FLASH configuration option tag
24 * [15:4] 0 - Reserved
25 * [3:0] option words (exclude option[0])
26 * option[1]:
27 * [31:28] Flash probe type
28 * 0 - SFDP SDR / 1 - SFDP DDR
29 * 2 - 1-4-4 Read (0xEB, 24-bit address) / 3 - 1-2-2 Read(0xBB, 24-bit address)
30 * 4 - HyperFLASH 1.8V / 5 - HyperFLASH 3V
31 * 6 - OctaBus DDR (SPI -> OPI DDR)
32 * 8 - Xccela DDR (SPI -> OPI DDR)
33 * 10 - EcoXiP DDR (SPI -> OPI DDR)
34 * [27:24] Command Pads after Power-on Reset
35 * 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI
36 * [23:20] Command Pads after Configuring FLASH
37 * 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI
38 * [19:16] Quad Enable Sequence (for the device support SFDP 1.0 only)
39 * 0 - Not needed
40 * 1 - QE bit is at bit 6 in Status Register 1
41 * 2 - QE bit is at bit1 in Status Register 2
42 * 3 - QE bit is at bit7 in Status Register 2
43 * 4 - QE bit is at bit1 in Status Register 2 and should be programmed by 0x31
44 * [15:8] Dummy cycles
45 * 0 - Auto-probed / detected / default value
46 * Others - User specified value, for DDR read, the dummy cycles should be 2 * cycles on FLASH datasheet
47 * [7:4] Misc.
48 * 0 - Not used
49 * 1 - SPI mode
50 * 2 - Internal loopback
51 * 3 - External DQS
52 * [3:0] Frequency option
53 * 1 - 30MHz / 2 - 50MHz / 3 - 66MHz / 4 - 80MHz / 5 - 100MHz / 6 - 120MHz / 7 - 133MHz / 8 - 166MHz
54 *
55 * option[2] (Effective only if the bit[3:0] in option[0] > 1)
56 * [31:20] Reserved
57 * [19:16] IO voltage
58 * 0 - 3V / 1 - 1.8V
59 * [15:12] Pin group
60 * 0 - 1st group / 1 - 2nd group
61 * [11:8] Connection selection
62 * 0 - CA_CS0 / 1 - CB_CS0 / 2 - CA_CS0 + CB_CS0 (Two FLASH connected to CA and CB respectively)
63 * [7:0] Drive Strength
64 * 0 - Default value
65 * option[3] (Effective only if the bit[3:0] in option[0] > 2, required only for the QSPI NOR FLASH that not supports
66 * JESD216)
67 * [31:16] reserved
68 * [15:12] Sector Erase Command Option, not required here
69 * [11:8] Sector Size Option, not required here
70 * [7:0] Flash Size Option
71 * 0 - 4MB / 1 - 8MB / 2 - 16MB
72 */
73 #if defined(FLASH_XIP) && FLASH_XIP
74 __attribute__ ((section(".nor_cfg_option"))) const uint32_t option[4] = {0xfcf90002, 0x00000006, 0x1000, 0x0};
75 #endif
76
77 #if defined(FLASH_UF2) && FLASH_UF2
78 ATTR_PLACE_AT(".uf2_signature") const uint32_t uf2_signature = BOARD_UF2_SIGNATURE;
79 #endif
80
board_init_console(void)81 void board_init_console(void)
82 {
83 #if !defined(CONFIG_NDEBUG_CONSOLE) || !CONFIG_NDEBUG_CONSOLE
84 #if BOARD_CONSOLE_TYPE == CONSOLE_TYPE_UART
85 console_config_t cfg;
86
87 /* uart needs to configure pin function before enabling clock, otherwise the level change of
88 * uart rx pin when configuring pin function will cause a wrong data to be received.
89 * And a uart rx dma request will be generated by default uart fifo dma trigger level.
90 */
91 init_uart_pins((UART_Type *) BOARD_CONSOLE_BASE);
92
93 /* Configure the UART clock to 24MHz */
94 clock_set_source_divider(BOARD_CONSOLE_CLK_NAME, clk_src_osc24m, 1U);
95 clock_add_to_group(BOARD_CONSOLE_CLK_NAME, 0);
96
97 cfg.type = BOARD_CONSOLE_TYPE;
98 cfg.base = (uint32_t)BOARD_CONSOLE_BASE;
99 cfg.src_freq_in_hz = clock_get_frequency(BOARD_CONSOLE_CLK_NAME);
100 cfg.baudrate = BOARD_CONSOLE_BAUDRATE;
101
102 if (status_success != console_init(&cfg)) {
103 /* failed to initialize debug console */
104 while (1) {
105 }
106 }
107 #else
108 while (1)
109 ;
110 #endif
111 #endif
112 }
113
board_print_banner(void)114 void board_print_banner(void)
115 {
116 const uint8_t banner[] = "\n"
117 "----------------------------------------------------------------------\n"
118 "$$\\ $$\\ $$$$$$$\\ $$\\ $$\\ $$\\\n"
119 "$$ | $$ |$$ __$$\\ $$$\\ $$$ |\\__|\n"
120 "$$ | $$ |$$ | $$ |$$$$\\ $$$$ |$$\\ $$$$$$$\\ $$$$$$\\ $$$$$$\\\n"
121 "$$$$$$$$ |$$$$$$$ |$$\\$$\\$$ $$ |$$ |$$ _____|$$ __$$\\ $$ __$$\\\n"
122 "$$ __$$ |$$ ____/ $$ \\$$$ $$ |$$ |$$ / $$ | \\__|$$ / $$ |\n"
123 "$$ | $$ |$$ | $$ |\\$ /$$ |$$ |$$ | $$ | $$ | $$ |\n"
124 "$$ | $$ |$$ | $$ | \\_/ $$ |$$ |\\$$$$$$$\\ $$ | \\$$$$$$ |\n"
125 "\\__| \\__|\\__| \\__| \\__|\\__| \\_______|\\__| \\______/\n"
126 "----------------------------------------------------------------------\n";
127 #ifdef SDK_VERSION_STRING
128 printf("hpm_sdk: %s\n", SDK_VERSION_STRING);
129 #endif
130 printf("%s", banner);
131 }
132
board_print_clock_freq(void)133 void board_print_clock_freq(void)
134 {
135 printf("==============================\n");
136 printf(" %s clock summary\n", BOARD_NAME);
137 printf("==============================\n");
138 printf("cpu0:\t\t %luHz\n", clock_get_frequency(clock_cpu0));
139 printf("ahb:\t\t %luHz\n", clock_get_frequency(clock_ahb));
140 printf("mchtmr0:\t %luHz\n", clock_get_frequency(clock_mchtmr0));
141 printf("xpi0:\t\t %luHz\n", clock_get_frequency(clock_xpi0));
142 printf("==============================\n");
143 }
144
board_init(void)145 void board_init(void)
146 {
147 init_xtal_pins();
148 init_py_pins_as_pgpio();
149 board_init_usb_dp_dm_pins();
150
151 board_init_clock();
152 board_init_console();
153 board_init_pmp();
154 #if BOARD_SHOW_CLOCK
155 board_print_clock_freq();
156 #endif
157 #if BOARD_SHOW_BANNER
158 board_print_banner();
159 #endif
160 }
161
board_init_usb_dp_dm_pins(void)162 void board_init_usb_dp_dm_pins(void)
163 {
164 /* Disconnect usb dp/dm pins pull down 45ohm resistance */
165
166 while (sysctl_resource_any_is_busy(HPM_SYSCTL)) {
167 ;
168 }
169 if (pllctlv2_xtal_is_stable(HPM_PLLCTLV2) && pllctlv2_xtal_is_enabled(HPM_PLLCTLV2)) {
170 if (clock_check_in_group(clock_usb0, 0)) {
171 usb_phy_disable_dp_dm_pulldown(HPM_USB0);
172 } else {
173 clock_add_to_group(clock_usb0, 0);
174 usb_phy_disable_dp_dm_pulldown(HPM_USB0);
175 clock_remove_from_group(clock_usb0, 0);
176 }
177 } else {
178 uint8_t tmp;
179 tmp = sysctl_resource_target_get_mode(HPM_SYSCTL, sysctl_resource_xtal);
180 sysctl_resource_target_set_mode(HPM_SYSCTL, sysctl_resource_xtal, 0x03);
181 clock_add_to_group(clock_usb0, 0);
182 usb_phy_disable_dp_dm_pulldown(HPM_USB0);
183 clock_remove_from_group(clock_usb0, 0);
184 while (sysctl_resource_target_is_busy(HPM_SYSCTL, sysctl_resource_usb0)) {
185 ;
186 }
187 sysctl_resource_target_set_mode(HPM_SYSCTL, sysctl_resource_xtal, tmp);
188 }
189 }
190
board_init_clock(void)191 void board_init_clock(void)
192 {
193 uint32_t cpu0_freq = clock_get_frequency(clock_cpu0);
194
195 if (cpu0_freq == PLLCTL_SOC_PLL_REFCLK_FREQ) {
196 /* Configure the External OSC ramp-up time: ~9ms */
197 pllctlv2_xtal_set_rampup_time(HPM_PLLCTLV2, 32UL * 1000UL * 9U);
198
199 /* Select clock setting preset1 */
200 sysctl_clock_set_preset(HPM_SYSCTL, 2);
201 }
202
203 /* group0[0] */
204 clock_add_to_group(clock_cpu0, 0);
205 clock_add_to_group(clock_ahb, 0);
206 clock_add_to_group(clock_lmm0, 0);
207 clock_add_to_group(clock_mchtmr0, 0);
208 clock_add_to_group(clock_rom, 0);
209 clock_add_to_group(clock_gptmr0, 0);
210 clock_add_to_group(clock_gptmr1, 0);
211 clock_add_to_group(clock_i2c2, 0);
212 clock_add_to_group(clock_spi1, 0);
213 clock_add_to_group(clock_uart0, 0);
214 clock_add_to_group(clock_uart3, 0);
215
216 clock_add_to_group(clock_watchdog0, 0);
217 clock_add_to_group(clock_watchdog1, 0);
218 clock_add_to_group(clock_mbx0, 0);
219 clock_add_to_group(clock_tsns, 0);
220 clock_add_to_group(clock_crc0, 0);
221 clock_add_to_group(clock_adc0, 0);
222 clock_add_to_group(clock_acmp, 0);
223 clock_add_to_group(clock_kman, 0);
224 clock_add_to_group(clock_gpio, 0);
225 clock_add_to_group(clock_hdma, 0);
226 clock_add_to_group(clock_xpi0, 0);
227 clock_add_to_group(clock_usb0, 0);
228
229 /* Connect Group0 to CPU0 */
230 clock_connect_group_to_cpu(0, 0);
231
232 /* Bump up DCDC voltage to 1175mv */
233 pcfg_dcdc_set_voltage(HPM_PCFG, 1175);
234
235 /* Configure CPU to 360MHz, AXI/AHB to 120MHz */
236 sysctl_config_cpu0_domain_clock(HPM_SYSCTL, clock_source_pll0_clk0, 2, 3);
237 /* Configure PLL0 Post Divider */
238 pllctlv2_set_postdiv(HPM_PLLCTLV2, 0, 0, 0); /* PLL0CLK0: 720MHz */
239 pllctlv2_set_postdiv(HPM_PLLCTLV2, 0, 1, 3); /* PLL0CLK1: 450MHz */
240 pllctlv2_set_postdiv(HPM_PLLCTLV2, 0, 2, 7); /* PLL0CLK2: 300MHz */
241 /* Configure PLL0 Frequency to 720MHz */
242 pllctlv2_init_pll_with_freq(HPM_PLLCTLV2, 0, 720000000);
243
244 clock_update_core_clock();
245
246 /* Configure mchtmr to 24MHz */
247 clock_set_source_divider(clock_mchtmr0, clk_src_osc24m, 1);
248 }
249
board_delay_us(uint32_t us)250 void board_delay_us(uint32_t us)
251 {
252 clock_cpu_delay_us(us);
253 }
254
board_delay_ms(uint32_t ms)255 void board_delay_ms(uint32_t ms)
256 {
257 clock_cpu_delay_ms(ms);
258 }
259
board_timer_isr(void)260 void board_timer_isr(void)
261 {
262 if (gptmr_check_status(BOARD_CALLBACK_TIMER, GPTMR_CH_RLD_STAT_MASK(BOARD_CALLBACK_TIMER_CH))) {
263 gptmr_clear_status(BOARD_CALLBACK_TIMER, GPTMR_CH_RLD_STAT_MASK(BOARD_CALLBACK_TIMER_CH));
264 timer_cb();
265 }
266 }
267 SDK_DECLARE_EXT_ISR_M(BOARD_CALLBACK_TIMER_IRQ, board_timer_isr);
268
board_timer_create(uint32_t ms,board_timer_cb cb)269 void board_timer_create(uint32_t ms, board_timer_cb cb)
270 {
271 uint32_t gptmr_freq;
272 gptmr_channel_config_t config;
273
274 timer_cb = cb;
275 gptmr_channel_get_default_config(BOARD_CALLBACK_TIMER, &config);
276
277 clock_add_to_group(BOARD_CALLBACK_TIMER_CLK_NAME, 0);
278 gptmr_freq = clock_get_frequency(BOARD_CALLBACK_TIMER_CLK_NAME);
279
280 config.reload = gptmr_freq / 1000 * ms;
281 gptmr_channel_config(BOARD_CALLBACK_TIMER, BOARD_CALLBACK_TIMER_CH, &config, false);
282 gptmr_enable_irq(BOARD_CALLBACK_TIMER, GPTMR_CH_RLD_IRQ_MASK(BOARD_CALLBACK_TIMER_CH));
283 intc_m_enable_irq_with_priority(BOARD_CALLBACK_TIMER_IRQ, 1);
284
285 gptmr_start_counter(BOARD_CALLBACK_TIMER, BOARD_CALLBACK_TIMER_CH);
286 }
287
board_init_gpio_pins(void)288 void board_init_gpio_pins(void)
289 {
290 init_gpio_pins();
291 gpio_set_pin_input(BOARD_APP_GPIO_CTRL, BOARD_APP_GPIO_INDEX, BOARD_APP_GPIO_PIN);
292 }
293
board_init_led_pins(void)294 void board_init_led_pins(void)
295 {
296 init_led_pins_as_gpio();
297 gpio_set_pin_output_with_initial(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN, board_get_led_gpio_off_level());
298 }
299
board_init_usb_pins(void)300 void board_init_usb_pins(void)
301 {
302 init_usb_pins();
303 usb_hcd_set_power_ctrl_polarity(BOARD_USB, true);
304
305 /* As QFN32, QFN48 and LQFP64 has no vbus pin, so should be call usb_phy_using_internal_vbus() API to use internal vbus. */
306 usb_phy_using_internal_vbus(BOARD_USB);
307 }
308
board_led_write(uint8_t state)309 void board_led_write(uint8_t state)
310 {
311 gpio_write_pin(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN, state);
312 }
313
board_led_toggle(void)314 void board_led_toggle(void)
315 {
316 gpio_toggle_pin(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN);
317 }
318
board_init_uart(UART_Type * ptr)319 void board_init_uart(UART_Type *ptr)
320 {
321 /* configure uart's pin before opening uart's clock */
322 init_uart_pins(ptr);
323 board_init_uart_clock(ptr);
324 }
325
board_ungate_mchtmr_at_lp_mode(void)326 void board_ungate_mchtmr_at_lp_mode(void)
327 {
328 /* Keep cpu clock on wfi, so that mchtmr irq can still work after wfi */
329 sysctl_set_cpu_lp_mode(HPM_SYSCTL, BOARD_RUNNING_CORE, cpu_lp_mode_ungate_cpu_clock);
330 }
331
board_init_spi_clock(SPI_Type * ptr)332 uint32_t board_init_spi_clock(SPI_Type *ptr)
333 {
334 if (ptr == HPM_SPI1) {
335 clock_add_to_group(clock_spi1, 0);
336 return clock_get_frequency(clock_spi1);
337 }
338 return 0;
339 }
340
board_init_spi_pins(SPI_Type * ptr)341 void board_init_spi_pins(SPI_Type *ptr)
342 {
343 init_spi_pins(ptr);
344 }
345
board_write_spi_cs(uint32_t pin,uint8_t state)346 void board_write_spi_cs(uint32_t pin, uint8_t state)
347 {
348 gpio_write_pin(BOARD_SPI_CS_GPIO_CTRL, GPIO_GET_PORT_INDEX(pin), GPIO_GET_PIN_INDEX(pin), state);
349 }
350
board_init_spi_pins_with_gpio_as_cs(SPI_Type * ptr)351 void board_init_spi_pins_with_gpio_as_cs(SPI_Type *ptr)
352 {
353 init_spi_pins_with_gpio_as_cs(ptr);
354 gpio_set_pin_output_with_initial(BOARD_SPI_CS_GPIO_CTRL, GPIO_GET_PORT_INDEX(BOARD_SPI_CS_PIN),
355 GPIO_GET_PIN_INDEX(BOARD_SPI_CS_PIN), !BOARD_SPI_CS_ACTIVE_LEVEL);
356 }
357
board_usb_vbus_ctrl(uint8_t usb_index,uint8_t level)358 void board_usb_vbus_ctrl(uint8_t usb_index, uint8_t level)
359 {
360 (void) usb_index;
361 (void) level;
362 }
363
board_init_adc16_clock(ADC16_Type * ptr,bool clk_src_ahb)364 uint32_t board_init_adc16_clock(ADC16_Type *ptr, bool clk_src_ahb)
365 {
366 uint32_t freq = 0;
367
368 if (ptr == HPM_ADC0) {
369 if (clk_src_ahb) {
370 /* Configure the ADC clock from AHB (@200MHz by default)*/
371 clock_set_adc_source(clock_adc0, clk_adc_src_ahb0);
372 } else {
373 /* Configure the ADC clock from pll0_clk0 divided by 2 (@200MHz by default) */
374 clock_set_adc_source(clock_adc0, clk_adc_src_ana0);
375 clock_set_source_divider(clock_ana0, clk_src_pll0_clk2, 2U);
376 }
377
378 freq = clock_get_frequency(clock_adc0);
379 }
380
381 return freq;
382 }
383
board_init_adc16_pins(void)384 void board_init_adc16_pins(void)
385 {
386 init_adc_pins();
387 }
388
board_disable_output_rgb_led(uint8_t color)389 void board_disable_output_rgb_led(uint8_t color)
390 {
391 (void) color;
392 }
393
board_enable_output_rgb_led(uint8_t color)394 void board_enable_output_rgb_led(uint8_t color)
395 {
396 (void) color;
397 }
398
board_get_led_gpio_off_level(void)399 uint8_t board_get_led_gpio_off_level(void)
400 {
401 return BOARD_LED_OFF_LEVEL;
402 }
403
board_init_pmp(void)404 void board_init_pmp(void)
405 {
406 }
407
board_init_uart_clock(UART_Type * ptr)408 uint32_t board_init_uart_clock(UART_Type *ptr)
409 {
410 uint32_t freq = 0U;
411 if (ptr == HPM_UART0) {
412 clock_set_source_divider(clock_uart0, clk_src_osc24m, 1);
413 clock_add_to_group(clock_uart0, 0);
414 freq = clock_get_frequency(clock_uart0);
415 } else if (ptr == HPM_UART3) {
416 clock_set_source_divider(clock_uart3, clk_src_osc24m, 1);
417 clock_add_to_group(clock_uart3, 0);
418 freq = clock_get_frequency(clock_uart3);
419 }
420
421 return freq;
422 }
423
board_i2c_bus_clear(I2C_Type * ptr)424 void board_i2c_bus_clear(I2C_Type *ptr)
425 {
426 if (i2c_get_line_scl_status(ptr) == false) {
427 printf("CLK is low, please power cycle the board\n");
428 while (1) {
429 }
430 }
431 if (i2c_get_line_sda_status(ptr) == false) {
432 printf("SDA is low, try to issue I2C bus clear\n");
433 } else {
434 printf("I2C bus is ready\n");
435 return;
436 }
437 i2s_gen_reset_signal(ptr, 9);
438 board_delay_ms(100);
439 printf("I2C bus is cleared\n");
440 }
441
board_init_i2c(I2C_Type * ptr)442 void board_init_i2c(I2C_Type *ptr)
443 {
444 i2c_config_t config;
445 hpm_stat_t stat;
446 uint32_t freq;
447 if (ptr == NULL) {
448 return;
449 }
450 init_i2c_pins(ptr);
451 board_i2c_bus_clear(ptr);
452
453 clock_add_to_group(clock_i2c2, 0);
454 /* Configure the I2C clock to 24MHz */
455 clock_set_source_divider(BOARD_APP_I2C_CLK_NAME, clk_src_osc24m, 1U);
456
457 config.i2c_mode = i2c_mode_normal;
458 config.is_10bit_addressing = false;
459 freq = clock_get_frequency(BOARD_APP_I2C_CLK_NAME);
460 stat = i2c_init_master(ptr, freq, &config);
461 if (stat != status_success) {
462 printf("failed to initialize i2c 0x%lx\n", (uint32_t) ptr);
463 while (1) {
464 }
465 }
466
467 }
468
469