1 /*
2 * Copyright (c) 2023 HPMicro
3 * SPDX-License-Identifier: BSD-3-Clause
4 *
5 *
6 */
7
8 #include "board.h"
9 #include "hpm_uart_drv.h"
10 #include "hpm_gptmr_drv.h"
11 #include "hpm_lcdc_drv.h"
12 #include "hpm_i2c_drv.h"
13 #include "hpm_gpio_drv.h"
14 #include "pinmux.h"
15 #include "hpm_pmp_drv.h"
16 #include "hpm_clock_drv.h"
17 #include "hpm_sysctl_drv.h"
18 #include "hpm_pwm_drv.h"
19 #include "hpm_trgm_drv.h"
20 #include "hpm_pllctlv2_drv.h"
21 #include "hpm_pcfg_drv.h"
22
23 static board_timer_cb timer_cb;
24
25 /**
26 * @brief FLASH configuration option definitions:
27 * option[0]:
28 * [31:16] 0xfcf9 - FLASH configuration option tag
29 * [15:4] 0 - Reserved
30 * [3:0] option words (exclude option[0])
31 * option[1]:
32 * [31:28] Flash probe type
33 * 0 - SFDP SDR / 1 - SFDP DDR
34 * 2 - 1-4-4 Read (0xEB, 24-bit address) / 3 - 1-2-2 Read(0xBB, 24-bit address)
35 * 4 - HyperFLASH 1.8V / 5 - HyperFLASH 3V
36 * 6 - OctaBus DDR (SPI -> OPI DDR)
37 * 8 - Xccela DDR (SPI -> OPI DDR)
38 * 10 - EcoXiP DDR (SPI -> OPI DDR)
39 * [27:24] Command Pads after Power-on Reset
40 * 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI
41 * [23:20] Command Pads after Configuring FLASH
42 * 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI
43 * [19:16] Quad Enable Sequence (for the device support SFDP 1.0 only)
44 * 0 - Not needed
45 * 1 - QE bit is at bit 6 in Status Register 1
46 * 2 - QE bit is at bit1 in Status Register 2
47 * 3 - QE bit is at bit7 in Status Register 2
48 * 4 - QE bit is at bit1 in Status Register 2 and should be programmed by 0x31
49 * [15:8] Dummy cycles
50 * 0 - Auto-probed / detected / default value
51 * Others - User specified value, for DDR read, the dummy cycles should be 2 * cycles on FLASH datasheet
52 * [7:4] Misc.
53 * 0 - Not used
54 * 1 - SPI mode
55 * 2 - Internal loopback
56 * 3 - External DQS
57 * [3:0] Frequency option
58 * 1 - 30MHz / 2 - 50MHz / 3 - 66MHz / 4 - 80MHz / 5 - 100MHz / 6 - 120MHz / 7 - 133MHz / 8 - 166MHz
59 *
60 * option[2] (Effective only if the bit[3:0] in option[0] > 1)
61 * [31:20] Reserved
62 * [19:16] IO voltage
63 * 0 - 3V / 1 - 1.8V
64 * [15:12] Pin group
65 * 0 - 1st group / 1 - 2nd group
66 * [11:8] Connection selection
67 * 0 - CA_CS0 / 1 - CB_CS0 / 2 - CA_CS0 + CB_CS0 (Two FLASH connected to CA and CB respectively)
68 * [7:0] Drive Strength
69 * 0 - Default value
70 * option[3] (Effective only if the bit[3:0] in option[0] > 2, required only for the QSPI NOR FLASH that not supports
71 * JESD216)
72 * [31:16] reserved
73 * [15:12] Sector Erase Command Option, not required here
74 * [11:8] Sector Size Option, not required here
75 * [7:0] Flash Size Option
76 * 0 - 4MB / 1 - 8MB / 2 - 16MB
77 */
78 #if defined(FLASH_XIP) && FLASH_XIP
79 __attribute__((section(".nor_cfg_option"))) const uint32_t option[4] = { 0xfcf90001, 0x00000007, 0x0, 0x0 };
80 #endif
81
82 #if defined(FLASH_UF2) && FLASH_UF2
83 ATTR_PLACE_AT(".uf2_signature") const uint32_t uf2_signature = BOARD_UF2_SIGNATURE;
84 #endif
85
board_init_console(void)86 void board_init_console(void)
87 {
88 #if !defined(CONFIG_NDEBUG_CONSOLE) || !CONFIG_NDEBUG_CONSOLE
89 #if BOARD_CONSOLE_TYPE == CONSOLE_TYPE_UART
90 console_config_t cfg;
91
92 /* uart needs to configure pin function before enabling clock, otherwise the level change of
93 uart rx pin when configuring pin function will cause a wrong data to be received.
94 And a uart rx dma request will be generated by default uart fifo dma trigger level. */
95 init_uart_pins((UART_Type *) BOARD_CONSOLE_BASE);
96
97 /* Configure the UART clock to 24MHz */
98 clock_set_source_divider(BOARD_CONSOLE_CLK_NAME, clk_src_osc24m, 1U);
99 clock_add_to_group(BOARD_CONSOLE_CLK_NAME, 0);
100
101 cfg.type = BOARD_CONSOLE_TYPE;
102 cfg.base = (uint32_t)BOARD_CONSOLE_BASE;
103 cfg.src_freq_in_hz = clock_get_frequency(BOARD_CONSOLE_CLK_NAME);
104 cfg.baudrate = BOARD_CONSOLE_BAUDRATE;
105
106 if (status_success != console_init(&cfg)) {
107 /* failed to initialize debug console */
108 while (1) {
109 }
110 }
111 #else
112 while (1)
113 ;
114 #endif
115 #endif
116 }
117
board_print_clock_freq(void)118 void board_print_clock_freq(void)
119 {
120 printf("==============================\n");
121 printf(" %s clock summary\n", BOARD_NAME);
122 printf("==============================\n");
123 printf("cpu0:\t\t %luHz\n", clock_get_frequency(clock_cpu0));
124 printf("cpu1:\t\t %luHz\n", clock_get_frequency(clock_cpu1));
125 printf("axi:\t\t %luHz\n", clock_get_frequency(clock_axi));
126 printf("ahb:\t\t %luHz\n", clock_get_frequency(clock_ahb));
127 printf("mchtmr0:\t %luHz\n", clock_get_frequency(clock_mchtmr0));
128 printf("mchtmr1:\t %luHz\n", clock_get_frequency(clock_mchtmr1));
129 printf("xpi0:\t\t %luHz\n", clock_get_frequency(clock_xpi0));
130 printf("==============================\n");
131 }
132
board_init_uart(UART_Type * ptr)133 void board_init_uart(UART_Type *ptr)
134 {
135 /* configure uart's pin before opening uart's clock */
136 init_uart_pins(ptr);
137 board_init_uart_clock(ptr);
138 }
139
board_print_banner(void)140 void board_print_banner(void)
141 {
142 const uint8_t banner[] = { "\n\
143 ----------------------------------------------------------------------\n\
144 $$\\ $$\\ $$$$$$$\\ $$\\ $$\\ $$\\\n\
145 $$ | $$ |$$ __$$\\ $$$\\ $$$ |\\__|\n\
146 $$ | $$ |$$ | $$ |$$$$\\ $$$$ |$$\\ $$$$$$$\\ $$$$$$\\ $$$$$$\\\n\
147 $$$$$$$$ |$$$$$$$ |$$\\$$\\$$ $$ |$$ |$$ _____|$$ __$$\\ $$ __$$\\\n\
148 $$ __$$ |$$ ____/ $$ \\$$$ $$ |$$ |$$ / $$ | \\__|$$ / $$ |\n\
149 $$ | $$ |$$ | $$ |\\$ /$$ |$$ |$$ | $$ | $$ | $$ |\n\
150 $$ | $$ |$$ | $$ | \\_/ $$ |$$ |\\$$$$$$$\\ $$ | \\$$$$$$ |\n\
151 \\__| \\__|\\__| \\__| \\__|\\__| \\_______|\\__| \\______/\n\
152 ----------------------------------------------------------------------\n"};
153 #ifdef SDK_VERSION_STRING
154 printf("hpm_sdk: %s\n", SDK_VERSION_STRING);
155 #endif
156 printf("%s", banner);
157 }
158
board_get_led_pwm_off_level(void)159 uint8_t board_get_led_pwm_off_level(void)
160 {
161 return BOARD_LED_OFF_LEVEL;
162 }
163
board_get_led_gpio_off_level(void)164 uint8_t board_get_led_gpio_off_level(void)
165 {
166 return BOARD_LED_OFF_LEVEL;
167 }
168
board_ungate_mchtmr_at_lp_mode(void)169 void board_ungate_mchtmr_at_lp_mode(void)
170 {
171 /* Keep cpu clock on wfi, so that mchtmr irq can still work after wfi */
172 sysctl_set_cpu_lp_mode(HPM_SYSCTL, BOARD_RUNNING_CORE, cpu_lp_mode_ungate_cpu_clock);
173 }
174
board_init(void)175 void board_init(void)
176 {
177 board_init_clock();
178 board_init_console();
179 board_init_pmp();
180 #if BOARD_SHOW_CLOCK
181 board_print_clock_freq();
182 #endif
183 #if BOARD_SHOW_BANNER
184 board_print_banner();
185 #endif
186 }
187
board_delay_us(uint32_t us)188 void board_delay_us(uint32_t us)
189 {
190 clock_cpu_delay_us(us);
191 }
192
board_delay_ms(uint32_t ms)193 void board_delay_ms(uint32_t ms)
194 {
195 clock_cpu_delay_ms(ms);
196 }
197
board_timer_isr(void)198 void board_timer_isr(void)
199 {
200 if (gptmr_check_status(BOARD_CALLBACK_TIMER, GPTMR_CH_RLD_STAT_MASK(BOARD_CALLBACK_TIMER_CH))) {
201 gptmr_clear_status(BOARD_CALLBACK_TIMER, GPTMR_CH_RLD_STAT_MASK(BOARD_CALLBACK_TIMER_CH));
202 timer_cb();
203 }
204 }
205 SDK_DECLARE_EXT_ISR_M(BOARD_CALLBACK_TIMER_IRQ, board_timer_isr);
206
board_timer_create(uint32_t ms,board_timer_cb cb)207 void board_timer_create(uint32_t ms, board_timer_cb cb)
208 {
209 uint32_t gptmr_freq;
210 gptmr_channel_config_t config;
211
212 timer_cb = cb;
213 gptmr_channel_get_default_config(BOARD_CALLBACK_TIMER, &config);
214
215 clock_add_to_group(BOARD_CALLBACK_TIMER_CLK_NAME, 0);
216 gptmr_freq = clock_get_frequency(BOARD_CALLBACK_TIMER_CLK_NAME);
217
218 config.reload = gptmr_freq / 1000 * ms;
219 gptmr_channel_config(BOARD_CALLBACK_TIMER, BOARD_CALLBACK_TIMER_CH, &config, false);
220 gptmr_enable_irq(BOARD_CALLBACK_TIMER, GPTMR_CH_RLD_IRQ_MASK(BOARD_CALLBACK_TIMER_CH));
221 intc_m_enable_irq_with_priority(BOARD_CALLBACK_TIMER_IRQ, 1);
222
223 gptmr_start_counter(BOARD_CALLBACK_TIMER, BOARD_CALLBACK_TIMER_CH);
224 }
225
board_i2c_bus_clear(I2C_Type * ptr)226 void board_i2c_bus_clear(I2C_Type *ptr)
227 {
228 init_i2c_pins_as_gpio(ptr);
229 if (ptr == BOARD_APP_I2C_BASE) {
230 gpio_set_pin_input(BOARD_I2C_GPIO_CTRL, BOARD_I2C_SDA_GPIO_INDEX, BOARD_I2C_SDA_GPIO_PIN);
231 gpio_set_pin_input(BOARD_I2C_GPIO_CTRL, BOARD_I2C_SCL_GPIO_INDEX, BOARD_I2C_SCL_GPIO_PIN);
232 if (!gpio_read_pin(BOARD_I2C_GPIO_CTRL, BOARD_I2C_SCL_GPIO_INDEX, BOARD_I2C_SCL_GPIO_PIN)) {
233 printf("CLK is low, please power cycle the board\n");
234 while (1) {
235 }
236 }
237 if (!gpio_read_pin(BOARD_I2C_GPIO_CTRL, BOARD_I2C_SDA_GPIO_INDEX, BOARD_I2C_SDA_GPIO_PIN)) {
238 printf("SDA is low, try to issue I2C bus clear\n");
239 } else {
240 printf("I2C bus is ready\n");
241 return;
242 }
243
244 gpio_set_pin_output(BOARD_I2C_GPIO_CTRL, BOARD_I2C_SCL_GPIO_INDEX, BOARD_I2C_SCL_GPIO_PIN);
245 while (1) {
246 for (uint32_t i = 0; i < 9; i++) {
247 gpio_write_pin(BOARD_I2C_GPIO_CTRL, BOARD_I2C_SCL_GPIO_INDEX, BOARD_I2C_SCL_GPIO_PIN, 1);
248 board_delay_ms(10);
249 gpio_write_pin(BOARD_I2C_GPIO_CTRL, BOARD_I2C_SCL_GPIO_INDEX, BOARD_I2C_SCL_GPIO_PIN, 0);
250 board_delay_ms(10);
251 }
252 board_delay_ms(100);
253 }
254 printf("I2C bus is cleared\n");
255 }
256 }
257
board_init_i2c(I2C_Type * ptr)258 void board_init_i2c(I2C_Type *ptr)
259 {
260 i2c_config_t config;
261 hpm_stat_t stat;
262 uint32_t freq;
263 if (ptr == NULL) {
264 return;
265 }
266
267 board_i2c_bus_clear(ptr);
268 init_i2c_pins(ptr);
269 clock_add_to_group(clock_i2c0, 0);
270 clock_add_to_group(clock_i2c1, 0);
271 clock_add_to_group(clock_i2c2, 0);
272 clock_add_to_group(clock_i2c3, 0);
273 /* Configure the I2C clock to 24MHz */
274 clock_set_source_divider(BOARD_APP_I2C_CLK_NAME, clk_src_osc24m, 1U);
275
276 config.i2c_mode = i2c_mode_normal;
277 config.is_10bit_addressing = false;
278 freq = clock_get_frequency(BOARD_APP_I2C_CLK_NAME);
279 stat = i2c_init_master(ptr, freq, &config);
280 if (stat != status_success) {
281 printf("failed to initialize i2c 0x%lx\n", (uint32_t) ptr);
282 while (1) {
283 }
284 }
285 }
286
board_init_spi_clock(SPI_Type * ptr)287 uint32_t board_init_spi_clock(SPI_Type *ptr)
288 {
289 if (ptr == HPM_SPI1) {
290 /* SPI1 clock configure */
291 clock_add_to_group(clock_spi1, 0);
292 clock_set_source_divider(clock_spi1, clk_src_pll0_clk0, 5U); /* 80MHz */
293
294 return clock_get_frequency(clock_spi1);
295 } else if (ptr == HPM_SPI2) {
296 /* SPI2 clock configure */
297 clock_add_to_group(clock_spi2, 0);
298 clock_set_source_divider(clock_spi2, clk_src_pll0_clk0, 5U); /* 80MHz */
299
300 return clock_get_frequency(clock_spi2);
301 } else if (ptr == HPM_SPI3) {
302 /* SPI3 clock configure */
303 clock_add_to_group(clock_spi3, 0);
304 clock_set_source_divider(clock_spi3, clk_src_pll0_clk0, 5U); /* 80MHz */
305
306 return clock_get_frequency(clock_spi3);
307 }
308 return 0;
309 }
310
board_init_lin_pins(LIN_Type * ptr)311 void board_init_lin_pins(LIN_Type *ptr)
312 {
313 init_lin_pins(ptr);
314 }
315
board_init_lin_clock(LIN_Type * ptr)316 uint32_t board_init_lin_clock(LIN_Type *ptr)
317 {
318 if (ptr == HPM_LIN0) {
319 clock_add_to_group(clock_lin0, 0);
320 clock_set_source_divider(clock_lin0, clk_src_pll0_clk0, 20U); /* 20MHz */
321
322 return clock_get_frequency(clock_lin0);
323 }
324 return 0;
325 }
326
board_init_gpio_pins(void)327 void board_init_gpio_pins(void)
328 {
329 init_gpio_pins();
330 }
331
board_init_spi_pins(SPI_Type * ptr)332 void board_init_spi_pins(SPI_Type *ptr)
333 {
334 init_spi_pins(ptr);
335 }
336
board_init_spi_pins_with_gpio_as_cs(SPI_Type * ptr)337 void board_init_spi_pins_with_gpio_as_cs(SPI_Type *ptr)
338 {
339 init_spi_pins_with_gpio_as_cs(ptr);
340 gpio_set_pin_output_with_initial(BOARD_SPI_CS_GPIO_CTRL, GPIO_GET_PORT_INDEX(BOARD_SPI_CS_PIN),
341 GPIO_GET_PIN_INDEX(BOARD_SPI_CS_PIN), !BOARD_SPI_CS_ACTIVE_LEVEL);
342 }
343
board_write_spi_cs(uint32_t pin,uint8_t state)344 void board_write_spi_cs(uint32_t pin, uint8_t state)
345 {
346 gpio_write_pin(BOARD_SPI_CS_GPIO_CTRL, GPIO_GET_PORT_INDEX(pin), GPIO_GET_PIN_INDEX(pin), state);
347 }
348
board_init_led_pins(void)349 void board_init_led_pins(void)
350 {
351 init_led_pins_as_gpio();
352 gpio_set_pin_output_with_initial(BOARD_R_GPIO_CTRL, BOARD_R_GPIO_INDEX, BOARD_R_GPIO_PIN, board_get_led_gpio_off_level());
353 gpio_set_pin_output_with_initial(BOARD_G_GPIO_CTRL, BOARD_G_GPIO_INDEX, BOARD_G_GPIO_PIN, board_get_led_gpio_off_level());
354 gpio_set_pin_output_with_initial(BOARD_B_GPIO_CTRL, BOARD_B_GPIO_INDEX, BOARD_B_GPIO_PIN, board_get_led_gpio_off_level());
355 }
356
board_led_toggle(void)357 void board_led_toggle(void)
358 {
359 #ifdef BOARD_LED_TOGGLE_RGB
360 static uint8_t i;
361 switch (i) {
362 case 1:
363 gpio_write_pin(BOARD_R_GPIO_CTRL, BOARD_R_GPIO_INDEX, BOARD_R_GPIO_PIN, BOARD_LED_OFF_LEVEL);
364 gpio_write_pin(BOARD_G_GPIO_CTRL, BOARD_G_GPIO_INDEX, BOARD_G_GPIO_PIN, BOARD_LED_ON_LEVEL);
365 gpio_write_pin(BOARD_B_GPIO_CTRL, BOARD_B_GPIO_INDEX, BOARD_B_GPIO_PIN, BOARD_LED_OFF_LEVEL);
366 break;
367
368 case 2:
369 gpio_write_pin(BOARD_R_GPIO_CTRL, BOARD_R_GPIO_INDEX, BOARD_R_GPIO_PIN, BOARD_LED_OFF_LEVEL);
370 gpio_write_pin(BOARD_G_GPIO_CTRL, BOARD_G_GPIO_INDEX, BOARD_G_GPIO_PIN, BOARD_LED_OFF_LEVEL);
371 gpio_write_pin(BOARD_B_GPIO_CTRL, BOARD_B_GPIO_INDEX, BOARD_B_GPIO_PIN, BOARD_LED_ON_LEVEL);
372 break;
373
374 case 0:
375 default:
376 gpio_write_pin(BOARD_R_GPIO_CTRL, BOARD_R_GPIO_INDEX, BOARD_R_GPIO_PIN, BOARD_LED_ON_LEVEL);
377 gpio_write_pin(BOARD_G_GPIO_CTRL, BOARD_G_GPIO_INDEX, BOARD_G_GPIO_PIN, BOARD_LED_OFF_LEVEL);
378 gpio_write_pin(BOARD_B_GPIO_CTRL, BOARD_B_GPIO_INDEX, BOARD_B_GPIO_PIN, BOARD_LED_OFF_LEVEL);
379 break;
380 }
381 i++;
382 i = i % 3;
383 #else
384 gpio_toggle_pin(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN);
385 #endif
386 }
387
board_led_write(uint8_t state)388 void board_led_write(uint8_t state)
389 {
390 gpio_write_pin(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN, state);
391 }
392
board_init_usb_pins(void)393 void board_init_usb_pins(void)
394 {
395 /* set pull-up for USBx ID pin */
396 init_usb_pins();
397
398 /* configure USBx ID pin as input function */
399 gpio_set_pin_input(BOARD_USB0_ID_PORT, BOARD_USB0_ID_GPIO_INDEX, BOARD_USB0_ID_GPIO_PIN);
400 }
401
board_get_usb_id_status(void)402 uint8_t board_get_usb_id_status(void)
403 {
404 return gpio_read_pin(BOARD_USB0_ID_PORT, BOARD_USB0_ID_GPIO_INDEX, BOARD_USB0_ID_GPIO_PIN);
405 }
406
board_usb_vbus_ctrl(uint8_t usb_index,uint8_t level)407 void board_usb_vbus_ctrl(uint8_t usb_index, uint8_t level)
408 {
409 (void) usb_index;
410 (void) level;
411 }
412
board_init_pmp(void)413 void board_init_pmp(void)
414 {
415 uint32_t start_addr;
416 uint32_t end_addr;
417 uint32_t length;
418 pmp_entry_t pmp_entry[16];
419 uint8_t index = 0;
420
421 /* Init noncachable memory */
422 extern uint32_t __noncacheable_start__[];
423 extern uint32_t __noncacheable_end__[];
424 start_addr = (uint32_t)__noncacheable_start__;
425 end_addr = (uint32_t)__noncacheable_end__;
426 length = end_addr - start_addr;
427 if (length > 0) {
428 /* Ensure the address and the length are power of 2 aligned */
429 assert((length & (length - 1U)) == 0U);
430 assert((start_addr & (length - 1U)) == 0U);
431 pmp_entry[index].pmp_addr = PMP_NAPOT_ADDR(start_addr, length);
432 pmp_entry[index].pmp_cfg.val = PMP_CFG(READ_EN, WRITE_EN, EXECUTE_EN, ADDR_MATCH_NAPOT, REG_UNLOCK);
433 pmp_entry[index].pma_addr = PMA_NAPOT_ADDR(start_addr, length);
434 pmp_entry[index].pma_cfg.val = PMA_CFG(ADDR_MATCH_NAPOT, MEM_TYPE_MEM_NON_CACHE_BUF, AMO_EN);
435 index++;
436 }
437
438 /* Init share memory */
439 extern uint32_t __share_mem_start__[];
440 extern uint32_t __share_mem_end__[];
441 start_addr = (uint32_t)__share_mem_start__;
442 end_addr = (uint32_t)__share_mem_end__;
443 length = end_addr - start_addr;
444 if (length > 0) {
445 /* Ensure the address and the length are power of 2 aligned */
446 assert((length & (length - 1U)) == 0U);
447 assert((start_addr & (length - 1U)) == 0U);
448 pmp_entry[index].pmp_addr = PMP_NAPOT_ADDR(start_addr, length);
449 pmp_entry[index].pmp_cfg.val = PMP_CFG(READ_EN, WRITE_EN, EXECUTE_EN, ADDR_MATCH_NAPOT, REG_UNLOCK);
450 pmp_entry[index].pma_addr = PMA_NAPOT_ADDR(start_addr, length);
451 pmp_entry[index].pma_cfg.val = PMA_CFG(ADDR_MATCH_NAPOT, MEM_TYPE_MEM_NON_CACHE_BUF, AMO_EN);
452 index++;
453 }
454
455 pmp_config(&pmp_entry[0], index);
456 }
457
board_init_clock(void)458 void board_init_clock(void)
459 {
460 uint32_t cpu0_freq = clock_get_frequency(clock_cpu0);
461 if (cpu0_freq == PLLCTL_SOC_PLL_REFCLK_FREQ) {
462 /* Configure the External OSC ramp-up time: ~9ms */
463 pllctlv2_xtal_set_rampup_time(HPM_PLLCTLV2, 32UL * 1000UL * 9U);
464
465 /* Select clock setting preset1 */
466 sysctl_clock_set_preset(HPM_SYSCTL, 2);
467 }
468 /* Add most Clocks to group 0 */
469 /* not open uart clock in this API, uart should configure pin function before opening clock */
470 clock_add_to_group(clock_cpu0, 0);
471 clock_add_to_group(clock_ahbp, 0);
472 clock_add_to_group(clock_axic, 0);
473 clock_add_to_group(clock_axis, 0);
474
475 clock_add_to_group(clock_mchtmr0, 0);
476 clock_add_to_group(clock_xpi0, 0);
477 clock_add_to_group(clock_gptmr0, 0);
478 clock_add_to_group(clock_gptmr1, 0);
479 clock_add_to_group(clock_gptmr2, 0);
480 clock_add_to_group(clock_gptmr3, 0);
481 clock_add_to_group(clock_i2c0, 0);
482 clock_add_to_group(clock_i2c1, 0);
483 clock_add_to_group(clock_i2c2, 0);
484 clock_add_to_group(clock_i2c3, 0);
485 clock_add_to_group(clock_lin0, 0);
486 clock_add_to_group(clock_lin1, 0);
487 clock_add_to_group(clock_lin2, 0);
488 clock_add_to_group(clock_lin3, 0);
489 clock_add_to_group(clock_spi0, 0);
490 clock_add_to_group(clock_spi1, 0);
491 clock_add_to_group(clock_spi2, 0);
492 clock_add_to_group(clock_spi3, 0);
493 clock_add_to_group(clock_can0, 0);
494 clock_add_to_group(clock_can1, 0);
495 clock_add_to_group(clock_can2, 0);
496 clock_add_to_group(clock_can3, 0);
497 clock_add_to_group(clock_ptpc, 0);
498 clock_add_to_group(clock_ref0, 0);
499 clock_add_to_group(clock_ref1, 0);
500 clock_add_to_group(clock_watchdog0, 0);
501 clock_add_to_group(clock_sdp, 0);
502 clock_add_to_group(clock_xdma, 0);
503 clock_add_to_group(clock_ram0, 0);
504 clock_add_to_group(clock_usb0, 0);
505 clock_add_to_group(clock_kman, 0);
506 clock_add_to_group(clock_gpio, 0);
507 clock_add_to_group(clock_mbx0, 0);
508 clock_add_to_group(clock_hdma, 0);
509 clock_add_to_group(clock_rng, 0);
510 clock_add_to_group(clock_mot0, 0);
511 clock_add_to_group(clock_mot1, 0);
512 clock_add_to_group(clock_mot2, 0);
513 clock_add_to_group(clock_mot3, 0);
514 clock_add_to_group(clock_acmp, 0);
515 clock_add_to_group(clock_msyn, 0);
516 clock_add_to_group(clock_lmm0, 0);
517 clock_add_to_group(clock_lmm1, 0);
518
519 clock_add_to_group(clock_adc0, 0);
520 clock_add_to_group(clock_adc1, 0);
521 clock_add_to_group(clock_adc2, 0);
522
523 clock_add_to_group(clock_dac0, 0);
524 clock_add_to_group(clock_dac1, 0);
525
526 clock_add_to_group(clock_tsns, 0);
527 clock_add_to_group(clock_crc0, 0);
528 clock_add_to_group(clock_sdm0, 0);
529
530 /* Connect Group0 to CPU0 */
531 clock_connect_group_to_cpu(0, 0);
532
533 /* Add the CPU1 clock to Group1 */
534 clock_add_to_group(clock_mchtmr1, 1);
535
536 /* Connect Group1 to CPU1 */
537 clock_connect_group_to_cpu(1, 1);
538
539 /* Bump up DCDC voltage to 1275mv */
540 pcfg_dcdc_set_voltage(HPM_PCFG, 1275);
541
542 /* Connect CAN2/CAN3 to pll0clk0*/
543 clock_set_source_divider(clock_can2, clk_src_pll0_clk0, 1);
544 clock_set_source_divider(clock_can3, clk_src_pll0_clk0, 1);
545
546 /* Configure CPU to 600MHz, AXI/AHB to 200MHz */
547 sysctl_config_cpu0_domain_clock(HPM_SYSCTL, clock_source_pll1_clk0, 1, 3, 3);
548 /* Configure PLL1_CLK0 Post Divider to 1 */
549 pllctlv2_set_postdiv(HPM_PLLCTLV2, 1, 0, 0);
550 pllctlv2_init_pll_with_freq(HPM_PLLCTLV2, 1, 600000000);
551 clock_update_core_clock();
552
553 /* Configure mchtmr to 24MHz */
554 clock_set_source_divider(clock_mchtmr0, clk_src_osc24m, 1);
555 clock_set_source_divider(clock_mchtmr1, clk_src_osc24m, 1);
556 }
557
board_init_adc16_clock(ADC16_Type * ptr,bool clk_src_ahb)558 uint32_t board_init_adc16_clock(ADC16_Type *ptr, bool clk_src_ahb)
559 {
560 uint32_t freq = 0;
561
562 if (ptr == HPM_ADC0) {
563 if (clk_src_ahb) {
564 /* Configure the ADC clock from AHB (@200MHz by default)*/
565 clock_set_adc_source(clock_adc0, clk_adc_src_ahb0);
566 } else {
567 /* Configure the ADC clock from pll0_clk0 divided by 2 (@200MHz by default) */
568 clock_set_adc_source(clock_adc0, clk_adc_src_ana0);
569 clock_set_source_divider(clock_ana0, clk_src_pll0_clk0, 2U);
570 }
571
572 freq = clock_get_frequency(clock_adc0);
573 } else if (ptr == HPM_ADC1) {
574 if (clk_src_ahb) {
575 /* Configure the ADC clock from AHB (@200MHz by default)*/
576 clock_set_adc_source(clock_adc1, clk_adc_src_ahb0);
577 } else {
578 /* Configure the ADC clock from pll0_clk0 divided by 2 (@200MHz by default) */
579 clock_set_adc_source(clock_adc1, clk_adc_src_ana1);
580 clock_set_source_divider(clock_ana1, clk_src_pll0_clk0, 2U);
581 }
582
583 freq = clock_get_frequency(clock_adc1);
584 } else if (ptr == HPM_ADC2) {
585 if (clk_src_ahb) {
586 /* Configure the ADC clock from AHB (@200MHz by default)*/
587 clock_set_adc_source(clock_adc2, clk_adc_src_ahb0);
588 } else {
589 /* Configure the ADC clock from pll0_clk0 divided by 2 (@200MHz by default) */
590 clock_set_adc_source(clock_adc2, clk_adc_src_ana2);
591 clock_set_source_divider(clock_ana2, clk_src_pll0_clk0, 2U);
592 }
593
594 freq = clock_get_frequency(clock_adc2);
595 }
596
597 return freq;
598 }
599
board_init_dac_clock(DAC_Type * ptr,bool clk_src_ahb)600 uint32_t board_init_dac_clock(DAC_Type *ptr, bool clk_src_ahb)
601 {
602 uint32_t freq = 0;
603
604 if (ptr == HPM_DAC0) {
605 if (clk_src_ahb == true) {
606 /* Configure the DAC clock to 200MHz */
607 clock_set_dac_source(clock_dac0, clk_dac_src_ahb0);
608 } else {
609 /* Configure the DAC clock to 166MHz */
610 clock_set_dac_source(clock_dac0, clk_dac_src_ana3);
611 clock_set_source_divider(clock_ana3, clk_src_pll0_clk1, 2);
612 }
613
614 freq = clock_get_frequency(clock_dac0);
615 } else if (ptr == HPM_DAC1) {
616 if (clk_src_ahb == true) {
617 /* Configure the DAC clock to 200MHz */
618 clock_set_dac_source(clock_dac1, clk_dac_src_ahb0);
619 } else {
620 /* Configure the DAC clock to 166MHz */
621 clock_set_dac_source(clock_dac1, clk_dac_src_ana4);
622 clock_set_source_divider(clock_ana4, clk_src_pll0_clk1, 2);
623 }
624
625 freq = clock_get_frequency(clock_dac1);
626 }
627
628 return freq;
629 }
630
board_init_can(MCAN_Type * ptr)631 void board_init_can(MCAN_Type *ptr)
632 {
633 init_can_pins(ptr);
634 }
635
board_init_can_clock(MCAN_Type * ptr)636 uint32_t board_init_can_clock(MCAN_Type *ptr)
637 {
638 uint32_t freq = 0;
639 if (ptr == HPM_MCAN0) {
640 /* Set the CAN0 peripheral clock to 8MHz */
641 clock_set_source_divider(clock_can0, clk_src_pll0_clk0, 5);
642 freq = clock_get_frequency(clock_can0);
643 } else if (ptr == HPM_MCAN1) {
644 /* Set the CAN1 peripheral clock to 8MHz */
645 clock_set_source_divider(clock_can1, clk_src_pll0_clk0, 5);
646 freq = clock_get_frequency(clock_can1);
647 } else if (ptr == HPM_MCAN2) {
648 /* Set the CAN2 peripheral clock to 8MHz */
649 clock_set_source_divider(clock_can2, clk_src_pll0_clk0, 5);
650 freq = clock_get_frequency(clock_can2);
651 } else if (ptr == HPM_MCAN3) {
652 /* Set the CAN2 peripheral clock to 8MHz */
653 clock_set_source_divider(clock_can3, clk_src_pll0_clk0, 5);
654 freq = clock_get_frequency(clock_can3);
655 } else {
656 /* Invalid CAN instance */
657 }
658 return freq;
659 }
660
board_init_adc16_pins(void)661 void board_init_adc16_pins(void)
662 {
663 init_adc_pins();
664 }
665
board_init_rgb_pwm_pins(void)666 void board_init_rgb_pwm_pins(void)
667 {
668 init_led_pins_as_pwm();
669 }
670
board_disable_output_rgb_led(uint8_t color)671 void board_disable_output_rgb_led(uint8_t color)
672 {
673 switch (color) {
674 case BOARD_RGB_RED:
675 pwm_disable_output(BOARD_RED_PWM, BOARD_RED_PWM_OUT);
676 break;
677 case BOARD_RGB_GREEN:
678 pwm_disable_output(BOARD_GREEN_PWM, BOARD_GREEN_PWM_OUT);
679 break;
680 case BOARD_RGB_BLUE:
681 pwm_disable_output(BOARD_BLUE_PWM, BOARD_BLUE_PWM_OUT);
682 break;
683 default:
684 while (1) {
685 ;
686 }
687 }
688 }
689
board_enable_output_rgb_led(uint8_t color)690 void board_enable_output_rgb_led(uint8_t color)
691 {
692 switch (color) {
693 case BOARD_RGB_RED:
694 pwm_enable_output(BOARD_RED_PWM, BOARD_RED_PWM_OUT);
695 break;
696 case BOARD_RGB_GREEN:
697 pwm_enable_output(BOARD_GREEN_PWM, BOARD_GREEN_PWM_OUT);
698 break;
699 case BOARD_RGB_BLUE:
700 pwm_enable_output(BOARD_BLUE_PWM, BOARD_BLUE_PWM_OUT);
701 break;
702 default:
703 while (1) {
704 ;
705 }
706 }
707 }
board_init_dac_pins(DAC_Type * ptr)708 void board_init_dac_pins(DAC_Type *ptr)
709 {
710 init_dac_pins(ptr);
711 }
712
board_init_uart_clock(UART_Type * ptr)713 uint32_t board_init_uart_clock(UART_Type *ptr)
714 {
715 uint32_t freq = 0U;
716 if (ptr == HPM_UART0) {
717 clock_set_source_divider(clock_uart0, clk_src_osc24m, 1);
718 clock_add_to_group(clock_uart0, 0);
719 freq = clock_get_frequency(clock_uart0);
720 } else if (ptr == HPM_UART1) {
721 clock_set_source_divider(clock_uart1, clk_src_osc24m, 1);
722 clock_add_to_group(clock_uart1, 0);
723 freq = clock_get_frequency(clock_uart1);
724 } else if (ptr == HPM_UART2) {
725 clock_set_source_divider(clock_uart2, clk_src_osc24m, 1);
726 clock_add_to_group(clock_uart2, 0);
727 freq = clock_get_frequency(clock_uart2);
728 } else {
729 /* Not supported */
730 }
731 return freq;
732 }
733