1 /* 2 * Copyright (c) 2023 HPMicro 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 */ 7 8 #ifndef _HPM_BOARD_H 9 #define _HPM_BOARD_H 10 #include <stdio.h> 11 #include "hpm_common.h" 12 #include "hpm_clock_drv.h" 13 #include "hpm_soc.h" 14 #include "hpm_soc_feature.h" 15 #include "pinmux.h" 16 #if !defined(CONFIG_NDEBUG_CONSOLE) || !CONFIG_NDEBUG_CONSOLE 17 #include "hpm_debug_console.h" 18 #endif 19 20 #define BOARD_NAME "hpm6200evk" 21 #define BOARD_UF2_SIGNATURE (0x0A4D5048UL) 22 23 #define SEC_CORE_IMG_START CORE1_ILM_LOCAL_BASE 24 25 /* dma section */ 26 #define BOARD_APP_XDMA HPM_XDMA 27 #define BOARD_APP_HDMA HPM_HDMA 28 #define BOARD_APP_XDMA_IRQ IRQn_XDMA 29 #define BOARD_APP_HDMA_IRQ IRQn_HDMA 30 #define BOARD_APP_DMAMUX HPM_DMAMUX 31 32 /* uart section */ 33 #ifndef BOARD_RUNNING_CORE 34 #define BOARD_RUNNING_CORE HPM_CORE0 35 #endif 36 #ifndef BOARD_APP_UART_BASE 37 #define BOARD_APP_UART_BASE HPM_UART0 38 #define BOARD_APP_UART_IRQ IRQn_UART0 39 #else 40 #ifndef BOARD_APP_UART_IRQ 41 #warning no IRQ specified for application uart 42 #endif 43 #endif 44 45 #define BOARD_APP_UART_BAUDRATE (115200UL) 46 #define BOARD_APP_UART_CLK_NAME clock_uart0 47 #define BOARD_APP_UART_RX_DMA_REQ HPM_DMA_SRC_UART0_RX 48 #define BOARD_APP_UART_TX_DMA_REQ HPM_DMA_SRC_UART0_TX 49 50 #if !defined(CONFIG_NDEBUG_CONSOLE) || !CONFIG_NDEBUG_CONSOLE 51 #ifndef BOARD_CONSOLE_TYPE 52 #define BOARD_CONSOLE_TYPE CONSOLE_TYPE_UART 53 #endif 54 55 #if BOARD_CONSOLE_TYPE == CONSOLE_TYPE_UART 56 #ifndef BOARD_CONSOLE_BASE 57 #if BOARD_RUNNING_CORE == HPM_CORE0 58 #define BOARD_CONSOLE_BASE HPM_UART0 59 #define BOARD_CONSOLE_CLK_NAME clock_uart0 60 #else 61 #define BOARD_CONSOLE_BASE HPM_UART2 62 #define BOARD_CONSOLE_CLK_NAME clock_uart2 63 #endif 64 #endif 65 #define BOARD_CONSOLE_BAUDRATE (115200UL) 66 #endif 67 #endif 68 69 #define BOARD_FREEMASTER_UART_BASE HPM_UART0 70 #define BOARD_FREEMASTER_UART_IRQ IRQn_UART0 71 #define BOARD_FREEMASTER_UART_CLK_NAME clock_uart0 72 73 /* uart microros sample section */ 74 #define BOARD_MICROROS_UART_BASE HPM_UART2 75 #define BOARD_MICROROS_UART_IRQ IRQn_UART2 76 #define BOARD_MICROROS_UART_CLK_NAME clock_uart2 77 78 /* sdm section */ 79 #define BOARD_SDM HPM_SDM 80 #define BOARD_SDM_IRQ IRQn_SDFM 81 #define BOARD_SDM_CHANNEL 3 82 #define BOARD_SDM_TRGM HPM_TRGM3 83 #define BOARD_SDM_TRGM_GPTMR HPM_GPTMR3 84 #define BOARD_SDM_TRGM_GPTMR_CH 2 85 #define BOARD_SDM_TRGM_INPUT_SRC HPM_TRGM3_INPUT_SRC_GPTMR3_OUT2 86 #define BOARD_SDM_TRGM_OUTPUT_DST HPM_TRGM3_OUTPUT_SRC_SDFM_TRG15 87 88 /* lin section */ 89 #define BOARD_LIN HPM_LIN0 90 #define BOARD_LIN_CLK_NAME clock_lin0 91 #define BOARD_LIN_IRQ IRQn_LIN0 92 #define BOARD_LIN_BAUDRATE (19200U) 93 94 /* nor flash section */ 95 #define BOARD_FLASH_BASE_ADDRESS (0x80000000UL) 96 #define BOARD_FLASH_SIZE (16 * SIZE_1MB) 97 98 /* i2c section */ 99 #define BOARD_APP_I2C_BASE HPM_I2C0 100 #define BOARD_APP_I2C_IRQ IRQn_I2C0 101 #define BOARD_APP_I2C_CLK_NAME clock_i2c0 102 #define BOARD_APP_I2C_DMA HPM_HDMA 103 #define BOARD_APP_I2C_DMAMUX HPM_DMAMUX 104 #define BOARD_APP_I2C_DMA_SRC HPM_DMA_SRC_I2C0 105 #define BOARD_APP_I2C_DMAMUX_CH DMAMUX_MUXCFG_HDMA_MUX0 106 #define BOARD_I2C_GPIO_CTRL HPM_GPIO0 107 #define BOARD_I2C_SCL_GPIO_INDEX GPIO_DO_GPIOB 108 #define BOARD_I2C_SCL_GPIO_PIN 22 109 #define BOARD_I2C_SDA_GPIO_INDEX GPIO_DO_GPIOB 110 #define BOARD_I2C_SDA_GPIO_PIN 23 111 112 /* ACMP desction */ 113 #define BOARD_ACMP HPM_ACMP 114 #define BOARD_ACMP_CHANNEL ACMP_CHANNEL_CHN1 115 #define BOARD_ACMP_IRQ IRQn_ACMP_1 116 #define BOARD_ACMP_PLUS_INPUT ACMP_INPUT_DAC_OUT /* use internal DAC */ 117 #define BOARD_ACMP_MINUS_INPUT ACMP_INPUT_ANALOG_5 /* align with used pin */ 118 119 /* dma section */ 120 #define BOARD_APP_XDMA HPM_XDMA 121 #define BOARD_APP_HDMA HPM_HDMA 122 #define BOARD_APP_XDMA_IRQ IRQn_XDMA 123 #define BOARD_APP_HDMA_IRQ IRQn_HDMA 124 #define BOARD_APP_DMAMUX HPM_DMAMUX 125 126 /* gptmr section */ 127 #define BOARD_GPTMR HPM_GPTMR2 128 #define BOARD_GPTMR_IRQ IRQn_GPTMR2 129 #define BOARD_GPTMR_CHANNEL 0 130 #define BOARD_GPTMR_DMA_SRC HPM_DMA_SRC_GPTMR2_0 131 #define BOARD_GPTMR_CLK_NAME clock_gptmr2 132 #define BOARD_GPTMR_PWM HPM_GPTMR2 133 #define BOARD_GPTMR_PWM_CHANNEL 0 134 #define BOARD_GPTMR_PWM_DMA_SRC HPM_DMA_SRC_GPTMR2_0 135 #define BOARD_GPTMR_PWM_CLK_NAME clock_gptmr2 136 #define BOARD_GPTMR_PWM_IRQ IRQn_GPTMR2 137 #define BOARD_GPTMR_PWM_SYNC HPM_GPTMR2 138 #define BOARD_GPTMR_PWM_SYNC_CHANNEL 1 139 #define BOARD_GPTMR_PWM_SYNC_CLK_NAME clock_gptmr2 140 141 /* pinmux section */ 142 #define USING_GPIO0_FOR_GPIOZ 143 #ifndef USING_GPIO0_FOR_GPIOZ 144 #define BOARD_APP_GPIO_CTRL HPM_BGPIO 145 #define BOARD_APP_GPIO_IRQ IRQn_BGPIO 146 #else 147 #define BOARD_APP_GPIO_CTRL HPM_GPIO0 148 #define BOARD_APP_GPIO_IRQ IRQn_GPIO0_Z 149 #endif 150 151 /* gpiom section */ 152 #define BOARD_APP_GPIOM_BASE HPM_GPIOM 153 #define BOARD_APP_GPIOM_USING_CTRL HPM_FGPIO 154 #define BOARD_APP_GPIOM_USING_CTRL_NAME gpiom_core0_fast 155 156 /* spi section */ 157 #define BOARD_APP_SPI_BASE HPM_SPI1 158 #define BOARD_APP_SPI_CLK_NAME clock_spi1 159 #define BOARD_APP_SPI_IRQ IRQn_SPI1 160 #define BOARD_APP_SPI_SCLK_FREQ (20000000UL) 161 #define BOARD_APP_SPI_ADDR_LEN_IN_BYTES (1U) 162 #define BOARD_APP_SPI_DATA_LEN_IN_BITS (8U) 163 #define BOARD_APP_SPI_RX_DMA HPM_DMA_SRC_SPI1_RX 164 #define BOARD_APP_SPI_TX_DMA HPM_DMA_SRC_SPI1_TX 165 #define BOARD_SPI_CS_GPIO_CTRL HPM_GPIO0 166 #define BOARD_SPI_CS_PIN IOC_PAD_PB02 167 #define BOARD_SPI_CS_ACTIVE_LEVEL (0U) 168 169 /* mtimer section */ 170 #define BOARD_MCHTMR_FREQ_IN_HZ (1000000UL) 171 172 /* Flash section */ 173 #define BOARD_APP_XPI_NOR_XPI_BASE (HPM_XPI0) 174 #define BOARD_APP_XPI_NOR_CFG_OPT_HDR (0xfcf90001U) 175 #define BOARD_APP_XPI_NOR_CFG_OPT_OPT0 (0x00000005U) 176 #define BOARD_APP_XPI_NOR_CFG_OPT_OPT1 (0x00001000U) 177 178 /* ADC section */ 179 #define BOARD_APP_ADC16_NAME "ADC0" 180 #define BOARD_APP_ADC16_BASE HPM_ADC0 181 #define BOARD_APP_ADC16_IRQn IRQn_ADC0 182 #define BOARD_APP_ADC16_CH_1 (1U) 183 #define BOARD_APP_ADC16_CLK_NAME (clock_adc0) 184 185 #define BOARD_APP_ADC16_HW_TRIG_SRC HPM_PWM0 186 #define BOARD_APP_ADC16_HW_TRGM HPM_TRGM0 187 #define BOARD_APP_ADC16_HW_TRGM_IN HPM_TRGM0_INPUT_SRC_PWM0_CH8REF 188 #define BOARD_APP_ADC16_HW_TRGM_OUT_SEQ TRGM_TRGOCFG_ADC0_STRGI 189 #define BOARD_APP_ADC16_HW_TRGM_OUT_PMT TRGM_TRGOCFG_ADCX_PTRGI0A 190 191 #define BOARD_APP_ADC16_PMT_TRIG_CH ADC16_CONFIG_TRG0A 192 193 /* DAC section */ 194 #define BOARD_DAC_BASE HPM_DAC0 195 #define BOARD_DAC_IRQn IRQn_DAC0 196 #define BOARD_APP_DAC_CLOCK_NAME clock_dac0 197 198 /* CAN section */ 199 #define BOARD_APP_CAN_BASE HPM_MCAN0 200 #define BOARD_APP_CAN_IRQn IRQn_CAN0 201 202 /* 203 * timer for board delay 204 */ 205 #define BOARD_DELAY_TIMER (HPM_GPTMR3) 206 #define BOARD_DELAY_TIMER_CH 0 207 #define BOARD_DELAY_TIMER_CLK_NAME (clock_gptmr3) 208 209 #define BOARD_CALLBACK_TIMER (HPM_GPTMR3) 210 #define BOARD_CALLBACK_TIMER_CH 1 211 #define BOARD_CALLBACK_TIMER_IRQ IRQn_GPTMR3 212 #define BOARD_CALLBACK_TIMER_CLK_NAME (clock_gptmr3) 213 214 /* USB section */ 215 #define BOARD_USB0_ID_PORT (HPM_GPIO0) 216 #define BOARD_USB0_ID_GPIO_INDEX (GPIO_DO_GPIOC) 217 #define BOARD_USB0_ID_GPIO_PIN (23) 218 219 /*BLDC pwm*/ 220 221 /*PWM define*/ 222 #define BOARD_BLDCPWM HPM_PWM0 223 #define BOARD_BLDC_UH_PWM_OUTPIN (0U) 224 #define BOARD_BLDC_UL_PWM_OUTPIN (1U) 225 #define BOARD_BLDC_VH_PWM_OUTPIN (2U) 226 #define BOARD_BLDC_VL_PWM_OUTPIN (3U) 227 #define BOARD_BLDC_WH_PWM_OUTPIN (4U) 228 #define BOARD_BLDC_WL_PWM_OUTPIN (5U) 229 #define BOARD_BLDCPWM_TRGM HPM_TRGM0 230 #define BOARD_BLDCAPP_PWM_IRQ IRQn_PWM0 231 #define BOARD_BLDCPWM_CMP_INDEX_0 (0U) 232 #define BOARD_BLDCPWM_CMP_INDEX_1 (1U) 233 #define BOARD_BLDCPWM_CMP_INDEX_2 (2U) 234 #define BOARD_BLDCPWM_CMP_INDEX_3 (3U) 235 #define BOARD_BLDCPWM_CMP_INDEX_4 (4U) 236 #define BOARD_BLDCPWM_CMP_INDEX_5 (5U) 237 #define BOARD_BLDCPWM_CMP_INDEX_6 (6U) 238 #define BOARD_BLDCPWM_CMP_INDEX_7 (7U) 239 #define BOARD_BLDCPWM_CMP_TRIG_CMP (15U) 240 241 /*HALL define*/ 242 243 #define BOARD_BLDC_HALL_BASE HPM_HALL0 244 #define BOARD_BLDC_HALL_TRGM HPM_TRGM0 245 #define BOARD_BLDC_HALL_IRQ IRQn_HALL0 246 #define BOARD_BLDC_HALL_TRGM_HALL_U_SRC HPM_TRGM0_INPUT_SRC_TRGM0_P8 247 #define BOARD_BLDC_HALL_TRGM_HALL_V_SRC HPM_TRGM0_INPUT_SRC_TRGM0_P7 248 #define BOARD_BLDC_HALL_TRGM_HALL_W_SRC HPM_TRGM0_INPUT_SRC_TRGM0_P6 249 #define BOARD_BLDC_HALL_MOTOR_PHASE_COUNT_PER_REV (1000U) 250 251 252 253 /*QEI*/ 254 255 #define BOARD_BLDC_QEI_BASE HPM_QEI0 256 #define BOARD_BLDC_QEI_IRQ IRQn_QEI0 257 #define BOARD_BLDC_QEI_TRGM HPM_TRGM0 258 #define BOARD_BLDC_QEI_TRGM_QEI_A_SRC HPM_TRGM0_INPUT_SRC_TRGM0_P6 259 #define BOARD_BLDC_QEI_TRGM_QEI_B_SRC HPM_TRGM0_INPUT_SRC_TRGM0_P7 260 #define BOARD_BLDC_QEI_MOTOR_PHASE_COUNT_PER_REV (16U) 261 #define BOARD_BLDC_QEI_CLOCK_SOURCE clock_mot0 262 #define BOARD_BLDC_QEI_FOC_PHASE_COUNT_PER_REV (4000U) 263 264 /*Timer define*/ 265 266 #define BOARD_BLDC_TMR_1MS HPM_GPTMR2 267 #define BOARD_BLDC_TMR_CH 0 268 #define BOARD_BLDC_TMR_CMP 0 269 #define BOARD_BLDC_TMR_IRQ IRQn_GPTMR2 270 #define BOARD_BLDC_TMR_RELOAD (100000U) 271 272 /*adc*/ 273 #define BOARD_BLDC_ADC_MODULE ADCX_MODULE_ADC16 274 #define BOARD_BLDC_ADC_U_BASE HPM_ADC0 275 #define BOARD_BLDC_ADC_V_BASE HPM_ADC1 276 #define BOARD_BLDC_ADC_W_BASE HPM_ADC2 277 #define BOARD_BLDC_ADC_TRIG_FLAG adc16_event_trig_complete 278 279 #define BOARD_BLDC_ADC_CH_U (11U) 280 #define BOARD_BLDC_ADC_CH_V (9U) 281 #define BOARD_BLDC_ADC_CH_W (4U) 282 #define BOARD_BLDC_ADC_IRQn IRQn_ADC0 283 #define BOARD_BLDC_ADC_PMT_DMA_SIZE_IN_4BYTES (ADC_SOC_PMT_MAX_DMA_BUFF_LEN_IN_4BYTES) 284 #define BOARD_BLDC_ADC_TRG ADC16_CONFIG_TRG0A 285 #define BOARD_BLDC_ADC_PREEMPT_TRIG_LEN (1U) 286 #define BOARD_BLDC_PWM_TRIG_CMP_INDEX (8U) 287 #define BOARD_BLDC_TRIGMUX_IN_NUM HPM_TRGM0_INPUT_SRC_PWM0_CH8REF 288 #define BOARD_BLDC_TRG_NUM TRGM_TRGOCFG_ADCX_PTRGI0A 289 290 /*PLA*/ 291 #define BOARD_PLA_COUNTER HPM_PLA0 292 #define BOARD_PLA_PWM_BASE HPM_PWM0 293 #define BOARD_PLA_PWM_CLOCK_NAME clock_mot0 294 #define BOARD_PLA_TRGM HPM_TRGM0 295 #define BOARD_PLA_PWM_TRG (HPM_TRGM0_INPUT_SRC_PWM0_CH8REF) 296 #define BOARD_PLA_IN_TRG_NUM (TRGM_TRGOCFG_PLA_IN0) 297 #define BOARD_PLA_OUT_TRG (HPM_TRGM0_INPUT_SRC_PLA0_OUT0) 298 #define BOARD_PLA_IO_TRG_NUM (TRGM_TRGOCFG_TRGM_OUT5) 299 #define BOARD_PLA_PWM_CMP (8U) 300 #define BOARD_PLA_PWM_CHN (8U) 301 302 /* APP PWM */ 303 #define BOARD_APP_PWM HPM_PWM0 304 #define BOARD_APP_PWM_CLOCK_NAME clock_mot0 305 #define BOARD_APP_PWM_OUT1 0 306 #define BOARD_APP_PWM_OUT2 1 307 #define BOARD_APP_TRGM HPM_TRGM0 308 #define BOARD_APP_PWM_IRQ IRQn_PWM0 309 #define BOARD_APP_TRGM_PWM_OUTPUT TRGM_TRGOCFG_PWM_SYNCI 310 311 /* APP HRPWM */ 312 #define BOARD_APP_HRPWM HPM_PWM1 313 #define BOARD_APP_HRPWM_CLOCK_NAME clock_mot1 314 #define BOARD_APP_HRPWM_OUT1 0 315 #define BOARD_APP_HRPWM_OUT2 2 316 #define BOARD_APP_HRPWM_TRGM HPM_TRGM1 317 318 #define BOARD_CPU_FREQ (480000000UL) 319 320 /* LED */ 321 #define BOARD_R_GPIO_CTRL HPM_GPIO0 322 #define BOARD_R_GPIO_INDEX GPIO_DI_GPIOA 323 #define BOARD_R_GPIO_PIN 27 324 #define BOARD_G_GPIO_CTRL HPM_GPIO0 325 #define BOARD_G_GPIO_INDEX GPIO_DI_GPIOB 326 #define BOARD_G_GPIO_PIN 1 327 #define BOARD_B_GPIO_CTRL HPM_GPIO0 328 #define BOARD_B_GPIO_INDEX GPIO_DI_GPIOB 329 #define BOARD_B_GPIO_PIN 19 330 331 #define BOARD_LED_GPIO_CTRL BOARD_G_GPIO_CTRL 332 #define BOARD_LED_GPIO_INDEX BOARD_G_GPIO_INDEX 333 #define BOARD_LED_GPIO_PIN BOARD_G_GPIO_PIN 334 335 #define BOARD_LED_OFF_LEVEL 0 336 #define BOARD_LED_ON_LEVEL !BOARD_LED_OFF_LEVEL 337 #define BOARD_LED_TOGGLE_RGB 1 338 339 /* Key Section */ 340 #define BOARD_APP_GPIO_INDEX GPIO_DI_GPIOZ 341 #define BOARD_APP_GPIO_PIN 2 342 343 /* RGB LED Section */ 344 #define BOARD_RED_PWM_IRQ IRQn_PWM3 345 #define BOARD_RED_PWM HPM_PWM3 346 #define BOARD_RED_PWM_OUT 7 347 #define BOARD_RED_PWM_CMP 8 348 #define BOARD_RED_PWM_CMP_INITIAL_ZERO true 349 #define BOARD_RED_PWM_CLOCK_NAME clock_mot3 350 351 #define BOARD_GREEN_PWM_IRQ IRQn_PWM1 352 #define BOARD_GREEN_PWM HPM_PWM1 353 #define BOARD_GREEN_PWM_OUT 1 354 #define BOARD_GREEN_PWM_CMP 8 355 #define BOARD_GREEN_PWM_CMP_INITIAL_ZERO true 356 #define BOARD_GREEN_PWM_CLOCK_NAME clock_mot1 357 358 #define BOARD_BLUE_PWM_IRQ IRQn_PWM0 359 #define BOARD_BLUE_PWM HPM_PWM0 360 #define BOARD_BLUE_PWM_OUT 7 361 #define BOARD_BLUE_PWM_CMP 8 362 #define BOARD_BLUE_PWM_CMP_INITIAL_ZERO true 363 #define BOARD_BLUE_PWM_CLOCK_NAME clock_mot0 364 365 #define BOARD_RGB_RED 0 366 #define BOARD_RGB_GREEN (BOARD_RGB_RED + 1) 367 #define BOARD_RGB_BLUE (BOARD_RGB_RED + 2) 368 369 /* PLA TAMAGAWA*/ 370 371 #define PLA_TMGW_SPI HPM_SPI2 372 #define PLA_TMGW_SPI_DMA BOARD_APP_HDMA 373 #define PLA_TMGW_SPI_DMAMUX BOARD_APP_DMAMUX 374 #define PLA_TMGW_SPI_RX_DMA_REQ HPM_DMA_SRC_SPI2_RX 375 #define PLA_TMGW_SPI_TX_DMA_REQ HPM_DMA_SRC_SPI2_TX 376 #define PLA_TMGW_SPI_RX_DMA_CH 0 377 #define PLA_TMGW_SPI_TX_DMA_CH 1 378 #define PLA_TMGW_SPI_RX_DMAMUX_CH DMA_SOC_CHN_TO_DMAMUX_CHN(PLA_TMGW_SPI_DMA, PLA_TMGW_SPI_RX_DMA_CH) 379 #define PLA_TMGW_SPI_TX_DMAMUX_CH DMA_SOC_CHN_TO_DMAMUX_CHN(PLA_TMGW_SPI_DMA, PLA_TMGW_SPI_TX_DMA_CH) 380 381 #define PLA_TMGW_SPI_CS_GPIO_CTRL HPM_GPIO0 382 #define PLA_TMGW_SPI_CS_GPIO_INDEX GPIO_DI_GPIOB 383 #define PLA_TMGW_SPI_CS_GPIO_PIN 30 384 385 #define PLA_TMGW_DATA_DIR_GPIO_CTRL HPM_GPIO0 386 #define PLA_TMGW_DATA_DIR_GPIO_INDEX GPIO_DI_GPIOB 387 #define PLA_TMGW_DATA_DIR_GPIO_PIN 21 388 389 #define PLA_TMGW_POWER_GPIO_CTRL HPM_GPIO0 390 #define PLA_TMGW_POWER_GPIO_INDEX GPIO_DI_GPIOB 391 #define PLA_TMGW_POWER_GPIO_PIN 31 392 393 #define PLA_TMGW_SPI_485_DIR_TRG (HPM_TRGM0_INPUT_SRC_PLA0_OUT1) 394 #define PLA_TMGW_SPI_485_DIR_TRGNUM (TRGM_TRGOCFG_TRGM_OUT1) 395 #define PLA_TMGW_SPI_MOSI_DATA_TRG (HPM_TRGM0_INPUT_SRC_TRGM0_P3) 396 #define PLA_TMGW_SPI_MOSI_DATA_TRGNUM (TRGM_TRGOCFG_PLA_IN3) 397 398 #define PLA_TMGW_SPI_CS_TRG (TEST_MOTOR_PWM_TRG_PLA_TRG) 399 #define PLA_TMGW_SPI_CS_TRGNUM (TRGM_TRGOCFG_TRGM_OUT0) 400 401 #define PLA_TMGW_COUNTER HPM_PLA0 402 #define PLA_TMGW_PWM_BASE HPM_PWM3 403 #define PLA_TMGW_PWM_CLOCK_NAME clock_mot3 404 #define PLA_TMGW_TRGM_CLK_IN_TRG (HPM_TRGM0_INPUT_SRC_TRGM3_OUTX0) 405 #define PLA_TMGW_TRGM_CLK_To_PLA_TRGNUM (TRGM_TRGOCFG_PLA_IN0) 406 #define PLA_TMGW_TRGM (HPM_TRGM0) 407 #define PLA_TMGW_CLK_TRGM (HPM_TRGM3) 408 #define PLA_TMGW_CLK_PWM_TRG (HPM_TRGM3_INPUT_SRC_PWM3_CH15REF) 409 #define PLA_TMGW_CLK_TRG_NUM (TRGM_TRGOCFG_TRGM_OUTX0) 410 #define PLA_TMGW_OUT_TRG (HPM_TRGM0_INPUT_SRC_PLA0_OUT0) 411 #define PLA_TMGW_IO_TRG_NUM (TRGM_TRGOCFG_TRGM_OUT5) 412 #define PLA_TMGW_PWM_CMP (15U) 413 #define PLA_TMGW_PWM_CHN (15U) 414 #define PLA_TMGW_PWM_SYNCI_TRG (HPM_TRGM0_INPUT_SRC_PLA0_OUT2) 415 #define PLA_TMGW_PWM_SYNCI_TRGNUM (TRGM_TRGOCFG_TRGM_OUTX0) 416 #define PLA_TMGW_PWM_SYNCI_IN_TRG (HPM_TRGM3_INPUT_SRC_TRGM0_OUTX0) 417 #define PLA_TMGW_PWM_SYNCI_IN_TRGNUM (TRGM_TRGOCFG_PWM_SYNCI) 418 419 #define PLA_TMGW_HALL_TIME_TRG (HPM_TRGM0_INPUT_SRC_PLA0_OUT2) 420 421 #define PLA_TMGW_IN_MOTOR_TRG_NUM (TRGM_TRGOCFG_PLA_IN2) 422 423 #define PLA_TMGW_QEI_BASE HPM_QEI0 424 #define PLA_TMGW_QEI_TRGM HPM_TRGM0 425 #define PLA_TMGW_QEI_TRGM_QEI_A_SRC HPM_TRGM0_INPUT_SRC_PLA0_OUT0 426 #define PLA_TMGW_QEI_IRQ IRQn_QEI0 427 #define PLA_TMGW_QEI_MOTOR_PHASE_COUNT_MAX (0xffffff) 428 429 #define PLA_TMGW_QEI_TRGM_QEI_TRG0 HPM_TRGM0_INPUT_SRC_QEI0_TRGO 430 #define PLA_TMGW_QEI_TRGM_QEI_PLA_IN TRGM_TRGOCFG_PLA_IN1 431 432 #define PLA_TMGW_QEI_DMA BOARD_APP_HDMA 433 #define PLA_TMGW_QEI_DMAMUX BOARD_APP_DMAMUX 434 #define PLA_TMGW_QEI_DMAREQ HPM_DMA_SRC_MOT0_0 435 #define PLA_TMGW_QEI_DMACH (2UL) 436 #define PLA_TMGW_QEI_DMAMUX_CH DMA_SOC_CHN_TO_DMAMUX_CHN(PLA_TMGW_QEI_DMA, PLA_TMGW_QEI_DMACH) 437 438 #define PLA_TMGW_HALL_BASE HPM_HALL0 439 #define PLA_TMGW_HALL_TRGM HPM_TRGM0 440 #define PLA_TMGW_HALL_DMA BOARD_APP_HDMA 441 #define PLA_TMGW_HALL_DMAMUX BOARD_APP_DMAMUX 442 #define PLA_TMGW_HALL_DMA_CH (3U) 443 #define PLA_TMGW_HALL_DMAMUX_CH DMA_SOC_CHN_TO_DMAMUX_CHN(PLA_TMGW_HALL_DMA, PLA_TMGW_HALL_DMA_CH) 444 #define PLA_TMGW_HALL_TRAN_SIZE (4U) /* four world */ 445 #define PLA_TMGW_HALL_DMA_REQ HPM_DMA_SRC_MOT0_1 446 447 #define PLA_TMGW_DMA_LINK_NUM (25U) 448 #define PLA_TMGW_DMA_LINK_TRGM HPM_TRGM0 449 #define PLA_TMGW_DMA_LINK_DMA BOARD_APP_HDMA 450 #define PLA_TMGW_DMA_LINK_DMAMUX BOARD_APP_DMAMUX 451 #define PLA_TMGW_DMA_LINK_DMA_CH (4U) 452 #define PLA_TMGW_DMA_LINK_DMAMUX_CH DMA_SOC_CHN_TO_DMAMUX_CHN(PLA_TMGW_DMA_LINK_DMA, PLA_TMGW_DMA_LINK_DMA_CH) 453 #define PLA_TMGW_DMA_LINK_TRAN_SIZE (4U) 454 #define PLA_TMGW_DMA_LINK_DMA_REQ HPM_DMA_SRC_MOT0_2 455 #define PLA_TMGW_DMA_LINK_TRGM_INPUT HPM_TRGM0_INPUT_SRC_PLA0_OUT6 456 457 /** 458 * @brief Get adc phase current 459 * 460 */ 461 #define BOARD_BLDC_ADC_PHASE_CH_U (3U) 462 #define BOARD_BLDC_ADC_PHASE_CH_V (4U) 463 #define BOARD_BLDC_ADC_PHASE_CH_W (2U) 464 #define BOARD_BLDC_ADC_PHASE_U_BASE HPM_ADC0 465 #define BOARD_BLDC_ADC_PHASE_V_BASE HPM_ADC0 466 #define BOARD_BLDC_ADC_PHASE_W_BASE HPM_ADC0 467 #define BOARD_BLDC_ADC_PHASE_TRG ADC16_CONFIG_TRG0A 468 #define BOARD_BLDC_ADC_PHASE_PREEMPT_TRIG_LEN (3) 469 #define BOARD_BLDC_ADC_PHASE_IRQn IRQn_ADC0 470 #define BOARD_BLDC_ADC_PHASE_TRIG_FLAG adc16_event_trig_complete 471 472 #ifndef BOARD_SHOW_CLOCK 473 #define BOARD_SHOW_CLOCK 1 474 #endif 475 #ifndef BOARD_SHOW_BANNER 476 #define BOARD_SHOW_BANNER 1 477 #endif 478 479 /* FreeRTOS Definitions */ 480 #define BOARD_FREERTOS_TIMER HPM_GPTMR1 481 #define BOARD_FREERTOS_TIMER_CHANNEL 1 482 #define BOARD_FREERTOS_TIMER_IRQ IRQn_GPTMR1 483 #define BOARD_FREERTOS_TIMER_CLK_NAME clock_gptmr1 484 485 #if defined(__cplusplus) 486 extern "C" { 487 #endif /* __cplusplus */ 488 489 typedef void (*board_timer_cb)(void); 490 491 void board_init(void); 492 void board_init_console(void); 493 494 void board_init_uart(UART_Type *ptr); 495 void board_init_i2c(I2C_Type *ptr); 496 497 void board_init_can(MCAN_Type *ptr); 498 499 void board_init_gpio_pins(void); 500 void board_init_spi_pins(SPI_Type *ptr); 501 void board_init_spi_pins_with_gpio_as_cs(SPI_Type *ptr); 502 void board_write_spi_cs(uint32_t pin, uint8_t state); 503 uint8_t board_get_led_gpio_off_level(void); 504 uint8_t board_get_led_pwm_off_level(void); 505 void board_init_led_pins(void); 506 void board_disable_output_rgb_led(uint8_t color); 507 void board_enable_output_rgb_led(uint8_t color); 508 void board_init_rgb_pwm_pins(void); 509 510 void board_led_write(uint8_t state); 511 void board_led_toggle(void); 512 513 /* Initialize SoC overall clocks */ 514 void board_init_clock(void); 515 516 uint32_t board_init_spi_clock(SPI_Type *ptr); 517 518 void board_init_lin_pins(LIN_Type *ptr); 519 uint32_t board_init_lin_clock(LIN_Type *ptr); 520 521 uint32_t board_init_adc16_clock(ADC16_Type *ptr, bool clk_src_ahb); 522 523 uint32_t board_init_dac_clock(DAC_Type *ptr, bool clk_src_ahb); 524 525 void board_init_adc16_pins(void); 526 527 void board_init_dac_pins(DAC_Type *ptr); 528 529 uint32_t board_init_can_clock(MCAN_Type *ptr); 530 531 void board_init_usb_pins(void); 532 void board_usb_vbus_ctrl(uint8_t usb_index, uint8_t level); 533 uint8_t board_get_usb_id_status(void); 534 535 536 /* 537 * @brief Initialize PMP and PMA for but not limited to the following purposes: 538 * -- non-cacheable memory initialization 539 */ 540 void board_init_pmp(void); 541 542 void board_delay_us(uint32_t us); 543 void board_delay_ms(uint32_t ms); 544 545 void board_timer_create(uint32_t ms, board_timer_cb cb); 546 void board_ungate_mchtmr_at_lp_mode(void); 547 548 /* Initialize the UART clock */ 549 uint32_t board_init_uart_clock(UART_Type *ptr); 550 551 #if defined(__cplusplus) 552 } 553 #endif /* __cplusplus */ 554 #endif /* _HPM_BOARD_H */ 555