1 /*
2 * Copyright (c) 2022-2023 HPMicro
3 * SPDX-License-Identifier: BSD-3-Clause
4 *
5 */
6
7 #include "board.h"
8 #include "hpm_uart_drv.h"
9 #include "hpm_gptmr_drv.h"
10 #include "hpm_lcdc_drv.h"
11 #include "hpm_i2c_drv.h"
12 #include "hpm_gpio_drv.h"
13 #include "hpm_femc_drv.h"
14 #include "pinmux.h"
15 #include "hpm_pmp_drv.h"
16 #include "hpm_clock_drv.h"
17 #include "hpm_sysctl_drv.h"
18 #include "hpm_sdxc_drv.h"
19 #include "hpm_pwm_drv.h"
20 #include "hpm_trgm_drv.h"
21 #include "hpm_pllctlv2_drv.h"
22 #include "hpm_enet_drv.h"
23 #include "hpm_pcfg_drv.h"
24 #include "hpm_sdk_version.h"
25
26 static board_timer_cb timer_cb;
27
28 /**
29 * @brief FLASH configuration option definitions:
30 * option[0]:
31 * [31:16] 0xfcf9 - FLASH configuration option tag
32 * [15:4] 0 - Reserved
33 * [3:0] option words (exclude option[0])
34 * option[1]:
35 * [31:28] Flash probe type
36 * 0 - SFDP SDR / 1 - SFDP DDR
37 * 2 - 1-4-4 Read (0xEB, 24-bit address) / 3 - 1-2-2 Read(0xBB, 24-bit address)
38 * 4 - HyperFLASH 1.8V / 5 - HyperFLASH 3V
39 * 6 - OctaBus DDR (SPI -> OPI DDR)
40 * 8 - Xccela DDR (SPI -> OPI DDR)
41 * 10 - EcoXiP DDR (SPI -> OPI DDR)
42 * [27:24] Command Pads after Power-on Reset
43 * 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI
44 * [23:20] Command Pads after Configuring FLASH
45 * 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI
46 * [19:16] Quad Enable Sequence (for the device support SFDP 1.0 only)
47 * 0 - Not needed
48 * 1 - QE bit is at bit 6 in Status Register 1
49 * 2 - QE bit is at bit1 in Status Register 2
50 * 3 - QE bit is at bit7 in Status Register 2
51 * 4 - QE bit is at bit1 in Status Register 2 and should be programmed by 0x31
52 * [15:8] Dummy cycles
53 * 0 - Auto-probed / detected / default value
54 * Others - User specified value, for DDR read, the dummy cycles should be 2 * cycles on FLASH datasheet
55 * [7:4] Misc.
56 * 0 - Not used
57 * 1 - SPI mode
58 * 2 - Internal loopback
59 * 3 - External DQS
60 * [3:0] Frequency option
61 * 1 - 30MHz / 2 - 50MHz / 3 - 66MHz / 4 - 80MHz / 5 - 100MHz / 6 - 120MHz / 7 - 133MHz / 8 - 166MHz
62 *
63 * option[2] (Effective only if the bit[3:0] in option[0] > 1)
64 * [31:20] Reserved
65 * [19:16] IO voltage
66 * 0 - 3V / 1 - 1.8V
67 * [15:12] Pin group
68 * 0 - 1st group / 1 - 2nd group
69 * [11:8] Connection selection
70 * 0 - CA_CS0 / 1 - CB_CS0 / 2 - CA_CS0 + CB_CS0 (Two FLASH connected to CA and CB respectively)
71 * [7:0] Drive Strength
72 * 0 - Default value
73 * option[3] (Effective only if the bit[3:0] in option[0] > 2, required only for the QSPI NOR FLASH that not supports
74 * JESD216)
75 * [31:16] reserved
76 * [15:12] Sector Erase Command Option, not required here
77 * [11:8] Sector Size Option, not required here
78 * [7:0] Flash Size Option
79 * 0 - 4MB / 1 - 8MB / 2 - 16MB
80 */
81 #if defined(FLASH_XIP) && FLASH_XIP
82 __attribute__ ((section(".nor_cfg_option"))) const uint32_t option[4] = {0xfcf90001, 0x00000007, 0x0, 0x0};
83 #endif
84
85 #if defined(FLASH_UF2) && FLASH_UF2
86 ATTR_PLACE_AT(".uf2_signature") const uint32_t uf2_signature = BOARD_UF2_SIGNATURE;
87 #endif
88
board_init_console(void)89 void board_init_console(void)
90 {
91 #if !defined(CONFIG_NDEBUG_CONSOLE) || !CONFIG_NDEBUG_CONSOLE
92 #if CONSOLE_TYPE_UART == BOARD_CONSOLE_TYPE
93 console_config_t cfg;
94
95 /* uart needs to configure pin function before enabling clock, otherwise the level change of
96 uart rx pin when configuring pin function will cause a wrong data to be received.
97 And a uart rx dma request will be generated by default uart fifo dma trigger level. */
98 init_uart_pins((UART_Type *) BOARD_CONSOLE_BASE);
99
100 /* Configure the UART clock to 24MHz */
101 clock_set_source_divider(BOARD_CONSOLE_CLK_NAME, clk_src_osc24m, 1U);
102 clock_add_to_group(BOARD_CONSOLE_CLK_NAME, 0);
103
104 cfg.type = BOARD_CONSOLE_TYPE;
105 cfg.base = (uint32_t) BOARD_CONSOLE_BASE;
106 cfg.src_freq_in_hz = clock_get_frequency(BOARD_CONSOLE_CLK_NAME);
107 cfg.baudrate = BOARD_CONSOLE_BAUDRATE;
108
109 if (status_success != console_init(&cfg)) {
110 /* failed to initialize debug console */
111 while (1) {
112 }
113 }
114 #else
115 while (1) {
116 }
117 #endif
118 #endif
119 }
120
board_print_clock_freq(void)121 void board_print_clock_freq(void)
122 {
123 printf("==============================\n");
124 printf(" %s clock summary\n", BOARD_NAME);
125 printf("==============================\n");
126 printf("cpu0:\t\t %luHz\n", clock_get_frequency(clock_cpu0));
127 printf("axi:\t\t %luHz\n", clock_get_frequency(clock_axi));
128 printf("ahb:\t\t %luHz\n", clock_get_frequency(clock_ahb));
129 printf("mchtmr0:\t %luHz\n", clock_get_frequency(clock_mchtmr0));
130 printf("xpi0:\t\t %luHz\n", clock_get_frequency(clock_xpi0));
131 printf("xpi1:\t\t %luHz\n", clock_get_frequency(clock_xpi1));
132 printf("femc:\t\t %luHz\n", clock_get_frequency(clock_femc));
133 printf("==============================\n");
134 }
135
board_init_uart(UART_Type * ptr)136 void board_init_uart(UART_Type *ptr)
137 {
138 /* configure uart's pin before opening uart's clock */
139 init_uart_pins(ptr);
140 board_init_uart_clock(ptr);
141 }
142
board_print_banner(void)143 void board_print_banner(void)
144 {
145 const uint8_t banner[] = {"\n\
146 ----------------------------------------------------------------------\n\
147 $$\\ $$\\ $$$$$$$\\ $$\\ $$\\ $$\\\n\
148 $$ | $$ |$$ __$$\\ $$$\\ $$$ |\\__|\n\
149 $$ | $$ |$$ | $$ |$$$$\\ $$$$ |$$\\ $$$$$$$\\ $$$$$$\\ $$$$$$\\\n\
150 $$$$$$$$ |$$$$$$$ |$$\\$$\\$$ $$ |$$ |$$ _____|$$ __$$\\ $$ __$$\\\n\
151 $$ __$$ |$$ ____/ $$ \\$$$ $$ |$$ |$$ / $$ | \\__|$$ / $$ |\n\
152 $$ | $$ |$$ | $$ |\\$ /$$ |$$ |$$ | $$ | $$ | $$ |\n\
153 $$ | $$ |$$ | $$ | \\_/ $$ |$$ |\\$$$$$$$\\ $$ | \\$$$$$$ |\n\
154 \\__| \\__|\\__| \\__| \\__|\\__| \\_______|\\__| \\______/\n\
155 ----------------------------------------------------------------------\n"};
156 #ifdef SDK_VERSION_STRING
157 printf("hpm_sdk: %s\n", SDK_VERSION_STRING);
158 #endif
159 printf("%s", banner);
160 }
161
board_ungate_mchtmr_at_lp_mode(void)162 void board_ungate_mchtmr_at_lp_mode(void)
163 {
164 /* Keep cpu clock on wfi, so that mchtmr irq can still work after wfi */
165 sysctl_set_cpu_lp_mode(HPM_SYSCTL, BOARD_RUNNING_CORE, cpu_lp_mode_ungate_cpu_clock);
166 }
167
board_init(void)168 void board_init(void)
169 {
170 pcfg_dcdc_set_voltage(HPM_PCFG, 1100);
171 board_init_clock();
172 board_init_console();
173 board_init_pmp();
174 #if BOARD_SHOW_CLOCK
175 board_print_clock_freq();
176 #endif
177 #if BOARD_SHOW_BANNER
178 board_print_banner();
179 #endif
180 }
181
board_init_sdram_pins(void)182 void board_init_sdram_pins(void)
183 {
184 init_sdram_pins();
185 }
186
board_init_femc_clock(void)187 uint32_t board_init_femc_clock(void)
188 {
189 clock_add_to_group(clock_femc, 0);
190 /* Configure the SDRAM to 166MHz */
191 clock_set_source_divider(clock_femc, clk_src_pll0_clk1, 2U);
192
193 return clock_get_frequency(clock_femc);
194 }
195
board_delay_us(uint32_t us)196 void board_delay_us(uint32_t us)
197 {
198 clock_cpu_delay_us(us);
199 }
200
board_delay_ms(uint32_t ms)201 void board_delay_ms(uint32_t ms)
202 {
203 clock_cpu_delay_ms(ms);
204 }
205
board_timer_isr(void)206 void board_timer_isr(void)
207 {
208 if (gptmr_check_status(BOARD_CALLBACK_TIMER, GPTMR_CH_RLD_STAT_MASK(BOARD_CALLBACK_TIMER_CH))) {
209 gptmr_clear_status(BOARD_CALLBACK_TIMER, GPTMR_CH_RLD_STAT_MASK(BOARD_CALLBACK_TIMER_CH));
210 timer_cb();
211 }
212 }
213 SDK_DECLARE_EXT_ISR_M(BOARD_CALLBACK_TIMER_IRQ, board_timer_isr);
214
board_timer_create(uint32_t ms,board_timer_cb cb)215 void board_timer_create(uint32_t ms, board_timer_cb cb)
216 {
217 uint32_t gptmr_freq;
218 gptmr_channel_config_t config;
219
220 timer_cb = cb;
221 gptmr_channel_get_default_config(BOARD_CALLBACK_TIMER, &config);
222
223 clock_add_to_group(BOARD_CALLBACK_TIMER_CLK_NAME, 0);
224 gptmr_freq = clock_get_frequency(BOARD_CALLBACK_TIMER_CLK_NAME);
225
226 config.reload = gptmr_freq / 1000 * ms;
227 gptmr_channel_config(BOARD_CALLBACK_TIMER, BOARD_CALLBACK_TIMER_CH, &config, false);
228 gptmr_enable_irq(BOARD_CALLBACK_TIMER, GPTMR_CH_RLD_IRQ_MASK(BOARD_CALLBACK_TIMER_CH));
229 intc_m_enable_irq_with_priority(BOARD_CALLBACK_TIMER_IRQ, 1);
230
231 gptmr_start_counter(BOARD_CALLBACK_TIMER, BOARD_CALLBACK_TIMER_CH);
232 }
233
board_i2c_bus_clear(I2C_Type * ptr)234 void board_i2c_bus_clear(I2C_Type *ptr)
235 {
236 init_i2c_pins_as_gpio(ptr);
237 if (ptr == BOARD_APP_I2C_BASE) {
238 gpio_set_pin_input(BOARD_I2C_GPIO_CTRL, BOARD_I2C_SDA_GPIO_INDEX, BOARD_I2C_SDA_GPIO_PIN);
239 gpio_set_pin_input(BOARD_I2C_GPIO_CTRL, BOARD_I2C_SCL_GPIO_INDEX, BOARD_I2C_SCL_GPIO_PIN);
240 if (!gpio_read_pin(BOARD_I2C_GPIO_CTRL, BOARD_I2C_SCL_GPIO_INDEX, BOARD_I2C_SCL_GPIO_PIN)) {
241 printf("CLK is low, please power cycle the board\n");
242 while (1) {
243 }
244 }
245 if (!gpio_read_pin(BOARD_I2C_GPIO_CTRL, BOARD_I2C_SDA_GPIO_INDEX, BOARD_I2C_SDA_GPIO_PIN)) {
246 printf("SDA is low, try to issue I2C bus clear\n");
247 } else {
248 printf("I2C bus is ready\n");
249 return;
250 }
251
252 gpio_set_pin_output(BOARD_I2C_GPIO_CTRL, BOARD_I2C_SCL_GPIO_INDEX, BOARD_I2C_SCL_GPIO_PIN);
253 while (1) {
254 for (uint32_t i = 0; i < 9; i++) {
255 gpio_write_pin(BOARD_I2C_GPIO_CTRL, BOARD_I2C_SCL_GPIO_INDEX, BOARD_I2C_SCL_GPIO_PIN, 1);
256 board_delay_ms(10);
257 gpio_write_pin(BOARD_I2C_GPIO_CTRL, BOARD_I2C_SCL_GPIO_INDEX, BOARD_I2C_SCL_GPIO_PIN, 0);
258 board_delay_ms(10);
259 }
260 board_delay_ms(100);
261 }
262 printf("I2C bus is cleared\n");
263 }
264 }
265
board_init_i2c(I2C_Type * ptr)266 void board_init_i2c(I2C_Type *ptr)
267 {
268 i2c_config_t config;
269 hpm_stat_t stat;
270 uint32_t freq;
271 if (ptr == NULL) {
272 return;
273 }
274
275 board_i2c_bus_clear(ptr);
276 init_i2c_pins(ptr);
277 clock_add_to_group(clock_i2c0, 0);
278 clock_add_to_group(clock_i2c1, 0);
279 clock_add_to_group(clock_i2c2, 0);
280 clock_add_to_group(clock_i2c3, 0);
281 /* Configure the I2C clock to 24MHz */
282 clock_set_source_divider(BOARD_APP_I2C_CLK_NAME, clk_src_osc24m, 1U);
283
284 config.i2c_mode = i2c_mode_normal;
285 config.is_10bit_addressing = false;
286 freq = clock_get_frequency(BOARD_APP_I2C_CLK_NAME);
287 stat = i2c_init_master(ptr, freq, &config);
288 if (stat != status_success) {
289 printf("failed to initialize i2c 0x%lx\n", (uint32_t) ptr);
290 while (1) {
291 }
292 }
293 }
294
board_init_spi_clock(SPI_Type * ptr)295 uint32_t board_init_spi_clock(SPI_Type *ptr)
296 {
297 if (ptr == HPM_SPI3) {
298 /* SPI3 clock configure */
299 clock_add_to_group(clock_spi3, 0);
300 clock_set_source_divider(clock_spi3, clk_src_pll0_clk0, 5U); /* 80MHz */
301
302 return clock_get_frequency(clock_spi3);
303 }
304 return 0;
305 }
306
board_init_gpio_pins(void)307 void board_init_gpio_pins(void)
308 {
309 init_gpio_pins();
310 }
311
board_init_spi_pins(SPI_Type * ptr)312 void board_init_spi_pins(SPI_Type *ptr)
313 {
314 init_spi_pins(ptr);
315 }
316
board_init_spi_pins_with_gpio_as_cs(SPI_Type * ptr)317 void board_init_spi_pins_with_gpio_as_cs(SPI_Type *ptr)
318 {
319 init_spi_pins_with_gpio_as_cs(ptr);
320 gpio_set_pin_output_with_initial(BOARD_SPI_CS_GPIO_CTRL, GPIO_GET_PORT_INDEX(BOARD_SPI_CS_PIN),
321 GPIO_GET_PIN_INDEX(BOARD_SPI_CS_PIN), !BOARD_SPI_CS_ACTIVE_LEVEL);
322 }
323
board_write_spi_cs(uint32_t pin,uint8_t state)324 void board_write_spi_cs(uint32_t pin, uint8_t state)
325 {
326 gpio_write_pin(BOARD_SPI_CS_GPIO_CTRL, GPIO_GET_PORT_INDEX(pin), GPIO_GET_PIN_INDEX(pin), state);
327 }
328
board_get_led_gpio_off_level(void)329 uint8_t board_get_led_gpio_off_level(void)
330 {
331 return BOARD_LED_OFF_LEVEL;
332 }
333
board_init_led_pins(void)334 void board_init_led_pins(void)
335 {
336 init_led_pins();
337 gpio_set_pin_output_with_initial(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN, board_get_led_gpio_off_level());
338 }
339
board_led_toggle(void)340 void board_led_toggle(void)
341 {
342 gpio_toggle_pin(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN);
343 }
344
board_led_write(uint8_t state)345 void board_led_write(uint8_t state)
346 {
347 gpio_write_pin(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN, state);
348 }
349
board_init_usb_pins(void)350 void board_init_usb_pins(void)
351 {
352 /* set pull-up for USBx ID pin */
353 init_usb_pins();
354
355 /* configure USBx ID pin as input function */
356 gpio_set_pin_input(BOARD_USB0_ID_PORT, BOARD_USB0_ID_GPIO_INDEX, BOARD_USB0_ID_GPIO_PIN);
357 }
358
board_get_usb_id_status(void)359 uint8_t board_get_usb_id_status(void)
360 {
361 return gpio_read_pin(BOARD_USB0_ID_PORT, BOARD_USB0_ID_GPIO_INDEX, BOARD_USB0_ID_GPIO_PIN);
362 }
363
board_usb_vbus_ctrl(uint8_t usb_index,uint8_t level)364 void board_usb_vbus_ctrl(uint8_t usb_index, uint8_t level)
365 {
366 (void) usb_index;
367 (void) level;
368 }
369
board_init_pmp(void)370 void board_init_pmp(void)
371 {
372 extern uint32_t __noncacheable_start__[];
373 extern uint32_t __noncacheable_end__[];
374
375 uint32_t start_addr = (uint32_t) __noncacheable_start__;
376 uint32_t end_addr = (uint32_t) __noncacheable_end__;
377 uint32_t length = end_addr - start_addr;
378
379 if (length == 0) {
380 return;
381 }
382
383 /* Ensure the address and the length are power of 2 aligned */
384 assert((length & (length - 1U)) == 0U);
385 assert((start_addr & (length - 1U)) == 0U);
386
387 pmp_entry_t pmp_entry[3] = {0};
388 pmp_entry[0].pmp_addr = PMP_NAPOT_ADDR(0x0000000, 0x80000000);
389 pmp_entry[0].pmp_cfg.val = PMP_CFG(READ_EN, WRITE_EN, EXECUTE_EN, ADDR_MATCH_NAPOT, REG_UNLOCK);
390
391
392 pmp_entry[1].pmp_addr = PMP_NAPOT_ADDR(0x80000000, 0x80000000);
393 pmp_entry[1].pmp_cfg.val = PMP_CFG(READ_EN, WRITE_EN, EXECUTE_EN, ADDR_MATCH_NAPOT, REG_UNLOCK);
394
395 pmp_entry[2].pmp_addr = PMP_NAPOT_ADDR(start_addr, length);
396 pmp_entry[2].pmp_cfg.val = PMP_CFG(READ_EN, WRITE_EN, EXECUTE_EN, ADDR_MATCH_NAPOT, REG_UNLOCK);
397 pmp_entry[2].pma_addr = PMA_NAPOT_ADDR(start_addr, length);
398 pmp_entry[2].pma_cfg.val = PMA_CFG(ADDR_MATCH_NAPOT, MEM_TYPE_MEM_NON_CACHE_BUF, AMO_EN);
399 pmp_config(&pmp_entry[0], ARRAY_SIZE(pmp_entry));
400 }
401
board_init_clock(void)402 void board_init_clock(void)
403 {
404 uint32_t cpu0_freq = clock_get_frequency(clock_cpu0);
405 if (cpu0_freq == PLLCTL_SOC_PLL_REFCLK_FREQ) {
406 /* Configure the External OSC ramp-up time: ~9ms */
407 pllctlv2_xtal_set_rampup_time(HPM_PLLCTLV2, 32UL * 1000UL * 9U);
408
409 /* Select clock setting preset1 */
410 sysctl_clock_set_preset(HPM_SYSCTL, 2);
411 }
412
413
414 /* Add most Clocks to group 0 */
415 /* not open uart clock in this API, uart should configure pin function before opening clock */
416 clock_add_to_group(clock_cpu0, 0);
417 clock_add_to_group(clock_ahbp, 0);
418 clock_add_to_group(clock_axic, 0);
419 clock_add_to_group(clock_axis, 0);
420
421 clock_add_to_group(clock_mchtmr0, 0);
422 clock_add_to_group(clock_femc, 0);
423 clock_add_to_group(clock_xpi0, 0);
424 clock_add_to_group(clock_xpi1, 0);
425 clock_add_to_group(clock_gptmr0, 0);
426 clock_add_to_group(clock_gptmr1, 0);
427 clock_add_to_group(clock_gptmr2, 0);
428 clock_add_to_group(clock_gptmr3, 0);
429 clock_add_to_group(clock_i2c0, 0);
430 clock_add_to_group(clock_i2c1, 0);
431 clock_add_to_group(clock_i2c2, 0);
432 clock_add_to_group(clock_i2c3, 0);
433 clock_add_to_group(clock_spi0, 0);
434 clock_add_to_group(clock_spi1, 0);
435 clock_add_to_group(clock_spi2, 0);
436 clock_add_to_group(clock_spi3, 0);
437 clock_add_to_group(clock_can0, 0);
438 clock_add_to_group(clock_can1, 0);
439 clock_add_to_group(clock_sdxc0, 0);
440 clock_add_to_group(clock_ptpc, 0);
441 clock_add_to_group(clock_ref0, 0);
442 clock_add_to_group(clock_ref1, 0);
443 clock_add_to_group(clock_watchdog0, 0);
444 clock_add_to_group(clock_eth0, 0);
445 clock_add_to_group(clock_sdp, 0);
446 clock_add_to_group(clock_xdma, 0);
447 clock_add_to_group(clock_ram0, 0);
448 clock_add_to_group(clock_usb0, 0);
449 clock_add_to_group(clock_kman, 0);
450 clock_add_to_group(clock_gpio, 0);
451 clock_add_to_group(clock_mbx0, 0);
452 clock_add_to_group(clock_hdma, 0);
453 clock_add_to_group(clock_rng, 0);
454 clock_add_to_group(clock_mot0, 0);
455 clock_add_to_group(clock_mot1, 0);
456 clock_add_to_group(clock_acmp, 0);
457 clock_add_to_group(clock_dao, 0);
458 clock_add_to_group(clock_msyn, 0);
459 clock_add_to_group(clock_lmm0, 0);
460 clock_add_to_group(clock_pdm, 0);
461
462 clock_add_to_group(clock_adc0, 0);
463 clock_add_to_group(clock_adc1, 0);
464 clock_add_to_group(clock_adc2, 0);
465
466 clock_add_to_group(clock_dac0, 0);
467
468 clock_add_to_group(clock_i2s0, 0);
469 clock_add_to_group(clock_i2s1, 0);
470
471 clock_add_to_group(clock_ffa0, 0);
472 clock_add_to_group(clock_tsns, 0);
473
474 /* Connect Group0 to CPU0 */
475 clock_connect_group_to_cpu(0, 0);
476
477 /* Configure CPU to 480MHz, AXI/AHB to 160MHz */
478 sysctl_config_cpu0_domain_clock(HPM_SYSCTL, clock_source_pll1_clk0, 1, 3, 3);
479 /* Configure PLL1_CLK0 Post Divider to 1.2 */
480 pllctlv2_set_postdiv(HPM_PLLCTLV2, 1, 0, 1);
481 /* Configure PLL1 clock frequencey to 576MHz, the PLL1_CLK0 frequency = 576MHz / 1.2 = 480MHz */
482 pllctlv2_init_pll_with_freq(HPM_PLLCTLV2, 1, 576000000);
483 clock_update_core_clock();
484
485 /* Configure mchtmr to 24MHz */
486 clock_set_source_divider(clock_mchtmr0, clk_src_osc24m, 1);
487 }
488
board_init_dao_clock(void)489 uint32_t board_init_dao_clock(void)
490 {
491 return clock_get_frequency(clock_dao);
492 }
493
board_init_pdm_clock(void)494 uint32_t board_init_pdm_clock(void)
495 {
496 return clock_get_frequency(clock_pdm);
497 }
498
board_set_audio_pll_clock(uint32_t freq)499 hpm_stat_t board_set_audio_pll_clock(uint32_t freq)
500 {
501 return pllctlv2_init_pll_with_freq(HPM_PLLCTLV2, 2, freq); /* pll2clk */
502 }
503
board_init_i2s_clock(I2S_Type * ptr)504 uint32_t board_init_i2s_clock(I2S_Type *ptr)
505 {
506 (void) ptr;
507 return 0;
508 }
509
board_init_adc16_clock(ADC16_Type * ptr,bool clk_src_ahb)510 uint32_t board_init_adc16_clock(ADC16_Type *ptr, bool clk_src_ahb)
511 {
512 uint32_t freq = 0;
513
514 if (ptr == HPM_ADC0) {
515 if (clk_src_ahb) {
516 /* Configure the ADC clock from AHB (@160MHz by default)*/
517 clock_set_adc_source(clock_adc0, clk_adc_src_ahb0);
518 } else {
519 /* Configure the ADC clock from pll0_clk1 divided by 2 (@166MHz by default) */
520 clock_set_adc_source(clock_adc0, clk_adc_src_ana0);
521 clock_set_source_divider(clock_ana0, clk_src_pll0_clk1, 2U);
522 }
523
524 freq = clock_get_frequency(clock_adc0);
525 } else if (ptr == HPM_ADC1) {
526 if (clk_src_ahb) {
527 /* Configure the ADC clock from AHB (@160MHz by default)*/
528 clock_set_adc_source(clock_adc1, clk_adc_src_ahb0);
529 } else {
530 /* Configure the ADC clock from pll1_clk1 divided by 2 (@166MHz by default) */
531 clock_set_adc_source(clock_adc1, clk_adc_src_ana1);
532 clock_set_source_divider(clock_ana1, clk_src_pll0_clk1, 2U);
533 }
534
535 freq = clock_get_frequency(clock_adc1);
536 } else if (ptr == HPM_ADC2) {
537 if (clk_src_ahb) {
538 /* Configure the ADC clock from AHB (@160MHz by default)*/
539 clock_set_adc_source(clock_adc2, clk_adc_src_ahb0);
540 } else {
541 /* Configure the ADC clock from pll1_clk1 divided by 2 (@166MHz by default) */
542 clock_set_adc_source(clock_adc2, clk_adc_src_ana2);
543 clock_set_source_divider(clock_ana2, clk_src_pll0_clk1, 2U);
544 }
545
546 freq = clock_get_frequency(clock_adc2);
547 }
548
549 return freq;
550 }
551
board_init_dac_clock(DAC_Type * ptr,bool clk_src_ahb)552 uint32_t board_init_dac_clock(DAC_Type *ptr, bool clk_src_ahb)
553 {
554 uint32_t freq = 0;
555
556 if (ptr == HPM_DAC) {
557 if (clk_src_ahb == true) {
558 /* Configure the DAC clock to 160MHz */
559 clock_set_dac_source(clock_dac0, clk_dac_src_ahb0);
560 } else {
561 /* Configure the DAC clock to 166MHz */
562 clock_set_dac_source(clock_dac0, clk_dac_src_ana3);
563 clock_set_source_divider(clock_ana3, clk_src_pll0_clk1, 2);
564 }
565
566 freq = clock_get_frequency(clock_dac0);
567 }
568
569 return freq;
570 }
571
board_init_can(CAN_Type * ptr)572 void board_init_can(CAN_Type *ptr)
573 {
574 init_can_pins(ptr);
575 }
576
board_init_can_clock(CAN_Type * ptr)577 uint32_t board_init_can_clock(CAN_Type *ptr)
578 {
579 uint32_t freq = 0;
580 if (ptr == HPM_CAN0) {
581 /* Set the CAN0 peripheral clock to 80MHz */
582 clock_set_source_divider(clock_can0, clk_src_pll0_clk0, 5);
583 freq = clock_get_frequency(clock_can0);
584 } else if (ptr == HPM_CAN1) {
585 /* Set the CAN1 peripheral clock to 80MHz */
586 clock_set_source_divider(clock_can1, clk_src_pll0_clk0, 5);
587 freq = clock_get_frequency(clock_can1);
588 } else {
589 /* Invalid CAN instance */
590 }
591 return freq;
592 }
593
594 #ifdef INIT_EXT_RAM_FOR_DATA
595 /*
596 * this function will be called during startup to initialize external memory for data use
597 */
_init_ext_ram(void)598 void _init_ext_ram(void)
599 {
600 uint32_t femc_clk_in_hz;
601 board_init_sdram_pins();
602 femc_clk_in_hz = board_init_femc_clock();
603
604 femc_config_t config = {0};
605 femc_sdram_config_t sdram_config = {0};
606
607 femc_default_config(HPM_FEMC, &config);
608 config.dqs = FEMC_DQS_INTERNAL;
609 femc_init(HPM_FEMC, &config);
610
611 sdram_config.bank_num = FEMC_SDRAM_BANK_NUM_4;
612 sdram_config.prescaler = 0x3;
613 sdram_config.burst_len_in_byte = 8;
614 sdram_config.auto_refresh_count_in_one_burst = 1;
615 sdram_config.col_addr_bits = FEMC_SDRAM_COLUMN_ADDR_9_BITS;
616 sdram_config.cas_latency = FEMC_SDRAM_CAS_LATENCY_3;
617
618 sdram_config.precharge_to_act_in_ns = 18; /* Trp */
619 sdram_config.act_to_rw_in_ns = 18; /* Trcd */
620 sdram_config.refresh_recover_in_ns = 70; /* Trfc/Trc */
621 sdram_config.write_recover_in_ns = 12; /* Twr/Tdpl */
622 sdram_config.cke_off_in_ns = 42; /* Trcd */
623 sdram_config.act_to_precharge_in_ns = 42; /* Tras */
624
625 sdram_config.self_refresh_recover_in_ns = 66; /* Txsr */
626 sdram_config.refresh_to_refresh_in_ns = 66; /* Trfc/Trc */
627 sdram_config.act_to_act_in_ns = 12; /* Trrd */
628 sdram_config.idle_timeout_in_ns = 6;
629 sdram_config.cs_mux_pin = FEMC_IO_MUX_NOT_USED;
630
631 sdram_config.cs = BOARD_SDRAM_CS;
632 sdram_config.base_address = BOARD_SDRAM_ADDRESS;
633 sdram_config.size_in_byte = BOARD_SDRAM_SIZE;
634 sdram_config.port_size = BOARD_SDRAM_PORT_SIZE;
635 sdram_config.refresh_count = BOARD_SDRAM_REFRESH_COUNT;
636 sdram_config.refresh_in_ms = BOARD_SDRAM_REFRESH_IN_MS;
637 sdram_config.data_width_in_byte = BOARD_SDRAM_DATA_WIDTH_IN_BYTE;
638 sdram_config.delay_cell_value = 29;
639
640 femc_config_sdram(HPM_FEMC, femc_clk_in_hz, &sdram_config);
641 }
642 #endif
643
board_sd_configure_clock(SDXC_Type * ptr,uint32_t freq,bool need_inverse)644 uint32_t board_sd_configure_clock(SDXC_Type *ptr, uint32_t freq, bool need_inverse)
645 {
646 uint32_t actual_freq = 0;
647 do {
648 if (ptr != HPM_SDXC0) {
649 break;
650 }
651 clock_name_t sdxc_clk = clock_sdxc0;
652 sdxc_enable_inverse_clock(ptr, false);
653 sdxc_enable_sd_clock(ptr, false);
654 /* Configure the SDXC Frequency to 200MHz */
655 clock_set_source_divider(sdxc_clk, clk_src_pll0_clk0, 2);
656 sdxc_enable_freq_selection(ptr);
657
658 /* Configure the clock below 400KHz for the identification state */
659 if (freq <= 400000UL) {
660 sdxc_set_clock_divider(ptr, 600);
661 }
662 /* configure the clock to 24MHz for the SDR12/Default speed */
663 else if (freq <= 26000000UL) {
664 sdxc_set_clock_divider(ptr, 8);
665 }
666 /* Configure the clock to 50MHz for the SDR25/High speed/50MHz DDR/50MHz SDR */
667 else if (freq <= 52000000UL) {
668 sdxc_set_clock_divider(ptr, 4);
669 }
670 /* Configure the clock to 100MHz for the SDR50 */
671 else if (freq <= 100000000UL) {
672 sdxc_set_clock_divider(ptr, 2);
673 }
674 /* Configure the clock to 166MHz for SDR104/HS200/HS400 */
675 else if (freq <= 208000000UL) {
676 sdxc_set_clock_divider(ptr, 1);
677 }
678 /* For other unsupported clock ranges, configure the clock to 24MHz */
679 else {
680 sdxc_set_clock_divider(ptr, 8);
681 }
682 if (need_inverse) {
683 sdxc_enable_inverse_clock(ptr, true);
684 }
685 sdxc_enable_sd_clock(ptr, true);
686 actual_freq = clock_get_frequency(sdxc_clk) / sdxc_get_clock_divider(ptr);
687 } while (false);
688
689 return actual_freq;
690 }
691
board_sd_switch_pins_to_1v8(SDXC_Type * ptr)692 void board_sd_switch_pins_to_1v8(SDXC_Type *ptr)
693 {
694 (void) ptr;
695 /* This feature is not supported */
696 }
697
board_sd_detect_card(SDXC_Type * ptr)698 bool board_sd_detect_card(SDXC_Type *ptr)
699 {
700 return sdxc_is_card_inserted(ptr);
701 }
702
board_init_enet_ptp_clock(ENET_Type * ptr)703 hpm_stat_t board_init_enet_ptp_clock(ENET_Type *ptr)
704 {
705 /* set clock source */
706 if (ptr == HPM_ENET0) {
707 /* make sure pll0_clk0 output clock at 400MHz to get a clock at 100MHz for ent0 ptp clock */
708 clock_set_source_divider(clock_ptp0, clk_src_pll0_clk0, 4); /* 100MHz */
709 } else {
710 return status_invalid_argument;
711 }
712
713 return status_success;
714 }
715
board_init_enet_rmii_reference_clock(ENET_Type * ptr,bool internal)716 hpm_stat_t board_init_enet_rmii_reference_clock(ENET_Type *ptr, bool internal)
717 {
718 /* Configure Enet clock to output reference clock */
719 if (ptr == HPM_ENET0) {
720 if (internal) {
721 /* set pll output frequency at 1GHz */
722 if (pllctlv2_init_pll_with_freq(HPM_PLLCTLV2, PLLCTLV2_PLL_PLL2, 1000000000UL) == status_success) {
723 /* set pll2_clk1 output frequence at 250MHz from PLL2 divided by 4 (1 + 15 / 5) */
724 pllctlv2_set_postdiv(HPM_PLLCTLV2, PLLCTLV2_PLL_PLL2, 1, 15);
725 /* set eth clock frequency at 50MHz for enet0 */
726 clock_set_source_divider(clock_eth0, clk_src_pll2_clk1, 5);
727 } else {
728 return status_fail;
729 }
730 }
731 } else {
732 return status_invalid_argument;
733 }
734
735 enet_rmii_enable_clock(ptr, internal);
736
737 return status_success;
738 }
739
board_init_adc16_pins(void)740 void board_init_adc16_pins(void)
741 {
742 init_adc_pins();
743 }
744
board_init_enet_pins(ENET_Type * ptr)745 hpm_stat_t board_init_enet_pins(ENET_Type *ptr)
746 {
747 init_enet_pins(ptr);
748
749 return status_success;
750 }
751
board_reset_enet_phy(ENET_Type * ptr)752 hpm_stat_t board_reset_enet_phy(ENET_Type *ptr)
753 {
754 (void) ptr;
755 return status_success;
756 }
757
board_init_dac_pins(DAC_Type * ptr)758 void board_init_dac_pins(DAC_Type *ptr)
759 {
760 init_dac_pins(ptr);
761 }
762
board_init_uart_clock(UART_Type * ptr)763 uint32_t board_init_uart_clock(UART_Type *ptr)
764 {
765 uint32_t freq = 0U;
766 if (ptr == HPM_UART0) {
767 clock_set_source_divider(clock_uart0, clk_src_osc24m, 1);
768 clock_add_to_group(clock_uart0, 0);
769 freq = clock_get_frequency(clock_uart0);
770 } else if (ptr == HPM_UART1) {
771 clock_set_source_divider(clock_uart1, clk_src_osc24m, 1);
772 clock_add_to_group(clock_uart1, 0);
773 freq = clock_get_frequency(clock_uart1);
774 } else if (ptr == HPM_UART2) {
775 clock_set_source_divider(clock_uart2, clk_src_osc24m, 1);
776 clock_add_to_group(clock_uart2, 0);
777 freq = clock_get_frequency(clock_uart2);
778 } else {
779 /* Not supported */
780 }
781 return freq;
782 }
783
board_get_enet_dma_pbl(ENET_Type * ptr)784 uint8_t board_get_enet_dma_pbl(ENET_Type *ptr)
785 {
786 (void) ptr;
787 return enet_pbl_16;
788 }
789
board_enable_enet_irq(ENET_Type * ptr)790 hpm_stat_t board_enable_enet_irq(ENET_Type *ptr)
791 {
792 if (ptr == HPM_ENET0) {
793 intc_m_enable_irq(IRQn_ENET0);
794 } else {
795 return status_invalid_argument;
796 }
797
798 return status_success;
799 }
800
board_disable_enet_irq(ENET_Type * ptr)801 hpm_stat_t board_disable_enet_irq(ENET_Type *ptr)
802 {
803 if (ptr == HPM_ENET0) {
804 intc_m_disable_irq(IRQn_ENET0);
805 } else {
806 return status_invalid_argument;
807 }
808
809 return status_success;
810 }
811
board_init_enet_pps_pins(ENET_Type * ptr)812 void board_init_enet_pps_pins(ENET_Type *ptr)
813 {
814 (void) ptr;
815 init_enet_pps_pins();
816 }
817