1 /* 2 * Copyright (c) 2021-2023 HPMicro 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 */ 7 8 #ifndef _HPM_BOARD_H 9 #define _HPM_BOARD_H 10 #include <stdio.h> 11 #include "hpm_common.h" 12 #include "hpm_clock_drv.h" 13 #include "hpm_soc.h" 14 #include "hpm_soc_feature.h" 15 #include "pinmux.h" 16 #include "hpm_lcdc_drv.h" 17 #include "hpm_trgm_drv.h" 18 #ifdef CONFIG_HPM_PANEL 19 #include "hpm_panel.h" 20 #endif 21 #if !defined(CONFIG_NDEBUG_CONSOLE) || !CONFIG_NDEBUG_CONSOLE 22 #include "hpm_debug_console.h" 23 #endif 24 25 #define BOARD_NAME "hpm6750evk" 26 #define BOARD_UF2_SIGNATURE (0x0A4D5048UL) 27 28 #define SEC_CORE_IMG_START ILM_LOCAL_BASE 29 30 /* uart section */ 31 #ifndef BOARD_RUNNING_CORE 32 #define BOARD_RUNNING_CORE HPM_CORE0 33 #endif 34 #ifndef BOARD_APP_UART_BASE 35 #define BOARD_APP_UART_BASE HPM_UART0 36 #define BOARD_APP_UART_IRQ IRQn_UART0 37 #else 38 #ifndef BOARD_APP_UART_IRQ 39 #warning no IRQ specified for application uart 40 #endif 41 #endif 42 43 /* uart rx idle demo section */ 44 #define BOARD_UART_IDLE HPM_UART13 45 #define BOARD_UART_IDLE_IRQ IRQn_UART13 46 #define BOARD_UART_IDLE_CLK_NAME clock_uart13 47 #define BOARD_UART_IDLE_TX_DMA_SRC HPM_DMA_SRC_UART13_TX 48 #define BOARD_UART_IDLE_DMA_SRC HPM_DMA_SRC_UART13_RX 49 50 #define BOARD_UART_IDLE_TRGM HPM_TRGM2 51 #define BOARD_UART_IDLE_TRGM_PIN IOC_PAD_PD19 52 #define BOARD_UART_IDLE_TRGM_INPUT_SRC HPM_TRGM2_INPUT_SRC_TRGM2_P9 53 #define BOARD_UART_IDLE_TRGM_OUTPUT_GPTMR_IN HPM_TRGM2_OUTPUT_SRC_GPTMR4_IN2 54 #define BOARD_UART_IDLE_TRGM_OUTPUT_GPTMR_SYNCI HPM_TRGM2_OUTPUT_SRC_GPTMR4_SYNCI 55 56 #define BOARD_UART_IDLE_GPTMR HPM_GPTMR4 57 #define BOARD_UART_IDLE_GPTMR_CLK_NAME clock_gptmr4 58 #define BOARD_UART_IDLE_GPTMR_IRQ IRQn_GPTMR4 59 #define BOARD_UART_IDLE_GPTMR_CMP_CH 0 60 #define BOARD_UART_IDLE_GPTMR_CAP_CH 2 61 62 /* uart microros sample section */ 63 #define BOARD_MICROROS_UART_BASE HPM_UART13 64 #define BOARD_MICROROS_UART_IRQ IRQn_UART13 65 #define BOARD_MICROROS_UART_CLK_NAME clock_uart13 66 67 /* uart lin sample section */ 68 #define BOARD_UART_LIN HPM_UART13 69 #define BOARD_UART_LIN_IRQ IRQn_UART13 70 #define BOARD_UART_LIN_CLK_NAME clock_uart13 71 #define BOARD_UART_LIN_TX_PORT GPIO_DI_GPIOZ 72 #define BOARD_UART_LIN_TX_PIN (9U) /* PZ09 should align with used pin in pinmux configuration */ 73 74 #define BOARD_APP_UART_BAUDRATE (115200UL) 75 #define BOARD_APP_UART_CLK_NAME clock_uart0 76 #define BOARD_APP_UART_RX_DMA_REQ HPM_DMA_SRC_UART0_RX 77 #define BOARD_APP_UART_TX_DMA_REQ HPM_DMA_SRC_UART0_TX 78 79 #if !defined(CONFIG_NDEBUG_CONSOLE) || !CONFIG_NDEBUG_CONSOLE 80 #ifndef BOARD_CONSOLE_TYPE 81 #define BOARD_CONSOLE_TYPE CONSOLE_TYPE_UART 82 #endif 83 84 #if BOARD_CONSOLE_TYPE == CONSOLE_TYPE_UART 85 #ifndef BOARD_CONSOLE_BASE 86 #if BOARD_RUNNING_CORE == HPM_CORE0 87 #define BOARD_CONSOLE_BASE HPM_UART0 88 #define BOARD_CONSOLE_CLK_NAME clock_uart0 89 #else 90 #define BOARD_CONSOLE_BASE HPM_UART13 91 #define BOARD_CONSOLE_CLK_NAME clock_uart13 92 #endif 93 #endif 94 #define BOARD_CONSOLE_BAUDRATE (115200UL) 95 #endif 96 #endif 97 98 99 #define BOARD_FREEMASTER_UART_BASE HPM_UART0 100 #define BOARD_FREEMASTER_UART_IRQ IRQn_UART0 101 #define BOARD_FREEMASTER_UART_CLK_NAME clock_uart0 102 103 /* sdram section */ 104 #define BOARD_SDRAM_ADDRESS (0x40000000UL) 105 #define BOARD_SDRAM_SIZE (32*SIZE_1MB) 106 #define BOARD_SDRAM_CS FEMC_SDRAM_CS0 107 #define BOARD_SDRAM_PORT_SIZE FEMC_SDRAM_PORT_SIZE_32_BITS 108 #define BOARD_SDRAM_REFRESH_COUNT (8192UL) 109 #define BOARD_SDRAM_REFRESH_IN_MS (64UL) 110 #define BOARD_SDRAM_DATA_WIDTH_IN_BYTE (4UL) 111 112 #define BOARD_FLASH_BASE_ADDRESS (0x80000000UL) 113 #define BOARD_FLASH_SIZE (16 << 20) 114 115 /* lcd section */ 116 #define BOARD_LCD_BASE HPM_LCDC 117 #define BOARD_LCD_IRQ IRQn_LCDC_D0 118 #define BOARD_LCD_POWER_GPIO_BASE HPM_GPIO0 119 #define BOARD_LCD_POWER_GPIO_INDEX GPIO_DO_GPIOB 120 #define BOARD_LCD_POWER_GPIO_PIN 16 121 #define BOARD_LCD_BACKLIGHT_GPIO_BASE HPM_GPIO0 122 #define BOARD_LCD_BACKLIGHT_GPIO_INDEX GPIO_DO_GPIOB 123 #define BOARD_LCD_BACKLIGHT_GPIO_PIN 10 124 125 /* i2c section */ 126 #define BOARD_APP_I2C_BASE HPM_I2C0 127 #define BOARD_APP_I2C_IRQ IRQn_I2C0 128 #define BOARD_APP_I2C_CLK_NAME clock_i2c0 129 #define BOARD_APP_I2C_DMA HPM_HDMA 130 #define BOARD_APP_I2C_DMAMUX HPM_DMAMUX 131 #define BOARD_APP_I2C_DMA_SRC HPM_DMA_SRC_I2C0 132 133 #define BOARD_CAM_I2C_BASE HPM_I2C0 134 #define BOARD_CAM_I2C_CLK_NAME clock_i2c0 135 #define BOARD_SUPPORT_CAM_RESET 136 #define BOARD_CAM_RST_GPIO_CTRL HPM_GPIO0 137 #define BOARD_CAM_RST_GPIO_INDEX GPIO_DI_GPIOY 138 #define BOARD_CAM_RST_GPIO_PIN 5 139 140 #define BOARD_CAP_I2C_BASE (HPM_I2C0) 141 #define BOARD_CAP_I2C_CLK_NAME clock_i2c0 142 #define BOARD_CAP_RST_GPIO (HPM_GPIO0) 143 #define BOARD_CAP_RST_GPIO_INDEX (GPIO_DI_GPIOB) 144 #define BOARD_CAP_RST_GPIO_PIN (9) 145 #define BOARD_CAP_RST_GPIO_IRQ (IRQn_GPIO0_B) 146 #define BOARD_CAP_INTR_GPIO (HPM_GPIO0) 147 #define BOARD_CAP_INTR_GPIO_INDEX (GPIO_DI_GPIOB) 148 #define BOARD_CAP_INTR_GPIO_PIN (8) 149 #define BOARD_CAP_INTR_GPIO_IRQ (IRQn_GPIO0_B) 150 #define BOARD_CAP_I2C_SDA_GPIO_INDEX (GPIO_DI_GPIOZ) 151 #define BOARD_CAP_I2C_SDA_GPIO_PIN (10) 152 #define BOARD_CAP_I2C_CLK_GPIO_INDEX (GPIO_DI_GPIOZ) 153 #define BOARD_CAP_I2C_CLK_GPIO_PIN (11) 154 155 /* ACMP desction */ 156 #define BOARD_ACMP HPM_ACMP 157 #define BOARD_ACMP_CHANNEL ACMP_CHANNEL_CHN1 158 #define BOARD_ACMP_IRQ IRQn_ACMP_1 159 #define BOARD_ACMP_PLUS_INPUT ACMP_INPUT_DAC_OUT /* use internal DAC */ 160 #define BOARD_ACMP_MINUS_INPUT ACMP_INPUT_ANALOG_6 /* align with used pin */ 161 162 /* dma section */ 163 #define BOARD_APP_XDMA HPM_XDMA 164 #define BOARD_APP_HDMA HPM_HDMA 165 #define BOARD_APP_XDMA_IRQ IRQn_XDMA 166 #define BOARD_APP_HDMA_IRQ IRQn_HDMA 167 #define BOARD_APP_DMAMUX HPM_DMAMUX 168 169 /* gptmr section */ 170 #define BOARD_GPTMR HPM_GPTMR4 171 #define BOARD_GPTMR_IRQ IRQn_GPTMR4 172 #define BOARD_GPTMR_CHANNEL 1 173 #define BOARD_GPTMR_DMA_SRC HPM_DMA_SRC_GPTMR4_1 174 #define BOARD_GPTMR_CLK_NAME clock_gptmr4 175 #define BOARD_GPTMR_PWM HPM_GPTMR5 176 #define BOARD_GPTMR_PWM_DMA_SRC HPM_DMA_SRC_GPTMR5_2 177 #define BOARD_GPTMR_PWM_CHANNEL 2 178 #define BOARD_GPTMR_PWM_CLK_NAME clock_gptmr5 179 #define BOARD_GPTMR_PWM_IRQ IRQn_GPTMR5 180 #define BOARD_GPTMR_PWM_SYNC HPM_GPTMR5 181 #define BOARD_GPTMR_PWM_SYNC_CHANNEL 3 182 #define BOARD_GPTMR_PWM_SYNC_CLK_NAME clock_gptmr5 183 184 /* gpio section */ 185 #define BOARD_R_GPIO_CTRL HPM_GPIO0 186 #define BOARD_R_GPIO_INDEX GPIO_DI_GPIOB 187 #define BOARD_R_GPIO_PIN 11 188 #define BOARD_G_GPIO_CTRL HPM_GPIO0 189 #define BOARD_G_GPIO_INDEX GPIO_DI_GPIOB 190 #define BOARD_G_GPIO_PIN 12 191 #define BOARD_B_GPIO_CTRL HPM_GPIO0 192 #define BOARD_B_GPIO_INDEX GPIO_DI_GPIOB 193 #define BOARD_B_GPIO_PIN 13 194 195 #define BOARD_LED_GPIO_CTRL HPM_GPIO0 196 197 #define BOARD_LED_GPIO_INDEX GPIO_DI_GPIOB 198 #define BOARD_LED_GPIO_PIN 12 199 #define BOARD_LED_OFF_LEVEL 1 200 #define BOARD_LED_ON_LEVEL 0 201 202 #define BOARD_LED_TOGGLE_RGB 1 203 204 #define BOARD_APP_GPIO_INDEX GPIO_DI_GPIOZ 205 #define BOARD_APP_GPIO_PIN 2 206 207 /* pinmux section */ 208 #define USING_GPIO0_FOR_GPIOZ 209 #ifndef USING_GPIO0_FOR_GPIOZ 210 #define BOARD_APP_GPIO_CTRL HPM_BGPIO 211 #define BOARD_APP_GPIO_IRQ IRQn_BGPIO 212 #else 213 #define BOARD_APP_GPIO_CTRL HPM_GPIO0 214 #define BOARD_APP_GPIO_IRQ IRQn_GPIO0_Z 215 #endif 216 217 /* gpiom section */ 218 #define BOARD_APP_GPIOM_BASE HPM_GPIOM 219 #define BOARD_APP_GPIOM_USING_CTRL HPM_FGPIO 220 #define BOARD_APP_GPIOM_USING_CTRL_NAME gpiom_core0_fast 221 222 /* spi section */ 223 #define BOARD_APP_SPI_BASE HPM_SPI2 224 #define BOARD_APP_SPI_CLK_NAME clock_spi2 225 #define BOARD_APP_SPI_IRQ IRQn_SPI2 226 #define BOARD_APP_SPI_SCLK_FREQ (20000000UL) 227 #define BOARD_APP_SPI_ADDR_LEN_IN_BYTES (1U) 228 #define BOARD_APP_SPI_DATA_LEN_IN_BITS (8U) 229 #define BOARD_APP_SPI_RX_DMA HPM_DMA_SRC_SPI2_RX 230 #define BOARD_APP_SPI_TX_DMA HPM_DMA_SRC_SPI2_TX 231 #define BOARD_SPI_CS_GPIO_CTRL HPM_GPIO0 232 #define BOARD_SPI_CS_PIN IOC_PAD_PE31 233 #define BOARD_SPI_CS_ACTIVE_LEVEL (0U) 234 235 /* Flash section */ 236 #define BOARD_APP_XPI_NOR_XPI_BASE (HPM_XPI0) 237 #define BOARD_APP_XPI_NOR_CFG_OPT_HDR (0xfcf90001U) 238 #define BOARD_APP_XPI_NOR_CFG_OPT_OPT0 (0x00000005U) 239 #define BOARD_APP_XPI_NOR_CFG_OPT_OPT1 (0x00001000U) 240 241 /* lcd section */ 242 243 #ifndef BOARD_LCD_WIDTH 244 #define BOARD_LCD_WIDTH PANEL_SIZE_WIDTH 245 #endif 246 #ifndef BOARD_LCD_HEIGHT 247 #define BOARD_LCD_HEIGHT PANEL_SIZE_HEIGHT 248 #endif 249 250 /* pdma section */ 251 #define BOARD_PDMA_BASE HPM_PDMA 252 253 /* i2s section */ 254 #define BOARD_APP_I2S_BASE HPM_I2S0 255 #define BOARD_APP_I2S_DATA_LINE (2U) 256 #define BOARD_APP_I2S_CLK_NAME clock_i2s0 257 #define BOARD_APP_I2S_TX_DMA_REQ HPM_DMA_SRC_I2S0_TX 258 #define BOARD_APP_I2S_IRQ IRQn_I2S0 259 #define BOARD_APP_AUDIO_CLK_SRC clock_source_pll3_clk0 260 #define BOARD_APP_AUDIO_CLK_SRC_NAME clk_pll3clk0 261 #define BOARD_PDM_SINGLE_CHANNEL_MASK (1U) 262 #define BOARD_PDM_DUAL_CHANNEL_MASK (0x11U) 263 264 /* enet section */ 265 #define BOARD_ENET_COUNT (2U) 266 #define BOARD_ENET_PPS HPM_ENET0 267 #define BOARD_ENET_PPS_IDX enet_pps_0 268 #define BOARD_ENET_PPS_PTP_CLOCK clock_ptp0 269 270 #define BOARD_ENET_RGMII_PHY_ITF enet_inf_rgmii 271 #define BOARD_ENET_RGMII_RST_GPIO HPM_GPIO0 272 #define BOARD_ENET_RGMII_RST_GPIO_INDEX GPIO_DO_GPIOF 273 #define BOARD_ENET_RGMII_RST_GPIO_PIN (0U) 274 #define BOARD_ENET_RGMII HPM_ENET0 275 #define BOARD_ENET_RGMII_TX_DLY (0U) 276 #define BOARD_ENET_RGMII_RX_DLY (23U) 277 #define BOARD_ENET_RGMII_PTP_CLOCK clock_ptp0 278 #define BOARD_ENET_RGMII_PPS0_PINOUT (1) 279 280 #define BOARD_ENET_RMII_PHY_ITF enet_inf_rmii 281 #define BOARD_ENET_RMII_RST_GPIO HPM_GPIO0 282 #define BOARD_ENET_RMII_RST_GPIO_INDEX GPIO_DO_GPIOE 283 #define BOARD_ENET_RMII_RST_GPIO_PIN (26U) 284 #define BOARD_ENET_RMII HPM_ENET1 285 #define BOARD_ENET_RMII_INT_REF_CLK (1U) 286 #define BOARD_ENET_RMII_PTP_CLOCK clock_ptp1 287 #define BOARD_ENET_RMII_PPS0_PINOUT (0) 288 289 /* ADC section */ 290 #define BOARD_APP_ADC12_NAME "ADC0" 291 #define BOARD_APP_ADC12_BASE HPM_ADC0 292 #define BOARD_APP_ADC12_IRQn IRQn_ADC0 293 #define BOARD_APP_ADC12_CH_1 (11U) 294 #define BOARD_APP_ADC12_CH_2 (10U) 295 #define BOARD_APP_ADC12_CH_3 (7U) 296 #define BOARD_APP_ADC12_CLK_NAME (clock_adc0) 297 298 #define BOARD_APP_ADC16_NAME "ADC3" 299 #define BOARD_APP_ADC16_BASE HPM_ADC3 300 #define BOARD_APP_ADC16_IRQn IRQn_ADC3 301 #define BOARD_APP_ADC16_CH_1 (2U) 302 #define BOARD_APP_ADC16_CLK_NAME (clock_adc3) 303 304 #define BOARD_APP_ADC12_HW_TRIG_SRC HPM_PWM0 305 #define BOARD_APP_ADC12_HW_TRGM HPM_TRGM0 306 #define BOARD_APP_ADC12_HW_TRGM_IN HPM_TRGM0_INPUT_SRC_PWM0_CH8REF 307 #define BOARD_APP_ADC12_HW_TRGM_OUT_SEQ TRGM_TRGOCFG_ADC0_STRGI 308 #define BOARD_APP_ADC12_HW_TRGM_OUT_PMT TRGM_TRGOCFG_ADCX_PTRGI0A 309 310 #define BOARD_APP_ADC16_HW_TRIG_SRC HPM_PWM0 311 #define BOARD_APP_ADC16_HW_TRGM HPM_TRGM0 312 #define BOARD_APP_ADC16_HW_TRGM_IN HPM_TRGM0_INPUT_SRC_PWM0_CH8REF 313 #define BOARD_APP_ADC16_HW_TRGM_OUT_SEQ TRGM_TRGOCFG_ADC3_STRGI 314 #define BOARD_APP_ADC16_HW_TRGM_OUT_PMT TRGM_TRGOCFG_ADCX_PTRGI0A 315 316 #define BOARD_APP_ADC12_PMT_TRIG_CH ADC12_CONFIG_TRG0A 317 #define BOARD_APP_ADC16_PMT_TRIG_CH ADC16_CONFIG_TRG0A 318 319 /* CAN section */ 320 #define BOARD_APP_CAN_BASE HPM_CAN0 321 #define BOARD_APP_CAN_IRQn IRQn_CAN0 322 323 324 /* 325 * timer for board delay 326 */ 327 #define BOARD_DELAY_TIMER (HPM_GPTMR7) 328 #define BOARD_DELAY_TIMER_CH 0 329 #define BOARD_DELAY_TIMER_CLK_NAME (clock_gptmr7) 330 331 #define BOARD_CALLBACK_TIMER (HPM_GPTMR7) 332 #define BOARD_CALLBACK_TIMER_CH 1 333 #define BOARD_CALLBACK_TIMER_IRQ IRQn_GPTMR7 334 #define BOARD_CALLBACK_TIMER_CLK_NAME (clock_gptmr7) 335 336 /* SDXC section */ 337 #define BOARD_APP_SDCARD_SDXC_BASE (HPM_SDXC1) 338 #define BOARD_APP_SDCARD_SUPPORT_3V3 (1) 339 #define BOARD_APP_SDCARD_SUPPORT_1V8 (0) 340 #define BOARD_APP_SDCARD_SUPPORT_4BIT (1) 341 #define BOARD_APP_SDCARD_SUPPORT_CARD_DETECTION (1) 342 #define BOARD_APP_SDCARD_SUPPORT_POWER_SWITCH (0) 343 #define BOARD_APP_SDCARD_SUPPORT_VOLTAGE_SWITCH (0) 344 #define BOARD_APP_SDCARD_SUPPORT_CARD_DETECTION (1) 345 #define BOARD_APP_SDCARD_CARD_DETECTION_USING_GPIO (1) 346 #if defined(BOARD_APP_SDCARD_CARD_DETECTION_USING_GPIO) && (BOARD_APP_SDCARD_CARD_DETECTION_USING_GPIO == 1) 347 #define BOARD_APP_SDCARD_CARD_DETECTION_PIN IOC_PAD_PD15 348 #define BOARD_APP_SDCARD_CARD_DETECTION_PIN_POL 1 /* PIN value 0 means card is inserted */ 349 #endif 350 351 #define BOARD_APP_EMMC_SDXC_BASE (HPM_SDXC1) 352 #define BOARD_APP_EMMC_SUPPORT_3V3 (1) 353 #define BOARD_APP_EMMC_SUPPORT_1V8 (0) 354 #define BOARD_APP_EMMC_SUPPORT_4BIT (1) 355 #define BOARD_APP_EMMC_HOST_USING_IRQ (0) 356 357 /* USB section */ 358 #define BOARD_USB0_ID_PORT (HPM_GPIO0) 359 #define BOARD_USB0_ID_GPIO_INDEX (GPIO_DO_GPIOF) 360 #define BOARD_USB0_ID_GPIO_PIN (10) 361 362 #define BOARD_USB0_OC_PORT (HPM_GPIO0) 363 #define BOARD_USB0_OC_GPIO_INDEX (GPIO_DI_GPIOF) 364 #define BOARD_USB0_OC_GPIO_PIN (8) 365 366 #define BOARD_USB1_ID_PORT (HPM_GPIO0) 367 #define BOARD_USB1_ID_GPIO_INDEX (GPIO_DO_GPIOF) 368 #define BOARD_USB1_ID_GPIO_PIN (7) 369 370 #define BOARD_USB1_OC_PORT (HPM_GPIO0) 371 #define BOARD_USB1_OC_GPIO_INDEX (GPIO_DI_GPIOF) 372 #define BOARD_USB1_OC_GPIO_PIN (5) 373 374 /*BLDC pwm*/ 375 376 /*PWM define*/ 377 #define BOARD_BLDCPWM HPM_PWM2 378 #define BOARD_BLDC_UH_PWM_OUTPIN (0U) 379 #define BOARD_BLDC_UL_PWM_OUTPIN (1U) 380 #define BOARD_BLDC_VH_PWM_OUTPIN (2U) 381 #define BOARD_BLDC_VL_PWM_OUTPIN (3U) 382 #define BOARD_BLDC_WH_PWM_OUTPIN (4U) 383 #define BOARD_BLDC_WL_PWM_OUTPIN (5U) 384 #define BOARD_BLDCPWM_TRGM HPM_TRGM2 385 #define BOARD_BLDCAPP_PWM_IRQ IRQn_PWM2 386 #define BOARD_BLDCPWM_CMP_INDEX_0 (0U) 387 #define BOARD_BLDCPWM_CMP_INDEX_1 (1U) 388 #define BOARD_BLDCPWM_CMP_INDEX_2 (2U) 389 #define BOARD_BLDCPWM_CMP_INDEX_3 (3U) 390 #define BOARD_BLDCPWM_CMP_INDEX_4 (4U) 391 #define BOARD_BLDCPWM_CMP_INDEX_5 (5U) 392 #define BOARD_BLDCPWM_CMP_INDEX_6 (6U) 393 #define BOARD_BLDCPWM_CMP_INDEX_7 (7U) 394 #define BOARD_BLDCPWM_CMP_TRIG_CMP (20U) 395 396 /*HALL define*/ 397 398 #define BOARD_BLDC_HALL_BASE HPM_HALL2 399 #define BOARD_BLDC_HALL_TRGM HPM_TRGM2 400 #define BOARD_BLDC_HALL_IRQ IRQn_HALL2 401 #define BOARD_BLDC_HALL_TRGM_HALL_U_SRC HPM_TRGM2_INPUT_SRC_TRGM2_P6 402 #define BOARD_BLDC_HALL_TRGM_HALL_V_SRC HPM_TRGM2_INPUT_SRC_TRGM2_P7 403 #define BOARD_BLDC_HALL_TRGM_HALL_W_SRC HPM_TRGM2_INPUT_SRC_TRGM2_P8 404 #define BOARD_BLDC_HALL_MOTOR_PHASE_COUNT_PER_REV (1000U) 405 406 407 408 /*QEI*/ 409 410 #define BOARD_BLDC_QEI_BASE HPM_QEI2 411 #define BOARD_BLDC_QEI_IRQ IRQn_QEI2 412 #define BOARD_BLDC_QEI_TRGM HPM_TRGM2 413 #define BOARD_BLDC_QEI_TRGM_QEI_A_SRC HPM_TRGM2_INPUT_SRC_TRGM2_P9 414 #define BOARD_BLDC_QEI_TRGM_QEI_B_SRC HPM_TRGM2_INPUT_SRC_TRGM2_P10 415 #define BOARD_BLDC_QEI_MOTOR_PHASE_COUNT_PER_REV (16U) 416 #define BOARD_BLDC_QEI_CLOCK_SOURCE clock_mot2 417 #define BOARD_BLDC_QEI_FOC_PHASE_COUNT_PER_REV (4000U) 418 419 /*Timer define*/ 420 421 #define BOARD_TMR_1MS HPM_GPTMR2 422 #define BOARD_TMR_1MS_CH 0 423 #define BOARD_TMR_1MS_CMP 0 424 #define BOARD_TMR_1MS_IRQ IRQn_GPTMR2 425 #define BOARD_TMR_1MS_RELOAD (100000U) 426 427 #define BOARD_BLDC_TMR_1MS BOARD_TMR_1MS 428 #define BOARD_BLDC_TMR_CH BOARD_TMR_1MS_CH 429 #define BOARD_BLDC_TMR_CMP BOARD_TMR_1MS_CMP 430 #define BOARD_BLDC_TMR_IRQ BOARD_TMR_1MS_IRQ 431 #define BOARD_BLDC_TMR_RELOAD BOARD_TMR_1MS_RELOAD 432 433 /*adc*/ 434 #define BOARD_BLDC_ADC_MODULE ADCX_MODULE_ADC12 435 #define BOARD_BLDC_ADC_U_BASE HPM_ADC0 436 #define BOARD_BLDC_ADC_V_BASE HPM_ADC1 437 #define BOARD_BLDC_ADC_W_BASE HPM_ADC2 438 #define BOARD_BLDC_ADC_TRIG_FLAG adc12_event_trig_complete 439 440 #define BOARD_BLDC_ADC_CH_U (7U) 441 #define BOARD_BLDC_ADC_CH_V (10U) 442 #define BOARD_BLDC_ADC_CH_W (11U) 443 #define BOARD_BLDC_ADC_IRQn IRQn_ADC0 444 #define BOARD_BLDC_ADC_PMT_DMA_SIZE_IN_4BYTES (ADC_SOC_PMT_MAX_DMA_BUFF_LEN_IN_4BYTES) 445 #define BOARD_BLDC_ADC_TRG ADC12_CONFIG_TRG2A 446 #define BOARD_BLDC_ADC_PREEMPT_TRIG_LEN (1U) 447 #define BOARD_BLDC_PWM_TRIG_CMP_INDEX (8U) 448 #define BOARD_BLDC_TRIGMUX_IN_NUM HPM_TRGM2_INPUT_SRC_PWM2_CH8REF 449 #define BOARD_BLDC_TRG_NUM TRGM_TRGOCFG_ADCX_PTRGI0A 450 #define BOARD_BLDC_ADC_IRQn IRQn_ADC0 451 452 /* APP PWM */ 453 #define BOARD_APP_PWM HPM_PWM2 454 #define BOARD_APP_PWM_CLOCK_NAME clock_mot2 455 #define BOARD_APP_PWM_OUT1 0 456 #define BOARD_APP_PWM_OUT2 1 457 #define BOARD_APP_TRGM HPM_TRGM2 458 #define BOARD_APP_PWM_IRQ IRQn_PWM2 459 #define BOARD_APP_TRGM_PWM_OUTPUT TRGM_TRGOCFG_PWM_SYNCI 460 461 /* RGB LED Section */ 462 #define BOARD_RED_PWM_IRQ IRQn_PWM1 463 #define BOARD_RED_PWM HPM_PWM1 464 #define BOARD_RED_PWM_OUT 8 465 #define BOARD_RED_PWM_CMP 8 466 #define BOARD_RED_PWM_CMP_INITIAL_ZERO true 467 #define BOARD_RED_PWM_CLOCK_NAME clock_mot1 468 469 #define BOARD_GREEN_PWM_IRQ IRQn_PWM0 470 #define BOARD_GREEN_PWM HPM_PWM0 471 #define BOARD_GREEN_PWM_OUT 8 472 #define BOARD_GREEN_PWM_CMP 8 473 #define BOARD_GREEN_PWM_CMP_INITIAL_ZERO true 474 #define BOARD_GREEN_PWM_CLOCK_NAME clock_mot0 475 476 #define BOARD_BLUE_PWM_IRQ IRQn_PWM1 477 #define BOARD_BLUE_PWM HPM_PWM1 478 #define BOARD_BLUE_PWM_OUT 9 479 #define BOARD_BLUE_PWM_CMP 9 480 #define BOARD_BLUE_PWM_CMP_INITIAL_ZERO true 481 #define BOARD_BLUE_PWM_CLOCK_NAME clock_mot1 482 483 #define BOARD_RGB_RED 0 484 #define BOARD_RGB_GREEN (BOARD_RGB_RED + 1) 485 #define BOARD_RGB_BLUE (BOARD_RGB_RED + 2) 486 487 #define BOARD_CPU_FREQ (648000000UL) 488 489 #define BOARD_APP_DISPLAY_CLOCK clock_display 490 491 #ifndef BOARD_SHOW_CLOCK 492 #define BOARD_SHOW_CLOCK 1 493 #endif 494 #ifndef BOARD_SHOW_BANNER 495 #define BOARD_SHOW_BANNER 1 496 #endif 497 498 /* FreeRTOS Definitions */ 499 #define BOARD_FREERTOS_TIMER HPM_GPTMR4 500 #define BOARD_FREERTOS_TIMER_CHANNEL 1 501 #define BOARD_FREERTOS_TIMER_IRQ IRQn_GPTMR4 502 #define BOARD_FREERTOS_TIMER_CLK_NAME clock_gptmr4 503 504 #if defined(__cplusplus) 505 extern "C" { 506 #endif /* __cplusplus */ 507 508 typedef void (*board_timer_cb)(void); 509 510 void board_init(void); 511 void board_init_console(void); 512 513 void board_init_uart(UART_Type *ptr); 514 void board_init_i2c(I2C_Type *ptr); 515 void board_init_lcd(void); 516 void board_lcd_backlight(bool is_on); 517 void board_panel_para_to_lcdc(lcdc_config_t *config); 518 void board_init_can(CAN_Type *ptr); 519 520 uint32_t board_init_femc_clock(void); 521 522 void board_init_sdram_pins(void); 523 void board_init_gpio_pins(void); 524 void board_init_spi_pins(SPI_Type *ptr); 525 void board_init_spi_pins_with_gpio_as_cs(SPI_Type *ptr); 526 void board_write_spi_cs(uint32_t pin, uint8_t state); 527 void board_init_led_pins(void); 528 529 /* cap touch */ 530 void board_init_cap_touch(void); 531 532 void board_led_write(uint8_t state); 533 void board_led_toggle(void); 534 535 void board_fpga_power_enable(void); 536 537 void board_init_cam_pins(void); 538 void board_write_cam_rst(uint8_t state); 539 /* Initialize SoC overall clocks */ 540 void board_init_clock(void); 541 542 /* Initialize the UART clock */ 543 uint32_t board_init_uart_clock(UART_Type *ptr); 544 545 /* Initialize the CAM(camera) dot clock */ 546 uint32_t board_init_cam_clock(CAM_Type *ptr); 547 548 /* Initialize the LCD pixel clock */ 549 uint32_t board_init_lcd_clock(void); 550 551 uint32_t board_init_spi_clock(SPI_Type *ptr); 552 553 uint32_t board_init_adc12_clock(ADC12_Type *ptr, bool clk_src_ahb); 554 555 uint32_t board_init_adc16_clock(ADC16_Type *ptr, bool clk_src_ahb); 556 557 uint32_t board_init_can_clock(CAN_Type *ptr); 558 559 hpm_stat_t board_set_audio_pll_clock(uint32_t freq); 560 561 void board_init_i2s_pins(I2S_Type *ptr); 562 uint32_t board_init_i2s_clock(I2S_Type *ptr); 563 uint32_t board_config_i2s_clock(I2S_Type *ptr, uint32_t sample_rate); 564 uint32_t board_init_pdm_clock(void); 565 uint32_t board_init_dao_clock(void); 566 567 uint32_t board_sd_configure_clock(SDXC_Type *ptr, uint32_t freq, bool need_inverse); 568 569 void board_init_dao_pins(void); 570 571 void board_init_adc12_pins(void); 572 void board_init_adc16_pins(void); 573 574 void board_init_usb_pins(void); 575 void board_usb_vbus_ctrl(uint8_t usb_index, uint8_t level); 576 577 void board_init_enet_pps_pins(ENET_Type *ptr); 578 uint8_t board_get_enet_dma_pbl(ENET_Type *ptr); 579 hpm_stat_t board_reset_enet_phy(ENET_Type *ptr); 580 hpm_stat_t board_init_enet_pins(ENET_Type *ptr); 581 hpm_stat_t board_init_enet_rmii_reference_clock(ENET_Type *ptr, bool internal); 582 hpm_stat_t board_init_enet_rgmii_clock_delay(ENET_Type *ptr); 583 hpm_stat_t board_init_enet_ptp_clock(ENET_Type *ptr); 584 hpm_stat_t board_enable_enet_irq(ENET_Type *ptr); 585 hpm_stat_t board_disable_enet_irq(ENET_Type *ptr); 586 587 #if defined(ENET_MULTIPLE_PORT) && ENET_MULTIPLE_PORT 588 hpm_stat_t board_init_multiple_enet_pins(void); 589 hpm_stat_t board_init_multiple_enet_clock(void); 590 hpm_stat_t board_reset_multiple_enet_phy(void); 591 hpm_stat_t board_init_enet_phy(ENET_Type *ptr); 592 ENET_Type *board_get_enet_base(uint8_t idx); 593 uint8_t board_get_enet_phy_itf(uint8_t idx); 594 void board_get_enet_phy_status(uint8_t idx, void *status); 595 #endif 596 597 /* 598 * @brief Initialize PMP and PMA for but not limited to the following purposes: 599 * -- non-cacheable memory initialization 600 */ 601 void board_init_pmp(void); 602 603 void board_delay_ms(uint32_t ms); 604 void board_delay_us(uint32_t us); 605 606 void board_timer_create(uint32_t ms, board_timer_cb cb); 607 608 void board_init_rgb_pwm_pins(void); 609 void board_enable_output_rgb_led(uint8_t color); 610 void board_disable_output_rgb_led(uint8_t color); 611 612 /* 613 * Keep mchtmr clock on low power mode 614 */ 615 void board_ungate_mchtmr_at_lp_mode(void); 616 617 /* 618 * Get PWM output level of onboard LED 619 */ 620 uint8_t board_get_led_pwm_off_level(void); 621 622 /* 623 * Get GPIO pin level of onboard LED 624 */ 625 uint8_t board_get_led_gpio_off_level(void); 626 627 void board_init_trgm0_p6_pin(void); 628 629 #if defined(__cplusplus) 630 } 631 #endif /* __cplusplus */ 632 #endif /* _HPM_BOARD_H */ 633