1 /* 2 * Copyright (c) 2021-2023 HPMicro 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 */ 7 8 #ifndef _HPM_BOARD_H 9 #define _HPM_BOARD_H 10 #include <stdio.h> 11 #include "hpm_common.h" 12 #include "hpm_clock_drv.h" 13 #include "hpm_soc.h" 14 #include "hpm_soc_feature.h" 15 #include "pinmux.h" 16 #include "hpm_lcdc_drv.h" 17 #include "hpm_trgm_drv.h" 18 #ifdef CONFIG_HPM_PANEL 19 #include "hpm_panel.h" 20 #endif 21 #if !defined(CONFIG_NDEBUG_CONSOLE) || !CONFIG_NDEBUG_CONSOLE 22 #include "hpm_debug_console.h" 23 #endif 24 25 #define BOARD_NAME "hpm6750evk2" 26 #define BOARD_UF2_SIGNATURE (0x0A4D5048UL) 27 28 #define SEC_CORE_IMG_START ILM_LOCAL_BASE 29 30 /* uart section */ 31 #ifndef BOARD_RUNNING_CORE 32 #define BOARD_RUNNING_CORE HPM_CORE0 33 #endif 34 #ifndef BOARD_APP_UART_BASE 35 #define BOARD_APP_UART_BASE HPM_UART0 36 #define BOARD_APP_UART_IRQ IRQn_UART0 37 #else 38 #ifndef BOARD_APP_UART_IRQ 39 #warning no IRQ specified for application uart 40 #endif 41 #endif 42 43 /* uart rx idle demo section */ 44 #define BOARD_UART_IDLE HPM_UART13 45 #define BOARD_UART_IDLE_IRQ IRQn_UART13 46 #define BOARD_UART_IDLE_CLK_NAME clock_uart13 47 #define BOARD_UART_IDLE_TX_DMA_SRC HPM_DMA_SRC_UART13_TX 48 #define BOARD_UART_IDLE_DMA_SRC HPM_DMA_SRC_UART13_RX 49 50 #define BOARD_UART_IDLE_TRGM HPM_TRGM2 51 #define BOARD_UART_IDLE_TRGM_PIN IOC_PAD_PD19 52 #define BOARD_UART_IDLE_TRGM_INPUT_SRC HPM_TRGM2_INPUT_SRC_TRGM2_P9 53 #define BOARD_UART_IDLE_TRGM_OUTPUT_GPTMR_IN HPM_TRGM2_OUTPUT_SRC_GPTMR4_IN2 54 #define BOARD_UART_IDLE_TRGM_OUTPUT_GPTMR_SYNCI HPM_TRGM2_OUTPUT_SRC_GPTMR4_SYNCI 55 56 #define BOARD_UART_IDLE_GPTMR HPM_GPTMR4 57 #define BOARD_UART_IDLE_GPTMR_CLK_NAME clock_gptmr4 58 #define BOARD_UART_IDLE_GPTMR_IRQ IRQn_GPTMR4 59 #define BOARD_UART_IDLE_GPTMR_CMP_CH 0 60 #define BOARD_UART_IDLE_GPTMR_CAP_CH 2 61 62 /* uart microros sample section */ 63 #define BOARD_MICROROS_UART_BASE HPM_UART13 64 #define BOARD_MICROROS_UART_IRQ IRQn_UART13 65 #define BOARD_MICROROS_UART_CLK_NAME clock_uart13 66 67 /* uart lin sample section */ 68 #define BOARD_UART_LIN HPM_UART13 69 #define BOARD_UART_LIN_IRQ IRQn_UART13 70 #define BOARD_UART_LIN_CLK_NAME clock_uart13 71 #define BOARD_UART_LIN_TX_PORT GPIO_DI_GPIOZ 72 #define BOARD_UART_LIN_TX_PIN (9U) /* PZ09 should align with used pin in pinmux configuration */ 73 74 #define BOARD_APP_UART_BAUDRATE (115200UL) 75 #define BOARD_APP_UART_CLK_NAME clock_uart0 76 #define BOARD_APP_UART_RX_DMA_REQ HPM_DMA_SRC_UART0_RX 77 #define BOARD_APP_UART_TX_DMA_REQ HPM_DMA_SRC_UART0_TX 78 79 #if !defined(CONFIG_NDEBUG_CONSOLE) || !CONFIG_NDEBUG_CONSOLE 80 #ifndef BOARD_CONSOLE_TYPE 81 #define BOARD_CONSOLE_TYPE CONSOLE_TYPE_UART 82 #endif 83 84 #if BOARD_CONSOLE_TYPE == CONSOLE_TYPE_UART 85 #ifndef BOARD_CONSOLE_BASE 86 #if BOARD_RUNNING_CORE == HPM_CORE0 87 #define BOARD_CONSOLE_BASE HPM_UART0 88 #define BOARD_CONSOLE_CLK_NAME clock_uart0 89 #else 90 #define BOARD_CONSOLE_BASE HPM_UART13 91 #define BOARD_CONSOLE_CLK_NAME clock_uart13 92 #endif 93 #endif 94 #define BOARD_CONSOLE_BAUDRATE (115200UL) 95 #endif 96 #endif 97 98 99 #define BOARD_FREEMASTER_UART_BASE HPM_UART0 100 #define BOARD_FREEMASTER_UART_IRQ IRQn_UART0 101 #define BOARD_FREEMASTER_UART_CLK_NAME clock_uart0 102 103 /* sdram section */ 104 #define BOARD_SDRAM_ADDRESS (0x40000000UL) 105 #define BOARD_SDRAM_SIZE (32*SIZE_1MB) 106 #define BOARD_SDRAM_CS FEMC_SDRAM_CS0 107 #define BOARD_SDRAM_PORT_SIZE FEMC_SDRAM_PORT_SIZE_32_BITS 108 #define BOARD_SDRAM_REFRESH_COUNT (8192UL) 109 #define BOARD_SDRAM_REFRESH_IN_MS (64UL) 110 #define BOARD_SDRAM_DATA_WIDTH_IN_BYTE (4UL) 111 112 #define BOARD_FLASH_BASE_ADDRESS (0x80000000UL) 113 #define BOARD_FLASH_SIZE (16 << 20) 114 115 /* lcd section */ 116 #define BOARD_LCD_BASE HPM_LCDC 117 #define BOARD_LCD_IRQ IRQn_LCDC_D0 118 #define BOARD_LCD_RESET_GPIO_BASE HPM_GPIO0 119 #define BOARD_LCD_RESET_GPIO_INDEX GPIO_DO_GPIOB 120 #define BOARD_LCD_RESET_GPIO_PIN 16 121 #define BOARD_LCD_BACKLIGHT_GPIO_BASE HPM_GPIO0 122 #define BOARD_LCD_BACKLIGHT_GPIO_INDEX GPIO_DO_GPIOB 123 #define BOARD_LCD_BACKLIGHT_GPIO_PIN 10 124 #define BOARD_LCD_POWER_EN_GPIO_BASE HPM_GPIO0 125 #define BOARD_LCD_POWER_EN_GPIO_INDEX GPIO_DO_GPIOZ 126 #define BOARD_LCD_POWER_EN_GPIO_PIN 00 127 128 /* i2c section */ 129 #define BOARD_APP_I2C_BASE HPM_I2C0 130 #define BOARD_APP_I2C_IRQ IRQn_I2C0 131 #define BOARD_APP_I2C_CLK_NAME clock_i2c0 132 #define BOARD_APP_I2C_DMA HPM_HDMA 133 #define BOARD_APP_I2C_DMAMUX HPM_DMAMUX 134 #define BOARD_APP_I2C_DMA_SRC HPM_DMA_SRC_I2C0 135 136 #define BOARD_CAM_I2C_BASE HPM_I2C0 137 #define BOARD_CAM_I2C_CLK_NAME clock_i2c0 138 #define BOARD_SUPPORT_CAM_RESET 139 #define BOARD_CAM_RST_GPIO_CTRL HPM_GPIO0 140 #define BOARD_CAM_RST_GPIO_INDEX GPIO_DI_GPIOY 141 #define BOARD_CAM_RST_GPIO_PIN 5 142 143 #define BOARD_CAP_I2C_BASE (HPM_I2C0) 144 #define BOARD_CAP_I2C_CLK_NAME clock_i2c0 145 #define BOARD_CAP_RST_GPIO (HPM_GPIO0) 146 #define BOARD_CAP_RST_GPIO_INDEX (GPIO_DI_GPIOB) 147 #define BOARD_CAP_RST_GPIO_PIN (9) 148 #define BOARD_CAP_RST_GPIO_IRQ (IRQn_GPIO0_B) 149 #define BOARD_CAP_INTR_GPIO (HPM_GPIO0) 150 #define BOARD_CAP_INTR_GPIO_INDEX (GPIO_DI_GPIOB) 151 #define BOARD_CAP_INTR_GPIO_PIN (8) 152 #define BOARD_CAP_INTR_GPIO_IRQ (IRQn_GPIO0_B) 153 #define BOARD_CAP_I2C_SDA_GPIO_INDEX (GPIO_DI_GPIOZ) 154 #define BOARD_CAP_I2C_SDA_GPIO_PIN (10) 155 #define BOARD_CAP_I2C_CLK_GPIO_INDEX (GPIO_DI_GPIOZ) 156 #define BOARD_CAP_I2C_CLK_GPIO_PIN (11) 157 158 /* ACMP desction */ 159 #define BOARD_ACMP HPM_ACMP 160 #define BOARD_ACMP_CHANNEL ACMP_CHANNEL_CHN1 161 #define BOARD_ACMP_IRQ IRQn_ACMP_1 162 #define BOARD_ACMP_PLUS_INPUT ACMP_INPUT_DAC_OUT /* use internal DAC */ 163 #define BOARD_ACMP_MINUS_INPUT ACMP_INPUT_ANALOG_6 /* align with used pin */ 164 165 /* dma section */ 166 #define BOARD_APP_XDMA HPM_XDMA 167 #define BOARD_APP_HDMA HPM_HDMA 168 #define BOARD_APP_XDMA_IRQ IRQn_XDMA 169 #define BOARD_APP_HDMA_IRQ IRQn_HDMA 170 #define BOARD_APP_DMAMUX HPM_DMAMUX 171 172 /* gptmr section */ 173 #define BOARD_GPTMR HPM_GPTMR4 174 #define BOARD_GPTMR_IRQ IRQn_GPTMR4 175 #define BOARD_GPTMR_CHANNEL 1 176 #define BOARD_GPTMR_DMA_SRC HPM_DMA_SRC_GPTMR4_1 177 #define BOARD_GPTMR_CLK_NAME clock_gptmr4 178 #define BOARD_GPTMR_PWM HPM_GPTMR5 179 #define BOARD_GPTMR_PWM_DMA_SRC HPM_DMA_SRC_GPTMR5_2 180 #define BOARD_GPTMR_PWM_CHANNEL 2 181 #define BOARD_GPTMR_PWM_CLK_NAME clock_gptmr5 182 #define BOARD_GPTMR_PWM_IRQ IRQn_GPTMR5 183 #define BOARD_GPTMR_PWM_SYNC HPM_GPTMR5 184 #define BOARD_GPTMR_PWM_SYNC_CHANNEL 3 185 #define BOARD_GPTMR_PWM_SYNC_CLK_NAME clock_gptmr5 186 187 /* gpio section */ 188 #define BOARD_R_GPIO_CTRL HPM_GPIO0 189 #define BOARD_R_GPIO_INDEX GPIO_DI_GPIOB 190 #define BOARD_R_GPIO_PIN 11 191 #define BOARD_G_GPIO_CTRL HPM_GPIO0 192 #define BOARD_G_GPIO_INDEX GPIO_DI_GPIOB 193 #define BOARD_G_GPIO_PIN 12 194 #define BOARD_B_GPIO_CTRL HPM_GPIO0 195 #define BOARD_B_GPIO_INDEX GPIO_DI_GPIOB 196 #define BOARD_B_GPIO_PIN 13 197 198 #define BOARD_LED_GPIO_CTRL HPM_GPIO0 199 200 #define BOARD_LED_GPIO_INDEX GPIO_DI_GPIOB 201 #define BOARD_LED_GPIO_PIN 12 202 #define BOARD_LED_OFF_LEVEL 0 203 #define BOARD_LED_ON_LEVEL 1 204 205 #define BOARD_LED_TOGGLE_RGB 1 206 207 #define BOARD_APP_GPIO_INDEX GPIO_DI_GPIOZ 208 #define BOARD_APP_GPIO_PIN 2 209 210 /* pinmux section */ 211 #define USING_GPIO0_FOR_GPIOZ 212 #ifndef USING_GPIO0_FOR_GPIOZ 213 #define BOARD_APP_GPIO_CTRL HPM_BGPIO 214 #define BOARD_APP_GPIO_IRQ IRQn_BGPIO 215 #else 216 #define BOARD_APP_GPIO_CTRL HPM_GPIO0 217 #define BOARD_APP_GPIO_IRQ IRQn_GPIO0_Z 218 #endif 219 220 /* gpiom section */ 221 #define BOARD_APP_GPIOM_BASE HPM_GPIOM 222 #define BOARD_APP_GPIOM_USING_CTRL HPM_FGPIO 223 #define BOARD_APP_GPIOM_USING_CTRL_NAME gpiom_core0_fast 224 225 /* spi section */ 226 #define BOARD_APP_SPI_BASE HPM_SPI2 227 #define BOARD_APP_SPI_CLK_NAME clock_spi2 228 #define BOARD_APP_SPI_IRQ IRQn_SPI2 229 #define BOARD_APP_SPI_SCLK_FREQ (20000000UL) 230 #define BOARD_APP_SPI_ADDR_LEN_IN_BYTES (1U) 231 #define BOARD_APP_SPI_DATA_LEN_IN_BITS (8U) 232 #define BOARD_APP_SPI_RX_DMA HPM_DMA_SRC_SPI2_RX 233 #define BOARD_APP_SPI_TX_DMA HPM_DMA_SRC_SPI2_TX 234 #define BOARD_SPI_CS_GPIO_CTRL HPM_GPIO0 235 #define BOARD_SPI_CS_PIN IOC_PAD_PE31 236 #define BOARD_SPI_CS_ACTIVE_LEVEL (0U) 237 238 /* Flash section */ 239 #define BOARD_APP_XPI_NOR_XPI_BASE (HPM_XPI0) 240 #define BOARD_APP_XPI_NOR_CFG_OPT_HDR (0xfcf90001U) 241 #define BOARD_APP_XPI_NOR_CFG_OPT_OPT0 (0x00000005U) 242 #define BOARD_APP_XPI_NOR_CFG_OPT_OPT1 (0x00001000U) 243 244 /* lcd section */ 245 246 #ifndef BOARD_LCD_WIDTH 247 #define BOARD_LCD_WIDTH PANEL_SIZE_WIDTH 248 #endif 249 #ifndef BOARD_LCD_HEIGHT 250 #define BOARD_LCD_HEIGHT PANEL_SIZE_HEIGHT 251 #endif 252 253 /* pdma section */ 254 #define BOARD_PDMA_BASE HPM_PDMA 255 256 /* i2s section */ 257 #define BOARD_APP_I2S_BASE HPM_I2S0 258 #define BOARD_APP_I2S_DATA_LINE (2U) 259 #define BOARD_APP_I2S_CLK_NAME clock_i2s0 260 #define BOARD_APP_I2S_TX_DMA_REQ HPM_DMA_SRC_I2S0_TX 261 #define BOARD_APP_I2S_IRQ IRQn_I2S0 262 #define BOARD_APP_AUDIO_CLK_SRC clock_source_pll3_clk0 263 #define BOARD_APP_AUDIO_CLK_SRC_NAME clk_pll3clk0 264 #define BOARD_PDM_SINGLE_CHANNEL_MASK (1U) 265 #define BOARD_PDM_DUAL_CHANNEL_MASK (0x11U) 266 267 /* enet section */ 268 #define BOARD_ENET_COUNT (2U) 269 #define BOARD_ENET_PPS HPM_ENET0 270 #define BOARD_ENET_PPS_IDX enet_pps_0 271 #define BOARD_ENET_PPS_PTP_CLOCK clock_ptp0 272 273 #define BOARD_ENET_RGMII_PHY_ITF enet_inf_rgmii 274 #define BOARD_ENET_RGMII_RST_GPIO HPM_GPIO0 275 #define BOARD_ENET_RGMII_RST_GPIO_INDEX GPIO_DO_GPIOF 276 #define BOARD_ENET_RGMII_RST_GPIO_PIN (0U) 277 #define BOARD_ENET_RGMII HPM_ENET0 278 #define BOARD_ENET_RGMII_TX_DLY (0U) 279 #define BOARD_ENET_RGMII_RX_DLY (7U) 280 #define BOARD_ENET_RGMII_PTP_CLOCK (clock_ptp0) 281 #define BOARD_ENET_RGMII_PPS0_PINOUT (1) 282 283 #define BOARD_ENET_RMII_PHY_ITF enet_inf_rmii 284 #define BOARD_ENET_RMII_RST_GPIO HPM_GPIO0 285 #define BOARD_ENET_RMII_RST_GPIO_INDEX GPIO_DO_GPIOE 286 #define BOARD_ENET_RMII_RST_GPIO_PIN (26U) 287 #define BOARD_ENET_RMII HPM_ENET1 288 #define BOARD_ENET_RMII_INT_REF_CLK (1U) 289 #define BOARD_ENET_RMII_PTP_CLOCK (clock_ptp1) 290 #define BOARD_ENET_RMII_PPS0_PINOUT (0) 291 292 /* ADC section */ 293 #define BOARD_APP_ADC12_NAME "ADC0" 294 #define BOARD_APP_ADC12_BASE HPM_ADC0 295 #define BOARD_APP_ADC12_IRQn IRQn_ADC0 296 #define BOARD_APP_ADC12_CH_1 (11U) 297 #define BOARD_APP_ADC12_CH_2 (10U) 298 #define BOARD_APP_ADC12_CH_3 (7U) 299 #define BOARD_APP_ADC12_CLK_NAME (clock_adc0) 300 301 #define BOARD_APP_ADC16_NAME "ADC3" 302 #define BOARD_APP_ADC16_BASE HPM_ADC3 303 #define BOARD_APP_ADC16_IRQn IRQn_ADC3 304 #define BOARD_APP_ADC16_CH_1 (2U) 305 #define BOARD_APP_ADC16_CLK_NAME (clock_adc3) 306 307 #define BOARD_APP_ADC12_HW_TRIG_SRC HPM_PWM0 308 #define BOARD_APP_ADC12_HW_TRGM HPM_TRGM0 309 #define BOARD_APP_ADC12_HW_TRGM_IN HPM_TRGM0_INPUT_SRC_PWM0_CH8REF 310 #define BOARD_APP_ADC12_HW_TRGM_OUT_SEQ TRGM_TRGOCFG_ADC0_STRGI 311 #define BOARD_APP_ADC12_HW_TRGM_OUT_PMT TRGM_TRGOCFG_ADCX_PTRGI0A 312 313 #define BOARD_APP_ADC16_HW_TRIG_SRC HPM_PWM0 314 #define BOARD_APP_ADC16_HW_TRGM HPM_TRGM0 315 #define BOARD_APP_ADC16_HW_TRGM_IN HPM_TRGM0_INPUT_SRC_PWM0_CH8REF 316 #define BOARD_APP_ADC16_HW_TRGM_OUT_SEQ TRGM_TRGOCFG_ADC3_STRGI 317 #define BOARD_APP_ADC16_HW_TRGM_OUT_PMT TRGM_TRGOCFG_ADCX_PTRGI0A 318 319 #define BOARD_APP_ADC12_PMT_TRIG_CH ADC12_CONFIG_TRG0A 320 #define BOARD_APP_ADC16_PMT_TRIG_CH ADC16_CONFIG_TRG0A 321 322 /* CAN section */ 323 #define BOARD_APP_CAN_BASE HPM_CAN0 324 #define BOARD_APP_CAN_IRQn IRQn_CAN0 325 326 327 /* 328 * timer for board delay 329 */ 330 #define BOARD_DELAY_TIMER (HPM_GPTMR7) 331 #define BOARD_DELAY_TIMER_CH 0 332 #define BOARD_DELAY_TIMER_CLK_NAME (clock_gptmr7) 333 334 #define BOARD_CALLBACK_TIMER (HPM_GPTMR7) 335 #define BOARD_CALLBACK_TIMER_CH 1 336 #define BOARD_CALLBACK_TIMER_IRQ IRQn_GPTMR7 337 #define BOARD_CALLBACK_TIMER_CLK_NAME (clock_gptmr7) 338 339 /* SDXC section */ 340 #define BOARD_APP_SDCARD_SDXC_BASE (HPM_SDXC1) 341 #define BOARD_APP_SDCARD_SUPPORT_3V3 (1) 342 #define BOARD_APP_SDCARD_SUPPORT_1V8 (0) 343 #define BOARD_APP_SDCARD_SUPPORT_4BIT (1) 344 #define BOARD_APP_SDCARD_SUPPORT_CARD_DETECTION (1) 345 #define BOARD_APP_SDCARD_SUPPORT_POWER_SWITCH (1) 346 #define BOARD_APP_SDCARD_POWER_SWITCH_USING_GPIO (1) 347 #define BOARD_APP_SDCARD_SUPPORT_VOLTAGE_SWITCH (0) 348 #define BOARD_APP_SDCARD_SUPPORT_CARD_DETECTION (1) 349 #define BOARD_APP_SDCARD_CARD_DETECTION_USING_GPIO (1) 350 #if defined(BOARD_APP_SDCARD_CARD_DETECTION_USING_GPIO) && (BOARD_APP_SDCARD_CARD_DETECTION_USING_GPIO == 1) 351 #define BOARD_APP_SDCARD_CARD_DETECTION_PIN IOC_PAD_PD15 352 #define BOARD_APP_SDCARD_CARD_DETECTION_PIN_POL 1 /* PIN value 0 means card is inserted */ 353 #endif 354 #if defined(BOARD_APP_SDCARD_POWER_SWITCH_USING_GPIO) && (BOARD_APP_SDCARD_POWER_SWITCH_USING_GPIO == 1) 355 #define BOARD_APP_SDCARD_POWER_SWITCH_PIN IOC_PAD_PC20 356 #define BOARD_APP_SDCARD_POWER_SWITCH_PIN_POL 0 /* PIN value 1 means power is supplied */ 357 #endif 358 359 360 #define BOARD_APP_EMMC_SDXC_BASE (HPM_SDXC1) 361 #define BOARD_APP_EMMC_SUPPORT_3V3 (1) 362 #define BOARD_APP_EMMC_SUPPORT_1V8 (0) 363 #define BOARD_APP_EMMC_SUPPORT_4BIT (1) 364 #define BOARD_APP_EMMC_SUPPORT_POWER_SWITCH (1) 365 #define BOARD_APP_EMMC_POWER_SWITCH_USING_GPIO (1) 366 #define BOARD_APP_EMMC_HOST_USING_IRQ (0) 367 #if defined(BOARD_APP_EMMC_POWER_SWITCH_USING_GPIO) && (BOARD_APP_EMMC_POWER_SWITCH_USING_GPIO == 1) 368 #define BOARD_APP_EMMC_POWER_SWITCH_PIN IOC_PAD_PC20 369 #define BOARD_APP_EMMC_POWER_SWITCH_PIN_POL 0 /* PIN value 1 means power is supplied */ 370 #endif 371 372 /* USB section */ 373 #define BOARD_USB0_ID_PORT (HPM_GPIO0) 374 #define BOARD_USB0_ID_GPIO_INDEX (GPIO_DO_GPIOF) 375 #define BOARD_USB0_ID_GPIO_PIN (10) 376 377 #define BOARD_USB0_OC_PORT (HPM_GPIO0) 378 #define BOARD_USB0_OC_GPIO_INDEX (GPIO_DI_GPIOF) 379 #define BOARD_USB0_OC_GPIO_PIN (8) 380 381 #define BOARD_USB1_ID_PORT (HPM_GPIO0) 382 #define BOARD_USB1_ID_GPIO_INDEX (GPIO_DO_GPIOF) 383 #define BOARD_USB1_ID_GPIO_PIN (7) 384 385 #define BOARD_USB1_OC_PORT (HPM_GPIO0) 386 #define BOARD_USB1_OC_GPIO_INDEX (GPIO_DI_GPIOF) 387 #define BOARD_USB1_OC_GPIO_PIN (5) 388 389 /*BLDC pwm*/ 390 391 /*PWM define*/ 392 #define BOARD_BLDCPWM HPM_PWM2 393 #define BOARD_BLDC_UH_PWM_OUTPIN (0U) 394 #define BOARD_BLDC_UL_PWM_OUTPIN (1U) 395 #define BOARD_BLDC_VH_PWM_OUTPIN (2U) 396 #define BOARD_BLDC_VL_PWM_OUTPIN (3U) 397 #define BOARD_BLDC_WH_PWM_OUTPIN (4U) 398 #define BOARD_BLDC_WL_PWM_OUTPIN (5U) 399 #define BOARD_BLDCPWM_TRGM HPM_TRGM2 400 #define BOARD_BLDCAPP_PWM_IRQ IRQn_PWM2 401 #define BOARD_BLDCPWM_CMP_INDEX_0 (0U) 402 #define BOARD_BLDCPWM_CMP_INDEX_1 (1U) 403 #define BOARD_BLDCPWM_CMP_INDEX_2 (2U) 404 #define BOARD_BLDCPWM_CMP_INDEX_3 (3U) 405 #define BOARD_BLDCPWM_CMP_INDEX_4 (4U) 406 #define BOARD_BLDCPWM_CMP_INDEX_5 (5U) 407 #define BOARD_BLDCPWM_CMP_INDEX_6 (6U) 408 #define BOARD_BLDCPWM_CMP_INDEX_7 (7U) 409 #define BOARD_BLDCPWM_CMP_TRIG_CMP (20U) 410 411 /*HALL define*/ 412 413 #define BOARD_BLDC_HALL_BASE HPM_HALL2 414 #define BOARD_BLDC_HALL_TRGM HPM_TRGM2 415 #define BOARD_BLDC_HALL_IRQ IRQn_HALL2 416 #define BOARD_BLDC_HALL_TRGM_HALL_U_SRC HPM_TRGM2_INPUT_SRC_TRGM2_P6 417 #define BOARD_BLDC_HALL_TRGM_HALL_V_SRC HPM_TRGM2_INPUT_SRC_TRGM2_P7 418 #define BOARD_BLDC_HALL_TRGM_HALL_W_SRC HPM_TRGM2_INPUT_SRC_TRGM2_P8 419 #define BOARD_BLDC_HALL_MOTOR_PHASE_COUNT_PER_REV (1000U) 420 421 422 423 /*QEI*/ 424 425 #define BOARD_BLDC_QEI_BASE HPM_QEI2 426 #define BOARD_BLDC_QEI_IRQ IRQn_QEI2 427 #define BOARD_BLDC_QEI_TRGM HPM_TRGM2 428 #define BOARD_BLDC_QEI_TRGM_QEI_A_SRC HPM_TRGM2_INPUT_SRC_TRGM2_P9 429 #define BOARD_BLDC_QEI_TRGM_QEI_B_SRC HPM_TRGM2_INPUT_SRC_TRGM2_P10 430 #define BOARD_BLDC_QEI_MOTOR_PHASE_COUNT_PER_REV (16U) 431 #define BOARD_BLDC_QEI_CLOCK_SOURCE clock_mot2 432 #define BOARD_BLDC_QEI_FOC_PHASE_COUNT_PER_REV (4000U) 433 434 /*HFI define*/ 435 #define MOTOR0_HFI_SPD (0.5) 436 #define MOTOR0_HFI_KP (40) 437 438 /*Timer define*/ 439 440 #define BOARD_TMR_1MS HPM_GPTMR2 441 #define BOARD_TMR_1MS_CH 0 442 #define BOARD_TMR_1MS_CMP 0 443 #define BOARD_TMR_1MS_IRQ IRQn_GPTMR2 444 #define BOARD_TMR_1MS_RELOAD (100000U) 445 446 #define BOARD_BLDC_TMR_1MS BOARD_TMR_1MS 447 #define BOARD_BLDC_TMR_CH BOARD_TMR_1MS_CH 448 #define BOARD_BLDC_TMR_CMP BOARD_TMR_1MS_CMP 449 #define BOARD_BLDC_TMR_IRQ BOARD_TMR_1MS_IRQ 450 #define BOARD_BLDC_TMR_RELOAD BOARD_TMR_1MS_RELOAD 451 452 /*adc*/ 453 #define BOARD_BLDC_ADC_MODULE ADCX_MODULE_ADC12 454 #define BOARD_BLDC_ADC_U_BASE HPM_ADC0 455 #define BOARD_BLDC_ADC_V_BASE HPM_ADC1 456 #define BOARD_BLDC_ADC_W_BASE HPM_ADC2 457 #define BOARD_BLDC_ADC_TRIG_FLAG adc12_event_trig_complete 458 459 #define BOARD_BLDC_ADC_CH_U (7U) 460 #define BOARD_BLDC_ADC_CH_V (10U) 461 #define BOARD_BLDC_ADC_CH_W (11U) 462 #define BOARD_BLDC_ADC_IRQn IRQn_ADC0 463 #define BOARD_BLDC_ADC_PMT_DMA_SIZE_IN_4BYTES (ADC_SOC_PMT_MAX_DMA_BUFF_LEN_IN_4BYTES) 464 #define BOARD_BLDC_ADC_TRG ADC12_CONFIG_TRG2A 465 #define BOARD_BLDC_ADC_PREEMPT_TRIG_LEN (1U) 466 #define BOARD_BLDC_PWM_TRIG_CMP_INDEX (8U) 467 #define BOARD_BLDC_TRIGMUX_IN_NUM HPM_TRGM2_INPUT_SRC_PWM2_CH8REF 468 #define BOARD_BLDC_TRG_NUM TRGM_TRGOCFG_ADCX_PTRGI0A 469 #define BOARD_BLDC_ADC_IRQn IRQn_ADC0 470 471 /* APP PWM */ 472 #define BOARD_APP_PWM HPM_PWM2 473 #define BOARD_APP_PWM_CLOCK_NAME clock_mot2 474 #define BOARD_APP_PWM_OUT1 0 475 #define BOARD_APP_PWM_OUT2 1 476 #define BOARD_APP_TRGM HPM_TRGM2 477 #define BOARD_APP_PWM_IRQ IRQn_PWM2 478 #define BOARD_APP_TRGM_PWM_OUTPUT TRGM_TRGOCFG_PWM_SYNCI 479 480 /* RGB LED Section */ 481 #define BOARD_RED_PWM_IRQ IRQn_PWM1 482 #define BOARD_RED_PWM HPM_PWM1 483 #define BOARD_RED_PWM_OUT 8 484 #define BOARD_RED_PWM_CMP 8 485 #define BOARD_RED_PWM_CMP_INITIAL_ZERO true 486 #define BOARD_RED_PWM_CLOCK_NAME clock_mot1 487 488 #define BOARD_GREEN_PWM_IRQ IRQn_PWM0 489 #define BOARD_GREEN_PWM HPM_PWM0 490 #define BOARD_GREEN_PWM_OUT 8 491 #define BOARD_GREEN_PWM_CMP 8 492 #define BOARD_GREEN_PWM_CMP_INITIAL_ZERO true 493 #define BOARD_GREEN_PWM_CLOCK_NAME clock_mot0 494 495 #define BOARD_BLUE_PWM_IRQ IRQn_PWM1 496 #define BOARD_BLUE_PWM HPM_PWM1 497 #define BOARD_BLUE_PWM_OUT 9 498 #define BOARD_BLUE_PWM_CMP 9 499 #define BOARD_BLUE_PWM_CMP_INITIAL_ZERO true 500 #define BOARD_BLUE_PWM_CLOCK_NAME clock_mot1 501 502 #define BOARD_RGB_RED 0 503 #define BOARD_RGB_GREEN (BOARD_RGB_RED + 1) 504 #define BOARD_RGB_BLUE (BOARD_RGB_RED + 2) 505 506 #define BOARD_CPU_FREQ (648000000UL) 507 508 #define BOARD_APP_DISPLAY_CLOCK clock_display 509 510 #ifndef BOARD_SHOW_CLOCK 511 #define BOARD_SHOW_CLOCK 1 512 #endif 513 #ifndef BOARD_SHOW_BANNER 514 #define BOARD_SHOW_BANNER 1 515 #endif 516 517 /* FreeRTOS Definitions */ 518 #define BOARD_FREERTOS_TIMER HPM_GPTMR6 519 #define BOARD_FREERTOS_TIMER_CHANNEL 1 520 #define BOARD_FREERTOS_TIMER_IRQ IRQn_GPTMR6 521 #define BOARD_FREERTOS_TIMER_CLK_NAME clock_gptmr6 522 523 #if defined(__cplusplus) 524 extern "C" { 525 #endif /* __cplusplus */ 526 527 typedef void (*board_timer_cb)(void); 528 529 void board_init(void); 530 void board_init_console(void); 531 532 void board_init_uart(UART_Type *ptr); 533 void board_init_i2c(I2C_Type *ptr); 534 void board_init_lcd(void); 535 void board_lcd_backlight(bool is_on); 536 void board_panel_para_to_lcdc(lcdc_config_t *config); 537 void board_init_can(CAN_Type *ptr); 538 539 uint32_t board_init_femc_clock(void); 540 541 void board_init_sdram_pins(void); 542 void board_init_gpio_pins(void); 543 void board_init_spi_pins(SPI_Type *ptr); 544 void board_init_spi_pins_with_gpio_as_cs(SPI_Type *ptr); 545 void board_write_spi_cs(uint32_t pin, uint8_t state); 546 void board_init_led_pins(void); 547 548 /* cap touch */ 549 void board_init_cap_touch(void); 550 551 void board_led_write(uint8_t state); 552 void board_led_toggle(void); 553 554 void board_fpga_power_enable(void); 555 556 void board_init_cam_pins(void); 557 void board_write_cam_rst(uint8_t state); 558 /* Initialize SoC overall clocks */ 559 void board_init_clock(void); 560 561 /* Initialize the UART clock */ 562 uint32_t board_init_uart_clock(UART_Type *ptr); 563 564 /* Initialize the CAM(camera) dot clock */ 565 uint32_t board_init_cam_clock(CAM_Type *ptr); 566 567 /* Initialize the LCD pixel clock */ 568 uint32_t board_init_lcd_clock(void); 569 570 uint32_t board_init_spi_clock(SPI_Type *ptr); 571 572 uint32_t board_init_adc12_clock(ADC12_Type *ptr, bool clk_src_ahb); 573 574 uint32_t board_init_adc16_clock(ADC16_Type *ptr, bool clk_src_ahb); 575 576 uint32_t board_init_can_clock(CAN_Type *ptr); 577 578 hpm_stat_t board_set_audio_pll_clock(uint32_t freq); 579 580 void board_init_i2s_pins(I2S_Type *ptr); 581 uint32_t board_init_i2s_clock(I2S_Type *ptr); 582 uint32_t board_config_i2s_clock(I2S_Type *ptr, uint32_t sample_rate); 583 uint32_t board_init_pdm_clock(void); 584 uint32_t board_init_dao_clock(void); 585 586 uint32_t board_sd_configure_clock(SDXC_Type *ptr, uint32_t freq, bool need_inverse); 587 588 void board_init_dao_pins(void); 589 590 void board_init_adc12_pins(void); 591 void board_init_adc16_pins(void); 592 593 void board_init_usb_pins(void); 594 void board_usb_vbus_ctrl(uint8_t usb_index, uint8_t level); 595 596 void board_init_enet_pps_pins(ENET_Type *ptr); 597 uint8_t board_get_enet_dma_pbl(ENET_Type *ptr); 598 hpm_stat_t board_reset_enet_phy(ENET_Type *ptr); 599 hpm_stat_t board_init_enet_pins(ENET_Type *ptr); 600 hpm_stat_t board_init_enet_rmii_reference_clock(ENET_Type *ptr, bool internal); 601 hpm_stat_t board_init_enet_rgmii_clock_delay(ENET_Type *ptr); 602 hpm_stat_t board_init_enet_ptp_clock(ENET_Type *ptr); 603 hpm_stat_t board_enable_enet_irq(ENET_Type *ptr); 604 hpm_stat_t board_disable_enet_irq(ENET_Type *ptr); 605 606 #if defined(ENET_MULTIPLE_PORT) && ENET_MULTIPLE_PORT 607 hpm_stat_t board_init_multiple_enet_pins(void); 608 hpm_stat_t board_init_multiple_enet_clock(void); 609 hpm_stat_t board_reset_multiple_enet_phy(void); 610 hpm_stat_t board_init_enet_phy(ENET_Type *ptr); 611 ENET_Type *board_get_enet_base(uint8_t idx); 612 uint8_t board_get_enet_phy_itf(uint8_t idx); 613 void board_get_enet_phy_status(uint8_t idx, void *status); 614 #endif 615 616 /* 617 * @brief Initialize PMP and PMA for but not limited to the following purposes: 618 * -- non-cacheable memory initialization 619 */ 620 void board_init_pmp(void); 621 622 void board_delay_ms(uint32_t ms); 623 void board_delay_us(uint32_t us); 624 625 void board_timer_create(uint32_t ms, board_timer_cb cb); 626 627 void board_init_rgb_pwm_pins(void); 628 void board_enable_output_rgb_led(uint8_t color); 629 void board_disable_output_rgb_led(uint8_t color); 630 631 /* 632 * Keep mchtmr clock on low power mode 633 */ 634 void board_ungate_mchtmr_at_lp_mode(void); 635 636 /* 637 * Get PWM output level of onboard LED 638 */ 639 uint8_t board_get_led_pwm_off_level(void); 640 641 /* 642 * Get GPIO pin level of onboard LED 643 */ 644 uint8_t board_get_led_gpio_off_level(void); 645 #if defined(__cplusplus) 646 } 647 #endif /* __cplusplus */ 648 #endif /* _HPM_BOARD_H */ 649