1 /*
2 * Copyright (c) 2023 HPMicro
3 * SPDX-License-Identifier: BSD-3-Clause
4 *
5 *
6 */
7
8 #include "board.h"
9 #include "hpm_uart_drv.h"
10 #include "hpm_gptmr_drv.h"
11 #include "hpm_lcdc_drv.h"
12 #include "hpm_i2c_drv.h"
13 #include "hpm_gpio_drv.h"
14 #include "pinmux.h"
15 #include "hpm_pmp_drv.h"
16 #include "hpm_clock_drv.h"
17 #include "hpm_sysctl_drv.h"
18 #include "hpm_pllctlv2_drv.h"
19 #include "hpm_sdxc_drv.h"
20 #include "hpm_ddrctl_regs.h"
21 #include "hpm_ddrphy_regs.h"
22 #include "hpm_pcfg_drv.h"
23 #include "hpm_pixelmux_drv.h"
24 #include "hpm_lvb_drv.h"
25 #include "hpm_enet_drv.h"
26 #include "hpm_usb_drv.h"
27 #include "hpm_mipi_dsi_drv.h"
28 #include "hpm_mipi_dsi_phy_drv.h"
29
30 static board_timer_cb timer_cb;
31
32 /**
33 * @brief FLASH configuration option definitions:
34 * option[0]:
35 * [31:16] 0xfcf9 - FLASH configuration option tag
36 * [15:4] 0 - Reserved
37 * [3:0] option words (exclude option[0])
38 * option[1]:
39 * [31:28] Flash probe type
40 * 0 - SFDP SDR / 1 - SFDP DDR
41 * 2 - 1-4-4 Read (0xEB, 24-bit address) / 3 - 1-2-2 Read(0xBB, 24-bit address)
42 * 4 - HyperFLASH 1.8V / 5 - HyperFLASH 3V
43 * 6 - OctaBus DDR (SPI -> OPI DDR)
44 * 8 - Xccela DDR (SPI -> OPI DDR)
45 * 10 - EcoXiP DDR (SPI -> OPI DDR)
46 * [27:24] Command Pads after Power-on Reset
47 * 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI
48 * [23:20] Command Pads after Configuring FLASH
49 * 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI
50 * [19:16] Quad Enable Sequence (for the device support SFDP 1.0 only)
51 * 0 - Not needed
52 * 1 - QE bit is at bit 6 in Status Register 1
53 * 2 - QE bit is at bit1 in Status Register 2
54 * 3 - QE bit is at bit7 in Status Register 2
55 * 4 - QE bit is at bit1 in Status Register 2 and should be programmed by 0x31
56 * [15:8] Dummy cycles
57 * 0 - Auto-probed / detected / default value
58 * Others - User specified value, for DDR read, the dummy cycles should be 2 * cycles on FLASH datasheet
59 * [7:4] Misc.
60 * 0 - Not used
61 * 1 - SPI mode
62 * 2 - Internal loopback
63 * 3 - External DQS
64 * [3:0] Frequency option
65 * 1 - 30MHz / 2 - 50MHz / 3 - 66MHz / 4 - 80MHz / 5 - 100MHz / 6 - 120MHz / 7 - 133MHz / 8 - 166MHz
66 *
67 * option[2] (Effective only if the bit[3:0] in option[0] > 1)
68 * [31:20] Reserved
69 * [19:16] IO voltage
70 * 0 - 3V / 1 - 1.8V
71 * [15:12] Pin group
72 * 0 - 1st group / 1 - 2nd group
73 * [11:8] Connection selection
74 * 0 - CA_CS0 / 1 - CB_CS0 / 2 - CA_CS0 + CB_CS0 (Two FLASH connected to CA and CB respectively)
75 * [7:0] Drive Strength
76 * 0 - Default value
77 * option[3] (Effective only if the bit[3:0] in option[0] > 2, required only for the QSPI NOR FLASH that not supports
78 * JESD216)
79 * [31:16] reserved
80 * [15:12] Sector Erase Command Option, not required here
81 * [11:8] Sector Size Option, not required here
82 * [7:0] Flash Size Option
83 * 0 - 4MB / 1 - 8MB / 2 - 16MB
84 */
85 #if defined(FLASH_XIP) && FLASH_XIP
86 __attribute__((section(".nor_cfg_option"))) const uint32_t option[4] = { 0xfcf90001, 0x00000007, 0x0, 0x0 };
87 #endif
88
89 #if defined(FLASH_UF2) && FLASH_UF2
90 ATTR_PLACE_AT(".uf2_signature") const uint32_t uf2_signature = BOARD_UF2_SIGNATURE;
91 #endif
92
board_init_console(void)93 void board_init_console(void)
94 {
95 #if !defined(CONFIG_NDEBUG_CONSOLE) || !CONFIG_NDEBUG_CONSOLE
96 #if BOARD_CONSOLE_TYPE == CONSOLE_TYPE_UART
97 console_config_t cfg;
98
99 /* uart needs to configure pin function before enabling clock, otherwise the level change of
100 * uart rx pin when configuring pin function will cause a wrong data to be received.
101 * And a uart rx dma request will be generated by default uart fifo dma trigger level.
102 */
103 init_uart_pins((UART_Type *) BOARD_CONSOLE_BASE);
104
105 /* Configure the UART clock to 24MHz */
106 clock_set_source_divider(BOARD_CONSOLE_CLK_NAME, clk_src_osc24m, 1U);
107 clock_add_to_group(BOARD_CONSOLE_CLK_NAME, 0);
108
109 cfg.type = BOARD_CONSOLE_TYPE;
110 cfg.base = (uint32_t) BOARD_CONSOLE_BASE;
111 cfg.src_freq_in_hz = clock_get_frequency(BOARD_CONSOLE_CLK_NAME);
112 cfg.baudrate = BOARD_CONSOLE_BAUDRATE;
113
114 if (status_success != console_init(&cfg)) {
115 /* failed to initialize debug console */
116 while (1) {
117 }
118 }
119 #else
120 while (1)
121 ;
122 #endif
123 #endif
124 }
125
board_print_clock_freq(void)126 void board_print_clock_freq(void)
127 {
128 printf("==============================\n");
129 printf(" %s clock summary\n", BOARD_NAME);
130 printf("==============================\n");
131 printf("cpu0:\t\t %dHz\n", clock_get_frequency(clock_cpu0));
132 printf("gpu0:\t\t %dHz\n", clock_get_frequency(clock_gpu0));
133 printf("axis:\t\t %dHz\n", clock_get_frequency(clock_axis));
134 printf("axic:\t\t %dHz\n", clock_get_frequency(clock_axic));
135 printf("axif:\t\t %dHz\n", clock_get_frequency(clock_axif));
136 printf("axid:\t\t %dHz\n", clock_get_frequency(clock_axid));
137 printf("axiv:\t\t %dHz\n", clock_get_frequency(clock_axiv));
138 printf("axig:\t\t %dHz\n", clock_get_frequency(clock_axig));
139 printf("mchtmr0:\t %dHz\n", clock_get_frequency(clock_mchtmr0));
140 printf("xpi0:\t\t %dHz\n", clock_get_frequency(clock_xpi0));
141 printf("==============================\n");
142 }
143
board_init_uart(UART_Type * ptr)144 void board_init_uart(UART_Type *ptr)
145 {
146 /* configure uart's pin before opening uart's clock */
147 init_uart_pins(ptr);
148 board_init_uart_clock(ptr);
149 }
150
board_print_banner(void)151 void board_print_banner(void)
152 {
153 const uint8_t banner[] = { "\n\
154 ----------------------------------------------------------------------\n\
155 $$\\ $$\\ $$$$$$$\\ $$\\ $$\\ $$\\\n\
156 $$ | $$ |$$ __$$\\ $$$\\ $$$ |\\__|\n\
157 $$ | $$ |$$ | $$ |$$$$\\ $$$$ |$$\\ $$$$$$$\\ $$$$$$\\ $$$$$$\\\n\
158 $$$$$$$$ |$$$$$$$ |$$\\$$\\$$ $$ |$$ |$$ _____|$$ __$$\\ $$ __$$\\\n\
159 $$ __$$ |$$ ____/ $$ \\$$$ $$ |$$ |$$ / $$ | \\__|$$ / $$ |\n\
160 $$ | $$ |$$ | $$ |\\$ /$$ |$$ |$$ | $$ | $$ | $$ |\n\
161 $$ | $$ |$$ | $$ | \\_/ $$ |$$ |\\$$$$$$$\\ $$ | \\$$$$$$ |\n\
162 \\__| \\__|\\__| \\__| \\__|\\__| \\_______|\\__| \\______/\n\
163 ----------------------------------------------------------------------\n" };
164 #ifdef SDK_VERSION_STRING
165 printf("hpm_sdk: %s\n", SDK_VERSION_STRING);
166 #endif
167 printf("%s", banner);
168 }
169
170
board_get_led_gpio_off_level(void)171 uint8_t board_get_led_gpio_off_level(void)
172 {
173 return BOARD_LED_OFF_LEVEL;
174 }
175
board_ungate_mchtmr_at_lp_mode(void)176 void board_ungate_mchtmr_at_lp_mode(void)
177 {
178 /* Keep cpu clock on wfi, so that mchtmr irq can still work after wfi */
179 sysctl_set_cpu0_lp_mode(HPM_SYSCTL, cpu_lp_mode_ungate_cpu_clock);
180 }
181
board_init(void)182 void board_init(void)
183 {
184 board_init_clock();
185 board_init_console();
186 board_init_pmp();
187 #if BOARD_SHOW_CLOCK
188 board_print_clock_freq();
189 #endif
190 #if BOARD_SHOW_BANNER
191 board_print_banner();
192 #endif
193 }
194
board_delay_us(uint32_t us)195 void board_delay_us(uint32_t us)
196 {
197 clock_cpu_delay_us(us);
198 }
199
board_delay_ms(uint32_t ms)200 void board_delay_ms(uint32_t ms)
201 {
202 clock_cpu_delay_ms(ms);
203 }
204
board_timer_isr(void)205 void board_timer_isr(void)
206 {
207 if (gptmr_check_status(BOARD_CALLBACK_TIMER, GPTMR_CH_RLD_STAT_MASK(BOARD_CALLBACK_TIMER_CH))) {
208 gptmr_clear_status(BOARD_CALLBACK_TIMER, GPTMR_CH_RLD_STAT_MASK(BOARD_CALLBACK_TIMER_CH));
209 timer_cb();
210 }
211 }
212
213 SDK_DECLARE_EXT_ISR_M(BOARD_CALLBACK_TIMER_IRQ, board_timer_isr);
214
board_timer_create(uint32_t ms,board_timer_cb cb)215 void board_timer_create(uint32_t ms, board_timer_cb cb)
216 {
217 uint32_t gptmr_freq;
218 gptmr_channel_config_t config;
219
220 timer_cb = cb;
221 gptmr_channel_get_default_config(BOARD_CALLBACK_TIMER, &config);
222
223 clock_add_to_group(BOARD_CALLBACK_TIMER_CLK_NAME, 0);
224 gptmr_freq = clock_get_frequency(BOARD_CALLBACK_TIMER_CLK_NAME);
225
226 config.reload = gptmr_freq / 1000 * ms;
227 gptmr_channel_config(BOARD_CALLBACK_TIMER, BOARD_CALLBACK_TIMER_CH, &config, false);
228 gptmr_enable_irq(BOARD_CALLBACK_TIMER, GPTMR_CH_RLD_IRQ_MASK(BOARD_CALLBACK_TIMER_CH));
229 intc_m_enable_irq_with_priority(BOARD_CALLBACK_TIMER_IRQ, 1);
230
231 gptmr_start_counter(BOARD_CALLBACK_TIMER, BOARD_CALLBACK_TIMER_CH);
232 }
233
board_i2c_bus_clear(I2C_Type * ptr)234 void board_i2c_bus_clear(I2C_Type *ptr)
235 {
236 if (i2c_get_line_scl_status(ptr) == false) {
237 printf("CLK is low, please power cycle the board\n");
238 while (1) {
239 }
240 }
241 if (i2c_get_line_sda_status(ptr) == false) {
242 printf("SDA is low, try to issue I2C bus clear\n");
243 } else {
244 printf("I2C bus is ready\n");
245 return;
246 }
247 i2s_gen_reset_signal(ptr, 9);
248 board_delay_ms(100);
249 printf("I2C bus is cleared\n");
250 }
251
board_init_i2c(I2C_Type * ptr)252 void board_init_i2c(I2C_Type *ptr)
253 {
254 hpm_stat_t stat;
255 uint32_t freq;
256 i2c_config_t config;
257
258 init_i2c_pins(ptr);
259 board_i2c_bus_clear(ptr);
260
261 if (ptr == HPM_I2C0) {
262 clock_add_to_group(clock_i2c0, 0);
263 clock_set_source_divider(clock_i2c0, clk_src_osc24m, 1U);
264 freq = clock_get_frequency(clock_i2c0);
265 } else if (ptr == HPM_I2C1) {
266 clock_add_to_group(clock_i2c1, 0);
267 clock_set_source_divider(clock_i2c1, clk_src_osc24m, 1U);
268 freq = clock_get_frequency(clock_i2c1);
269 } else if (ptr == HPM_I2C2) {
270 clock_add_to_group(clock_i2c2, 0);
271 clock_set_source_divider(clock_i2c2, clk_src_osc24m, 1U);
272 freq = clock_get_frequency(clock_i2c2);
273 } else if (ptr == HPM_I2C3) {
274 clock_add_to_group(clock_i2c3, 0);
275 clock_set_source_divider(clock_i2c3, clk_src_osc24m, 1U);
276 freq = clock_get_frequency(clock_i2c3);
277 } else {
278 printf("invild i2c base address 0x%lx\n", (uint32_t) ptr);
279 while (1) {
280 }
281 }
282
283 config.i2c_mode = i2c_mode_normal;
284 config.is_10bit_addressing = false;
285 stat = i2c_init_master(ptr, freq, &config);
286 if (stat != status_success) {
287 printf("failed to initialize i2c 0x%lx\n", (uint32_t) ptr);
288 while (1) {
289 }
290 }
291 }
292
board_init_spi_clock(SPI_Type * ptr)293 uint32_t board_init_spi_clock(SPI_Type *ptr)
294 {
295 if (ptr == HPM_SPI1) {
296 /* SPI1 clock configure */
297 clock_add_to_group(clock_spi1, 0);
298 return clock_get_frequency(clock_spi1);
299 } else if (ptr == HPM_SPI2) {
300 /* SPI2 clock configure */
301 clock_add_to_group(clock_spi2, 0);
302 return clock_get_frequency(clock_spi2);
303 } else if (ptr == HPM_SPI3) {
304 /* SPI3 clock configure */
305 clock_add_to_group(clock_spi3, 0);
306 return clock_get_frequency(clock_spi3);
307 }
308 return 0;
309 }
310
board_init_gpio_pins(void)311 void board_init_gpio_pins(void)
312 {
313 init_gpio_pins();
314 }
315
board_init_spi_pins(SPI_Type * ptr)316 void board_init_spi_pins(SPI_Type *ptr)
317 {
318 init_spi_pins(ptr);
319 }
320
board_init_spi_pins_with_gpio_as_cs(SPI_Type * ptr)321 void board_init_spi_pins_with_gpio_as_cs(SPI_Type *ptr)
322 {
323 init_spi_pins_with_gpio_as_cs(ptr);
324 gpio_set_pin_output_with_initial(BOARD_SPI_CS_GPIO_CTRL, GPIO_GET_PORT_INDEX(BOARD_SPI_CS_PIN),
325 GPIO_GET_PIN_INDEX(BOARD_SPI_CS_PIN), !BOARD_SPI_CS_ACTIVE_LEVEL);
326 }
327
board_write_spi_cs(uint32_t pin,uint8_t state)328 void board_write_spi_cs(uint32_t pin, uint8_t state)
329 {
330 gpio_write_pin(BOARD_SPI_CS_GPIO_CTRL, GPIO_GET_PORT_INDEX(pin), GPIO_GET_PIN_INDEX(pin), state);
331 }
332
board_init_led_pins(void)333 void board_init_led_pins(void)
334 {
335 init_led_pins_as_gpio();
336 gpio_set_pin_output_with_initial(BOARD_R_GPIO_CTRL, BOARD_R_GPIO_INDEX, BOARD_R_GPIO_PIN,
337 board_get_led_gpio_off_level());
338 gpio_set_pin_output_with_initial(BOARD_G_GPIO_CTRL, BOARD_G_GPIO_INDEX, BOARD_G_GPIO_PIN,
339 board_get_led_gpio_off_level());
340 gpio_set_pin_output_with_initial(BOARD_B_GPIO_CTRL, BOARD_B_GPIO_INDEX, BOARD_B_GPIO_PIN,
341 board_get_led_gpio_off_level());
342 }
343
board_led_toggle(void)344 void board_led_toggle(void)
345 {
346 #ifdef BOARD_LED_TOGGLE_RGB
347 static uint8_t i;
348 switch (i) {
349 case 1:
350 gpio_write_pin(BOARD_R_GPIO_CTRL, BOARD_R_GPIO_INDEX, BOARD_R_GPIO_PIN, BOARD_LED_OFF_LEVEL);
351 gpio_write_pin(BOARD_G_GPIO_CTRL, BOARD_G_GPIO_INDEX, BOARD_G_GPIO_PIN, BOARD_LED_ON_LEVEL);
352 gpio_write_pin(BOARD_B_GPIO_CTRL, BOARD_B_GPIO_INDEX, BOARD_B_GPIO_PIN, BOARD_LED_OFF_LEVEL);
353 break;
354
355 case 2:
356 gpio_write_pin(BOARD_R_GPIO_CTRL, BOARD_R_GPIO_INDEX, BOARD_R_GPIO_PIN, BOARD_LED_OFF_LEVEL);
357 gpio_write_pin(BOARD_G_GPIO_CTRL, BOARD_G_GPIO_INDEX, BOARD_G_GPIO_PIN, BOARD_LED_OFF_LEVEL);
358 gpio_write_pin(BOARD_B_GPIO_CTRL, BOARD_B_GPIO_INDEX, BOARD_B_GPIO_PIN, BOARD_LED_ON_LEVEL);
359 break;
360
361 case 0:
362 default:
363 gpio_write_pin(BOARD_R_GPIO_CTRL, BOARD_R_GPIO_INDEX, BOARD_R_GPIO_PIN, BOARD_LED_ON_LEVEL);
364 gpio_write_pin(BOARD_G_GPIO_CTRL, BOARD_G_GPIO_INDEX, BOARD_G_GPIO_PIN, BOARD_LED_OFF_LEVEL);
365 gpio_write_pin(BOARD_B_GPIO_CTRL, BOARD_B_GPIO_INDEX, BOARD_B_GPIO_PIN, BOARD_LED_OFF_LEVEL);
366 break;
367 }
368 i++;
369 i = i % 3;
370 #else
371 gpio_toggle_pin(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN);
372 #endif
373 }
374
board_led_write(uint8_t state)375 void board_led_write(uint8_t state)
376 {
377 gpio_write_pin(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN, state);
378 }
379
board_init_pmp(void)380 void board_init_pmp(void)
381 {
382 extern uint32_t __noncacheable_start__[];
383 extern uint32_t __noncacheable_end__[];
384
385 uint32_t start_addr = (uint32_t) __noncacheable_start__;
386 uint32_t end_addr = (uint32_t) __noncacheable_end__;
387 uint32_t length = end_addr - start_addr;
388
389 if (length == 0) {
390 return;
391 }
392
393 /* Ensure the address and the length are power of 2 aligned */
394 assert((length & (length - 1U)) == 0U);
395 assert((start_addr & (length - 1U)) == 0U);
396
397 pmp_entry_t pmp_entry[3] = { 0 };
398 pmp_entry[0].pmp_addr = PMP_NAPOT_ADDR(0x0000000, 0x80000000);
399 pmp_entry[0].pmp_cfg.val = PMP_CFG(READ_EN, WRITE_EN, EXECUTE_EN, ADDR_MATCH_NAPOT, REG_UNLOCK);
400
401
402 pmp_entry[1].pmp_addr = PMP_NAPOT_ADDR(0x80000000, 0x80000000);
403 pmp_entry[1].pmp_cfg.val = PMP_CFG(READ_EN, WRITE_EN, EXECUTE_EN, ADDR_MATCH_NAPOT, REG_UNLOCK);
404
405 pmp_entry[2].pmp_addr = PMP_NAPOT_ADDR(start_addr, length);
406 pmp_entry[2].pmp_cfg.val = PMP_CFG(READ_EN, WRITE_EN, EXECUTE_EN, ADDR_MATCH_NAPOT, REG_UNLOCK);
407 pmp_entry[2].pma_addr = PMA_NAPOT_ADDR(start_addr, length);
408 pmp_entry[2].pma_cfg.val = PMA_CFG(ADDR_MATCH_NAPOT, MEM_TYPE_MEM_NON_CACHE_BUF, AMO_EN);
409 pmp_config(&pmp_entry[0], ARRAY_SIZE(pmp_entry));
410 }
411
board_init_display_system_clock(void)412 void board_init_display_system_clock(void)
413 {
414 clock_add_to_group(clock_gpu0, 0);
415 clock_add_to_group(clock_gwc0, 0);
416 clock_add_to_group(clock_gwc1, 0);
417 clock_add_to_group(clock_lvb, 0);
418 clock_add_to_group(clock_lcb, 0);
419 clock_add_to_group(clock_lcd0, 0);
420 clock_add_to_group(clock_dsi0, 0);
421 clock_add_to_group(clock_dsi1, 0);
422 clock_add_to_group(clock_cam0, 0);
423 clock_add_to_group(clock_cam1, 0);
424 clock_add_to_group(clock_jpeg, 0);
425 clock_add_to_group(clock_pdma, 0);
426 }
427
board_init_clock(void)428 void board_init_clock(void)
429 {
430 uint32_t cpu0_freq = clock_get_frequency(clock_cpu0);
431 if (cpu0_freq == PLLCTL_SOC_PLL_REFCLK_FREQ) {
432 /* Configure the External OSC ramp-up time: ~9ms */
433 pllctlv2_xtal_set_rampup_time(HPM_PLLCTLV2, 32UL * 1000UL * 9U);
434
435 /* Select clock setting preset1 */
436 sysctl_clock_set_preset(HPM_SYSCTL, 2);
437 }
438 /* Add most Clocks to group 0 */
439 /* not open uart clock in this API, uart should configure pin function before opening clock */
440 clock_add_to_group(clock_cpu0, 0);
441 clock_add_to_group(clock_ahb, 0);
442 clock_add_to_group(clock_axic, 0);
443 clock_add_to_group(clock_axis, 0);
444 clock_add_to_group(clock_axiv, 0);
445 clock_add_to_group(clock_axid, 0);
446 clock_add_to_group(clock_axig, 0);
447
448 clock_add_to_group(clock_mchtmr0, 0);
449 clock_add_to_group(clock_xpi0, 0);
450 clock_add_to_group(clock_gptmr0, 0);
451 clock_add_to_group(clock_gptmr1, 0);
452 clock_add_to_group(clock_gptmr2, 0);
453 clock_add_to_group(clock_gptmr3, 0);
454 clock_add_to_group(clock_i2c0, 0);
455 clock_add_to_group(clock_i2c1, 0);
456 clock_add_to_group(clock_i2c2, 0);
457 clock_add_to_group(clock_i2c3, 0);
458 clock_add_to_group(clock_spi0, 0);
459 clock_add_to_group(clock_spi1, 0);
460 clock_add_to_group(clock_spi2, 0);
461 clock_add_to_group(clock_spi3, 0);
462 clock_add_to_group(clock_can0, 0);
463 clock_add_to_group(clock_can1, 0);
464 clock_add_to_group(clock_can2, 0);
465 clock_add_to_group(clock_can3, 0);
466 clock_add_to_group(clock_can4, 0);
467 clock_add_to_group(clock_can5, 0);
468 clock_add_to_group(clock_can6, 0);
469 clock_add_to_group(clock_can7, 0);
470 clock_add_to_group(clock_ptpc, 0);
471 clock_add_to_group(clock_ref0, 0);
472 clock_add_to_group(clock_ref1, 0);
473 clock_add_to_group(clock_watchdog0, 0);
474 clock_add_to_group(clock_sdp, 0);
475 clock_add_to_group(clock_xdma, 0);
476 clock_add_to_group(clock_xram, 0);
477 clock_add_to_group(clock_usb0, 0);
478 clock_add_to_group(clock_kman, 0);
479 clock_add_to_group(clock_gpio, 0);
480 clock_add_to_group(clock_mbx0, 0);
481 clock_add_to_group(clock_hdma, 0);
482 clock_add_to_group(clock_rng, 0);
483 clock_add_to_group(clock_adc0, 0);
484 clock_add_to_group(clock_adc1, 0);
485 clock_add_to_group(clock_crc0, 0);
486 clock_add_to_group(clock_dao, 0);
487 clock_add_to_group(clock_pdm, 0);
488 clock_add_to_group(clock_smix, 0);
489
490 clock_add_to_group(clock_i2s0, 0);
491 clock_add_to_group(clock_i2s1, 0);
492 clock_add_to_group(clock_i2s2, 0);
493 clock_add_to_group(clock_i2s3, 0);
494
495 clock_add_to_group(clock_eth0, 0);
496 clock_add_to_group(clock_ffa, 0);
497
498 board_init_display_system_clock();
499
500 /* Connect Group0 to CPU0 */
501 clock_connect_group_to_cpu(0, 0);
502
503 /* Bump up DCDC voltage to 1150mv */
504 pcfg_dcdc_set_voltage(HPM_PCFG, 1150);
505
506 /* Configure PLL1_CLK0 Post Divider to 1 */
507 pllctlv2_set_postdiv(HPM_PLLCTLV2, 0, 0, 0);
508 pllctlv2_init_pll_with_freq(HPM_PLLCTLV2, 0, BOARD_CPU_FREQ);
509
510 /* Configure axis to 200MHz */
511 clock_set_source_divider(clock_axis, clk_src_pll1_clk0, 4);
512
513 /* Configure axig/clock_gpu0 to 400MHz */
514 clock_set_source_divider(clock_axig, clk_src_pll1_clk0, 2);
515
516 /* Configure mchtmr to 24MHz */
517 clock_set_source_divider(clock_mchtmr0, clk_src_osc24m, 1);
518
519 clock_update_core_clock();
520 }
521
board_init_can(MCAN_Type * ptr)522 void board_init_can(MCAN_Type *ptr)
523 {
524 init_can_pins(ptr);
525 }
526
board_init_can_clock(MCAN_Type * ptr)527 uint32_t board_init_can_clock(MCAN_Type *ptr)
528 {
529 uint32_t freq = 0;
530 if (ptr == HPM_MCAN0) {
531 /* Set the CAN0 peripheral clock to 80MHz */
532 clock_set_source_divider(clock_can0, clk_src_pll1_clk0, 10);
533 freq = clock_get_frequency(clock_can0);
534 } else if (ptr == HPM_MCAN1) {
535 /* Set the CAN1 peripheral clock to 80MHz */
536 clock_set_source_divider(clock_can1, clk_src_pll1_clk0, 10);
537 freq = clock_get_frequency(clock_can1);
538 } else if (ptr == HPM_MCAN2) {
539 /* Set the CAN2 peripheral clock to 8MHz */
540 clock_set_source_divider(clock_can2, clk_src_pll1_clk0, 10);
541 freq = clock_get_frequency(clock_can2);
542 } else if (ptr == HPM_MCAN3) {
543 /* Set the CAN3 peripheral clock to 80MHz */
544 clock_set_source_divider(clock_can3, clk_src_pll1_clk0, 10);
545 freq = clock_get_frequency(clock_can3);
546 } else if (ptr == HPM_MCAN4) {
547 /* Set the CAN4 peripheral clock to 80MHz */
548 clock_set_source_divider(clock_can4, clk_src_pll1_clk0, 10);
549 freq = clock_get_frequency(clock_can4);
550 } else if (ptr == HPM_MCAN5) {
551 /* Set the CAN5 peripheral clock to 80MHz */
552 clock_set_source_divider(clock_can5, clk_src_pll1_clk0, 10);
553 freq = clock_get_frequency(clock_can5);
554 } else if (ptr == HPM_MCAN6) {
555 /* Set the CAN6 peripheral clock to 80MHz */
556 clock_set_source_divider(clock_can6, clk_src_pll1_clk0, 10);
557 freq = clock_get_frequency(clock_can6);
558 } else if (ptr == HPM_MCAN7) {
559 /* Set the CAN7 peripheral clock to 80MHz */
560 clock_set_source_divider(clock_can7, clk_src_pll1_clk0, 10);
561 freq = clock_get_frequency(clock_can7);
562 } else {
563 /* Invalid CAN instance */
564 }
565 return freq;
566 }
567
board_init_uart_clock(UART_Type * ptr)568 uint32_t board_init_uart_clock(UART_Type *ptr)
569 {
570 uint32_t freq = 0U;
571 if (ptr == HPM_UART0) {
572 clock_set_source_divider(clock_uart0, clk_src_osc24m, 1);
573 clock_add_to_group(clock_uart0, 0);
574 freq = clock_get_frequency(clock_uart0);
575 } else if (ptr == HPM_UART1) {
576 clock_set_source_divider(clock_uart1, clk_src_osc24m, 1);
577 clock_add_to_group(clock_uart1, 0);
578 freq = clock_get_frequency(clock_uart1);
579 } else if (ptr == HPM_UART2) {
580 clock_set_source_divider(clock_uart2, clk_src_osc24m, 1);
581 clock_add_to_group(clock_uart2, 0);
582 freq = clock_get_frequency(clock_uart2);
583 } else {
584 /* Not supported */
585 }
586 return freq;
587 }
588
589 uint32_t board_lcdc_clock_init(clock_name_t clock_name, uint32_t pixel_clk_khz);
590
591 #if defined(CONFIG_PANEL_RGB_TM070RDH13) && CONFIG_PANEL_RGB_TM070RDH13
set_reset_pin_level_tm070rdh13(uint8_t level)592 static void set_reset_pin_level_tm070rdh13(uint8_t level)
593 {
594 gpio_write_pin(HPM_GPIO0, GPIO_DO_GPIOA, 14, level);
595 }
596
set_backlight_tm070rdh13(uint16_t percent)597 static void set_backlight_tm070rdh13(uint16_t percent)
598 {
599 gpio_write_pin(HPM_GPIO0, GPIO_DO_GPIOA, 9, percent > 0 ? 1 : 0);
600 }
601
set_video_router_tm070rdh13(void)602 static void set_video_router_tm070rdh13(void)
603 {
604 pixelmux_rgb_data_source_enable(pixelmux_rgb_sel_lcdc0);
605 }
606
board_init_lcd_rgb_tm070rdh13(void)607 void board_init_lcd_rgb_tm070rdh13(void)
608 {
609 init_lcd_rgb_ctl_pins();
610 init_lcd_rgb_pins();
611
612 gpio_set_pin_output(HPM_GPIO0, GPIO_DO_GPIOY, 5);
613 gpio_write_pin(HPM_GPIO0, GPIO_DO_GPIOY, 5, 1);
614
615 gpio_set_pin_output(HPM_GPIO0, GPIO_DO_GPIOA, 9);
616 gpio_set_pin_output(HPM_GPIO0, GPIO_DO_GPIOA, 14);
617
618 hpm_panel_hw_interface_t hw_if = {0};
619 hpm_panel_t *panel = hpm_panel_find_device_default();
620 const hpm_panel_timing_t *timing = hpm_panel_get_timing(panel);
621 uint32_t lcdc_pixel_clk_khz = board_lcdc_clock_init(clock_lcd0, timing->pixel_clock_khz);
622 hw_if.set_reset_pin_level = set_reset_pin_level_tm070rdh13;
623 hw_if.set_backlight = set_backlight_tm070rdh13;
624 hw_if.set_video_router = set_video_router_tm070rdh13;
625 hw_if.lcdc_pixel_clk_khz = lcdc_pixel_clk_khz;
626 hpm_panel_register_interface(panel, &hw_if);
627
628 printf("name: %s, lcdc_clk: %ukhz\n",
629 hpm_panel_get_name(panel),
630 lcdc_pixel_clk_khz);
631
632 hpm_panel_reset(panel);
633 hpm_panel_init(panel);
634 hpm_panel_power_on(panel);
635 }
636
637 #endif
638
639 #if defined(CONFIG_PANEL_LVDS_CC10128007) && CONFIG_PANEL_LVDS_CC10128007
set_backlight_cc10128007(uint16_t percent)640 static void set_backlight_cc10128007(uint16_t percent)
641 {
642 gpio_write_pin(HPM_GPIO0, GPIO_DO_GPIOA, 31, percent > 0 ? 1 : 0);
643 gpio_write_pin(HPM_GPIO0, GPIO_DO_GPIOA, 30, percent > 0 ? 1 : 0);
644 }
645
set_video_router_cc10128007(void)646 static void set_video_router_cc10128007(void)
647 {
648 pixelmux_config_tx_phy1_mode(pixelmux_tx_phy_mode_lvds);
649 pixelmux_lvb_di0_data_source_enable(pixelmux_lvb_di0_sel_lcdc0);
650 }
651
board_init_lcd_lvds_cc10128007(void)652 void board_init_lcd_lvds_cc10128007(void)
653 {
654 init_lcd_lvds_single_ctl_pins();
655 gpio_set_pin_output(HPM_GPIO0, GPIO_DO_GPIOA, 30);
656 gpio_set_pin_output(HPM_GPIO0, GPIO_DO_GPIOA, 31);
657
658 init_mipi_lvds_tx_phy1_pin();
659
660 hpm_panel_hw_interface_t hw_if = {0};
661 hpm_panel_t *panel = hpm_panel_find_device_default();
662 const hpm_panel_timing_t *timing = hpm_panel_get_timing(panel);
663
664 uint32_t lcdc_pixel_clk_khz = board_lcdc_clock_init(clock_lcd0, timing->pixel_clock_khz);
665 hw_if.set_video_router = set_video_router_cc10128007;
666 hw_if.set_backlight = set_backlight_cc10128007;
667 hw_if.lcdc_pixel_clk_khz = lcdc_pixel_clk_khz;
668 hw_if.video.lvds.channel_di_index = 0;
669 hw_if.video.lvds.channel_index = 1; /* ch1 -> phy1*/
670 hw_if.video.lvds.lvb_base = HPM_LVB;
671
672 hpm_panel_register_interface(panel, &hw_if);
673
674 printf("name: %s, lcdc_clk: %ukhz\n",
675 hpm_panel_get_name(panel),
676 lcdc_pixel_clk_khz);
677
678 hpm_panel_reset(panel);
679 hpm_panel_init(panel);
680 hpm_panel_power_on(panel);
681 }
682 #endif
683
684 #if defined(CONFIG_PANEL_MIPI_MC10128007_31B) && CONFIG_PANEL_MIPI_MC10128007_31B
set_reset_pin_level_mc10128007_31b(uint8_t level)685 static void set_reset_pin_level_mc10128007_31b(uint8_t level)
686 {
687 gpio_write_pin(HPM_GPIO0, GPIO_DO_GPIOB, 1, level);
688 }
689
set_video_router_mc10128007_31b(void)690 static void set_video_router_mc10128007_31b(void)
691 {
692 pixelmux_mipi_dsi0_data_source_enable(pixelmux_mipi_dsi0_sel_lcdc0);
693 pixelmux_config_tx_phy0_mode(pixelmux_tx_phy_mode_mipi);
694 }
695
board_init_lcd_mipi_mc10128007_31b(void)696 void board_init_lcd_mipi_mc10128007_31b(void)
697 {
698 /* RESET */
699 init_lcd_mipi_ctl_pins();
700 gpio_set_pin_output(HPM_GPIO0, GPIO_DO_GPIOB, 1);
701
702 init_mipi_lvds_tx_phy0_pin();
703
704 hpm_panel_hw_interface_t hw_if = {0};
705 hpm_panel_t *panel = hpm_panel_find_device_default();
706 const hpm_panel_timing_t *timing = hpm_panel_get_timing(panel);
707 uint32_t lcdc_pixel_clk_khz = board_lcdc_clock_init(clock_lcd0, timing->pixel_clock_khz);
708 hw_if.set_reset_pin_level = set_reset_pin_level_mc10128007_31b;
709 hw_if.set_video_router = set_video_router_mc10128007_31b;
710 hw_if.lcdc_pixel_clk_khz = lcdc_pixel_clk_khz;
711 hw_if.video.mipi.format = HPM_PANEL_MIPI_FORMAT_RGB888;
712 hw_if.video.mipi.mipi_host_base = HPM_MIPI_DSI0;
713 hw_if.video.mipi.mipi_phy_base = HPM_MIPI_DSI_PHY0;
714 hpm_panel_register_interface(panel, &hw_if);
715
716 printf("name: %s, lcdc_clk: %ukhz\n",
717 hpm_panel_get_name(panel),
718 lcdc_pixel_clk_khz);
719
720 hpm_panel_reset(panel);
721 hpm_panel_init(panel);
722 hpm_panel_power_on(panel);
723 }
724 #endif
725
726 #if defined(CONFIG_PANEL_LVDS_TM103XDGP01) && CONFIG_PANEL_LVDS_TM103XDGP01
set_reset_pin_level_tm103xdgp01(uint8_t level)727 static void set_reset_pin_level_tm103xdgp01(uint8_t level)
728 {
729 gpio_write_pin(HPM_GPIO0, GPIO_DO_GPIOA, 31, level);
730 }
731
set_video_router_tm103xdgp01(void)732 static void set_video_router_tm103xdgp01(void)
733 {
734 pixelmux_config_tx_phy0_mode(pixelmux_tx_phy_mode_lvds);
735 pixelmux_config_tx_phy1_mode(pixelmux_tx_phy_mode_lvds);
736
737 pixelmux_lvb_di1_data_source_enable(pixelmux_lvb_di1_sel_lcdc0);
738 pixelmux_lvb_di0_data_source_enable(pixelmux_lvb_di0_sel_lcdc0);
739 }
740
board_init_lcd_lvds_tm103xdgp01(void)741 void board_init_lcd_lvds_tm103xdgp01(void)
742 {
743 init_lcd_lvds_double_ctl_pins();
744 gpio_set_pin_output(HPM_GPIO0, GPIO_DO_GPIOA, 31);
745
746 init_mipi_lvds_tx_phy0_pin();
747 init_mipi_lvds_tx_phy1_pin();
748
749 hpm_panel_hw_interface_t hw_if = {0};
750 hpm_panel_t *panel = hpm_panel_find_device_default();
751 const hpm_panel_timing_t *timing = hpm_panel_get_timing(panel);
752
753 /* In split mode: lcdc_pixel_clk = 2 * panel_pixel_clk */
754 uint32_t lcdc_pixel_clk_khz = board_lcdc_clock_init(clock_lcd0, timing->pixel_clock_khz * 2);
755 hw_if.set_reset_pin_level = set_reset_pin_level_tm103xdgp01;
756 hw_if.set_video_router = set_video_router_tm103xdgp01;
757 hw_if.lcdc_pixel_clk_khz = lcdc_pixel_clk_khz;
758 hw_if.video.lvds.channel_di_index = 0;
759 hw_if.video.lvds.lvb_base = HPM_LVB;
760
761 hpm_panel_register_interface(panel, &hw_if);
762
763 printf("name: %s, lcdc_clk: %ukhz\n",
764 hpm_panel_get_name(panel),
765 lcdc_pixel_clk_khz);
766
767 hpm_panel_reset(panel);
768 hpm_panel_init(panel);
769 hpm_panel_power_on(panel);
770 }
771 #endif
772
773 #ifdef CONFIG_HPM_PANEL
774
board_lcd_backlight(bool is_on)775 void board_lcd_backlight(bool is_on)
776 {
777 hpm_panel_t *panel = hpm_panel_find_device_default();
778 hpm_panel_set_backlight(panel, is_on == true ? 100 : 0);
779 }
780
board_lcdc_clock_init(clock_name_t clock_name,uint32_t pixel_clk_khz)781 uint32_t board_lcdc_clock_init(clock_name_t clock_name, uint32_t pixel_clk_khz)
782 {
783 clock_add_to_group(clock_name, 0);
784
785 uint32_t freq_khz = clock_get_frequency(clk_pll4clk0) / 1000;
786 uint32_t div = (freq_khz + pixel_clk_khz / 2) / pixel_clk_khz;
787 clock_set_source_divider(clock_name, clk_src_pll4_clk0, div);
788 return clock_get_frequency(clock_name) / 1000;
789 }
790
board_init_lcd(void)791 void board_init_lcd(void)
792 {
793 #if defined(CONFIG_PANEL_RGB_TM070RDH13) && CONFIG_PANEL_RGB_TM070RDH13
794 board_init_lcd_rgb_tm070rdh13();
795 #endif
796
797 #if defined(CONFIG_PANEL_LVDS_CC10128007) && CONFIG_PANEL_LVDS_CC10128007
798 board_init_lcd_lvds_cc10128007();
799 #endif
800
801 #if defined(CONFIG_PANEL_MIPI_MC10128007_31B) && CONFIG_PANEL_MIPI_MC10128007_31B
802 board_init_lcd_mipi_mc10128007_31b();
803 #endif
804
805 #if defined(CONFIG_PANEL_LVDS_TM103XDGP01) && CONFIG_PANEL_LVDS_TM103XDGP01
806 board_init_lcd_lvds_tm103xdgp01();
807 #endif
808 }
809
board_panel_para_to_lcdc(lcdc_config_t * config)810 void board_panel_para_to_lcdc(lcdc_config_t *config)
811 {
812 const hpm_panel_timing_t *timing;
813 hpm_panel_t *panel = hpm_panel_find_device_default();
814
815 timing = hpm_panel_get_timing(panel);
816 config->resolution_x = timing->hactive;
817 config->resolution_y = timing->vactive;
818
819 config->hsync.pulse_width = timing->hsync_len;
820 config->hsync.back_porch_pulse = timing->hback_porch;
821 config->hsync.front_porch_pulse = timing->hfront_porch;
822
823 config->vsync.pulse_width = timing->vsync_len;
824 config->vsync.back_porch_pulse = timing->vback_porch;
825 config->vsync.front_porch_pulse = timing->vfront_porch;
826
827 config->control.invert_hsync = timing->hsync_pol;
828 config->control.invert_vsync = timing->vsync_pol;
829 config->control.invert_href = timing->de_pol;
830 config->control.invert_pixel_data = timing->pixel_data_pol;
831 config->control.invert_pixel_clock = timing->pixel_clk_pol;
832 }
833 #endif
834
board_init_gwc(void)835 void board_init_gwc(void)
836 {
837 clock_add_to_group(clock_gwc0, 0);
838 clock_add_to_group(clock_gwc1, 0);
839 clock_add_to_group(clock_lcd0, 0);
840 }
841
board_init_cap_touch(void)842 void board_init_cap_touch(void)
843 {
844 init_cap_pins();
845 gpio_set_pin_output_with_initial(BOARD_CAP_RST_GPIO, BOARD_CAP_RST_GPIO_INDEX, BOARD_CAP_RST_GPIO_PIN, 0);
846 gpio_set_pin_output_with_initial(BOARD_CAP_INTR_GPIO, BOARD_CAP_INTR_GPIO_INDEX, BOARD_CAP_INTR_GPIO_PIN, 0);
847
848 board_delay_ms(1);
849 gpio_write_pin(BOARD_CAP_INTR_GPIO, BOARD_CAP_INTR_GPIO_INDEX, BOARD_CAP_INTR_GPIO_PIN, 0);
850 board_delay_ms(1);
851 gpio_write_pin(BOARD_CAP_RST_GPIO, BOARD_CAP_RST_GPIO_INDEX, BOARD_CAP_RST_GPIO_PIN, 1);
852 board_delay_ms(6);
853 gpio_write_pin(BOARD_CAP_RST_GPIO, BOARD_CAP_INTR_GPIO_INDEX, BOARD_CAP_INTR_GPIO_PIN, 0);
854
855 board_init_i2c(BOARD_CAP_I2C_BASE);
856 }
857
board_init_cam_pins(void)858 void board_init_cam_pins(void)
859 {
860 init_cam_pins();
861 /* enable cam RST pin out with high level */
862 gpio_set_pin_output_with_initial(BOARD_CAM_RST_GPIO_CTRL, BOARD_CAM_RST_GPIO_INDEX, BOARD_CAM_RST_GPIO_PIN, 1);
863 /* PWDN pin set to low when power up */
864 gpio_set_pin_output_with_initial(BOARD_CAM_PWDN_GPIO_CTRL, BOARD_CAM_PWDN_GPIO_INDEX, BOARD_CAM_PWDN_GPIO_PIN, 0);
865 pixelmux_cam0_data_source_enable(pixelmux_cam0_sel_dvp);
866 }
867
board_write_cam_rst(uint8_t state)868 void board_write_cam_rst(uint8_t state)
869 {
870 gpio_write_pin(BOARD_CAM_RST_GPIO_CTRL, BOARD_CAM_RST_GPIO_INDEX, BOARD_CAM_RST_GPIO_PIN, state);
871 }
872
board_write_cam_pwdn(uint8_t state)873 void board_write_cam_pwdn(uint8_t state)
874 {
875 gpio_write_pin(BOARD_CAM_PWDN_GPIO_CTRL, BOARD_CAM_PWDN_GPIO_INDEX, BOARD_CAM_PWDN_GPIO_PIN, state);
876 }
877
board_init_cam_clock(CAM_Type * ptr)878 uint32_t board_init_cam_clock(CAM_Type *ptr)
879 {
880 uint32_t freq = 0;
881 if (ptr == HPM_CAM0) {
882 /* Configure camera clock to 24MHz */
883 clock_set_source_divider(clock_cam0, clk_src_osc24m, 1U);
884 freq = clock_get_frequency(clock_cam0);
885 } else if (ptr == HPM_CAM1) {
886 /* Configure camera clock to 24MHz */
887 clock_set_source_divider(clock_cam1, clk_src_osc24m, 1U);
888 freq = clock_get_frequency(clock_cam1);
889 } else {
890 /* Invalid camera instance */
891 }
892 return freq;
893 }
894
board_init_mipi_csi_cam_pins(void)895 void board_init_mipi_csi_cam_pins(void)
896 {
897 init_cam_mipi_csi_pins();
898 init_mipi_lvds_rx_phy1_pin();
899
900 /* enable cam RST pin out with high level */
901 gpio_set_pin_output_with_initial(HPM_GPIO0, GPIO_DI_GPIOB, 0, 1);
902 }
903
board_write_mipi_csi_cam_rst(uint8_t state)904 void board_write_mipi_csi_cam_rst(uint8_t state)
905 {
906 gpio_write_pin(HPM_GPIO0, GPIO_DI_GPIOB, 0, state);
907 }
908
909
_cpu_wait_ms(uint32_t cpu_freq,uint32_t ms)910 static void _cpu_wait_ms(uint32_t cpu_freq, uint32_t ms)
911 {
912 uint32_t ticks_per_us = (cpu_freq + 1000000UL - 1UL) / 1000000UL;
913 uint64_t expected_ticks = hpm_csr_get_core_mcycle() + (uint64_t)ticks_per_us * 1000UL * ms;
914 while (hpm_csr_get_core_mcycle() < expected_ticks) {
915 }
916 }
917
init_ddr2_800(void)918 void init_ddr2_800(void)
919 {
920 /* Enable On-chip DCDC 1.8V output */
921 HPM_PCFG->DCDCM_MODE = PCFG_DCDCM_MODE_VOLT_SET(1800) | PCFG_DCDCM_MODE_MODE_SET(1);
922
923 /* Change DDR clock to 200MHz, namely: DDR2-800 */
924 clock_set_source_divider(clock_axif, clk_src_pll1_clk0, 4);
925
926 /* Enable DDR clock first */
927 clock_add_to_group(clock_ddr0, 0);
928
929 /* Wait until the clock is stable */
930 uint32_t core_clock_freq = clock_get_frequency(clock_cpu0);
931 _cpu_wait_ms(core_clock_freq, 5);
932
933 /* Clear DFI_INIT_COMPLETE_EN bit */
934 HPM_DDRCTL->DFIMISC &= ~DDRCTL_DFIMISC_DFI_INIT_COMPLETE_EN_MASK;
935
936 /* Release DDR core reset */
937 *(volatile uint32_t *) (HPM_DDRCTL_BASE + 0x3000UL) |= (1UL << 26);
938
939 /* Enable PORT */
940 HPM_DDRCTL->PCFG[0].CTRL = 1;
941
942 /* Configure W972GG6KB parameters, configure DDRCTL first */
943 HPM_DDRCTL->MSTR = DDRCTL_MSTR_ACTIVE_RANKS_SET(1) /* RANK=1 */
944 | DDRCTL_MSTR_BURST_RDWR_SET(4) /* Burst Length = 8 */
945 | DDRCTL_MSTR_DATA_BUS_WIDTH_SET(0) /* Full DQ bus width */
946 | DDRCTL_MSTR_DDR3_SET(0); /* DDR2 Device */
947
948 /* Skip SDRAM Initialization in controller, the initialization sequence will be performed by PHY */
949 HPM_DDRCTL->INIT0 = DDRCTL_INIT0_SKIP_DRAM_INIT_SET(1)
950 | DDRCTL_INIT0_POST_CKE_X1024_SET(2) /* Default setting */
951 | DDRCTL_INIT0_PRE_CKE_X1024_SET(0x4e); /* Default setting */
952
953 /* Configure DFI timing */
954 HPM_DDRCTL->DFITMG0 = 0x03010101UL;
955 HPM_DDRCTL->DFITMG1 = 0x00020101UL;
956 HPM_DDRCTL->DFIUPD0 = 0x40005UL;
957 HPM_DDRCTL->DFIUPD1 = 0x00020008UL;
958
959 HPM_DDRCTL->ODTCFG = 0x06000600UL; /* BL=8 */
960
961 /* Configure ADDRMAP */
962 HPM_DDRCTL->ADDRMAP0 = 0x001F1F1FUL; /* RANK0 not used */
963 HPM_DDRCTL->ADDRMAP1 = 0x00121212UL; /* HIF bit[24:22] as BANK[2:0] */
964 HPM_DDRCTL->ADDRMAP2 = 0; /* HIF bit[6:3] as COL_B[6:3] */
965 HPM_DDRCTL->ADDRMAP3 = 0; /* HIF bit [10:7] as COL_B[11,9:6:7] */
966 HPM_DDRCTL->ADDRMAP4 = 0xF0FUL; /* not used */
967 HPM_DDRCTL->ADDRMAP5 = 0x06030303UL; /* HIF bit[21:11] as ROW[10:0], HIF bit[25] as ROW[11] */
968 HPM_DDRCTL->ADDRMAP6 = 0x0F0F0606UL; /* HIF bit[27:26] as ROW[13:12] */
969
970 /* Release DDR AXI reset */
971 *(volatile uint32_t *) (HPM_DDRCTL_BASE + 0x3000UL) |= (1UL << 27);
972
973 /* Release DDR PHY */
974 *(volatile uint32_t *) (HPM_DDRPHY_BASE + 0x3000UL) |= (1UL << 4);
975
976 HPM_DDRPHY->DCR = DDRPHY_DCR_DDRMD_SET(2) /* Set to DDR2 mode */
977 | DDRPHY_DCR_DDR8BNK_MASK /* BANK = 8 */
978 | DDRPHY_DCR_BYTEMASK_MASK; /* BYTEMASK = 1 */
979 HPM_DDRPHY->DSGCR |= DDRPHY_DSGCR_RRMODE_MASK; /* Enable RRMode */
980
981 /* Configure DDR2 registers */
982 HPM_DDRPHY->MR = (3UL << 0) /* BL = 3 */
983 | (0UL << 3) /* BT = 0 */
984 | (6UL << 4) /* CL = 6 */
985 | (0UL << 7) /* Operating mode */
986 | (0UL << 8) /* DLL Reset = 0 */
987 | (6UL << 9); /* WR = 6 */
988 HPM_DDRPHY->EMR = (1UL << 0) /* DLL Enable */
989 | (0UL << 1) /* Output Driver Impedance Control */
990 | (0UL << 6) | (1UL << 2) /* On Die Termination */
991 | (0UL << 3) /* AL(Posted CAS Additive Latency) = 0 */
992 | (0UL << 7) /* OCD = 0*/
993 | (0UL << 10) /* DQS */
994 | (0UL << 11) /* RDQS */
995 | (0UL << 12); /* QOFF */
996 HPM_DDRPHY->EMR2 = 0;
997 HPM_DDRPHY->EMR3 = 0;
998 HPM_DDRPHY->DTPR0 = (4UL << 0)
999 | (5UL << 4)
1000 | (14UL << 8)
1001 | (15UL << 12)
1002 | (50UL << 16)
1003 | (10UL << 22)
1004 | (60 << 26);
1005 HPM_DDRPHY->DTPR1 = (2UL << 0)
1006 | (31UL << 5)
1007 | (80UL << 11)
1008 | (40UL << 20)
1009 | (0x8 << 26);
1010 HPM_DDRPHY->DTPR2 = (256UL << 0)
1011 | (6UL << 10)
1012 | (4UL << 15)
1013 | (512UL << 19);
1014
1015 /* tREFPRD */
1016 HPM_DDRPHY->PGCR2 = 0xF06D50;
1017
1018 /* Set DFI_INIT_COMPLETE_EN bit */
1019 HPM_DDRCTL->DFIMISC |= DDRCTL_DFIMISC_DFI_INIT_COMPLETE_EN_MASK;
1020
1021 /* Start PHY Init First */
1022 HPM_DDRPHY->PIR |= DDRPHY_PIR_INIT_MASK;
1023 while ((HPM_DDRPHY->PGSR0 & DDRPHY_PGSR0_IDONE_MASK) == 0) {
1024 }
1025 /** Data training
1026 * RANKEN = 1, Others: default value
1027 */
1028 HPM_DDRPHY->DTCR = 0x91003587UL;
1029
1030 /* Trigger PHY to do the PHY initialization and DRAM initialization */
1031 HPM_DDRPHY->PIR = 0xF501UL;
1032
1033 /* Wait until the initialization sequence started */
1034 while ((HPM_DDRPHY->PGSR0 & DDRPHY_PGSR0_IDONE_MASK) != 0) {
1035 }
1036 /* Wait until the initialization sequence completed */
1037 while ((HPM_DDRPHY->PGSR0 & DDRPHY_PGSR0_IDONE_MASK) == 0) {
1038 }
1039
1040 /* Wait for normal mode */
1041 while ((HPM_DDRCTL->STAT & DDRCTL_STAT_OPERATING_MODE_MASK) != 0x1) {
1042 }
1043 }
1044
init_ddr3l_1333(void)1045 void init_ddr3l_1333(void)
1046 {
1047 /* Enable On-chip DCDC 1.4V output */
1048 HPM_PCFG->DCDCM_MODE = PCFG_DCDCM_MODE_VOLT_SET(1400) | PCFG_DCDCM_MODE_MODE_SET(5);
1049
1050 /* Change DDR clock to 333.33MHz, namely: DDR3-1333 */
1051 clock_set_source_divider(clock_axif, clk_src_pll1_clk1, 2);
1052
1053 /* Enable DDR clock first */
1054 clock_add_to_group(clock_ddr0, 0);
1055
1056 /* Wait until the clock is stable */
1057 uint32_t core_clock_freq = clock_get_frequency(clock_cpu0);
1058 _cpu_wait_ms(core_clock_freq, 5);
1059
1060 /* Release DDR PHY */
1061 *(volatile uint32_t *) (HPM_DDRPHY_BASE + 0x3000UL) |= (1UL << 4);
1062
1063 /* Clear DFI_INIT_COMPLETE_EN bit */
1064 HPM_DDRCTL->DFIMISC &= ~DDRCTL_DFIMISC_DFI_INIT_COMPLETE_EN_MASK;
1065
1066 HPM_DDRPHY->DSGCR = 0xf004641f;
1067
1068 *(volatile uint32_t *) (HPM_DDRPHY_BASE + 0x3000UL) |= (1UL << 0);
1069
1070 /* Release DDR core reset */
1071 *(volatile uint32_t *) (HPM_DDRCTL_BASE + 0x3000UL) |= (1UL << 26);
1072
1073 /* Configure DDRCTL first */
1074 HPM_DDRCTL->MSTR = DDRCTL_MSTR_ACTIVE_RANKS_SET(1) /* RANK=1 */
1075 | DDRCTL_MSTR_BURST_RDWR_SET(4) /* Burst Length = 8 */
1076 | DDRCTL_MSTR_DATA_BUS_WIDTH_SET(0) /* Full DQ bus width */
1077 | DDRCTL_MSTR_DDR3_SET(1); /* DDR3 Device */
1078
1079 /* Enable PORT */
1080 HPM_DDRCTL->PCFG[0].CTRL = 1;
1081
1082 /* Skip SDRAM Initialization in controller, the initialization sequence will be performed by PHY */
1083 HPM_DDRCTL->INIT0 = DDRCTL_INIT0_SKIP_DRAM_INIT_SET(1)
1084 | DDRCTL_INIT0_POST_CKE_X1024_SET(2) /* Default setting */
1085 | DDRCTL_INIT0_PRE_CKE_X1024_SET(0x4e); /* Default setting */
1086 HPM_DDRCTL->DRAMTMG4 = 0x05010407;
1087
1088 /* Configure DFI timing */
1089 HPM_DDRCTL->DFITMG0 = 0x07040102;
1090 HPM_DDRCTL->DFITMG1 = 0x20404;
1091 HPM_DDRCTL->DFIUPD1 = 0x20008;
1092 HPM_DDRCTL->ODTCFG = 0x06000600UL; /* BL=8 */
1093 HPM_DDRCTL->ODTMAP = 0x11;
1094
1095 /* Configure ADDRMAP */
1096 HPM_DDRCTL->ADDRMAP0 = 0x001F1F1FUL; /* RANK0 not used */
1097 HPM_DDRCTL->ADDRMAP1 = 0x00121212UL; /* HIF bit[24:22] as BANK[2:0] */
1098 HPM_DDRCTL->ADDRMAP2 = 0; /* HIF bit[6:3] as COL_B[6:3] */
1099 HPM_DDRCTL->ADDRMAP3 = 0; /* HIF bit [10:7] as COL_B[11,9:6:7] */
1100 HPM_DDRCTL->ADDRMAP4 = 0xF0FUL; /* not used */
1101 HPM_DDRCTL->ADDRMAP5 = 0x06030303UL; /* HIF bit[21:11] as ROW[10:0], HIF bit[25] as ROW[11] */
1102 HPM_DDRCTL->ADDRMAP6 = 0x0F060606UL; /* HIF bit[27:26] as ROW[13:12] */
1103
1104 /* Release DDR AXI reset */
1105 *(volatile uint32_t *) (HPM_DDRCTL_BASE + 0x3000UL) |= (1UL << 27);
1106
1107 /* Configure DDR3 registers */
1108 HPM_DDRPHY->MR0 = 0xC70;
1109 HPM_DDRPHY->MR1 = 0x6;
1110 HPM_DDRPHY->MR2 = 0x18;
1111 HPM_DDRPHY->MR3 = 0;
1112
1113 HPM_DDRPHY->ODTCR = 0x84210000;
1114
1115 HPM_DDRPHY->DTPR0 = 0x919c8866;
1116 HPM_DDRPHY->DTPR1 = 0x1a838360;
1117 HPM_DDRPHY->DTPR2 = 0x3002d200;
1118
1119 /* tREFPRD */
1120 HPM_DDRPHY->PGCR2 = 0xf06d28;
1121
1122 /* Set DFI_INIT_COMPLETE_EN bit */
1123 HPM_DDRCTL->DFIMISC |= DDRCTL_DFIMISC_DFI_INIT_COMPLETE_EN_MASK;
1124
1125 /* Start PHY Init First */
1126 HPM_DDRPHY->PIR |= DDRPHY_PIR_INIT_MASK;
1127 while ((HPM_DDRPHY->PGSR0 & DDRPHY_PGSR0_IDONE_MASK) == 0) {
1128 }
1129 /** Data training
1130 * RANKEN = 1, Others: default value
1131 */
1132 HPM_DDRPHY->DTCR = 0x930035D7;
1133
1134 /* Trigger PHY to do the PHY initialization and DRAM initialization */
1135 HPM_DDRPHY->PIR = 0xFF81UL;
1136
1137 /* Wait until the initialization sequence started */
1138 while ((HPM_DDRPHY->PGSR0 & DDRPHY_PGSR0_IDONE_MASK) != 0) {
1139 }
1140 /* Wait until the initialization sequence completed */
1141 while ((HPM_DDRPHY->PGSR0 & DDRPHY_PGSR0_IDONE_MASK) == 0) {
1142 }
1143
1144 /* Wait for normal mode */
1145 while ((HPM_DDRCTL->STAT & DDRCTL_STAT_OPERATING_MODE_MASK) != 0x1) {
1146 }
1147 }
1148
_init_ext_ram(void)1149 void _init_ext_ram(void)
1150 {
1151 #if (BOARD_DDR_TYPE == DDR_TYPE_DDR2)
1152 init_ddr2_800();
1153 #endif
1154 #if (BOARD_DDR_TYPE == DDR_TYPE_DDR3L)
1155 init_ddr3l_1333();
1156 #endif
1157 }
1158
board_init_usb_pins(void)1159 void board_init_usb_pins(void)
1160 {
1161 init_usb_pins();
1162 usb_hcd_set_power_ctrl_polarity(BOARD_USB, true);
1163 }
1164
board_usb_vbus_ctrl(uint8_t usb_index,uint8_t level)1165 void board_usb_vbus_ctrl(uint8_t usb_index, uint8_t level)
1166 {
1167 (void) usb_index;
1168 (void) level;
1169 }
1170
board_sd_configure_clock(SDXC_Type * ptr,uint32_t freq,bool need_inverse)1171 uint32_t board_sd_configure_clock(SDXC_Type *ptr, uint32_t freq, bool need_inverse)
1172 {
1173 uint32_t actual_freq = 0;
1174 do {
1175 if ((ptr != HPM_SDXC0) && (ptr != HPM_SDXC1)) {
1176 break;
1177 }
1178 clock_name_t sdxc_clk = (ptr == HPM_SDXC0) ? clock_sdxc0 : clock_sdxc1;
1179 clock_add_to_group(sdxc_clk, 0);
1180 sdxc_enable_inverse_clock(ptr, false);
1181 sdxc_enable_sd_clock(ptr, false);
1182
1183
1184 clock_set_source_divider(sdxc_clk, clk_src_pll1_clk0, 4U);
1185 /* Configure the clock below 400KHz for the identification state */
1186 if (freq <= 400000UL) {
1187 /* Set clock to 375KHz */
1188 sdxc_set_clock_divider(ptr, 534U);
1189 }
1190 /* configure the clock to 24MHz for the SDR12/Default speed */
1191 else if (freq <= 26000000UL) {
1192 /* Set clock to 25MHz */
1193 sdxc_set_clock_divider(ptr, 8U);
1194 }
1195 /* Configure the clock to 50MHz for the SDR25/High speed/50MHz DDR/50MHz SDR */
1196 else if (freq <= 52000000UL) {
1197 /* Set clock to 50MHz */
1198 sdxc_set_clock_divider(ptr, 4U);
1199 }
1200 /* Configure the clock to 100MHz for the SDR50 */
1201 else if (freq <= 100000000UL) {
1202 /* Set clock to 100MHz */
1203 sdxc_set_clock_divider(ptr, 2U);
1204 }
1205 /* Configure the clock to 166MHz for SDR104/HS200/HS400 */
1206 else if (freq <= 208000000UL) {
1207 /* 166MHz */
1208 clock_set_source_divider(sdxc_clk, clk_src_pll1_clk1, 4U);
1209 sdxc_set_clock_divider(ptr, 1U);
1210 }
1211 /* For other unsupported clock ranges, configure the clock to 24MHz */
1212 else {
1213 /* Set clock to 25MHz */
1214 sdxc_set_clock_divider(ptr, 5U);
1215 }
1216 if (need_inverse) {
1217 sdxc_enable_inverse_clock(ptr, true);
1218 }
1219 sdxc_enable_sd_clock(ptr, true);
1220 actual_freq = clock_get_frequency(sdxc_clk) / sdxc_get_clock_divider(ptr);
1221 } while (false);
1222
1223 return actual_freq;
1224 }
1225
board_init_dao_clock(void)1226 uint32_t board_init_dao_clock(void)
1227 {
1228 return clock_get_frequency(clock_dao);
1229 }
1230
board_init_pdm_clock(void)1231 uint32_t board_init_pdm_clock(void)
1232 {
1233 return clock_get_frequency(clock_pdm);
1234 }
1235
board_init_i2s_clock(I2S_Type * ptr)1236 uint32_t board_init_i2s_clock(I2S_Type *ptr)
1237 {
1238 if (ptr == HPM_I2S0) {
1239 return clock_get_frequency(clock_i2s0);
1240 } else if (ptr == HPM_I2S1) {
1241 return clock_get_frequency(clock_i2s1);
1242 } else if (ptr == HPM_I2S2) {
1243 return clock_get_frequency(clock_i2s2);
1244 } else if (ptr == HPM_I2S3) {
1245 return clock_get_frequency(clock_i2s3);
1246 } else {
1247 return 0;
1248 }
1249 }
1250
1251 /* adjust I2S source clock base on sample rate */
board_config_i2s_clock(I2S_Type * ptr,uint32_t sample_rate)1252 uint32_t board_config_i2s_clock(I2S_Type *ptr, uint32_t sample_rate)
1253 {
1254 if (ptr == HPM_I2S0) {
1255 if ((sample_rate % 22050) == 0) {
1256 clock_set_source_divider(clock_aud0, clk_src_pll1_clk0, 71); /* config clock_aud1 for 22050*n sample rate */
1257 clock_add_to_group(clock_i2s0, 0);
1258 clock_set_i2s_source(clock_i2s0, clk_i2s_src_aud0);
1259 } else {
1260 clock_set_source_divider(clock_aud0, clk_src_pll3_clk0, 21); /* default 24576000Hz */
1261 clock_add_to_group(clock_i2s0, 0);
1262 clock_set_i2s_source(clock_i2s0, clk_i2s_src_aud0);
1263 }
1264 return clock_get_frequency(clock_i2s0);
1265 } else if (ptr == HPM_I2S1) {
1266 if ((sample_rate % 22050) == 0) {
1267 clock_set_source_divider(clock_aud1, clk_src_pll1_clk0, 71); /* config clock_aud1 for 22050*n sample rate */
1268 clock_add_to_group(clock_i2s1, 0);
1269 clock_set_i2s_source(clock_i2s1, clk_i2s_src_aud1);
1270 } else {
1271 clock_set_source_divider(clock_aud1, clk_src_pll3_clk0, 21); /* default 24576000Hz */
1272 clock_add_to_group(clock_i2s1, 0);
1273 clock_set_i2s_source(clock_i2s1, clk_i2s_src_aud1);
1274 }
1275 return clock_get_frequency(clock_i2s1);
1276 } else if (ptr == HPM_I2S3) {
1277 if ((sample_rate % 22050) == 0) {
1278 clock_set_source_divider(clock_aud3, clk_src_pll1_clk0, 71); /* config clock_aud1 for 22050*n sample rate */
1279 clock_add_to_group(clock_i2s3, 0);
1280 clock_set_i2s_source(clock_i2s3, clk_i2s_src_aud3);
1281 } else {
1282 clock_set_source_divider(clock_aud3, clk_src_pll3_clk0, 21); /* default 24576000Hz */
1283 clock_add_to_group(clock_i2s3, 0);
1284 clock_set_i2s_source(clock_i2s3, clk_i2s_src_aud3);
1285 }
1286 return clock_get_frequency(clock_i2s3);
1287 }
1288 return 0;
1289 }
1290
board_init_enet_pins(ENET_Type * ptr)1291 hpm_stat_t board_init_enet_pins(ENET_Type *ptr)
1292 {
1293 init_enet_pins(ptr);
1294
1295 if (ptr == HPM_ENET0) {
1296 gpio_set_pin_output_with_initial(BOARD_ENET_RGMII_RST_GPIO, BOARD_ENET_RGMII_RST_GPIO_INDEX,
1297 BOARD_ENET_RGMII_RST_GPIO_PIN, 0);
1298 } else {
1299 return status_invalid_argument;
1300 }
1301
1302 return status_success;
1303 }
1304
board_reset_enet_phy(ENET_Type * ptr)1305 hpm_stat_t board_reset_enet_phy(ENET_Type *ptr)
1306 {
1307 if (ptr == HPM_ENET0) {
1308 gpio_write_pin(BOARD_ENET_RGMII_RST_GPIO, BOARD_ENET_RGMII_RST_GPIO_INDEX, BOARD_ENET_RGMII_RST_GPIO_PIN, 0);
1309 board_delay_ms(1);
1310 gpio_write_pin(BOARD_ENET_RGMII_RST_GPIO, BOARD_ENET_RGMII_RST_GPIO_INDEX, BOARD_ENET_RGMII_RST_GPIO_PIN, 1);
1311 } else {
1312 return status_invalid_argument;
1313 }
1314
1315 return status_success;
1316 }
1317
board_get_enet_dma_pbl(ENET_Type * ptr)1318 uint8_t board_get_enet_dma_pbl(ENET_Type *ptr)
1319 {
1320 (void) ptr;
1321 return enet_pbl_32;
1322 }
1323
board_enable_enet_irq(ENET_Type * ptr)1324 hpm_stat_t board_enable_enet_irq(ENET_Type *ptr)
1325 {
1326 if (ptr == HPM_ENET0) {
1327 intc_m_enable_irq(IRQn_ENET0);
1328 } else {
1329 return status_invalid_argument;
1330 }
1331
1332 return status_success;
1333 }
1334
board_disable_enet_irq(ENET_Type * ptr)1335 hpm_stat_t board_disable_enet_irq(ENET_Type *ptr)
1336 {
1337 if (ptr == HPM_ENET0) {
1338 intc_m_disable_irq(IRQn_ENET0);
1339 } else {
1340 return status_invalid_argument;
1341 }
1342
1343 return status_success;
1344 }
1345
board_init_enet_pps_pins(ENET_Type * ptr)1346 void board_init_enet_pps_pins(ENET_Type *ptr)
1347 {
1348 (void) ptr;
1349 init_enet_pps_pins();
1350 }
1351
board_init_enet_ptp_clock(ENET_Type * ptr)1352 hpm_stat_t board_init_enet_ptp_clock(ENET_Type *ptr)
1353 {
1354 /* set clock source */
1355 if (ptr == HPM_ENET0) {
1356 /* make sure pll0_clk0 output clock at 800MHz to get a clock at 100MHz for the enet0 ptp function */
1357 clock_set_source_divider(clock_ptp0, clk_src_pll1_clk0, 8); /* 100MHz */
1358 } else {
1359 return status_invalid_argument;
1360 }
1361
1362 return status_success;
1363 }
1364
board_init_enet_rmii_reference_clock(ENET_Type * ptr,bool internal)1365 hpm_stat_t board_init_enet_rmii_reference_clock(ENET_Type *ptr, bool internal)
1366 {
1367 (void) ptr;
1368 (void) internal;
1369 return status_success;
1370 }
1371
board_init_enet_rgmii_clock_delay(ENET_Type * ptr)1372 hpm_stat_t board_init_enet_rgmii_clock_delay(ENET_Type *ptr)
1373 {
1374 if (ptr == HPM_ENET0) {
1375 return enet_rgmii_set_clock_delay(ptr, BOARD_ENET_RGMII_TX_DLY, BOARD_ENET_RGMII_RX_DLY);
1376 }
1377
1378 return status_invalid_argument;
1379 }
1380
board_init_adc16_pins(void)1381 void board_init_adc16_pins(void)
1382 {
1383 init_adc_pins();
1384 }
1385
board_init_adc16_clock(ADC16_Type * ptr,bool clk_src_ahb)1386 uint32_t board_init_adc16_clock(ADC16_Type *ptr, bool clk_src_ahb)
1387 {
1388 uint32_t freq = 0;
1389
1390 if (ptr == HPM_ADC0) {
1391 if (clk_src_ahb) {
1392 /* Configure the ADC clock from AXI (@200MHz by default)*/
1393 clock_set_adc_source(clock_adc0, clk_adc_src_ahb0);
1394 } else {
1395 /* Configure the ADC clock from pll0_clk1 divided by 4 (@200MHz by default) */
1396 clock_set_adc_source(clock_adc0, clk_adc_src_ana0);
1397 clock_set_source_divider(clock_ana0, clk_src_pll1_clk0, 4U);
1398 }
1399
1400 freq = clock_get_frequency(clock_adc0);
1401 }
1402
1403 return freq;
1404 }
1405
board_init_sadc_clock(SDADC_Type * ptr,bool clk_src_ahb)1406 uint32_t board_init_sadc_clock(SDADC_Type *ptr, bool clk_src_ahb)
1407 {
1408 uint32_t freq = 0;
1409
1410 if (ptr == HPM_ADC1) {
1411 if (clk_src_ahb) {
1412 /* Configure the ADC clock from AXI (@200MHz by default)*/
1413 clock_set_adc_source(clock_adc1, clk_adc_src_ahb0);
1414 } else {
1415 /* Configure the ADC clock from pll1_clk1 divided by 2 (@200MHz by default) */
1416 clock_set_adc_source(clock_adc1, clk_adc_src_ana1);
1417 clock_set_source_divider(clock_ana1, clk_src_pll1_clk0, 4U);
1418 }
1419
1420 freq = clock_get_frequency(clock_adc1);
1421 }
1422
1423 return freq;
1424 }
1425