1 /*
2 * Copyright (c) 2023 hpmicro
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 *
6 */
7
8 /*
9 * Note:
10 * PY and PZ IOs: if any SOC pin function needs to be routed to these IOs,
11 * besides of IOC, PIOC/BIOC needs to be configured SOC_GPIO_X_xx, so that
12 * expected SoC function can be enabled on these IOs.
13 *
14 */
15 #include "board.h"
16
init_uart_pins(UART_Type * ptr)17 void init_uart_pins(UART_Type *ptr)
18 {
19 if (ptr == HPM_UART0) {
20 HPM_IOC->PAD[IOC_PAD_PA00].FUNC_CTL = IOC_PA00_FUNC_CTL_UART0_TXD;
21 HPM_IOC->PAD[IOC_PAD_PA01].FUNC_CTL = IOC_PA01_FUNC_CTL_UART0_RXD;
22 } else if (ptr == HPM_UART3) {
23 HPM_IOC->PAD[IOC_PAD_PE14].FUNC_CTL = IOC_PE14_FUNC_CTL_UART3_RXD;
24 HPM_IOC->PAD[IOC_PAD_PE15].FUNC_CTL = IOC_PE15_FUNC_CTL_UART3_TXD;
25 } else if (ptr == HPM_PUART) {
26 HPM_PIOC->PAD[IOC_PAD_PY00].FUNC_CTL = IOC_PY00_FUNC_CTL_PURT_TXD;
27 HPM_PIOC->PAD[IOC_PAD_PY01].FUNC_CTL = IOC_PY01_FUNC_CTL_PURT_RXD;
28 } else {
29 ;
30 }
31 }
32
init_cap_pins(void)33 void init_cap_pins(void)
34 {
35 /* CAP_INT */
36 HPM_IOC->PAD[IOC_PAD_PY06].PAD_CTL = IOC_PAD_PAD_CTL_PE_MASK;
37 HPM_IOC->PAD[IOC_PAD_PY06].FUNC_CTL = IOC_PY06_FUNC_CTL_GPIO_Y_06;
38 HPM_PIOC->PAD[IOC_PAD_PY06].FUNC_CTL = IOC_PY06_FUNC_CTL_SOC_PY_06;
39 /* CAP_RST */
40 HPM_IOC->PAD[IOC_PAD_PY07].PAD_CTL = IOC_PAD_PAD_CTL_PE_MASK;
41 HPM_IOC->PAD[IOC_PAD_PY07].FUNC_CTL = IOC_PY07_FUNC_CTL_GPIO_Y_07;
42 HPM_PIOC->PAD[IOC_PAD_PY07].FUNC_CTL = IOC_PY07_FUNC_CTL_SOC_PY_07;
43 }
44
init_i2c_pins_as_gpio(I2C_Type * ptr)45 void init_i2c_pins_as_gpio(I2C_Type *ptr)
46 {
47 if (ptr == HPM_I2C3) {
48 HPM_IOC->PAD[IOC_PAD_PD28].FUNC_CTL = IOC_PD28_FUNC_CTL_GPIO_D_28;
49 HPM_IOC->PAD[IOC_PAD_PD29].FUNC_CTL = IOC_PD29_FUNC_CTL_GPIO_D_29;
50 } else if (ptr == HPM_I2C1) {
51 HPM_IOC->PAD[IOC_PAD_PE12].FUNC_CTL = IOC_PE12_FUNC_CTL_GPIO_E_12;
52 HPM_IOC->PAD[IOC_PAD_PE13].FUNC_CTL = IOC_PE13_FUNC_CTL_GPIO_E_13;
53 } else if (ptr == HPM_I2C0) {
54 HPM_IOC->PAD[IOC_PAD_PF09].FUNC_CTL = IOC_PF09_FUNC_CTL_GPIO_F_09;
55 HPM_IOC->PAD[IOC_PAD_PF08].FUNC_CTL = IOC_PF08_FUNC_CTL_GPIO_F_08;
56 } else {
57 ;
58 }
59 }
60
init_i2c_pins(I2C_Type * ptr)61 void init_i2c_pins(I2C_Type *ptr)
62 {
63 if (ptr == HPM_I2C3) { /* Audio */
64 HPM_IOC->PAD[IOC_PAD_PD28].FUNC_CTL = IOC_PD28_FUNC_CTL_I2C3_SDA
65 | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK;
66 HPM_IOC->PAD[IOC_PAD_PD29].FUNC_CTL = IOC_PD29_FUNC_CTL_I2C3_SCL
67 | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK;
68 HPM_IOC->PAD[IOC_PAD_PD28].PAD_CTL = IOC_PAD_PAD_CTL_OD_MASK;
69 HPM_IOC->PAD[IOC_PAD_PD29].PAD_CTL = IOC_PAD_PAD_CTL_OD_MASK;
70 } else if (ptr == HPM_I2C1) { /* Storage */
71 HPM_IOC->PAD[IOC_PAD_PE12].FUNC_CTL = IOC_PE12_FUNC_CTL_I2C1_SDA
72 | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK;
73 HPM_IOC->PAD[IOC_PAD_PE13].FUNC_CTL = IOC_PE13_FUNC_CTL_I2C1_SCL
74 | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK;
75 HPM_IOC->PAD[IOC_PAD_PE12].PAD_CTL = IOC_PAD_PAD_CTL_OD_MASK;
76 HPM_IOC->PAD[IOC_PAD_PE13].PAD_CTL = IOC_PAD_PAD_CTL_OD_MASK;
77 } else if (ptr == HPM_I2C0) { /* Touch Panel/ Camera */
78 HPM_IOC->PAD[IOC_PAD_PF09].FUNC_CTL = IOC_PF09_FUNC_CTL_I2C0_SDA
79 | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK;
80 HPM_IOC->PAD[IOC_PAD_PF08].FUNC_CTL = IOC_PF08_FUNC_CTL_I2C0_SCL
81 | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK;
82 HPM_IOC->PAD[IOC_PAD_PF09].PAD_CTL = IOC_PAD_PAD_CTL_OD_MASK;
83 HPM_IOC->PAD[IOC_PAD_PF08].PAD_CTL = IOC_PAD_PAD_CTL_OD_MASK;
84 } else {
85 ;
86 }
87 }
88
init_cam_pins(void)89 void init_cam_pins(void)
90 {
91 /* configure rst pin function */
92 HPM_IOC->PAD[IOC_PAD_PA22].FUNC_CTL = IOC_PA22_FUNC_CTL_GPIO_A_22;
93 /* configure pwdn pin function */
94 HPM_PIOC->PAD[IOC_PAD_PA21].FUNC_CTL = IOC_PA21_FUNC_CTL_GPIO_A_21;
95
96 HPM_IOC->PAD[IOC_PAD_PA29].FUNC_CTL = IOC_PA29_FUNC_CTL_CAM0_XCLK;
97 HPM_IOC->PAD[IOC_PAD_PA26].FUNC_CTL = IOC_PA26_FUNC_CTL_CAM0_PIXCLK;
98 HPM_IOC->PAD[IOC_PAD_PB21].FUNC_CTL = IOC_PB21_FUNC_CTL_CAM0_VSYNC;
99 HPM_IOC->PAD[IOC_PAD_PB20].FUNC_CTL = IOC_PB20_FUNC_CTL_CAM0_HSYNC;
100 HPM_IOC->PAD[IOC_PAD_PA27].FUNC_CTL = IOC_PA27_FUNC_CTL_CAM0_D_2;
101 HPM_IOC->PAD[IOC_PAD_PA25].FUNC_CTL = IOC_PA25_FUNC_CTL_CAM0_D_3;
102 HPM_IOC->PAD[IOC_PAD_PA23].FUNC_CTL = IOC_PA23_FUNC_CTL_CAM0_D_4;
103 HPM_IOC->PAD[IOC_PAD_PA24].FUNC_CTL = IOC_PA24_FUNC_CTL_CAM0_D_5;
104 HPM_IOC->PAD[IOC_PAD_PB16].FUNC_CTL = IOC_PB16_FUNC_CTL_CAM0_D_6;
105 HPM_IOC->PAD[IOC_PAD_PB17].FUNC_CTL = IOC_PB17_FUNC_CTL_CAM0_D_7;
106 HPM_IOC->PAD[IOC_PAD_PB19].FUNC_CTL = IOC_PB19_FUNC_CTL_CAM0_D_8;
107 HPM_IOC->PAD[IOC_PAD_PB18].FUNC_CTL = IOC_PB18_FUNC_CTL_CAM0_D_9;
108 }
109
init_cam_mipi_csi_pins(void)110 void init_cam_mipi_csi_pins(void)
111 {
112 /* configure rst pin function */
113 HPM_IOC->PAD[IOC_PAD_PB00].FUNC_CTL = IOC_PB00_FUNC_CTL_GPIO_B_00;
114 HPM_IOC->PAD[IOC_PAD_PB00].PAD_CTL = IOC_PAD_PAD_CTL_OD_MASK;
115 }
116
init_sdm_pins(void)117 void init_sdm_pins(void)
118 {
119
120 }
121
init_gpio_pins(void)122 void init_gpio_pins(void)
123 {
124 /* configure pad setting: pull enable and pull up, schmitt trigger enable */
125 /* enable schmitt trigger to eliminate jitter of pin used as button */
126 HPM_IOC->PAD[IOC_PAD_PF06].FUNC_CTL = IOC_PF06_FUNC_CTL_GPIO_F_06;
127 HPM_IOC->PAD[IOC_PAD_PF06].PAD_CTL = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1) | IOC_PAD_PAD_CTL_HYS_MASK;
128
129 HPM_IOC->PAD[IOC_PAD_PF07].FUNC_CTL = IOC_PF07_FUNC_CTL_GPIO_F_07;
130 HPM_IOC->PAD[IOC_PAD_PF07].PAD_CTL = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1) | IOC_PAD_PAD_CTL_HYS_MASK;
131 }
132
init_spi_pins(SPI_Type * ptr)133 void init_spi_pins(SPI_Type *ptr)
134 {
135 if (ptr == HPM_SPI3) {
136 HPM_IOC->PAD[IOC_PAD_PE05].FUNC_CTL = IOC_PE05_FUNC_CTL_SPI3_SCLK | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1);
137 HPM_IOC->PAD[IOC_PAD_PE06].FUNC_CTL = IOC_PE06_FUNC_CTL_SPI3_MISO;
138 HPM_IOC->PAD[IOC_PAD_PE07].FUNC_CTL = IOC_PE07_FUNC_CTL_SPI3_MOSI;
139 HPM_IOC->PAD[IOC_PAD_PE04].FUNC_CTL = IOC_PE04_FUNC_CTL_SPI3_CS_0;
140 }
141 }
142
init_spi_pins_with_gpio_as_cs(SPI_Type * ptr)143 void init_spi_pins_with_gpio_as_cs(SPI_Type *ptr)
144 {
145 if (ptr == HPM_SPI3) {
146 HPM_IOC->PAD[IOC_PAD_PE05].FUNC_CTL = IOC_PE05_FUNC_CTL_SPI3_SCLK | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1);
147 HPM_IOC->PAD[IOC_PAD_PE06].FUNC_CTL = IOC_PE06_FUNC_CTL_SPI3_MISO;
148 HPM_IOC->PAD[IOC_PAD_PE07].FUNC_CTL = IOC_PE07_FUNC_CTL_SPI3_MOSI;
149 HPM_IOC->PAD[IOC_PAD_PE04].FUNC_CTL = IOC_PE04_FUNC_CTL_GPIO_E_04;
150 }
151 }
152
init_pins(void)153 void init_pins(void)
154 {
155 #ifdef BOARD_CONSOLE_BASE
156 init_uart_pins(BOARD_CONSOLE_BASE);
157 #endif
158 }
159
init_gptmr_pins(GPTMR_Type * ptr)160 void init_gptmr_pins(GPTMR_Type *ptr)
161 {
162 if (ptr == HPM_GPTMR2) {
163 HPM_IOC->PAD[IOC_PAD_PE22].FUNC_CTL = IOC_PE22_FUNC_CTL_GPTMR2_CAPT_0;
164 HPM_IOC->PAD[IOC_PAD_PE23].FUNC_CTL = IOC_PE23_FUNC_CTL_GPTMR2_COMP_0;
165 HPM_IOC->PAD[IOC_PAD_PE24].FUNC_CTL = IOC_PE24_FUNC_CTL_GPTMR2_COMP_1;
166 }
167 }
168
init_butn_pins(void)169 void init_butn_pins(void)
170 {
171
172 }
173
init_acmp_pins(void)174 void init_acmp_pins(void)
175 {
176
177 }
178
init_sdxc_cmd_pin(SDXC_Type * ptr,bool open_drain,bool is_1v8)179 void init_sdxc_cmd_pin(SDXC_Type *ptr, bool open_drain, bool is_1v8)
180 {
181 (void) is_1v8;
182 /* Pull-up */
183 uint32_t pad_ctl = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1) | IOC_PAD_PAD_CTL_PRS_SET(2) | \
184 IOC_PAD_PAD_CTL_SR_SET(1) | IOC_PAD_PAD_CTL_SPD_SET(3) | IOC_PAD_PAD_CTL_DS_SET(6);
185 if (ptr == HPM_SDXC0) {
186 if (open_drain) {
187 pad_ctl |= IOC_PAD_PAD_CTL_OD_MASK;
188 }
189 HPM_IOC->PAD[IOC_PAD_PC01].FUNC_CTL = IOC_PC01_FUNC_CTL_SDC0_CMD | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1);
190 HPM_IOC->PAD[IOC_PAD_PC01].PAD_CTL = pad_ctl;
191 }
192 if (ptr == HPM_SDXC1) {
193 HPM_IOC->PAD[IOC_PAD_PC13].FUNC_CTL = IOC_PC13_FUNC_CTL_SDC1_CMD | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1);
194 HPM_IOC->PAD[IOC_PAD_PC13].PAD_CTL = pad_ctl;
195 }
196 }
197
198
init_sdxc_ds_pin(SDXC_Type * ptr)199 void init_sdxc_ds_pin(SDXC_Type *ptr)
200 {
201 #define SDXC_DS_PIN_SETTING (IOC_PAD_PAD_CTL_PE_SET(1) \
202 | IOC_PAD_PAD_CTL_SPD_SET(3) \
203 | IOC_PAD_PAD_CTL_SR_SET(1))
204 if (ptr == HPM_SDXC0) {
205 HPM_IOC->PAD[IOC_PAD_PC00].FUNC_CTL = IOC_PC00_FUNC_CTL_SDC0_DS;
206 HPM_IOC->PAD[IOC_PAD_PC00].PAD_CTL = SDXC_DS_PIN_SETTING;
207 }
208 }
209
init_sdxc_pwr_pin(SDXC_Type * ptr,bool as_gpio)210 void init_sdxc_pwr_pin(SDXC_Type *ptr, bool as_gpio)
211 {
212 if (ptr == HPM_SDXC1) {
213 if (as_gpio) {
214 /* SD_PWR */
215 HPM_IOC->PAD[IOC_PAD_PD07].FUNC_CTL = IOC_PD07_FUNC_CTL_GPIO_D_07;
216 HPM_IOC->PAD[IOC_PAD_PD07].PAD_CTL =
217 IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_DS_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1);
218 HPM_GPIO0->OE[GPIO_OE_GPIOD].SET = 1UL << 7;
219 }
220 }
221 }
222
init_sdxc_vsel_pin(SDXC_Type * ptr,bool as_gpio)223 void init_sdxc_vsel_pin(SDXC_Type *ptr, bool as_gpio)
224 {
225 if (ptr == HPM_SDXC1) {
226 if (as_gpio) {
227 /* VSEL */
228 HPM_IOC->PAD[IOC_PAD_PD12].FUNC_CTL = IOC_PD12_FUNC_CTL_GPIO_D_12;
229 HPM_IOC->PAD[IOC_PAD_PD12].PAD_CTL =
230 IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_DS_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1);
231 HPM_GPIO0->OE[GPIO_OE_GPIOD].SET = 1UL << 12;
232 }
233 }
234 }
235
init_sdxc_cd_pin(SDXC_Type * ptr,bool as_gpio)236 void init_sdxc_cd_pin(SDXC_Type *ptr, bool as_gpio)
237 {
238 if (ptr == HPM_SDXC1) {
239 if (as_gpio) {
240 /* CDN */
241 HPM_IOC->PAD[IOC_PAD_PD05].FUNC_CTL = IOC_PD05_FUNC_CTL_GPIO_D_05;
242 HPM_IOC->PAD[IOC_PAD_PD05].PAD_CTL =
243 IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_DS_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1);
244 HPM_GPIO0->OE[GPIO_OE_GPIOD].CLEAR = 1UL << 5;
245 }
246 }
247 }
248
init_sdxc_clk_data_pins(SDXC_Type * ptr,uint32_t width,bool is_1v8)249 void init_sdxc_clk_data_pins(SDXC_Type *ptr, uint32_t width, bool is_1v8)
250 {
251 (void) is_1v8;
252 #define SDXC_PIN_SETTING_COMMON (IOC_PAD_PAD_CTL_PE_SET(1) \
253 | IOC_PAD_PAD_CTL_SPD_SET(3) \
254 | IOC_PAD_PAD_CTL_SR_SET(1))
255 #define SDXC_PIN_SETTING (IOC_PAD_PAD_CTL_DS_SET(3) \
256 | SDXC_PIN_SETTING_COMMON \
257 | IOC_PAD_PAD_CTL_PS_SET(1) \
258 | IOC_PAD_PAD_CTL_PRS_SET(3))
259
260 uint32_t pad_ctl = SDXC_PIN_SETTING;
261 if (ptr == HPM_SDXC0) {
262 /*CLK*/
263 HPM_IOC->PAD[IOC_PAD_PC02].FUNC_CTL = IOC_PC02_FUNC_CTL_SDC0_CLK | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1);
264 HPM_IOC->PAD[IOC_PAD_PC02].PAD_CTL = pad_ctl;
265
266 /* DAT0-DATA7 */
267 HPM_IOC->PAD[IOC_PAD_PC06].FUNC_CTL = IOC_PC06_FUNC_CTL_SDC0_DATA_0;
268 HPM_IOC->PAD[IOC_PAD_PC06].PAD_CTL = pad_ctl;
269 if ((width == 4) || (width == 8)) {
270 HPM_IOC->PAD[IOC_PAD_PC03].FUNC_CTL = IOC_PC03_FUNC_CTL_SDC0_DATA_1;
271 HPM_IOC->PAD[IOC_PAD_PC03].PAD_CTL = pad_ctl;
272 HPM_IOC->PAD[IOC_PAD_PC04].FUNC_CTL = IOC_PC04_FUNC_CTL_SDC0_DATA_2;
273 HPM_IOC->PAD[IOC_PAD_PC04].PAD_CTL = pad_ctl;
274 HPM_IOC->PAD[IOC_PAD_PC05].FUNC_CTL = IOC_PC05_FUNC_CTL_SDC0_DATA_3;
275 HPM_IOC->PAD[IOC_PAD_PC05].PAD_CTL = pad_ctl;
276 }
277 if (width == 8) {
278 HPM_IOC->PAD[IOC_PAD_PC08].FUNC_CTL = IOC_PC08_FUNC_CTL_SDC0_DATA_4;
279 HPM_IOC->PAD[IOC_PAD_PC08].PAD_CTL = pad_ctl;
280 HPM_IOC->PAD[IOC_PAD_PC09].FUNC_CTL = IOC_PC09_FUNC_CTL_SDC0_DATA_5;
281 HPM_IOC->PAD[IOC_PAD_PC09].PAD_CTL = pad_ctl;
282 HPM_IOC->PAD[IOC_PAD_PC10].FUNC_CTL = IOC_PC10_FUNC_CTL_SDC0_DATA_6;
283 HPM_IOC->PAD[IOC_PAD_PC10].PAD_CTL = pad_ctl;
284 HPM_IOC->PAD[IOC_PAD_PC11].FUNC_CTL = IOC_PC11_FUNC_CTL_SDC0_DATA_7;
285 HPM_IOC->PAD[IOC_PAD_PC11].PAD_CTL = pad_ctl;
286 }
287 }
288 if (ptr == HPM_SDXC1) {
289 /*CLK*/
290 HPM_IOC->PAD[IOC_PAD_PC16].FUNC_CTL = IOC_PC16_FUNC_CTL_SDC1_CLK | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1);
291 HPM_IOC->PAD[IOC_PAD_PC16].PAD_CTL = pad_ctl;
292
293 /* DAT0 -DATA3 */
294 HPM_IOC->PAD[IOC_PAD_PC17].FUNC_CTL = IOC_PC17_FUNC_CTL_SDC1_DATA_0;
295 HPM_IOC->PAD[IOC_PAD_PC17].PAD_CTL = pad_ctl;
296 HPM_IOC->PAD[IOC_PAD_PC15].FUNC_CTL = IOC_PC15_FUNC_CTL_SDC1_DATA_1;
297 HPM_IOC->PAD[IOC_PAD_PC15].PAD_CTL = pad_ctl;
298 HPM_IOC->PAD[IOC_PAD_PC14].FUNC_CTL = IOC_PC14_FUNC_CTL_SDC1_DATA_2;
299 HPM_IOC->PAD[IOC_PAD_PC14].PAD_CTL = pad_ctl;
300 HPM_IOC->PAD[IOC_PAD_PC12].FUNC_CTL = IOC_PC12_FUNC_CTL_SDC1_DATA_3;
301 HPM_IOC->PAD[IOC_PAD_PC12].PAD_CTL = pad_ctl;
302 }
303 }
304
305
306
init_usb_pins(void)307 void init_usb_pins(void)
308 {
309 /* USB0_ID */
310 HPM_IOC->PAD[IOC_PAD_PF04].FUNC_CTL = IOC_PF04_FUNC_CTL_USB0_ID;
311 /* USB0_OC */
312 HPM_IOC->PAD[IOC_PAD_PF03].FUNC_CTL = IOC_PF03_FUNC_CTL_USB0_OC;
313 /* USB0_PWR */
314 HPM_IOC->PAD[IOC_PAD_PF00].FUNC_CTL = IOC_PF00_FUNC_CTL_USB0_PWR;
315 }
316
init_can_pins(MCAN_Type * ptr)317 void init_can_pins(MCAN_Type *ptr)
318 {
319 if (ptr == HPM_MCAN3) {
320 HPM_IOC->PAD[IOC_PAD_PD15].FUNC_CTL = IOC_PD15_FUNC_CTL_CAN3_TXD;
321 HPM_IOC->PAD[IOC_PAD_PD14].FUNC_CTL = IOC_PD14_FUNC_CTL_CAN3_RXD;
322 HPM_IOC->PAD[IOC_PAD_PD13].FUNC_CTL = IOC_PD13_FUNC_CTL_CAN3_STBY;
323 }
324 }
325
init_clk_obs_pins(void)326 void init_clk_obs_pins(void)
327 {
328 /* HPM_IOC->PAD[IOC_PAD_PB02].FUNC_CTL = IOC_PB02_FUNC_CTL_SYSCTL_CLK_OBS_0; */
329 }
330
init_led_pins_as_gpio(void)331 void init_led_pins_as_gpio(void)
332 {
333 HPM_IOC->PAD[IOC_PAD_PF01].FUNC_CTL = IOC_PF01_FUNC_CTL_GPIO_F_01;
334 HPM_IOC->PAD[IOC_PAD_PF02].FUNC_CTL = IOC_PF02_FUNC_CTL_GPIO_F_02;
335 HPM_IOC->PAD[IOC_PAD_PF05].FUNC_CTL = IOC_PF05_FUNC_CTL_GPIO_F_05;
336 }
337
init_mipi_lvds_tx_phy0_pin(void)338 void init_mipi_lvds_tx_phy0_pin(void)
339 {
340 HPM_IOC->PAD[IOC_PAD_PB04].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
341 HPM_IOC->PAD[IOC_PAD_PB05].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
342 HPM_IOC->PAD[IOC_PAD_PB06].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
343 HPM_IOC->PAD[IOC_PAD_PB07].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
344 HPM_IOC->PAD[IOC_PAD_PB08].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
345 HPM_IOC->PAD[IOC_PAD_PB09].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
346 HPM_IOC->PAD[IOC_PAD_PB10].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
347 HPM_IOC->PAD[IOC_PAD_PB11].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
348 HPM_IOC->PAD[IOC_PAD_PB12].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
349 HPM_IOC->PAD[IOC_PAD_PB13].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
350 HPM_IOC->PAD[IOC_PAD_PB14].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; /*REXT*/
351 }
352
init_mipi_lvds_tx_phy1_pin(void)353 void init_mipi_lvds_tx_phy1_pin(void)
354 {
355 HPM_IOC->PAD[IOC_PAD_PB22].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
356 HPM_IOC->PAD[IOC_PAD_PB23].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
357 HPM_IOC->PAD[IOC_PAD_PB24].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
358 HPM_IOC->PAD[IOC_PAD_PB25].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
359 HPM_IOC->PAD[IOC_PAD_PB26].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
360 HPM_IOC->PAD[IOC_PAD_PB27].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
361 HPM_IOC->PAD[IOC_PAD_PB28].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
362 HPM_IOC->PAD[IOC_PAD_PB29].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
363 HPM_IOC->PAD[IOC_PAD_PB30].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
364 HPM_IOC->PAD[IOC_PAD_PB31].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
365 HPM_IOC->PAD[IOC_PAD_PB15].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; /*REXT*/
366 }
367
init_mipi_lvds_rx_phy0_pin(void)368 void init_mipi_lvds_rx_phy0_pin(void)
369 {
370 HPM_IOC->PAD[IOC_PAD_PA30].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
371 HPM_IOC->PAD[IOC_PAD_PA31].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
372 HPM_IOC->PAD[IOC_PAD_PB00].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
373 HPM_IOC->PAD[IOC_PAD_PB01].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
374 HPM_IOC->PAD[IOC_PAD_PB02].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
375 HPM_IOC->PAD[IOC_PAD_PB03].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
376 HPM_IOC->PAD[IOC_PAD_PA28].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; /*REXT*/
377 }
378
init_mipi_lvds_rx_phy1_pin(void)379 void init_mipi_lvds_rx_phy1_pin(void)
380 {
381 HPM_IOC->PAD[IOC_PAD_PB16].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
382 HPM_IOC->PAD[IOC_PAD_PB17].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
383 HPM_IOC->PAD[IOC_PAD_PB18].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
384 HPM_IOC->PAD[IOC_PAD_PB19].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
385 HPM_IOC->PAD[IOC_PAD_PB20].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
386 HPM_IOC->PAD[IOC_PAD_PB21].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
387 HPM_IOC->PAD[IOC_PAD_PA29].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; /*REXT*/
388 }
389
init_lcd_mipi_ctl_pins(void)390 void init_lcd_mipi_ctl_pins(void)
391 {
392 /* RESET */
393 HPM_IOC->PAD[IOC_PAD_PB01].FUNC_CTL = IOC_PB01_FUNC_CTL_GPIO_B_01;
394 }
395
init_lcd_lvds_double_ctl_pins(void)396 void init_lcd_lvds_double_ctl_pins(void)
397 {
398 /* RESET */
399 HPM_IOC->PAD[IOC_PAD_PA31].FUNC_CTL = IOC_PA31_FUNC_CTL_GPIO_A_31;
400 }
401
init_lcd_lvds_single_ctl_pins(void)402 void init_lcd_lvds_single_ctl_pins(void)
403 {
404 /* LED-EN */
405 HPM_IOC->PAD[IOC_PAD_PA30].FUNC_CTL = IOC_PA30_FUNC_CTL_GPIO_A_30;
406
407 /* PWM */
408 HPM_IOC->PAD[IOC_PAD_PA31].FUNC_CTL = IOC_PA31_FUNC_CTL_GPIO_A_31;
409 }
410
init_lcd_rgb_ctl_pins(void)411 void init_lcd_rgb_ctl_pins(void)
412 {
413 /* PWM */
414 HPM_IOC->PAD[IOC_PAD_PA09].FUNC_CTL = IOC_PA09_FUNC_CTL_GPIO_A_09;
415 /* RST */
416 HPM_IOC->PAD[IOC_PAD_PA14].FUNC_CTL = IOC_PA14_FUNC_CTL_GPIO_A_14;
417
418 HPM_IOC->PAD[IOC_PAD_PY05].PAD_CTL = IOC_PAD_PAD_CTL_PE_MASK;
419 HPM_IOC->PAD[IOC_PAD_PY05].FUNC_CTL = IOC_PY05_FUNC_CTL_GPIO_Y_05;
420 HPM_PIOC->PAD[IOC_PAD_PY05].FUNC_CTL = IOC_PY05_FUNC_CTL_SOC_PY_05;
421 }
422
init_lcd_rgb_pins(void)423 void init_lcd_rgb_pins(void)
424 {
425 HPM_IOC->PAD[IOC_PAD_PA10].FUNC_CTL = IOC_PA10_FUNC_CTL_DIS0_G_4;
426 HPM_IOC->PAD[IOC_PAD_PA11].FUNC_CTL = IOC_PA11_FUNC_CTL_DIS0_G_3;
427 HPM_IOC->PAD[IOC_PAD_PA12].FUNC_CTL = IOC_PA12_FUNC_CTL_DIS0_G_6;
428 HPM_IOC->PAD[IOC_PAD_PA13].FUNC_CTL = IOC_PA13_FUNC_CTL_DIS0_G_5;
429 HPM_IOC->PAD[IOC_PAD_PA15].FUNC_CTL = IOC_PA15_FUNC_CTL_DIS0_R_3;
430 HPM_IOC->PAD[IOC_PAD_PA16].FUNC_CTL = IOC_PA16_FUNC_CTL_DIS0_R_5;
431 HPM_IOC->PAD[IOC_PAD_PA17].FUNC_CTL = IOC_PA17_FUNC_CTL_DIS0_R_4;
432 HPM_IOC->PAD[IOC_PAD_PA18].FUNC_CTL = IOC_PA18_FUNC_CTL_DIS0_R_7;
433 HPM_IOC->PAD[IOC_PAD_PA19].FUNC_CTL = IOC_PA19_FUNC_CTL_DIS0_R_6;
434 HPM_IOC->PAD[IOC_PAD_PA20].FUNC_CTL = IOC_PA20_FUNC_CTL_DIS0_G_2;
435 HPM_IOC->PAD[IOC_PAD_PA28].FUNC_CTL = IOC_PA28_FUNC_CTL_DIS0_R_0;
436 HPM_IOC->PAD[IOC_PAD_PA30].FUNC_CTL = IOC_PA30_FUNC_CTL_DIS0_R_2;
437 HPM_IOC->PAD[IOC_PAD_PA31].FUNC_CTL = IOC_PA31_FUNC_CTL_DIS0_R_1;
438
439 HPM_IOC->PAD[IOC_PAD_PB00].FUNC_CTL = IOC_PB00_FUNC_CTL_DIS0_G_1;
440 HPM_IOC->PAD[IOC_PAD_PB01].FUNC_CTL = IOC_PB01_FUNC_CTL_DIS0_G_0;
441 HPM_IOC->PAD[IOC_PAD_PB02].FUNC_CTL = IOC_PB02_FUNC_CTL_DIS0_B_1;
442 HPM_IOC->PAD[IOC_PAD_PB03].FUNC_CTL = IOC_PB03_FUNC_CTL_DIS0_B_0;
443 HPM_IOC->PAD[IOC_PAD_PB04].FUNC_CTL = IOC_PB04_FUNC_CTL_DIS0_B_2;
444 HPM_IOC->PAD[IOC_PAD_PB05].FUNC_CTL = IOC_PB05_FUNC_CTL_DIS0_G_7;
445 HPM_IOC->PAD[IOC_PAD_PB06].FUNC_CTL = IOC_PB06_FUNC_CTL_DIS0_B_3;
446 HPM_IOC->PAD[IOC_PAD_PB07].FUNC_CTL = IOC_PB07_FUNC_CTL_DIS0_B_4;
447 HPM_IOC->PAD[IOC_PAD_PB08].FUNC_CTL = IOC_PB08_FUNC_CTL_DIS0_B_6;
448 HPM_IOC->PAD[IOC_PAD_PB09].FUNC_CTL = IOC_PB09_FUNC_CTL_DIS0_B_5;
449 HPM_IOC->PAD[IOC_PAD_PB10].FUNC_CTL = IOC_PB10_FUNC_CTL_DIS0_EN;
450 HPM_IOC->PAD[IOC_PAD_PB11].FUNC_CTL = IOC_PB11_FUNC_CTL_DIS0_B_7;
451 HPM_IOC->PAD[IOC_PAD_PB12].FUNC_CTL = IOC_PB12_FUNC_CTL_DIS0_HSYNC;
452 HPM_IOC->PAD[IOC_PAD_PB14].FUNC_CTL = IOC_PB14_FUNC_CTL_DIS0_VSYNC;
453
454 HPM_IOC->PAD[IOC_PAD_PB13].FUNC_CTL = IOC_PB13_FUNC_CTL_DIS0_CLK; /*A.CLK*/
455 }
456
init_i2s_pins(I2S_Type * ptr)457 void init_i2s_pins(I2S_Type *ptr)
458 {
459 if (ptr == HPM_I2S3) {
460 HPM_IOC->PAD[IOC_PAD_PD30].FUNC_CTL = IOC_PD30_FUNC_CTL_I2S3_MCLK;
461 HPM_IOC->PAD[IOC_PAD_PD24].FUNC_CTL = IOC_PD24_FUNC_CTL_I2S3_BCLK;
462 HPM_IOC->PAD[IOC_PAD_PD25].FUNC_CTL = IOC_PD25_FUNC_CTL_I2S3_FCLK;
463 HPM_IOC->PAD[IOC_PAD_PD27].FUNC_CTL = IOC_PD27_FUNC_CTL_I2S3_TXD_2;
464 HPM_IOC->PAD[IOC_PAD_PD23].FUNC_CTL = IOC_PD23_FUNC_CTL_I2S3_RXD_2;
465 }
466 }
467
init_dao_pins(void)468 void init_dao_pins(void)
469 {
470 HPM_IOC->PAD[IOC_PAD_PC31].FUNC_CTL = IOC_PC31_FUNC_CTL_DAO_LP;
471 HPM_IOC->PAD[IOC_PAD_PC30].FUNC_CTL = IOC_PC30_FUNC_CTL_DAO_LN;
472 HPM_IOC->PAD[IOC_PAD_PD01].FUNC_CTL = IOC_PD01_FUNC_CTL_DAO_RP;
473 HPM_IOC->PAD[IOC_PAD_PD00].FUNC_CTL = IOC_PD00_FUNC_CTL_DAO_RN;
474 }
475
init_pdm_pins(void)476 void init_pdm_pins(void)
477 {
478 HPM_IOC->PAD[IOC_PAD_PE00].FUNC_CTL = IOC_PE00_FUNC_CTL_PDM0_CLK;
479 HPM_IOC->PAD[IOC_PAD_PE01].FUNC_CTL = IOC_PE01_FUNC_CTL_PDM0_D_1;
480 }
481
init_enet_pins(ENET_Type * ptr)482 void init_enet_pins(ENET_Type *ptr)
483 {
484 if (ptr == HPM_ENET0) {
485 HPM_IOC->PAD[IOC_PAD_PD18].FUNC_CTL = IOC_PD18_FUNC_CTL_GPIO_D_18;
486
487 HPM_IOC->PAD[IOC_PAD_PD02].FUNC_CTL = IOC_PD02_FUNC_CTL_ETH0_MDC;
488 HPM_IOC->PAD[IOC_PAD_PD03].FUNC_CTL = IOC_PD03_FUNC_CTL_ETH0_MDIO;
489
490 HPM_IOC->PAD[IOC_PAD_PC29].FUNC_CTL = IOC_PC29_FUNC_CTL_ETH0_RXD_0;
491 HPM_IOC->PAD[IOC_PAD_PC28].FUNC_CTL = IOC_PC28_FUNC_CTL_ETH0_RXD_1;
492 HPM_IOC->PAD[IOC_PAD_PC24].FUNC_CTL = IOC_PC24_FUNC_CTL_ETH0_RXD_2;
493 HPM_IOC->PAD[IOC_PAD_PC25].FUNC_CTL = IOC_PC25_FUNC_CTL_ETH0_RXD_3;
494 HPM_IOC->PAD[IOC_PAD_PC26].FUNC_CTL = IOC_PC26_FUNC_CTL_ETH0_RXCK;
495 HPM_IOC->PAD[IOC_PAD_PC27].FUNC_CTL = IOC_PC27_FUNC_CTL_ETH0_RXDV;
496
497 HPM_IOC->PAD[IOC_PAD_PC22].FUNC_CTL = IOC_PC22_FUNC_CTL_ETH0_TXD_0;
498 HPM_IOC->PAD[IOC_PAD_PC23].FUNC_CTL = IOC_PC23_FUNC_CTL_ETH0_TXD_1;
499 HPM_IOC->PAD[IOC_PAD_PC19].FUNC_CTL = IOC_PC19_FUNC_CTL_ETH0_TXD_2;
500 HPM_IOC->PAD[IOC_PAD_PC18].FUNC_CTL = IOC_PC18_FUNC_CTL_ETH0_TXD_3;
501 HPM_IOC->PAD[IOC_PAD_PC20].FUNC_CTL = IOC_PC20_FUNC_CTL_ETH0_TXCK;
502 HPM_IOC->PAD[IOC_PAD_PC21].FUNC_CTL = IOC_PC21_FUNC_CTL_ETH0_TXEN;
503 }
504 }
505
init_enet_pps_pins(void)506 void init_enet_pps_pins(void)
507 {
508 HPM_IOC->PAD[IOC_PAD_PD31].FUNC_CTL = IOC_PD31_FUNC_CTL_ETH0_EVTO_0;
509 }
510
init_adc_pins(void)511 void init_adc_pins(void)
512 {
513 HPM_IOC->PAD[IOC_PAD_PE16].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
514 HPM_IOC->PAD[IOC_PAD_PE17].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
515 HPM_IOC->PAD[IOC_PAD_PE18].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
516 HPM_IOC->PAD[IOC_PAD_PE19].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
517 HPM_IOC->PAD[IOC_PAD_PE21].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
518 HPM_IOC->PAD[IOC_PAD_PE22].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
519 HPM_IOC->PAD[IOC_PAD_PE23].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
520 HPM_IOC->PAD[IOC_PAD_PE24].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
521 HPM_IOC->PAD[IOC_PAD_PE25].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
522 HPM_IOC->PAD[IOC_PAD_PE26].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
523 HPM_IOC->PAD[IOC_PAD_PE27].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
524 HPM_IOC->PAD[IOC_PAD_PE28].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
525 HPM_IOC->PAD[IOC_PAD_PE29].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
526 HPM_IOC->PAD[IOC_PAD_PE30].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
527 HPM_IOC->PAD[IOC_PAD_PE31].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
528 }
529