1 /* 2 * Copyright (c) 2015, Freescale Semiconductor, Inc. 3 * Copyright 2016-2019 NXP 4 * Copyright (c) 2021 HPMicro 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 * 8 */ 9 10 #ifndef _HPM_SGTL5000_H_ 11 #define _HPM_SGTL5000_H_ 12 13 #include "hpm_i2c_drv.h" 14 15 /*! 16 * @addtogroup sgtl5000 17 * @ingroup codec 18 * @{ 19 */ 20 21 /******************************************************************************* 22 * Definitions 23 ******************************************************************************/ 24 25 /*! @brief Define the register address of sgtl5000. */ 26 #define CHIP_ID 0x0000U 27 #define CHIP_DIG_POWER 0x0002U 28 #define CHIP_CLK_CTRL 0x0004U 29 #define CHIP_I2S_CTRL 0x0006U 30 #define CHIP_SSS_CTRL 0x000AU 31 #define CHIP_ADCDAC_CTRL 0x000EU 32 #define CHIP_DAC_VOL 0x0010U 33 #define CHIP_PAD_STRENGTH 0x0014U 34 #define CHIP_ANA_ADC_CTRL 0x0020U 35 #define CHIP_ANA_HP_CTRL 0x0022U 36 #define CHIP_ANA_CTRL 0x0024U 37 #define CHIP_LINREG_CTRL 0x0026U 38 #define CHIP_REF_CTRL 0x0028U 39 #define CHIP_MIC_CTRL 0x002AU 40 #define CHIP_LINE_OUT_CTRL 0x002CU 41 #define CHIP_LINE_OUT_VOL 0x002EU 42 #define CHIP_ANA_POWER 0x0030U 43 #define CHIP_PLL_CTRL 0x0032U 44 #define CHIP_CLK_TOP_CTRL 0x0034U 45 #define CHIP_ANA_STATUS 0x0036U 46 #define CHIP_ANA_TEST2 0x003AU 47 #define CHIP_SHORT_CTRL 0x003CU 48 #define SGTL5000_DAP_CONTROL 0x0100U 49 #define SGTL5000_DAP_PEQ 0x0102U 50 #define SGTL5000_DAP_BASS_ENHANCE 0x0104U 51 #define SGTL5000_DAP_BASS_ENHANCE_CTRL 0x0106U 52 #define SGTL5000_DAP_AUDIO_EQ 0x0108U 53 #define SGTL5000_DAP_SGTL_SURROUND 0x010AU 54 #define SGTL5000_DAP_FILTER_COEF_ACCESS 0x010CU 55 #define SGTL5000_DAP_COEF_WR_B0_MSB 0x010EU 56 #define SGTL5000_DAP_COEF_WR_B0_LSB 0x0110U 57 #define SGTL5000_DAP_AUDIO_EQ_BASS_BAND0 0x0116U 58 #define SGTL5000_DAP_AUDIO_EQ_BAND1 0x0118U 59 #define SGTL5000_DAP_AUDIO_EQ_BAND2 0x011AU 60 #define SGTL5000_DAP_AUDIO_EQ_BAND3 0x011CU 61 #define SGTL5000_DAP_AUDIO_EQ_TREBLE_BAND4 0x011EU 62 #define SGTL5000_DAP_MAIN_CHAN 0x0120U 63 #define SGTL5000_DAP_MIX_CHAN 0x0122U 64 #define SGTL5000_DAP_AVC_CTRL 0x0124U 65 #define SGTL5000_DAP_AVC_THRESHOLD 0x0126U 66 #define SGTL5000_DAP_AVC_ATTACK 0x0128U 67 #define SGTL5000_DAP_AVC_DECAY 0x012AU 68 #define SGTL5000_DAP_COEF_WR_B1_MSB 0x012CU 69 #define SGTL5000_DAP_COEF_WR_B1_LSB 0x012EU 70 #define SGTL5000_DAP_COEF_WR_B2_MSB 0x0130U 71 #define SGTL5000_DAP_COEF_WR_B2_LSB 0x0132U 72 #define SGTL5000_DAP_COEF_WR_A1_MSB 0x0134U 73 #define SGTL5000_DAP_COEF_WR_A1_LSB 0x0136U 74 #define SGTL5000_DAP_COEF_WR_A2_MSB 0x0138U 75 #define SGTL5000_DAP_COEF_WR_A2_LSB 0x013AU 76 77 /* 78 * Field Definitions. 79 */ 80 81 /* 82 * SGTL5000_CHIP_DIG_POWER 83 */ 84 #define SGTL5000_ADC_ENABLE_CLR_MASK 0xFFBFU 85 #define SGTL5000_ADC_ENABLE_GET_MASK 0x0040U 86 #define SGTL5000_ADC_ENABLE_SHIFT 0x6U 87 #define SGTL5000_DAC_ENABLE_CLR_MASK 0xFFDFU 88 #define SGTL5000_DAC_ENABLE_GET_MASK 0x0020U 89 #define SGTL5000_DAC_ENABLE_SHIFT 0x5U 90 #define SGTL5000_DAP_ENABLE_CLR_MASK 0xFFEFU 91 #define SGTL5000_DAP_ENABLE_GET_MASK 0x0010U 92 #define SGTL5000_DAP_ENABLE_SHIFT 0x4U 93 #define SGTL5000_I2S_OUT_ENABLE_CLR_MASK 0xFFFDU 94 #define SGTL5000_I2S_OUT_ENABLE_GET_MASK 0x0002U 95 #define SGTL5000_I2S_OUT_ENABLE_SHIFT 0x1U 96 #define SGTL5000_I2S_IN_ENABLE_CLR_MASK 0xFFFEU 97 #define SGTL5000_I2S_IN_ENABLE_GET_MASK 0x0001U 98 #define SGTL5000_I2S_IN_ENABLE_SHIFT 0x0U 99 100 /* 101 * SGTL5000_CHIP_CLK_CTRL 102 */ 103 #define SGTL5000_RATE_MODE_CLR_MASK 0xFFCFU 104 #define SGTL5000_RATE_MODE_GET_MASK 0x0030U 105 #define SGTL5000_RATE_MODE_SHIFT 0x4U 106 #define SGTL5000_RATE_MODE_DIV_1 0x0000U 107 #define SGTL5000_RATE_MODE_DIV_2 0x0010U 108 #define SGTL5000_RATE_MODE_DIV_4 0x0020U 109 #define SGTL5000_RATE_MODE_DIV_6 0x0030U 110 #define SGTL5000_SYS_FS_CLR_MASK 0xFFF3U 111 #define SGTL5000_SYS_FS_GET_MASK 0x000CU 112 #define SGTL5000_SYS_FS_SHIFT 0x2U 113 #define SGTL5000_SYS_FS_32k 0x0000U 114 #define SGTL5000_SYS_FS_44_1k 0x0004U 115 #define SGTL5000_SYS_FS_48k 0x0008U 116 #define SGTL5000_SYS_FS_96k 0x000CU 117 #define SGTL5000_MCLK_FREQ_CLR_MASK 0xFFFCU 118 #define SGTL5000_MCLK_FREQ_GET_MASK 0x0003U 119 #define SGTL5000_MCLK_FREQ_SHIFT 0x0U 120 #define SGTL5000_MCLK_FREQ_256FS 0x0000U 121 #define SGTL5000_MCLK_FREQ_384FS 0x0001U 122 #define SGTL5000_MCLK_FREQ_512FS 0x0002U 123 #define SGTL5000_MCLK_FREQ_PLL 0x0003U 124 125 /* 126 * SGTL5000_CHIP_I2S_CTRL 127 */ 128 #define SGTL5000_I2S_SLCKFREQ_CLR_MASK 0xFEFFU 129 #define SGTL5000_I2S_SCLKFREQ_GET_MASK 0x0100U 130 #define SGTL5000_I2S_SCLKFREQ_SHIFT 0x8U 131 #define SGTL5000_I2S_SCLKFREQ_64FS 0x0000U 132 #define SGTL5000_I2S_SCLKFREQ_32FS 0x0100U /* Not for RJ mode */ 133 #define SGTL5000_I2S_MS_CLR_MASK 0xFF7FU 134 #define SGTL5000_I2S_MS_GET_MASK 0x0080U 135 #define SGTL5000_I2S_MS_SHIFT 0x7U 136 #define SGTL5000_I2S_MASTER 0x0080U 137 #define SGTL5000_I2S_SLAVE 0x0000U 138 #define SGTL5000_I2S_SCLK_INV_CLR_MASK 0xFFBFU 139 #define SGTL5000_I2S_SCLK_INV_GET_MASK 0x0040U 140 #define SGTL5000_I2S_SCLK_INV_SHIFT 0x6U 141 #define SGTL5000_I2S_VAILD_FALLING_EDGE 0x0040U 142 #define SGTL5000_I2S_VAILD_RISING_EDGE 0x0000U 143 #define SGTL5000_I2S_DLEN_CLR_MASK 0xFFCFU 144 #define SGTL5000_I2S_DLEN_GET_MASK 0x0030U 145 #define SGTL5000_I2S_DLEN_SHIFT 0x4U 146 #define SGTL5000_I2S_DLEN_32 0x0000U 147 #define SGTL5000_I2S_DLEN_24 0x0010U 148 #define SGTL5000_I2S_DLEN_20 0x0020U 149 #define SGTL5000_I2S_DLEN_16 0x0030U 150 #define SGTL5000_I2S_MODE_CLR_MASK 0xFFF3U 151 #define SGTL5000_I2S_MODE_GET_MASK 0x000CU 152 #define SGTL5000_I2S_MODE_SHIFT 0x2U 153 #define SGTL5000_I2S_MODE_I2S_LJ 0x0000U 154 #define SGTL5000_I2S_MODE_RJ 0x0004U 155 #define SGTL5000_I2S_MODE_PCM 0x0008U 156 #define SGTL5000_I2S_LRALIGN_CLR_MASK 0xFFFDU 157 #define SGTL5000_I2S_LRALIGN_GET_MASK 0x0002U 158 #define SGTL5000_I2S_LRALIGN_SHIFT 0x1U 159 #define SGTL5000_I2S_ONE_BIT_DELAY 0x0000U 160 #define SGTL5000_I2S_NO_DELAY 0x0002U 161 #define SGTL5000_I2S_LRPOL_CLR_MASK 0xFFFEU 162 #define SGTL5000_I2S_LRPOL_GET_MASK 0x0001U 163 #define SGTL5000_I2S_LRPOL_SHIFT 0x0U 164 #define SGTL5000_I2S_LEFT_FIRST 0x0000U 165 #define SGTL5000_I2S_RIGHT_FIRST 0x0001U 166 167 /* 168 * SGTL5000_CHIP_SSS_CTRL 169 */ 170 #define SGTL5000_DAP_MIX_LRSWAP_CLR_MASK 0xBFFFU 171 #define SGTL5000_DAP_MIX_LRSWAP_GET_MASK 0x4000U 172 #define SGTL5000_DAP_MIX_LRSWAP_SHIFT 0xEU 173 #define SGTL5000_DAP_LRSWAP_CLR_MASK 0xDFFFU 174 #define SGTL5000_DAP_LRSWAP_GET_MASK 0x2000U 175 #define SGTL5000_DAP_LRSWAP_SHIFT 0xDU 176 #define SGTL5000_DAC_LRSWAP_CLR_MASK 0xEFFFU 177 #define SGTL5000_DAC_LRSWAP_GET_MASK 0x1000U 178 #define SGTL5000_DAC_LRSWAP_SHIFT 0xCU 179 #define SGTL5000_I2S_LRSWAP_CLR_MASK 0xFBFFU 180 #define SGTL5000_I2S_LRSWAP_GET_MASK 0x0400U 181 #define SGTL5000_I2S_LRSWAP_SHIFT 0xAU 182 #define SGTL5000_DAP_MIX_SEL_CLR_MASK 0xFCFFU 183 #define SGTL5000_DAP_MIX_SEL_GET_MASK 0x0300U 184 #define SGTL5000_DAP_MIX_SEL_SHIFT 0x8U 185 #define SGTL5000_DAP_MIX_SEL_ADC 0x0000U 186 #define SGTL5000_DAP_MIX_SEL_I2S_IN 0x0100U 187 #define SGTL5000_DAP_SEL_CLR_MASK 0xFF3FU 188 #define SGTL5000_DAP_SEL_GET_MASK 0x00C0U 189 #define SGTL5000_DAP_SEL_SHIFT 0x6U 190 #define SGTL5000_DAP_SEL_ADC 0x0000U 191 #define SGTL5000_DAP_SEL_I2S_IN 0x0040U 192 #define SGTL5000_DAC_SEL_CLR_MASK 0xFFCFU 193 #define SGTL5000_DAC_SEL_GET_MASK 0x0030U 194 #define SGTL5000_DAC_SEL_SHIFT 0x4U 195 #define SGTL5000_DAC_SEL_ADC 0x0000U 196 #define SGTL5000_DAC_SEL_I2S_IN 0x0010U 197 #define SGTL5000_DAC_SEL_DAP 0x0030U 198 #define SGTL5000_I2S_OUT_SEL_CLR_MASK 0xFFFCU 199 #define SGTL5000_I2S_OUT_SEL_GET_MASK 0x0003U 200 #define SGTL5000_I2S_OUT_SEL_SHIFT 0x0U 201 #define SGTL5000_I2S_OUT_SEL_ADC 0x0000U 202 #define SGTL5000_I2S_OUT_SEL_I2S_IN 0x0001U 203 #define SGTL5000_I2S_OUT_SEL_DAP 0x0003U 204 205 /* 206 * SGTL5000_CHIP_ADCDAC_CTRL 207 */ 208 #define SGTL5000_VOL_BUSY_DAC_RIGHT 0x2000U 209 #define SGTL5000_VOL_BUSY_DAC_LEFT 0x1000U 210 #define SGTL5000_DAC_VOL_RAMP_EN_CLR_MASK 0xFDFFU 211 #define SGTL5000_DAC_VOL_RAMP_EN_GET_MASK 0x0200U 212 #define SGTL5000_DAC_VOL_RAMP_EN_SHIFT 0x9U 213 #define SGTL5000_DAC_VOL_RAMP_EXPO_CLR_MASK 0xFEFFU 214 #define SGTL5000_DAC_VOL_RAMP_EXPO_GET_MASK 0x0100U 215 #define SGTL5000_DAC_VOL_RAMP_EXPO_SHIFT 0x8U 216 #define SGTL5000_DAC_MUTE_RIGHT_CLR_MASK 0xFFF7U 217 #define SGTL5000_DAC_MUTE_RIGHT_GET_MASK 0x0008U 218 #define SGTL5000_DAC_MUTE_RIGHT_SHIFT 0x3U 219 #define SGTL5000_DAC_MUTE_LEFT_CLR_MASK 0xFFFBU 220 #define SGTL5000_DAC_MUTE_LEFT_GET_MASK 0x0004U 221 #define SGTL5000_DAC_MUTE_LEFT_SHIFT 0x2U 222 #define SGTL5000_ADC_HPF_FREEZE_CLR_MASK 0xFFFDU 223 #define SGTL5000_ADC_HPF_FREEZE_GET_MASK 0x0002U 224 #define SGTL5000_ADC_HPF_FREEZE_SHIFT 0x1U 225 #define SGTL5000_ADC_HPF_BYPASS_CLR_MASK 0xFFFEU 226 #define SGTL5000_ADC_HPF_BYPASS_GET_MASK 0x0001U 227 #define SGTL5000_ADC_HPF_BYPASS_SHIFT 0x0U 228 229 /* 230 * SGTL5000_CHIP_DAC_VOL 231 */ 232 #define SGTL5000_DAC_VOL_RIGHT_CLR_MASK 0x00FFU 233 #define SGTL5000_DAC_VOL_RIGHT_GET_MASK 0xFF00U 234 #define SGTL5000_DAC_VOL_RIGHT_SHIFT 0x8U 235 #define SGTL5000_DAC_VOL_LEFT_CLR_MASK 0xFF00U 236 #define SGTL5000_DAC_VOL_LEFT_GET_MASK 0x00FFU 237 #define SGTL5000_DAC_VOL_LEFT_SHIFT 0x0U 238 239 /* 240 * SGTL5000_CHIP_PAD_STRENGTH 241 */ 242 #define SGTL5000_PAD_I2S_LRCLK_CLR_MASK 0xFCFFU 243 #define SGTL5000_PAD_I2S_LRCLK_GET_MASK 0x0300U 244 #define SGTL5000_PAD_I2S_LRCLK_SHIFT 0x8U 245 #define SGTL5000_PAD_I2S_SCLK_CLR_MASK 0xFF3FU 246 #define SGTL5000_PAD_I2S_SCLK_GET_MASK 0x00C0U 247 #define SGTL5000_PAD_I2S_SCLK_SHIFT 0x6U 248 #define SGTL5000_PAD_I2S_DOUT_CLR_MASK 0xFFCFU 249 #define SGTL5000_PAD_I2S_DOUT_GET_MASK 0x0030U 250 #define SGTL5000_PAD_I2S_DOUT_SHIFT 0x4U 251 #define SGTL5000_PAD_I2C_SDA_CLR_MASK 0xFFF3U 252 #define SGTL5000_PAD_I2C_SDA_GET_MASK 0x000CU 253 #define SGTL5000_PAD_I2C_SDA_SHIFT 0x2U 254 #define SGTL5000_PAD_I2C_SCL_CLR_MASK 0xFFFCU 255 #define SGTL5000_PAD_I2C_SCL_GET_MASK 0x0003U 256 #define SGTL5000_PAD_I2C_SCL_SHIFT 0x0U 257 258 /* 259 * SGTL5000_CHIP_ANA_ADC_CTRL 260 */ 261 #define SGTL5000_ADC_VOL_M6DB_CLR_MASK 0xFEFFU 262 #define SGTL5000_ADC_VOL_M6DB_GET_MASK 0x0100U 263 #define SGTL5000_ADC_VOL_M6DB_SHIFT 0x8U 264 #define SGTL5000_ADC_VOL_RIGHT_CLR_MASK 0xFF0FU 265 #define SGTL5000_ADC_VOL_RIGHT_GET_MASK 0x00F0U 266 #define SGTL5000_ADC_VOL_RIGHT_SHIFT 0x4U 267 #define SGTL5000_ADC_VOL_LEFT_CLR_MASK 0xFFF0U 268 #define SGTL5000_ADC_VOL_LEFT_GET_MASK 0x000FU 269 #define SGTL5000_ADC_VOL_LEFT_SHIFT 0x0U 270 271 /* 272 * SGTL5000_CHIP_ANA_HP_CTRL 273 */ 274 #define SGTL5000_HP_VOL_RIGHT_CLR_MASK 0x80FFU 275 #define SGTL5000_HP_VOL_RIGHT_GET_MASK 0x7F00U 276 #define SGTL5000_HP_VOL_RIGHT_SHIFT 0x8U 277 #define SGTL5000_HP_VOL_LEFT_CLR_MASK 0xFF80U 278 #define SGTL5000_HP_VOL_LEFT_GET_MASK 0x007FU 279 #define SGTL5000_HP_VOL_LEFT_SHIFT 0x0U 280 281 /* 282 * SGTL5000_CHIP_ANA_CTRL 283 */ 284 #define SGTL5000_MUTE_LO_GET_MASK 0x0100U 285 #define SGTL5000_MUTE_LO_CLR_MASK 0xFEFFU 286 #define SGTL5000_MUTE_LO_SHIFT 0x8U 287 #define SGTL5000_SEL_HP_GET_MASK 0x0040U 288 #define SGTL5000_SEL_HP_CLR_MASK 0xFFBFU 289 #define SGTL5000_SEL_HP_SHIFT 0x6U 290 #define SGTL5000_SEL_HP_DAC 0x0000U 291 #define SGTL5000_SEL_HP_LINEIN 0x0040U 292 #define SGTL5000_EN_ZCD_HP_GET_MASK 0x0020U 293 #define SGTL5000_EN_ZCD_HP_CLR_MASK 0xFFDFU 294 #define SGTL5000_EN_ZCD_HP_SHIFT 0x5U 295 #define SGTL5000_MUTE_HP_GET_MASK 0x0010U 296 #define SGTL5000_MUTE_HP_CLR_MASK 0xFFEFU 297 #define SGTL5000_MUTE_HP_SHIFT 0x4U 298 #define SGTL5000_SEL_ADC_GET_MASK 0x0004U 299 #define SGTL5000_SEL_ADC_CLR_MASK 0xFFFBU 300 #define SGTL5000_SEL_ADC_SHIFT 0x2U 301 #define SGTL5000_SEL_ADC_MIC 0x0000U 302 #define SGTL5000_SEL_ADC_LINEIN 0x0004U 303 #define SGTL5000_EN_ZCD_ADC_GET_MASK 0x0002U 304 #define SGTL5000_EN_ZCD_ADC_CLR_MASK 0xFFFDU 305 #define SGTL5000_EN_ZCD_ADC_SHIFT 0x1U 306 #define SGTL5000_MUTE_ADC_GET_MASK 0x0001U 307 #define SGTL5000_MUTE_ADC_CLR_MASK 0xFFFEU 308 #define SGTL5000_MUTE_ADC_SHIFT 0x0U 309 310 /* 311 * SGTL5000_CHIP_LINREG_CTRL 312 */ 313 #define SGTL5000_VDDC_MAN_ASSN_CLR_MASK 0xFFBFU 314 #define SGTL5000_VDDC_MAN_ASSN_GET_MASK 0x0040U 315 #define SGTL5000_VDDC_MAN_ASSN_SHIFT 0x6U 316 #define SGTL5000_VDDC_MAN_ASSN_VDDA 0x0000U 317 #define SGTL5000_VDDC_MAN_ASSN_VDDIO 0x0040U 318 #define SGTL5000_VDDC_ASSN_OVRD 0x0020U 319 #define SGTL5000_LINREG_VDDD_CLR_MASK 0xFFF0U 320 #define SGTL5000_LINREG_VDDD_GET_MASK 0x000FU 321 #define SGTL5000_LINREG_VDDD_SHIFT 0x0U 322 323 /* 324 * SGTL5000_CHIP_REF_CTRL 325 */ 326 #define SGTL5000_ANA_GND_MASK 0x01f0U 327 #define SGTL5000_ANA_GND_SHIFT 0x4U 328 #define SGTL5000_ANA_GND_WIDTH 0x5U 329 #define SGTL5000_ANA_GND_BASE 0x320U /* mv */ 330 #define SGTL5000_ANA_GND_STP 0x19U /*mv */ 331 #define SGTL5000_BIAS_CTRL_MASK 0x000eU 332 #define SGTL5000_BIAS_CTRL_SHIFT 0x1U 333 #define SGTL5000_BIAS_CTRL_WIDTH 0x3U 334 #define SGTL5000_SMALL_POP 0x0001U 335 336 /* 337 * SGTL5000_CHIP_MIC_CTRL 338 */ 339 #define SGTL5000_BIAS_R__CLR_MASK 0xFCFFU 340 #define SGTL5000_BIAS_R_GET_MASK 0x0300U 341 #define SGTL5000_BIAS_R_SHIFT 0x8U 342 #define SGTL5000_BIAS_R_off 0x0000U 343 #define SGTL5000_BIAS_R_2K 0x0100U 344 #define SGTL5000_BIAS_R_4k 0x0200U 345 #define SGTL5000_BIAS_R_8k 0x0300U 346 #define SGTL5000_BIAS_VOLT_CLR_MASK 0xFF8FU 347 #define SGTL5000_BIAS_VOLT_GET_MASK 0x0070U 348 #define SGTL5000_BIAS_VOLT_SHIFT 0x4U 349 #define SGTL5000_MIC_GAIN_CLR_MASK 0xFFFCU 350 #define SGTL5000_MIC_GAIN_GET_MASK 0x0003U 351 #define SGTL5000_MIC_GAIN_SHIFT 0x0U 352 353 /* 354 * SGTL5000_CHIP_LINE_OUT_CTRL 355 */ 356 #define SGTL5000_LINE_OUT_CURRENT_CLR_MASK 0xF0FFU 357 #define SGTL5000_LINE_OUT_CURRENT_GET_MASK 0x0F00U 358 #define SGTL5000_LINE_OUT_CURRENT_SHIFT 0x8U 359 #define SGTL5000_LINE_OUT_CURRENT_180u 0x0000U 360 #define SGTL5000_LINE_OUT_CURRENT_270u 0x0100U 361 #define SGTL5000_LINE_OUT_CURRENT_360u 0x0300U 362 #define SGTL5000_LINE_OUT_CURRENT_450u 0x0700U 363 #define SGTL5000_LINE_OUT_CURRENT_540u 0x0F00U 364 #define SGTL5000_LINE_OUT_GND_CLR_MASK 0xFFC0U 365 #define SGTL5000_LINE_OUT_GND_GET_MASK 0x003FU 366 #define SGTL5000_LINE_OUT_GND_SHIFT 0x0U 367 #define SGTL5000_LINE_OUT_GND_BASE 0x320U /* mv */ 368 #define SGTL5000_LINE_OUT_GND_STP 0x19U 369 #define SGTL5000_LINE_OUT_GND_MAX 0x23U 370 371 /* 372 * SGTL5000_CHIP_LINE_OUT_VOL 373 */ 374 #define SGTL5000_LINE_OUT_VOL_RIGHT_CLR_MASK 0xE0FFU 375 #define SGTL5000_LINE_OUT_VOL_RIGHT_GET_MASK 0x1F00U 376 #define SGTL5000_LINE_OUT_VOL_RIGHT_SHIFT 0x8U 377 #define SGTL5000_LINE_OUT_VOL_LEFT_CLR_MASK 0xFFE0U 378 #define SGTL5000_LINE_OUT_VOL_LEFT_GET_MASK 0x001FU 379 #define SGTL5000_LINE_OUT_VOL_LEFT_SHIFT 0x0U 380 381 /* 382 * SGTL5000_CHIP_ANA_POWER 383 */ 384 #define SGTL5000_RIGHT_DAC_POWERUP_GET_MASK 0x4000U 385 #define SGTL5000_RIGHT_DAC_POWERUP_CLR_MASK 0xBFFFU 386 #define SGTL5000_RIGHT_DAC_POWERUP_SHIFT 0xEU 387 #define SGTL5000_LINREG_SIMPLE_POWERUP_GET_MASK 0x2000U 388 #define SGTL5000_LINREG_SIMPLE_POWERUP_CLR_MASK 0xDFFFU 389 #define SGTL5000_LINREG_SIMPLE_POWERUP_SHIFT 0xDU 390 #define SGTL5000_STARTUP_POWERUP_GET_MASK 0x1000U 391 #define SGTL5000_STARTUP_POWERUP_CLR_MASK 0xEFFFU 392 #define SGTL5000_STARTUP_POWERUP_SHIFT 0xCU 393 #define SGTL5000_VDDC_CHRGPMP_POWERUP_GET_MASK 0x0800U 394 #define SGTL5000_VDDC_CHRGPMP_POWERUP_CLR_MASK 0xF7FFU 395 #define SGTL5000_VDDC_CHRGPMP_POWERUP_SHIFT 0xBU 396 #define SGTL5000_PLL_POWERUP_GET_MASK 0x0400U 397 #define SGTL5000_PLL_POWERUP_CLR_MASK 0xFBFFU 398 #define SGTL5000_PLL_POWERUP_SHIFT 0xAU 399 #define SGTL5000_LINREG_D_POWERUP_GET_MASK 0x0200U 400 #define SGTL5000_LINREG_D_POWERUP_CLR_MASK 0xFDFFU 401 #define SGTL5000_LINREG_D_POWERUP_SHIFT 0x9U 402 #define SGTL5000_VCOAMP_POWERUP_GET_MASK 0x0100U 403 #define SGTL5000_VCOAMP_POWERUP_CLR_MASK 0xFEFFU 404 #define SGTL5000_VCOAMP_POWERUP_SHIFT 0x8U 405 #define SGTL5000_VAG_POWERUP_GET_MASK 0x0080U 406 #define SGTL5000_VAG_POWERUP_CLR_MASK 0xFF7FU 407 #define SGTL5000_VAG_POWERUP_SHIFT 0x7U 408 #define SGTL5000_RIGHT_ADC_POWERUP_GET_MASK 0x0040U 409 #define SGTL5000_RIGHT_ADC_POWERUP_CLR_MASK 0xFFBFU 410 #define SGTL5000_RIGHT_ADC_POWERUP_SHIFT 0x6U 411 #define SGTL5000_REFTOP_POWERUP_GET_MASK 0x0020U 412 #define SGTL5000_REFTOP_POWERUP_CLR_MASK 0xFFDFU 413 #define SGTL5000_REFTOP_POWERUP_SHIFT 0x5U 414 #define SGTL5000_HEADPHONE_POWERUP_GET_MASK 0x0010U 415 #define SGTL5000_HEADPHONE_POWERUP_CLR_MASK 0xFFEFU 416 #define SGTL5000_HEADPHONE_POWERUP_SHIFT 0x4U 417 #define SGTL5000_DAC_POWERUP_GET_MASK 0x0008U 418 #define SGTL5000_DAC_POWERUP_CLR_MASK 0xFFF7U 419 #define SGTL5000_DAC_POWERUP_SHIFT 0x3U 420 #define SGTL5000_CAPLESS_HEADPHONE_POWERUP_GET_MASK 0x0004U 421 #define SGTL5000_CAPLESS_HEADPHONE_POWERUP_CLR_MASK 0xFFFBU 422 #define SGTL5000_CAPLESS_HEADPHONE_POWERUP_SHIFT 0x2U 423 #define SGTL5000_ADC_POWERUP_GET_MASK 0x0002U 424 #define SGTL5000_ADC_POWERUP_CLR_MASK 0xFFFDU 425 #define SGTL5000_ADC_POWERUP_SHIFT 0x1U 426 #define SGTL5000_LINEOUT_POWERUP_GET_MASK 0x0001U 427 #define SGTL5000_LINEOUT_POWERUP_CLR_MASK 0xFFFEU 428 #define SGTL5000_LINEOUT_POWERUP_SHIFT 0x0U 429 430 /* 431 * SGTL5000_CHIP_PLL_CTRL 432 */ 433 #define SGTL5000_PLL_INT_DIV_CLR_MASK 0x07FFU 434 #define SGTL5000_PLL_INT_DIV_GET_MASK 0xF800U 435 #define SGTL5000_PLL_INT_DIV_SHIFT 0xBU 436 #define SGTL5000_PLL_FRAC_DIV_CLR_MASK 0xF8FFU 437 #define SGTL5000_PLL_FRAC_DIV_GET_MASK 0x0700U 438 #define SGTL5000_PLL_FRAC_DIV_SHIFT 0x0U 439 440 /* 441 * SGTL5000_CHIP_CLK_TOP_CTRL 442 */ 443 #define SGTL5000_ENABLE_INT_OSC_GET_MASK 0x0800U 444 #define SGTL5000_ENABLE_INT_OSC_CLR_MASK 0xF7FFU 445 #define SGTL5000_ENABLE_INT_OSC_SHIFT 0xBU 446 #define SGTL5000_INPUT_FREQ_DIV2_GET_MASK 0x0008U 447 #define SGTL5000_INPUT_FREQ_DIV2_CLR_MASK 0xFFF7U 448 #define SGTL5000_INPUT_FREQ_DIV2_SHIFT 0x3U 449 450 /* 451 * SGTL5000_CHIP_ANA_STATUS 452 */ 453 #define SGTL5000_HP_LRSHORT 0x0200U 454 #define SGTL5000_CAPLESS_SHORT 0x0100U 455 #define SGTL5000_PLL_LOCKED 0x0010U 456 457 /* 458 * SGTL5000_CHIP_SHORT_CTRL 459 */ 460 #define SGTL5000_LVLADJR_CLR_MASK 0x8FFFU 461 #define SGTL5000_LVLADJR_GET_MASK 0x7000U 462 #define SGTL5000_LVLADJR_SHIFT 0xCU 463 #define SGTL5000_LVLADJL_CLR_MASK 0xF8FFU 464 #define SGTL5000_LVLADJL_GET_MASK 0x0700U 465 #define SGTL5000_LVLADJL_SHIFT 0x8U 466 #define SGTL5000_LVLADJC_CLR_MASK 0xFF8FU 467 #define SGTL5000_LVLADJC_GET_MASK 0x0070U 468 #define SGTL5000_LVLADJC_SHIFT 0x4U 469 #define SGTL5000_LR_SHORT_MOD_CLR_MASK 0xFFF3U 470 #define SGTL5000_LR_SHORT_MOD_GET_MASK 0x000CU 471 #define SGTL5000_LR_SHORT_MOD_SHIFT 0x2U 472 #define SGTL5000_CM_SHORT_MOD_CLR_MASK 0xFFFCU 473 #define SGTL5000_CM_SHORT_MOD_GET_MASK 0x0003U 474 #define SGTL5000_CM_SHORT_MOD_SHIFT 0x0U 475 476 /* DAP control register */ 477 #define SGTL5000_DAP_CONTROL_MIX_EN_GET_MASK 0x0010U 478 #define SGTL5000_DAP_CONTROL_MIX_EN_CLR_MASK 0xFFEFU 479 #define SGTL5000_DAP_CONTROL_MIX_EN_SHIFT 0x4U 480 #define SGTL5000_DAP_CONTROL_DAP_EN_GET_MASK 0x0001U 481 #define SGTL5000_DAP_CONTROL_DAP_EN_CLR_MASK 0xFFFEU 482 #define SGTL5000_DAP_CONTROL_DAP_EN_SHIFT 0x0U 483 484 /* 485 * DAP_PEQ_REG 486 */ 487 #define SGTL5000_DAP_PEQ_EN_GET_MASK 0x0007U 488 #define SGTL5000_DAP_PEQ_EN_CLR_MASK 0xFFF8U 489 #define SGTL5000_DAP_PEQ_EN_SHIFT 0x0U 490 491 /* 492 * DAP_BASS_ENHANCE_REG 493 */ 494 #define SGTL5000_DAP_BASS_ENHANCE_MULT_GET_MASK 0xC000U 495 #define SGTL5000_DAP_BASS_ENHANCE_MULT_CLR_MASK 0x3FFFU 496 #define SGTL5000_DAP_BASS_ENHANCE_MULT_SHIFT 0xEU 497 #define SGTL5000_DAP_BASS_ENHANCE_CUTOFF_HPF_GET_MASK 0x0E00U 498 #define SGTL5000_DAP_BASS_ENHANCE_CUTOFF_HPF_CLR_MASK 0xF1FFU 499 #define SGTL5000_DAP_BASS_ENHANCE_CUTOFF_HPF_SHIFT 0x9U 500 #define SGTL5000_DAP_BASS_ENHANCE_BYPASS_HPF_GET_MASK 0x0100U 501 #define SGTL5000_DAP_BASS_ENHANCE_BYPASS_HPF_CLR_MASK 0xFEFFU 502 #define SGTL5000_DAP_BASS_ENHANCE_BYPASS_HPF_SHIFT 0x8U 503 #define SGTL5000_DAP_BASS_ENHANCE_CUTOFF_GET_MASK 0x0070U 504 #define SGTL5000_DAP_BASS_ENHANCE_CUTOFF_CLR_MASK 0xFF8FU 505 #define SGTL5000_DAP_BASS_ENHANCE_CUTOFF_SHIFT 0x4U 506 #define SGTL5000_DAP_BASS_ENHANCE_EN_GET_MASK 0x0001U 507 #define SGTL5000_DAP_BASS_ENHANCE_EN_CLR_MASK 0xFFFEU 508 #define SGTL5000_DAP_BASS_ENHANCE_EN_SHIFT 0x0U 509 510 /* 511 * DAP_BASS_ENHANCE_CTRL_REG 512 */ 513 #define SGTL5000_DAP_BASS_ENHANCE_CTRL_LR_LEVEL_GET_MASK 0x3F00U 514 #define SGTL5000_DAP_BASS_ENHANCE_CTRL_LR_LEVEL_CLR_MASK 0xC0FFU 515 #define SGTL5000_DAP_BASS_ENHANCE_CTRL_LR_LEVEL_SHIFT 0x8U 516 #define SGTL5000_DAP_BASS_ENHANCE_CTRL_BASS_LEVEL_GET_MASK 0x007FU 517 #define SGTL5000_DAP_BASS_ENHANCE_CTRL_BASS_LEVEL_CLR_MASK 0xFF80U 518 #define SGTL5000_DAP_BASS_ENHANCE_CTRL_BASS_LEVEL_SHIFT 0x0U 519 520 /* 521 * DAP_AUDIO_EQ_REG 522 */ 523 #define SGTL5000_DAP_AUDIO_EQ_EN_GET_MASK 0x0003U 524 #define SGTL5000_DAP_AUDIO_EQ_EN_CLR_MASK 0xFFFCU 525 #define SGTL5000_DAP_AUDIO_EQ_EN_SHIFT 0x0U 526 527 /* 528 * DAP_SGTL_SURROUND_REG 529 */ 530 #define SGTL5000_DAP_SGTL_SURROUND_WIDTH_CONTROL_GET_MASK 0x0070U 531 #define SGTL5000_DAP_SGTL_SURROUND_WIDTH_CONTROL_CLR_MASK 0xFF8FU 532 #define SGTL5000_DAP_SGTL_SURROUND_WIDTH_CONTROL_SHIFT 0x4U 533 #define SGTL5000_DAP_SGTL_SURROUND_SEL_GET_MASK 0x0003U 534 #define SGTL5000_DAP_SGTL_SURROUND_SEL_CLR_MASK 0xFFFCU 535 #define SGTL5000_DAP_SGTL_SURROUND_SEL_SHIFT 0x0U 536 537 /* 538 * DAP_FILTER_COEF_ACCESS_REG 539 */ 540 #define SGTL5000_DAP_FILTER_COEF_ACCESS_DEBUG_GET_MASK 0x1000U 541 #define SGTL5000_DAP_FILTER_COEF_ACCESS_DEBUG_CLR_MASK 0xEFFFU 542 #define SGTL5000_DAP_FILTER_COEF_ACCESS_DEBUG_SHIFT 0xCU 543 #define SGTL5000_DAP_FILTER_COEF_ACCESS_RD_GET_MASK 0x0200U 544 #define SGTL5000_DAP_FILTER_COEF_ACCESS_RD_CLR_MASK 0xFDFFU 545 #define SGTL5000_DAP_FILTER_COEF_ACCESS_RD_SHIFT 0x9U 546 #define SGTL5000_DAP_FILTER_COEF_ACCESS_WR_GET_MASK 0x0100U 547 #define SGTL5000_DAP_FILTER_COEF_ACCESS_WR_CLR_MASK 0xFEFFU 548 #define SGTL5000_DAP_FILTER_COEF_ACCESS_WR_SHIFT 0x8U 549 #define SGTL5000_DAP_FILTER_COEF_ACCESS_INDEX_GET_MASK 0x00FFU 550 #define SGTL5000_DAP_FILTER_COEF_ACCESS_INDEX_CLR_MASK 0xFF00U 551 #define SGTL5000_DAP_FILTER_COEF_ACCESS_INDEX_SHIFT 0x0U 552 553 /* 554 * DAP_COEF_WR_B0_MSB_REG 555 */ 556 #define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_19_GET_MASK 0x8000U 557 #define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_19_CLR_MASK 0x7FFFU 558 #define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_19_SHIFT 0xFU 559 #define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_18_GET_MASK 0x4000U 560 #define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_18_CLR_MASK 0xBFFFU 561 #define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_18_SHIFT 0xEU 562 #define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_17_GET_MASK 0x2000U 563 #define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_17_CLR_MASK 0xDFFFU 564 #define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_17_SHIFT 0xDU 565 #define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_16_GET_MASK 0x1000U 566 #define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_16_CLR_MASK 0xEFFFU 567 #define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_16_SHIFT 0xCU 568 #define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_15_GET_MASK 0x0800U 569 #define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_15_CLR_MASK 0xF7FFU 570 #define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_15_SHIFT 0xBU 571 #define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_14_GET_MASK 0x0400U 572 #define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_14_CLR_MASK 0xFBFFU 573 #define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_14_SHIFT 0xAU 574 #define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_13_GET_MASK 0x0200U 575 #define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_13_CLR_MASK 0xFDFFU 576 #define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_13_SHIFT 0x9U 577 #define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_12_GET_MASK 0x0100U 578 #define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_12_CLR_MASK 0xFEFFU 579 #define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_12_SHIFT 0x8U 580 #define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_11_GET_MASK 0x0080U 581 #define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_11_CLR_MASK 0xFF7FU 582 #define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_11_SHIFT 0x7U 583 #define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_10_GET_MASK 0x0040U 584 #define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_10_CLR_MASK 0xFFBFU 585 #define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_10_SHIFT 0x6U 586 #define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_9_GET_MASK 0x0020U 587 #define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_9_CLR_MASK 0xFFDFU 588 #define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_9_SHIFT 0x5U 589 #define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_8_GET_MASK 0x0010U 590 #define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_8_CLR_MASK 0xFFEFU 591 #define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_8_SHIFT 0x4U 592 #define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_7_GET_MASK 0x0008U 593 #define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_7_CLR_MASK 0xFFF7U 594 #define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_7_SHIFT 0x3U 595 #define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_6_GET_MASK 0x0004U 596 #define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_6_CLR_MASK 0xFFFBU 597 #define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_6_SHIFT 0x2U 598 #define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_5_GET_MASK 0x0002U 599 #define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_5_CLR_MASK 0xFFFDU 600 #define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_5_SHIFT 0x1U 601 #define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_4_GET_MASK 0x0001U 602 #define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_4_CLR_MASK 0xFFFEU 603 #define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_4_SHIFT 0x0U 604 605 /* 606 * DAP_COEF_WR_B0_LSB_REG 607 */ 608 #define SGTL5000_DAP_COEF_WR_B0_LSB_BIT_3_GET_MASK 0x0008U 609 #define SGTL5000_DAP_COEF_WR_B0_LSB_BIT_3_CLR_MASK 0xFFF7U 610 #define SGTL5000_DAP_COEF_WR_B0_LSB_BIT_3_SHIFT 0x3U 611 #define SGTL5000_DAP_COEF_WR_B0_LSB_BIT_2_GET_MASK 0x0004U 612 #define SGTL5000_DAP_COEF_WR_B0_LSB_BIT_2_CLR_MASK 0xFFFBU 613 #define SGTL5000_DAP_COEF_WR_B0_LSB_BIT_2_SHIFT 0x2U 614 #define SGTL5000_DAP_COEF_WR_B0_LSB_BIT_1_GET_MASK 0x0002U 615 #define SGTL5000_DAP_COEF_WR_B0_LSB_BIT_1_CLR_MASK 0xFFFDU 616 #define SGTL5000_DAP_COEF_WR_B0_LSB_BIT_1_SHIFT 0x1U 617 #define SGTL5000_DAP_COEF_WR_B0_LSB_BIT_0_GET_MASK 0x0001U 618 #define SGTL5000_DAP_COEF_WR_B0_LSB_BIT_0_CLR_MASK 0xFFFEU 619 #define SGTL5000_DAP_COEF_WR_B0_LSB_BIT_0_SHIFT 0x0U 620 621 /* 622 * DAP_AUDIO_EQ_BASS_BAND0_REG 623 */ 624 #define SGTL5000_DAP_AUDIO_EQ_BASS_BAND0_VOLUME_GET_MASK 0x007FU 625 #define SGTL5000_DAP_AUDIO_EQ_BASS_BAND0_VOLUME_CLR_MASK 0xFF80U 626 #define SGTL5000_DAP_AUDIO_EQ_BASS_BAND0_VOLUME_SHIFT 0x0U 627 628 /* 629 * DAP_AUDIO_EQ_BAND1_REG 630 */ 631 #define SGTL5000_DAP_AUDIO_EQ_BAND1_VOLUME_GET_MASK 0x007FU 632 #define SGTL5000_DAP_AUDIO_EQ_BAND1_VOLUME_CLR_MASK 0xFF80U 633 #define SGTL5000_DAP_AUDIO_EQ_BAND1_VOLUME_SHIFT 0x0U 634 635 /* 636 * DAP_AUDIO_EQ_BAND2_REG 637 */ 638 #define SGTL5000_DAP_AUDIO_EQ_BAND2_VOLUME_GET_MASK 0x007FU 639 #define SGTL5000_DAP_AUDIO_EQ_BAND2_VOLUME_CLR_MASK 0xFF80U 640 #define SGTL5000_DAP_AUDIO_EQ_BAND2_VOLUME_SHIFT 0x0U 641 642 /* 643 * DAP_AUDIO_EQ_BAND3_REG 644 */ 645 #define SGTL5000_DAP_AUDIO_EQ_BAND3_VOLUME_GET_MASK 0x007FU 646 #define SGTL5000_DAP_AUDIO_EQ_BAND3_VOLUME_CLR_MASK 0xFF80U 647 #define SGTL5000_DAP_AUDIO_EQ_BAND3_VOLUME_SHIFT 0x0U 648 649 /* 650 * DAP_AUDIO_EQ_TREBLE_BAND4_REG 651 */ 652 #define SGTL5000_DAP_AUDIO_EQ_TREBLE_BAND4_VOLUME_GET_MASK 0x007FU 653 #define SGTL5000_DAP_AUDIO_EQ_TREBLE_BAND4_VOLUME_CLR_MASK 0xFF80U 654 #define SGTL5000_DAP_AUDIO_EQ_TREBLE_BAND4_VOLUME_SHIFT 0x0U 655 656 /* 657 * DAP_MAIN_CHAN_REG 658 */ 659 #define SGTL5000_DAP_MAIN_CHAN_VOL_GET_MASK 0xFFFFU 660 #define SGTL5000_DAP_MAIN_CHAN_VOL_CLR_MASK 0x0000U 661 #define SGTL5000_DAP_MAIN_CHAN_VOL_SHIFT 0x0U 662 663 /* 664 * DAP_MIX_CHAN_REG 665 */ 666 #define SGTL5000_DAP_MIX_CHAN_VOL_GET_MASK 0xFFFFU 667 #define SGTL5000_DAP_MIX_CHAN_VOL_CLR_MASK 0x0000U 668 #define SGTL5000_DAP_MIX_CHAN_VOL_SHIFT 0x0U 669 670 /* 671 * DAP_AVC_CTRL_REG 672 */ 673 #define SGTL5000_DAP_AVC_CTRL_APOP_ENABLE_GET_MASK 0x4000U 674 #define SGTL5000_DAP_AVC_CTRL_APOP_ENABLE_CLR_MASK 0xBFFFU 675 #define SGTL5000_DAP_AVC_CTRL_APOP_ENABLE_SHIFT 0xEU 676 #define SGTL5000_DAP_AVC_CTRL_MAX_GAIN_GET_MASK 0x3000U 677 #define SGTL5000_DAP_AVC_CTRL_MAX_GAIN_CLR_MASK 0xCFFFU 678 #define SGTL5000_DAP_AVC_CTRL_MAX_GAIN_SHIFT 0xCU 679 #define SGTL5000_DAP_AVC_CTRL_LBI_RESPONSE_GET_MASK 0x0300U 680 #define SGTL5000_DAP_AVC_CTRL_LBI_RESPONSE_CLR_MASK 0xFCFFU 681 #define SGTL5000_DAP_AVC_CTRL_LBI_RESPONSE_SHIFT 0x8U 682 #define SGTL5000_DAP_AVC_CTRL_HARD_LIMIT_EN_GET_MASK 0x0020U 683 #define SGTL5000_DAP_AVC_CTRL_HARD_LIMIT_EN_CLR_MASK 0xFFDFU 684 #define SGTL5000_DAP_AVC_CTRL_HARD_LIMIT_EN_SHIFT 0x5U 685 #define SGTL5000_DAP_AVC_CTRL_STOP_GET_MASK 0x0004U 686 #define SGTL5000_DAP_AVC_CTRL_STOP_SHIFT 0x2U 687 #define SGTL5000_DAP_AVC_CTRL_RUNNING_GET_MASK 0x0002U 688 #define SGTL5000_DAP_AVC_CTRL_RUNNING_SHIFT 0x1U 689 #define SGTL5000_DAP_AVC_CTRL_EN_GET_MASK 0x0001U 690 #define SGTL5000_DAP_AVC_CTRL_EN_CLR_MASK 0xFFFEU 691 #define SGTL5000_DAP_AVC_CTRL_EN_SHIFT 0x0U 692 693 /* 694 * DAP_AVC_ATTACK_REG 695 */ 696 #define SGTL5000_DAP_AVC_ATTACK_RATE_GET_MASK 0x0FFFU 697 #define SGTL5000_DAP_AVC_ATTACK_RATE_CLR_MASK 0xF000U 698 #define SGTL5000_DAP_AVC_ATTACK_RATE_SHIFT 0x0U 699 700 /* 701 * DAP_AVC_DECAY_REG 702 */ 703 #define SGTL5000_DAP_AVC_DECAY_RATE_GET_MASK 0x0FFFU 704 #define SGTL5000_DAP_AVC_DECAY_RATE_CLR_MASK 0xF000U 705 #define SGTL5000_DAP_AVC_DECAY_RATE_SHIFT 0x0U 706 707 /* 708 * DAP_COEF_WR_B1_LSB_REG 709 */ 710 #define SGTL5000_DAP_COEF_WR_B1_LSB_LSB_GET_MASK 0x000FU 711 #define SGTL5000_DAP_COEF_WR_B1_LSB_LSB_CLR_MASK 0xFFF0U 712 #define SGTL5000_DAP_COEF_WR_B1_LSB_LSB_SHIFT 0x0U 713 714 /* 715 * DAP_COEF_WR_B2_LSB_REG 716 */ 717 #define SGTL5000_DAP_COEF_WR_B2_LSB_LSB_GET_MASK 0x000FU 718 #define SGTL5000_DAP_COEF_WR_B2_LSB_LSB_CLR_MASK 0xFFF0U 719 #define SGTL5000_DAP_COEF_WR_B2_LSB_LSB_SHIFT 0x0U 720 721 /* 722 * DAP_COEF_WR_A1_LSB_REG 723 */ 724 #define SGTL5000_DAP_COEF_WR_A1_LSB_LSB_GET_MASK 0x000FU 725 #define SGTL5000_DAP_COEF_WR_A1_LSB_LSB_CLR_MASK 0xFFF0U 726 #define SGTL5000_DAP_COEF_WR_A1_LSB_LSB_SHIFT 0x0U 727 728 /* 729 * DAP_COEF_WR_A2_LSB_REG 730 */ 731 #define SGTL5000_DAP_COEF_WR_A2_LSB_LSB_GET_MASK 0x000FU 732 #define SGTL5000_DAP_COEF_WR_A2_LSB_LSB_CLR_MASK 0xFFF0U 733 #define SGTL5000_DAP_COEF_WR_A2_LSB_LSB_SHIFT 0x0U 734 735 /*! @brief SGTL5000 volume setting range */ 736 #define SGTL5000_HEADPHONE_MAX_VOLUME_VALUE 0x7FU 737 #define SGTL5000_HEADPHONE_MIN_VOLUME_VALUE 0U 738 #define SGTL5000_LINE_OUT_MAX_VOLUME_VALUE 0x1FU 739 #define SGTL5000_LINE_OUT_MIN_VOLUME_VALUE 0U 740 #define SGTL5000_ADC_MAX_VOLUME_VALUE 0xFU 741 #define SGTL5000_ADC_MIN_VOLUME_VALUE 0U 742 #define SGTL5000_DAC_MAX_VOLUME_VALUE 0xF0U 743 #define SGTL5000_DAC_MIN_VOLUME_VALUE 0x3CU 744 745 /*! @brief SGTL5000 I2C address. */ 746 #define SGTL5000_I2C_ADDR 0x0A 747 748 /*! @brief sgtl i2c baudrate */ 749 #define SGTL_I2C_BITRATE 100000U 750 751 /*! @brief Modules in Sgtl5000 board. */ 752 typedef enum _sgtl5000_module { 753 sgtl_module_adc = 0x0, /*!< ADC module in SGTL5000 */ 754 sgtl_module_dac, /*!< DAC module in SGTL5000 */ 755 sgtl_module_dap, /*!< DAP module in SGTL5000 */ 756 sgtl_module_hp, /*!< Headphone module in SGTL5000 */ 757 sgtl_module_i2sin, /*!< I2S-IN module in SGTL5000 */ 758 sgtl_module_i2sout, /*!< I2S-OUT module in SGTL5000 */ 759 sgtl_module_linein, /*!< Line-in moudle in SGTL5000 */ 760 sgtl_module_lineout, /*!< Line-out module in SGTL5000 */ 761 sgtl_module_micin /*!< Micphone module in SGTL5000 */ 762 } sgtl_module_t; 763 764 /*! 765 * @brief Sgtl5000 data route. 766 * @note Only provide some typical data route, not all route listed. 767 * Users cannot combine any routes, once a new route is set, the precios one would be replaced. 768 */ 769 typedef enum _sgtl_route { 770 sgtl_route_bypass = 0x0, /*!< LINEIN->Headphone. */ 771 sgtl_route_playback, /*!< I2SIN->DAC->Headphone. */ 772 sgtl_route_playback_record, /*!< I2SIN->DAC->Headphone, LINEIN->ADC->I2SOUT. */ 773 sgtl_route_playback_with_dap, /*!< I2SIN->DAP->DAC->Headphone. */ 774 sgtl_route_playback_with_dap_record, /*!< I2SIN->DAP->DAC->HP, LINEIN->ADC->I2SOUT. */ 775 sgtl_route_record /*!< LINEIN->ADC->I2SOUT. */ 776 } sgtl_route_t; 777 778 /*! 779 * @brief The audio data transfer protocol choice. 780 * Sgtl5000 only supports I2S format and PCM format. 781 */ 782 typedef enum _sgtl_protocol { 783 sgtl_bus_i2s = 0x0, /*!< I2S Type */ 784 sgtl_bus_left_justified, /*!< Left justified */ 785 sgtl_bus_right_justified, /*!< Right Justified */ 786 sgtl_bus_pcma, /*!< PCMA */ 787 sgtl_bus_pcmb /*!< PCMB */ 788 } sgtl_protocol_t; 789 790 /*! @brief sgtl play channel 791 * @anchor _sgtl_play_channel 792 */ 793 enum { 794 sgtl_headphone_left = 0, /*!< headphone left channel */ 795 sgtl_headphone_right = 1, /*!< headphone right channel */ 796 sgtl_lineout_left = 2, /*!< lineout left channel */ 797 sgtl_lineout_right = 3, /*!< lineout right channel */ 798 }; 799 800 /*! @brief sgtl record source 801 * _sgtl_record_source 802 */ 803 enum { 804 sgtl_record_source_linein = 0U, /*!< record source line in */ 805 sgtl_record_source_mic = 1U, /*!< record source single end */ 806 }; 807 808 /*! @brief sgtl play source 809 * _stgl_play_source 810 */ 811 enum { 812 sgtl_play_source_linein = 0U, /*!< play source line in */ 813 sgtl_play_source_dac = 1U, /*!< play source line in */ 814 }; 815 816 /*! @brief SGTL SCLK valid edge */ 817 typedef enum _sgtl_sclk_edge { 818 sgtl_sclk_valid_edge_rising = 0U, /*!< SCLK valid edge */ 819 sgtl_sclk_valid_edge_failing = 1U, /*!< SCLK failling edge */ 820 } sgtl_sclk_edge_t; 821 822 /*! @brief Audio format configuration. */ 823 typedef struct _sgtl_audio_format { 824 uint32_t mclk_hz; /*!< master clock */ 825 uint32_t sample_rate; /*!< Sample rate */ 826 uint32_t bit_width; /*!< Bit width */ 827 sgtl_sclk_edge_t sclk_edge; /*!< sclk valid edge */ 828 } sgtl_audio_format_t; 829 830 /*! @brief Initailize structure of sgtl5000 */ 831 typedef struct _sgtl_config { 832 sgtl_route_t route; /*!< Audio data route.*/ 833 sgtl_protocol_t bus; /*!< Audio transfer protocol */ 834 bool master; /*!< Master or slave. True means master, false means slave. */ 835 sgtl_audio_format_t format; /*!< audio format */ 836 } sgtl_config_t; 837 838 typedef struct { 839 I2C_Type *ptr;; /*!< sgtl I2C pointer */ 840 uint8_t slave_address; /*!< code device slave address */ 841 } sgtl_context_t; 842 843 /******************************************************************************* 844 * API 845 ******************************************************************************/ 846 #if defined(__cplusplus) 847 extern "C" { 848 #endif 849 850 /*! 851 * @brief sgtl5000 initialize function. 852 * 853 * In this function, some configurations are fixed. 854 * The second parameter can be NULL. If users want to change the SGTL5000 settings, 855 * a configure structure should be prepared. 856 * @note If the codec_config is NULL, it would initialize sgtl5000 using default settings. 857 * The default setting: 858 * @code 859 * sgtl_init_t codec_config 860 * codec_config.route = sgtl_route_playback_record 861 * codec_config.bus = sgtl_bus_i2s 862 * codec_config.master = slave 863 * @endcode 864 * 865 * @param context Sgtl5000 context structure. 866 * @param config sgtl5000 configuration structure. If this pointer equals to NULL, 867 * it means using the default configuration. 868 * @return Initialization status 869 */ 870 hpm_stat_t sgtl_init(sgtl_context_t *context, sgtl_config_t *config); 871 872 /*! 873 * @brief Set audio data route in sgtl5000. 874 * 875 * This function would set the data route according to route. The route cannot be combined, 876 * as all route would enable different modules. 877 * 878 * @note If a new route is set, the previous route would not work. 879 * @param context Sgtl5000 context structure. 880 * @param route Audio data route in sgtl5000. 881 */ 882 hpm_stat_t sgtl_set_data_route(sgtl_context_t *context, sgtl_route_t route); 883 884 /*! 885 * @brief Set the audio transfer protocol. 886 * 887 * Sgtl5000 only supports I2S, I2S left, I2S right, PCM A, PCM B format. 888 * @param context Sgtl5000 context structure. 889 * @param protocol Audio data transfer protocol. 890 */ 891 hpm_stat_t sgtl_set_protocol(sgtl_context_t *context, sgtl_protocol_t protocol); 892 893 /*! 894 * @brief Set sgtl5000 as master or slave. 895 * 896 * @param context Sgtl5000 context structure. 897 * @param master 1 represent master, 0 represent slave. 898 */ 899 void sgtl_set_master_mode(sgtl_context_t *context, bool master); 900 901 /*! 902 * @brief Set the volume of different modules in sgtl5000. 903 * 904 * This function would set the volume of sgtl5000 modules. This interface set module volume. 905 * The function assume that left channel and right channel has the same volume. 906 * 907 * sgtl_module_adc volume range: 0 - 0xF, 0dB - 22.5dB 908 * sgtl_module_dac volume range: 0x3C - 0xF0, 0dB - -90dB 909 * sgtl_module_hp volume range: 0 - 0x7F, 12dB - -51.5dB 910 * sgtl_module_lineout volume range: 0 - 0x1F, 0.5dB steps 911 * 912 * @param context Sgtl5000 context structure. 913 * @param module Sgtl5000 module, such as DAC, ADC and etc. 914 * @param volume Volume value need to be set. The value is the exact value in register. 915 */ 916 hpm_stat_t sgtl_set_volume(sgtl_context_t *context, sgtl_module_t module, uint32_t volume); 917 918 /*! 919 * @brief Get the volume of different modules in sgtl5000. 920 * 921 * This function gets the volume of sgtl5000 modules. This interface get DAC module volume. 922 * The function assume that left channel and right channel has the same volume. 923 * @param context Sgtl5000 context structure. 924 * @param module Sgtl5000 module, such as DAC, ADC and etc. 925 * @return Module value, the value is exact value in register. 926 */ 927 uint32_t sgtl_get_volume(sgtl_context_t *context, sgtl_module_t module); 928 929 /*! 930 * @brief Mute/unmute modules in sgtl5000. 931 * 932 * @param context Sgtl5000 context structure. 933 * @param module Sgtl5000 module, such as DAC, ADC and etc. 934 * @param mute True means mute, and false means unmute. 935 */ 936 hpm_stat_t sgtl_set_mute(sgtl_context_t *context, sgtl_module_t module, bool mute); 937 938 /*! 939 * @brief Enable expected devices. 940 * @param context Sgtl5000 context structure. 941 * @param module Module expected to enable. 942 */ 943 hpm_stat_t sgtl_enable_module(sgtl_context_t *context, sgtl_module_t module); 944 945 /*! 946 * @brief Disable expected devices. 947 * @param context Sgtl5000 context structure. 948 * @param module Module expected to enable. 949 */ 950 hpm_stat_t sgtl_disable_module(sgtl_context_t *context, sgtl_module_t module); 951 952 /*! 953 * @brief Deinit the sgtl5000 codec. Shut down Sgtl5000 modules. 954 * @param context Sgtl5000 context structure pointer. 955 */ 956 hpm_stat_t sgtl_deint(sgtl_context_t *context); 957 958 /*! 959 * @brief Configure the data format of audio data. 960 * 961 * This function would configure the registers about the sample rate, bit depths. 962 * @param context Sgtl5000 context structure pointer. 963 * @param mclk Master clock frequency of I2S. 964 * @param sample_rate Sample rate of audio file running in sgtl5000. Sgtl5000 now 965 * supports 8k, 11.025k, 12k, 16k, 22.05k, 24k, 32k, 44.1k, 48k and 96k sample rate. 966 * @param bits Bit depth of audio file (Sgtl5000 only supports 16bit, 20bit, 24bit 967 * and 32 bit in HW). 968 */ 969 hpm_stat_t sgtl_config_data_format(sgtl_context_t *context, uint32_t mclk, uint32_t sample_rate, uint32_t bits); 970 971 /*! 972 * @brief select SGTL codec play source. 973 * 974 * @param context Sgtl5000 context structure pointer. 975 * @param playSource play source value, reference _sgtl_play_source. 976 * 977 * @return kStatus_Success, else failed. 978 */ 979 hpm_stat_t sgtl_set_play(sgtl_context_t *context, uint32_t playSource); 980 981 /*! 982 * @brief select SGTL codec record source. 983 * 984 * @param context Sgtl5000 context structure pointer. 985 * @param recordSource record source value, reference _sgtl_record_source. 986 * 987 * @return kStatus_Success, else failed. 988 */ 989 hpm_stat_t sgtl_set_record(sgtl_context_t *context, uint32_t recordSource); 990 991 /*! 992 * @brief Write register to sgtl using I2C. 993 * @param context Sgtl5000 context structure. 994 * @param reg The register address in sgtl. 995 * @param val Value needs to write into the register. 996 */ 997 hpm_stat_t sgtl_write_reg(sgtl_context_t *context, uint16_t reg, uint16_t val); 998 999 /*! 1000 * @brief Read register from sgtl using I2C. 1001 * @param context Sgtl5000 context structure. 1002 * @param reg The register address in sgtl. 1003 * @param val Value written to. 1004 */ 1005 hpm_stat_t sgtl_read_reg(sgtl_context_t *context, uint16_t reg, uint16_t *val); 1006 1007 /*! 1008 * @brief Modify some bits in the register using I2C. 1009 * @param context Sgtl5000 context structure. 1010 * @param reg The register address in sgtl. 1011 * @param clr_mask The mask code for the bits want to write. The bit you want to write should be 0. 1012 * @param val Value needs to write into the register. 1013 */ 1014 hpm_stat_t sgtl_modify_reg(sgtl_context_t *context, uint16_t reg, uint16_t clr_mask, uint16_t val); 1015 1016 #if defined(__cplusplus) 1017 } 1018 #endif 1019 1020 /*! @} */ 1021 1022 #endif /* _HPM_SGTL5000_H_ */ 1023