1 /* 2 * Copyright (c) 2022 HPMicro 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 */ 7 8 #ifndef _HPM_WM8960_REG_H_ 9 #define _HPM_WM8960_REG_H_ 10 11 /* WM8960 register number */ 12 #define WM8960_REG_NUM 56U 13 14 /* Define the register address of WM8960 */ 15 #define WM8960_LINVOL 0x0U /* Left Input Volume */ 16 #define WM8960_RINVOL 0x1U /* Right Input Volume */ 17 #define WM8960_LOUT1 0x2U /* LOUT1 Volume */ 18 #define WM8960_ROUT1 0x3U /* ROUT1 Volume */ 19 #define WM8960_CLOCK1 0x4U /* Clocking(1) */ 20 #define WM8960_DACCTL1 0x5U /* ADC and DAC Control (1) */ 21 #define WM8960_DACCTL2 0x6U /* ADC and DAC Control (2) */ 22 #define WM8960_IFACE1 0x7U /* Audio Interface */ 23 #define WM8960_CLOCK2 0x8U /* Clocking(2) */ 24 #define WM8960_IFACE2 0x9U /* Audio Interface */ 25 #define WM8960_LDAC 0xaU /* Left DAC */ 26 #define WM8960_RDAC 0xbU /* Right DAC Volume */ 27 #define WM8960_RESET 0xfU /* RESET */ 28 #define WM8960_3D 0x10U /* 3D Control */ 29 #define WM8960_ALC1 0x11U /* ALC (1) */ 30 #define WM8960_ALC2 0x12U /* ALC (2) */ 31 #define WM8960_ALC3 0x13U /* ALC (3) */ 32 #define WM8960_NOISEG 0x14U /* Noise Gate */ 33 #define WM8960_LADC 0x15U /* Left ADC Volume */ 34 #define WM8960_RADC 0x16U /* Right ADC Volume */ 35 #define WM8960_ADDCTL1 0x17U /* Additional Control (1) */ 36 #define WM8960_ADDCTL2 0x18U /* Additional Control (2) */ 37 #define WM8960_POWER1 0x19U /* Power Mgmt (1) */ 38 #define WM8960_POWER2 0x1aU /* Power Mgmt (2) */ 39 #define WM8960_ADDCTL3 0x1bU /* Additional Control (3) */ 40 #define WM8960_APOP1 0x1cU /* Anti-Pop 1 */ 41 #define WM8960_APOP2 0x1dU /* Anti-pop 2 */ 42 #define WM8960_LINPATH 0x20U /* ADCL Signal Path */ 43 #define WM8960_RINPATH 0x21U /* ADCR Signal Path */ 44 #define WM8960_LOUTMIX 0x22U /* Left Out Mix */ 45 #define WM8960_ROUTMIX 0x25U /* Right Out Mix */ 46 #define WM8960_MONOMIX1 0x26U /* Mono Out Mix (1) */ 47 #define WM8960_MONOMIX2 0x27U /* Mono Out Mix (2) */ 48 #define WM8960_LOUT2 0x28U /* Left Speaker Volume */ 49 #define WM8960_ROUT2 0x29U /* Right Speaker Volume */ 50 #define WM8960_MONO 0x2aU /* OUT3 Volume */ 51 #define WM8960_INBMIX1 0x2bU /* Left Input Boost Mixer */ 52 #define WM8960_INBMIX2 0x2cU /* Right Input Boost Mixer */ 53 #define WM8960_BYPASS1 0x2dU /* Left Bypass */ 54 #define WM8960_BYPASS2 0x2eU /* Right Bypass */ 55 #define WM8960_POWER3 0x2fU /* Power Mgmt (3) */ 56 #define WM8960_ADDCTL4 0x30U /* Additional Control (4) */ 57 #define WM8960_CLASSD1 0x31U /* Class D Control (1) */ 58 #define WM8960_CLASSD3 0x33U /* Class D Control (2) */ 59 #define WM8960_PLL1 0x34U /* PLL (1) */ 60 #define WM8960_PLL2 0x35U /* PLL (2) */ 61 #define WM8960_PLL3 0x36U /* PLL (3) */ 62 #define WM8960_PLL4 0x37U /* PLL (4) */ 63 64 /* Bitfield definition for register: LINVO */ 65 /* 66 * IPVU (RW) 67 * 68 * Input PGA Volume Update 69 * Writing a 1 to this bit will cause left and right input PGA volumes to be updated (LINVOL and RINVOL) 70 */ 71 #define WM8960_LINVO_IPVU_MASK (0x100U) 72 #define WM8960_LINVO_IPVU_SHIFT (8U) 73 #define WM8960_LINVO_IPVU_SET(x) (((uint16_t)(x) << WM8960_LINVO_IPVU_SHIFT) & WM8960_LINVO_IPVU_MASK) 74 #define WM8960_LINVO_IPVU_GET(x) (((uint16_t)(x) & WM8960_LINVO_IPVU_MASK) >> WM8960_LINVO_IPVU_SHIFT) 75 76 /* 77 * LINMUTE (RW) 78 * 79 * Left Input PGA Analogue Mute 1 = Enable Mute 0 = Disable Mute Note: IPVU must be set to un-mute. 80 */ 81 #define WM8960_LINVO_LINMUTE_MASK (0x80U) 82 #define WM8960_LINVO_LINMUTE_SHIFT (7U) 83 #define WM8960_LINVO_LINMUTE_SET(x) (((uint16_t)(x) << WM8960_LINVO_LINMUTE_SHIFT) & WM8960_LINVO_LINMUTE_MASK) 84 #define WM8960_LINVO_LINMUTE_GET(x) (((uint16_t)(x) & WM8960_LINVO_LINMUTE_MASK) >> WM8960_LINVO_LINMUTE_SHIFT) 85 86 /* 87 * LIZC (RW) 88 * 89 * Left Input PGA Zero Cross Detector 1 = Change gain on zero cross only 0 = Change gain immediately 90 */ 91 #define WM8960_LINVO_LIZC_MASK (0x40U) 92 #define WM8960_LINVO_LIZC_SHIFT (6U) 93 #define WM8960_LINVO_LIZC_SET(x) (((uint16_t)(x) << WM8960_LINVO_LIZC_SHIFT) & WM8960_LINVO_LIZC_MASK) 94 #define WM8960_LINVO_LIZC_GET(x) (((uint16_t)(x) & WM8960_LINVO_LIZC_MASK) >> WM8960_LINVO_LIZC_SHIFT) 95 96 /* 97 * LINVOL (RW) 98 * 99 * Left Input PGA Volume Control 100 * 111111 = +30dB 101 * 111110 = +29.25dB 102 * . . 0.75dB steps down to 103 * 000000 = -17.25dB 104 */ 105 #define WM8960_LINVO_LINVOL_MASK (0x3FU) 106 #define WM8960_LINVO_LINVOL_SHIFT (0U) 107 #define WM8960_LINVO_LINVOL_SET(x) (((uint16_t)(x) << WM8960_LINVO_LINVOL_SHIFT) & WM8960_LINVO_LINVOL_MASK) 108 #define WM8960_LINVO_LINVOL_GET(x) (((uint16_t)(x) & WM8960_LINVO_LINVOL_MASK) >> WM8960_LINVO_LINVOL_SHIFT) 109 110 /* Bitfield definition for register: RINVOL */ 111 /* 112 * IPVU (RW) 113 * 114 * Input PGA Volume Update 115 * Writing a 1 to this bit will cause left and right 116 * input PGA volumes to be updated (LINVOL and RINVOL) 117 */ 118 #define WM8960_RINVOL_IPVU_MASK (0x100U) 119 #define WM8960_RINVOL_IPVU_SHIFT (8U) 120 #define WM8960_RINVOL_IPVU_SET(x) (((uint16_t)(x) << WM8960_RINVOL_IPVU_SHIFT) & WM8960_RINVOL_IPVU_MASK) 121 #define WM8960_RINVOL_IPVU_GET(x) (((uint16_t)(x) & WM8960_RINVOL_IPVU_MASK) >> WM8960_RINVOL_IPVU_SHIFT) 122 123 /* 124 * RINMUTE (RW) 125 * 126 * Right Input PGA Analogue Mute 127 * 1 = Enable Mute 128 * 0 = Disable Mute 129 * Note: IPVU must be set to un-mute. 130 */ 131 #define WM8960_RINVOL_RINMUTE_MASK (0x80U) 132 #define WM8960_RINVOL_RINMUTE_SHIFT (7U) 133 #define WM8960_RINVOL_RINMUTE_SET(x) (((uint16_t)(x) << WM8960_RINVOL_RINMUTE_SHIFT) & WM8960_RINVOL_RINMUTE_MASK) 134 #define WM8960_RINVOL_RINMUTE_GET(x) (((uint16_t)(x) & WM8960_RINVOL_RINMUTE_MASK) >> WM8960_RINVOL_RINMUTE_SHIFT) 135 136 /* 137 * RIZC (RW) 138 * 139 * Right Input PGA Zero Cross Detector 140 * 1 = Change gain on zero cross only 141 * 0 = Change gain immediately 142 */ 143 #define WM8960_RINVOL_RIZC_MASK (0x40U) 144 #define WM8960_RINVOL_RIZC_SHIFT (6U) 145 #define WM8960_RINVOL_RIZC_SET(x) (((uint16_t)(x) << WM8960_RINVOL_RIZC_SHIFT) & WM8960_RINVOL_RIZC_MASK) 146 #define WM8960_RINVOL_RIZC_GET(x) (((uint16_t)(x) & WM8960_RINVOL_RIZC_MASK) >> WM8960_RINVOL_RIZC_SHIFT) 147 148 /* 149 * RINVOL (RW) 150 * 151 * Right Input PGA Volume Control 152 * 111111 = +30dB 153 * 111110 = +29.25dB 154 * . . 0.75dB steps down to 155 * 000000 = -17.25dB 156 */ 157 #define WM8960_RINVOL_RINVOL_MASK (0x3FU) 158 #define WM8960_RINVOL_RINVOL_SHIFT (0U) 159 #define WM8960_RINVOL_RINVOL_SET(x) (((uint16_t)(x) << WM8960_RINVOL_RINVOL_SHIFT) & WM8960_RINVOL_RINVOL_MASK) 160 #define WM8960_RINVOL_RINVOL_GET(x) (((uint16_t)(x) & WM8960_RINVOL_RINVOL_MASK) >> WM8960_RINVOL_RINVOL_SHIFT) 161 162 /* Bitfield definition for register: LOUT1 */ 163 /* 164 * OUT1VU (RW) 165 * 166 * Headphone Output PGA Volume Update 167 * Writing a 1 to this bit will cause left and right 168 * headphone output volumes to be updated 169 * (LOUT1VOL and ROUT1VOL) 170 */ 171 #define WM8960_LOUT1_OUT1VU_MASK (0x100U) 172 #define WM8960_LOUT1_OUT1VU_SHIFT (8U) 173 #define WM8960_LOUT1_OUT1VU_SET(x) (((uint16_t)(x) << WM8960_LOUT1_OUT1VU_SHIFT) & WM8960_LOUT1_OUT1VU_MASK) 174 #define WM8960_LOUT1_OUT1VU_GET(x) (((uint16_t)(x) & WM8960_LOUT1_OUT1VU_MASK) >> WM8960_LOUT1_OUT1VU_SHIFT) 175 176 /* 177 * LO1ZC (RW) 178 * 179 * Left Headphone Output Zero Cross Enable 180 * 0 = Change gain immediately 181 * 1 = Change gain on zero cross only 182 */ 183 #define WM8960_LOUT1_LO1ZC_MASK (0x80U) 184 #define WM8960_LOUT1_LO1ZC_SHIFT (7U) 185 #define WM8960_LOUT1_LO1ZC_SET(x) (((uint16_t)(x) << WM8960_LOUT1_LO1ZC_SHIFT) & WM8960_LOUT1_LO1ZC_MASK) 186 #define WM8960_LOUT1_LO1ZC_GET(x) (((uint16_t)(x) & WM8960_LOUT1_LO1ZC_MASK) >> WM8960_LOUT1_LO1ZC_SHIFT) 187 188 /* 189 * LOUT1VOL (RW) 190 * 191 * LOUT1 Volume 192 * 1111111 = +6dB 193 * … 1dB steps down to 194 * 0110000 = -73dB 195 * 0101111 to 0000000 = Analogue MUTE 196 */ 197 #define WM8960_LOUT1_LOUT1VOL_MASK (0x7FU) 198 #define WM8960_LOUT1_LOUT1VOL_SHIFT (0U) 199 #define WM8960_LOUT1_LOUT1VOL_SET(x) (((uint16_t)(x) << WM8960_LOUT1_LOUT1VOL_SHIFT) & WM8960_LOUT1_LOUT1VOL_MASK) 200 #define WM8960_LOUT1_LOUT1VOL_GET(x) (((uint16_t)(x) & WM8960_LOUT1_LOUT1VOL_MASK) >> WM8960_LOUT1_LOUT1VOL_SHIFT) 201 202 /* Bitfield definition for register: ROUT1 */ 203 /* 204 * OUT1VU (RW) 205 * 206 * Headphone Output PGA Volume Update 207 * Writing a 1 to this bit will cause left and right 208 * headphone output volumes to be updated 209 * (LOUT1VOL and ROUT1VOL) 210 */ 211 #define WM8960_ROUT1_OUT1VU_MASK (0x100U) 212 #define WM8960_ROUT1_OUT1VU_SHIFT (8U) 213 #define WM8960_ROUT1_OUT1VU_SET(x) (((uint16_t)(x) << WM8960_ROUT1_OUT1VU_SHIFT) & WM8960_ROUT1_OUT1VU_MASK) 214 #define WM8960_ROUT1_OUT1VU_GET(x) (((uint16_t)(x) & WM8960_ROUT1_OUT1VU_MASK) >> WM8960_ROUT1_OUT1VU_SHIFT) 215 216 /* 217 * RO1ZC (RW) 218 * 219 * Right Headphone Output Zero Cross Enable 220 * 0 = Change gain immediately 221 * 1 = Change gain on zero cross only 222 */ 223 #define WM8960_ROUT1_RO1ZC_MASK (0x80U) 224 #define WM8960_ROUT1_RO1ZC_SHIFT (7U) 225 #define WM8960_ROUT1_RO1ZC_SET(x) (((uint16_t)(x) << WM8960_ROUT1_RO1ZC_SHIFT) & WM8960_ROUT1_RO1ZC_MASK) 226 #define WM8960_ROUT1_RO1ZC_GET(x) (((uint16_t)(x) & WM8960_ROUT1_RO1ZC_MASK) >> WM8960_ROUT1_RO1ZC_SHIFT) 227 228 /* 229 * ROUT1VOL (RW) 230 * 231 * ROUT1 Volume 232 * 1111111 = +6dB 233 * … 1dB steps down to 234 * 0110000 = -73dB 235 * 0101111 to 0000000 = Analogue MUTE 236 */ 237 #define WM8960_ROUT1_ROUT1VOL_MASK (0x7FU) 238 #define WM8960_ROUT1_ROUT1VOL_SHIFT (0U) 239 #define WM8960_ROUT1_ROUT1VOL_SET(x) (((uint16_t)(x) << WM8960_ROUT1_ROUT1VOL_SHIFT) & WM8960_ROUT1_ROUT1VOL_MASK) 240 #define WM8960_ROUT1_ROUT1VOL_GET(x) (((uint16_t)(x) & WM8960_ROUT1_ROUT1VOL_MASK) >> WM8960_ROUT1_ROUT1VOL_SHIFT) 241 242 /* Bitfield definition for register: CLOCK1 */ 243 /* 244 * ADCDIV (RW) 245 * 246 * ADC Sample rate divider (Also determines 247 * ADCLRC in master mode) 248 * 000 = SYSCLK / (1.0 * 256) 249 * 001 = SYSCLK / (1.5 * 256) 250 * 010 = SYSCLK / (2 * 256) 251 * 011 = SYSCLK / (3 * 256) 252 * 100 = SYSCLK / (4 * 256) 253 * 101 = SYSCLK / (5.5 * 256) 254 * 110 = SYSCLK / (6 * 256) 255 * 111 = Reserved 256 */ 257 #define WM8960_CLOCK1_ADCDIV_MASK (0x1C0U) 258 #define WM8960_CLOCK1_ADCDIV_SHIFT (6U) 259 #define WM8960_CLOCK1_ADCDIV_SET(x) (((uint16_t)(x) << WM8960_CLOCK1_ADCDIV_SHIFT) & WM8960_CLOCK1_ADCDIV_MASK) 260 #define WM8960_CLOCK1_ADCDIV_GET(x) (((uint16_t)(x) & WM8960_CLOCK1_ADCDIV_MASK) >> WM8960_CLOCK1_ADCDIV_SHIFT) 261 262 /* 263 * DACDIV (RW) 264 * 265 * DAC Sample rate divider (Also determines 266 * DACLRC in master mode) 267 * 000 = SYSCLK / (1.0 * 256) 268 * 001 = SYSCLK / (1.5 * 256) 269 * 010 = SYSCLK / (2 * 256) 270 * 011 = SYSCLK / (3 * 256) 271 * 100 = SYSCLK / (4 * 256) 272 * 101 = SYSCLK / (5.5 * 256) 273 * 110 = SYSCLK / (6 * 256) 274 * 111 = Reserved 275 */ 276 #define WM8960_CLOCK1_DACDIV_MASK (0x38U) 277 #define WM8960_CLOCK1_DACDIV_SHIFT (3U) 278 #define WM8960_CLOCK1_DACDIV_SET(x) (((uint16_t)(x) << WM8960_CLOCK1_DACDIV_SHIFT) & WM8960_CLOCK1_DACDIV_MASK) 279 #define WM8960_CLOCK1_DACDIV_GET(x) (((uint16_t)(x) & WM8960_CLOCK1_DACDIV_MASK) >> WM8960_CLOCK1_DACDIV_SHIFT) 280 281 /* 282 * SYSCLKDIV (RW) 283 * 284 * SYSCLK Pre-divider. Clock source (MCLK or 285 * PLL output) will be divided by this value to 286 * generate SYSCLK. 287 * 00 = Divide SYSCLK by 1 288 * 01 = Reserved 289 * 10 = Divide SYSCLK by 2 290 * 11 = Reserved 291 */ 292 #define WM8960_CLOCK1_SYSCLKDIV_MASK (0x6U) 293 #define WM8960_CLOCK1_SYSCLKDIV_SHIFT (1U) 294 #define WM8960_CLOCK1_SYSCLKDIV_SET(x) (((uint16_t)(x) << WM8960_CLOCK1_SYSCLKDIV_SHIFT) & WM8960_CLOCK1_SYSCLKDIV_MASK) 295 #define WM8960_CLOCK1_SYSCLKDIV_GET(x) (((uint16_t)(x) & WM8960_CLOCK1_SYSCLKDIV_MASK) >> WM8960_CLOCK1_SYSCLKDIV_SHIFT) 296 297 /* 298 * CLKSEL (RW) 299 * 300 * SYSCLK Selection 301 * 0 = SYSCLK derived from MCLK 302 * 1 = SYSCLK derived from PLL output 303 */ 304 #define WM8960_CLOCK1_CLKSEL_MASK (0x1U) 305 #define WM8960_CLOCK1_CLKSEL_SHIFT (0U) 306 #define WM8960_CLOCK1_CLKSEL_SET(x) (((uint16_t)(x) << WM8960_CLOCK1_CLKSEL_SHIFT) & WM8960_CLOCK1_CLKSEL_MASK) 307 #define WM8960_CLOCK1_CLKSEL_GET(x) (((uint16_t)(x) & WM8960_CLOCK1_CLKSEL_MASK) >> WM8960_CLOCK1_CLKSEL_SHIFT) 308 309 /* Bitfield definition for register: DACCTL1 */ 310 /* 311 * DACDIV2 (RW) 312 * 313 * DAC 6dB Attenuate Enable 314 * 0 = Disabled (0dB) 315 * 1 = -6dB Enabled 316 */ 317 #define WM8960_DACCTL1_DACDIV2_MASK (0x80U) 318 #define WM8960_DACCTL1_DACDIV2_SHIFT (7U) 319 #define WM8960_DACCTL1_DACDIV2_SET(x) (((uint16_t)(x) << WM8960_DACCTL1_DACDIV2_SHIFT) & WM8960_DACCTL1_DACDIV2_MASK) 320 #define WM8960_DACCTL1_DACDIV2_GET(x) (((uint16_t)(x) & WM8960_DACCTL1_DACDIV2_MASK) >> WM8960_DACCTL1_DACDIV2_SHIFT) 321 322 /* 323 * ADCPOL (RW) 324 * 325 * ADC polarity control: 326 * 00 = Polarity not inverted 327 * 01 = ADC L inverted 328 * 10 = ADC R inverted 329 * 11 = ADC L and R inverted 330 */ 331 #define WM8960_DACCTL1_ADCPOL_MASK (0x60U) 332 #define WM8960_DACCTL1_ADCPOL_SHIFT (5U) 333 #define WM8960_DACCTL1_ADCPOL_SET(x) (((uint16_t)(x) << WM8960_DACCTL1_ADCPOL_SHIFT) & WM8960_DACCTL1_ADCPOL_MASK) 334 #define WM8960_DACCTL1_ADCPOL_GET(x) (((uint16_t)(x) & WM8960_DACCTL1_ADCPOL_MASK) >> WM8960_DACCTL1_ADCPOL_SHIFT) 335 336 /* 337 * DACMU (RW) 338 * 339 * DAC Digital Soft Mute 340 * 1 = Mute 341 * 0 = No mute (signal active) 342 */ 343 #define WM8960_DACCTL1_DACMU_MASK (0x8U) 344 #define WM8960_DACCTL1_DACMU_SHIFT (3U) 345 #define WM8960_DACCTL1_DACMU_SET(x) (((uint16_t)(x) << WM8960_DACCTL1_DACMU_SHIFT) & WM8960_DACCTL1_DACMU_MASK) 346 #define WM8960_DACCTL1_DACMU_GET(x) (((uint16_t)(x) & WM8960_DACCTL1_DACMU_MASK) >> WM8960_DACCTL1_DACMU_SHIFT) 347 348 /* 349 * DEEMPH (RW) 350 * 351 * De-emphasis Control 352 * 11 = 48kHz sample rate 353 * 10 = 44.1kHz sample rate 354 * 01 = 32kHz sample rate 355 * 00 = No de-emphasis 356 */ 357 #define WM8960_DACCTL1_DEEMPH_MASK (0x6U) 358 #define WM8960_DACCTL1_DEEMPH_SHIFT (1U) 359 #define WM8960_DACCTL1_DEEMPH_SET(x) (((uint16_t)(x) << WM8960_DACCTL1_DEEMPH_SHIFT) & WM8960_DACCTL1_DEEMPH_MASK) 360 #define WM8960_DACCTL1_DEEMPH_GET(x) (((uint16_t)(x) & WM8960_DACCTL1_DEEMPH_MASK) >> WM8960_DACCTL1_DEEMPH_SHIFT) 361 362 /* 363 * ADCHPD (RW) 364 * 365 * ADC High Pass Filter Disable 366 * 0 = Enable high pass filter on left and right channels 367 * 1 = Disable high pass filter on left and right channels 368 */ 369 #define WM8960_DACCTL1_ADCHPD_MASK (0x1U) 370 #define WM8960_DACCTL1_ADCHPD_SHIFT (0U) 371 #define WM8960_DACCTL1_ADCHPD_SET(x) (((uint16_t)(x) << WM8960_DACCTL1_ADCHPD_SHIFT) & WM8960_DACCTL1_ADCHPD_MASK) 372 #define WM8960_DACCTL1_ADCHPD_GET(x) (((uint16_t)(x) & WM8960_DACCTL1_ADCHPD_MASK) >> WM8960_DACCTL1_ADCHPD_SHIFT) 373 374 /* Bitfield definition for register: DACCTL2 */ 375 /* 376 * DACPOL (RW) 377 * 378 * DAC polarity control: 379 * 00 = Polarity not inverted 380 * 01 = DAC L inverted 381 * 10 = DAC R inverted 382 * 11 = DAC L and R inverted 383 */ 384 #define WM8960_DACCTL2_DACPOL_MASK (0x60U) 385 #define WM8960_DACCTL2_DACPOL_SHIFT (5U) 386 #define WM8960_DACCTL2_DACPOL_SET(x) (((uint16_t)(x) << WM8960_DACCTL2_DACPOL_SHIFT) & WM8960_DACCTL2_DACPOL_MASK) 387 #define WM8960_DACCTL2_DACPOL_GET(x) (((uint16_t)(x) & WM8960_DACCTL2_DACPOL_MASK) >> WM8960_DACCTL2_DACPOL_SHIFT) 388 389 /* 390 * DACSMM (RW) 391 * 392 * DAC Soft Mute Mode 393 * 0 = Disabling soft-mute (DACMU=0) will cause 394 * the volume to change immediately to the 395 * LDACVOL / RDACVOL settings 396 * 1 = Disabling soft-mute (DACMU=0) will cause 397 * the volume to ramp up gradually to the 398 * LDACVOL / RDACVOL settings 399 */ 400 #define WM8960_DACCTL2_DACSMM_MASK (0x8U) 401 #define WM8960_DACCTL2_DACSMM_SHIFT (3U) 402 #define WM8960_DACCTL2_DACSMM_SET(x) (((uint16_t)(x) << WM8960_DACCTL2_DACSMM_SHIFT) & WM8960_DACCTL2_DACSMM_MASK) 403 #define WM8960_DACCTL2_DACSMM_GET(x) (((uint16_t)(x) & WM8960_DACCTL2_DACSMM_MASK) >> WM8960_DACCTL2_DACSMM_SHIFT) 404 405 /* 406 * DACMR (RW) 407 * 408 * DAC Soft Mute Ramp Rate 409 * 0 = Fast ramp (24kHz at fs=48k, providing 410 * maximum delay of 10.7ms) 411 * 1 = Slow ramp (1.5kHz at fs=48k, providing 412 * maximum delay of 171ms) 413 */ 414 #define WM8960_DACCTL2_DACMR_MASK (0x4U) 415 #define WM8960_DACCTL2_DACMR_SHIFT (2U) 416 #define WM8960_DACCTL2_DACMR_SET(x) (((uint16_t)(x) << WM8960_DACCTL2_DACMR_SHIFT) & WM8960_DACCTL2_DACMR_MASK) 417 #define WM8960_DACCTL2_DACMR_GET(x) (((uint16_t)(x) & WM8960_DACCTL2_DACMR_MASK) >> WM8960_DACCTL2_DACMR_SHIFT) 418 419 /* 420 * DACSLOPE (RW) 421 * 422 * Selects DAC filter characteristics 423 * 0 = Normal mode 424 * 1 = Sloping stopband 425 */ 426 #define WM8960_DACCTL2_DACSLOPE_MASK (0x2U) 427 #define WM8960_DACCTL2_DACSLOPE_SHIFT (1U) 428 #define WM8960_DACCTL2_DACSLOPE_SET(x) (((uint16_t)(x) << WM8960_DACCTL2_DACSLOPE_SHIFT) & WM8960_DACCTL2_DACSLOPE_MASK) 429 #define WM8960_DACCTL2_DACSLOPE_GET(x) (((uint16_t)(x) & WM8960_DACCTL2_DACSLOPE_MASK) >> WM8960_DACCTL2_DACSLOPE_SHIFT) 430 431 /* Bitfield definition for register: IFACE1 */ 432 /* 433 * ALRSWAP (RW) 434 * 435 * Left/Right ADC Channel Swap 436 * 1 = Swap left and right ADC data in audio 437 * interface 438 * 0 = Output left and right data as normal 439 */ 440 #define WM8960_IFACE1_ALRSWAP_MASK (0x100U) 441 #define WM8960_IFACE1_ALRSWAP_SHIFT (8U) 442 #define WM8960_IFACE1_ALRSWAP_SET(x) (((uint16_t)(x) << WM8960_IFACE1_ALRSWAP_SHIFT) & WM8960_IFACE1_ALRSWAP_MASK) 443 #define WM8960_IFACE1_ALRSWAP_GET(x) (((uint16_t)(x) & WM8960_IFACE1_ALRSWAP_MASK) >> WM8960_IFACE1_ALRSWAP_SHIFT) 444 445 /* 446 * BCLKINV (RW) 447 * 448 * BCLK invert bit (for master and slave modes) 449 * 0 = BCLK not inverted 450 * 1 = BCLK inverted 451 */ 452 #define WM8960_IFACE1_BCLKINV_MASK (0x80U) 453 #define WM8960_IFACE1_BCLKINV_SHIFT (7U) 454 #define WM8960_IFACE1_BCLKINV_SET(x) (((uint16_t)(x) << WM8960_IFACE1_BCLKINV_SHIFT) & WM8960_IFACE1_BCLKINV_MASK) 455 #define WM8960_IFACE1_BCLKINV_GET(x) (((uint16_t)(x) & WM8960_IFACE1_BCLKINV_MASK) >> WM8960_IFACE1_BCLKINV_SHIFT) 456 457 /* 458 * MS (RW) 459 * 460 * Master / Slave Mode Control 461 * 0 = Enable slave mode 462 * 1 = Enable master mode 463 */ 464 #define WM8960_IFACE1_MS_MASK (0x40U) 465 #define WM8960_IFACE1_MS_SHIFT (6U) 466 #define WM8960_IFACE1_MS_SET(x) (((uint16_t)(x) << WM8960_IFACE1_MS_SHIFT) & WM8960_IFACE1_MS_MASK) 467 #define WM8960_IFACE1_MS_GET(x) (((uint16_t)(x) & WM8960_IFACE1_MS_MASK) >> WM8960_IFACE1_MS_SHIFT) 468 469 /* 470 * DLRSWAP (RW) 471 * 472 * Left/Right DAC Channel Swap 473 * 0 = Output left and right data as normal 474 * 1 = Swap left and right DAC data in audio interface 475 */ 476 #define WM8960_IFACE1_DLRSWAP_MASK (0x20U) 477 #define WM8960_IFACE1_DLRSWAP_SHIFT (5U) 478 #define WM8960_IFACE1_DLRSWAP_SET(x) (((uint16_t)(x) << WM8960_IFACE1_DLRSWAP_SHIFT) & WM8960_IFACE1_DLRSWAP_MASK) 479 #define WM8960_IFACE1_DLRSWAP_GET(x) (((uint16_t)(x) & WM8960_IFACE1_DLRSWAP_MASK) >> WM8960_IFACE1_DLRSWAP_SHIFT) 480 481 /* 482 * LRP (RW) 483 * 484 * Right, left and I2S modes – LRCLK polarity 485 * 0 = normal LRCLK polarity 486 * 1 = invert LRCLK polarity 487 * DSP Mode – mode A/B select 488 * 0 = MSB is available on 2nd BCLK rising edge after LRC rising edge (mode A) 489 * 1 = MSB is available on 1st BCLK rising edge after LRC rising edge (mode B) 490 */ 491 #define WM8960_IFACE1_LRP_MASK (0x10U) 492 #define WM8960_IFACE1_LRP_SHIFT (4U) 493 #define WM8960_IFACE1_LRP_SET(x) (((uint16_t)(x) << WM8960_IFACE1_LRP_SHIFT) & WM8960_IFACE1_LRP_MASK) 494 #define WM8960_IFACE1_LRP_GET(x) (((uint16_t)(x) & WM8960_IFACE1_LRP_MASK) >> WM8960_IFACE1_LRP_SHIFT) 495 496 /* 497 * WL (RW) 498 * 499 * Audio Data Word Length 500 * 00 = 16 bits 501 * 01 = 20 bits 502 * 10 = 24 bits 503 * 11 = 32 bits (see Note) 504 */ 505 #define WM8960_IFACE1_WL_MASK (0xCU) 506 #define WM8960_IFACE1_WL_SHIFT (2U) 507 #define WM8960_IFACE1_WL_SET(x) (((uint16_t)(x) << WM8960_IFACE1_WL_SHIFT) & WM8960_IFACE1_WL_MASK) 508 #define WM8960_IFACE1_WL_GET(x) (((uint16_t)(x) & WM8960_IFACE1_WL_MASK) >> WM8960_IFACE1_WL_SHIFT) 509 510 /* 511 * FORMAT (RW) 512 * 513 * 00 = Right justified 514 * 01 = Left justified 515 * 10 = I2S Format 516 * 11 = DSP Mode 517 */ 518 #define WM8960_IFACE1_FORMAT_MASK (0x3U) 519 #define WM8960_IFACE1_FORMAT_SHIFT (0U) 520 #define WM8960_IFACE1_FORMAT_SET(x) (((uint16_t)(x) << WM8960_IFACE1_FORMAT_SHIFT) & WM8960_IFACE1_FORMAT_MASK) 521 #define WM8960_IFACE1_FORMAT_GET(x) (((uint16_t)(x) & WM8960_IFACE1_FORMAT_MASK) >> WM8960_IFACE1_FORMAT_SHIFT) 522 523 /* Bitfield definition for register: CLOCK2 */ 524 /* 525 * DCLKDIV (RW) 526 * 527 * Class D switching clock divider. 528 * 000 = SYSCLK / 1.5 (Not recommended) 529 * 001 = SYSCLK / 2 530 * 010 = SYSCLK / 3 531 * 011 = SYSCLK / 4 532 * 100 = SYSCLK / 6 533 * 101 = SYSCLK / 8 534 * 110 = SYSCLK / 12 535 * 111 = SYSCLK / 16 536 */ 537 #define WM8960_CLOCK2_DCLKDIV_MASK (0x1C0U) 538 #define WM8960_CLOCK2_DCLKDIV_SHIFT (6U) 539 #define WM8960_CLOCK2_DCLKDIV_SET(x) (((uint16_t)(x) << WM8960_CLOCK2_DCLKDIV_SHIFT) & WM8960_CLOCK2_DCLKDIV_MASK) 540 #define WM8960_CLOCK2_DCLKDIV_GET(x) (((uint16_t)(x) & WM8960_CLOCK2_DCLKDIV_MASK) >> WM8960_CLOCK2_DCLKDIV_SHIFT) 541 542 /* 543 * BCLKDIV (RW) 544 * 545 * BCLK Frequency (Master Mode) 546 * 0000 = SYSCLK 547 * 0001 = SYSCLK / 1.5 548 * 0010 = SYSCLK / 2 549 * 0011 = SYSCLK / 3 550 * 0100 = SYSCLK / 4 551 * 0101 = SYSCLK / 5.5 552 * 0110 = SYSCLK / 6 553 * 0111 = SYSCLK / 8 554 * 1000 = SYSCLK / 11 555 * 1001 = SYSCLK / 12 556 * 1010 = SYSCLK / 16 557 * 1011 = SYSCLK / 22 558 * 1100 = SYSCLK / 24 559 * 1101 to 1111 = SYSCLK / 32 560 */ 561 #define WM8960_CLOCK2_BCLKDIV_MASK (0xFU) 562 #define WM8960_CLOCK2_BCLKDIV_SHIFT (0U) 563 #define WM8960_CLOCK2_BCLKDIV_SET(x) (((uint16_t)(x) << WM8960_CLOCK2_BCLKDIV_SHIFT) & WM8960_CLOCK2_BCLKDIV_MASK) 564 #define WM8960_CLOCK2_BCLKDIV_GET(x) (((uint16_t)(x) & WM8960_CLOCK2_BCLKDIV_MASK) >> WM8960_CLOCK2_BCLKDIV_SHIFT) 565 566 /* Bitfield definition for register: IFACE2 */ 567 /* 568 * ALRCGPIO (RW) 569 * 570 * ADCLRC/GPIO1 Pin Function Select 571 * 0 = ADCLRC frame clock for ADC 572 * 1 = GPIO pin 573 */ 574 #define WM8960_IFACE2_ALRCGPIO_MASK (0x40U) 575 #define WM8960_IFACE2_ALRCGPIO_SHIFT (6U) 576 #define WM8960_IFACE2_ALRCGPIO_SET(x) (((uint16_t)(x) << WM8960_IFACE2_ALRCGPIO_SHIFT) & WM8960_IFACE2_ALRCGPIO_MASK) 577 #define WM8960_IFACE2_ALRCGPIO_GET(x) (((uint16_t)(x) & WM8960_IFACE2_ALRCGPIO_MASK) >> WM8960_IFACE2_ALRCGPIO_SHIFT) 578 579 /* 580 * WL8 (RW) 581 * 582 * 8-Bit Word Length Select (Used with 583 * companding) 584 * 0 = Off 585 * 1 = Device operates in 8-bit mode. 586 */ 587 #define WM8960_IFACE2_WL8_MASK (0x20U) 588 #define WM8960_IFACE2_WL8_SHIFT (5U) 589 #define WM8960_IFACE2_WL8_SET(x) (((uint16_t)(x) << WM8960_IFACE2_WL8_SHIFT) & WM8960_IFACE2_WL8_MASK) 590 #define WM8960_IFACE2_WL8_GET(x) (((uint16_t)(x) & WM8960_IFACE2_WL8_MASK) >> WM8960_IFACE2_WL8_SHIFT) 591 592 /* 593 * DACCOMP (RW) 594 * 595 * DAC companding 596 * 00 = off 597 * 01 = reserved 598 * 10 = μ-law 599 * 11 = A-law 600 */ 601 #define WM8960_IFACE2_DACCOMP_MASK (0x18U) 602 #define WM8960_IFACE2_DACCOMP_SHIFT (3U) 603 #define WM8960_IFACE2_DACCOMP_SET(x) (((uint16_t)(x) << WM8960_IFACE2_DACCOMP_SHIFT) & WM8960_IFACE2_DACCOMP_MASK) 604 #define WM8960_IFACE2_DACCOMP_GET(x) (((uint16_t)(x) & WM8960_IFACE2_DACCOMP_MASK) >> WM8960_IFACE2_DACCOMP_SHIFT) 605 606 /* 607 * ADCCOMP (RW) 608 * 609 * ADC companding 610 * 00 = off 611 * 01 = reserved 612 * 10 = μ-law 613 * 11 = A-law 614 */ 615 #define WM8960_IFACE2_ADCCOMP_MASK (0x6U) 616 #define WM8960_IFACE2_ADCCOMP_SHIFT (1U) 617 #define WM8960_IFACE2_ADCCOMP_SET(x) (((uint16_t)(x) << WM8960_IFACE2_ADCCOMP_SHIFT) & WM8960_IFACE2_ADCCOMP_MASK) 618 #define WM8960_IFACE2_ADCCOMP_GET(x) (((uint16_t)(x) & WM8960_IFACE2_ADCCOMP_MASK) >> WM8960_IFACE2_ADCCOMP_SHIFT) 619 620 /* 621 * LOOPBACK (RW) 622 * 623 * Digital Loopback Function 624 * 0 = No loopback. 625 * 1 = Loopback enabled, ADC data output is fed 626 * directly into DAC data input 627 */ 628 #define WM8960_IFACE2_LOOPBACK_MASK (0x1U) 629 #define WM8960_IFACE2_LOOPBACK_SHIFT (0U) 630 #define WM8960_IFACE2_LOOPBACK_SET(x) (((uint16_t)(x) << WM8960_IFACE2_LOOPBACK_SHIFT) & WM8960_IFACE2_LOOPBACK_MASK) 631 #define WM8960_IFACE2_LOOPBACK_GET(x) (((uint16_t)(x) & WM8960_IFACE2_LOOPBACK_MASK) >> WM8960_IFACE2_LOOPBACK_SHIFT) 632 633 /* Bitfield definition for register: LDAC */ 634 /* 635 * DACVU (RW) 636 * 637 * DAC Volume Update 638 * Writing a 1 to this bit will cause left and right 639 * DAC volumes to be updated (LDACVOL and RDACVOL) 640 */ 641 #define WM8960_LDAC_DACVU_MASK (0x100U) 642 #define WM8960_LDAC_DACVU_SHIFT (8U) 643 #define WM8960_LDAC_DACVU_SET(x) (((uint16_t)(x) << WM8960_LDAC_DACVU_SHIFT) & WM8960_LDAC_DACVU_MASK) 644 #define WM8960_LDAC_DACVU_GET(x) (((uint16_t)(x) & WM8960_LDAC_DACVU_MASK) >> WM8960_LDAC_DACVU_SHIFT) 645 646 /* 647 * LDACVOL (RW) 648 * 649 * Left DAC Digital Volume Control 650 * 0000 0000 = Digital Mute 651 * 0000 0001 = -127dB 652 * 0000 0010 = -126.5dB 653 * ... 0.5dB steps up to 654 * 1111 1111 = 0dB 655 */ 656 #define WM8960_LDAC_LDACVOL_MASK (0xFFU) 657 #define WM8960_LDAC_LDACVOL_SHIFT (0U) 658 #define WM8960_LDAC_LDACVOL_SET(x) (((uint16_t)(x) << WM8960_LDAC_LDACVOL_SHIFT) & WM8960_LDAC_LDACVOL_MASK) 659 #define WM8960_LDAC_LDACVOL_GET(x) (((uint16_t)(x) & WM8960_LDAC_LDACVOL_MASK) >> WM8960_LDAC_LDACVOL_SHIFT) 660 661 /* Bitfield definition for register: RDAC */ 662 /* 663 * DACVU (RW) 664 * 665 * DAC Volume Update 666 * Writing a 1 to this bit will cause left and right 667 * DAC volumes to be updated (LDACVOL and RDACVOL) 668 */ 669 #define WM8960_RDAC_DACVU_MASK (0x100U) 670 #define WM8960_RDAC_DACVU_SHIFT (8U) 671 #define WM8960_RDAC_DACVU_SET(x) (((uint16_t)(x) << WM8960_RDAC_DACVU_SHIFT) & WM8960_RDAC_DACVU_MASK) 672 #define WM8960_RDAC_DACVU_GET(x) (((uint16_t)(x) & WM8960_RDAC_DACVU_MASK) >> WM8960_RDAC_DACVU_SHIFT) 673 674 /* 675 * RDACVOL (RW) 676 * 677 * Right DAC Digital Volume Control 678 * 0000 0000 = Digital Mute 679 * 0000 0001 = -127dB 680 * 0000 0010 = -126.5dB 681 * ... 0.5dB steps up to 682 * 1111 1111 = 0dB 683 */ 684 #define WM8960_RDAC_RDACVOL_MASK (0xFFU) 685 #define WM8960_RDAC_RDACVOL_SHIFT (0U) 686 #define WM8960_RDAC_RDACVOL_SET(x) (((uint16_t)(x) << WM8960_RDAC_RDACVOL_SHIFT) & WM8960_RDAC_RDACVOL_MASK) 687 #define WM8960_RDAC_RDACVOL_GET(x) (((uint16_t)(x) & WM8960_RDAC_RDACVOL_MASK) >> WM8960_RDAC_RDACVOL_SHIFT) 688 689 /* Bitfield definition for register: RESET */ 690 /* 691 * RESET (RW) 692 * 693 * Writing to this register resets all registers to their default state. 694 */ 695 #define WM8960_RESET_RESET_MASK (0x1FFU) 696 #define WM8960_RESET_RESET_SHIFT (0U) 697 #define WM8960_RESET_RESET_SET(x) (((uint16_t)(x) << WM8960_RESET_RESET_SHIFT) & WM8960_RESET_RESET_MASK) 698 #define WM8960_RESET_RESET_GET(x) (((uint16_t)(x) & WM8960_RESET_RESET_MASK) >> WM8960_RESET_RESET_SHIFT) 699 700 /* Bitfield definition for register: 3D */ 701 /* 702 * 3DUC (RW) 703 * 704 * 3D Enhance Filter Upper Cut-Off Frequency 705 * 0 = High (Recommended for fs>=32kHz) 706 * 1 = Low (Recommended for fs<32kHz) 707 */ 708 #define WM8960_3D_3DUC_MASK (0x40U) 709 #define WM8960_3D_3DUC_SHIFT (6U) 710 #define WM8960_3D_3DUC_SET(x) (((uint16_t)(x) << WM8960_3D_3DUC_SHIFT) & WM8960_3D_3DUC_MASK) 711 #define WM8960_3D_3DUC_GET(x) (((uint16_t)(x) & WM8960_3D_3DUC_MASK) >> WM8960_3D_3DUC_SHIFT) 712 713 /* 714 * 3DLC (RW) 715 * 716 * 3D Enhance Filter Lower Cut-Off Frequency 717 * 0 = Low (Recommended for fs>=32kHz) 718 * 1 = High (Recommended for fs<32kHz) 719 */ 720 #define WM8960_3D_3DLC_MASK (0x20U) 721 #define WM8960_3D_3DLC_SHIFT (5U) 722 #define WM8960_3D_3DLC_SET(x) (((uint16_t)(x) << WM8960_3D_3DLC_SHIFT) & WM8960_3D_3DLC_MASK) 723 #define WM8960_3D_3DLC_GET(x) (((uint16_t)(x) & WM8960_3D_3DLC_MASK) >> WM8960_3D_3DLC_SHIFT) 724 725 /* 726 * 3DDEPTH (RW) 727 * 728 * 3D Stereo Depth 729 * 0000 = 0% (minimum 3D effect) 730 * 0001 = 6.67% 731 * .... 732 * 1110 = 93.3% 733 * 1111 = 100% (maximum 3D effect) 734 */ 735 #define WM8960_3D_3DDEPTH_MASK (0x1EU) 736 #define WM8960_3D_3DDEPTH_SHIFT (1U) 737 #define WM8960_3D_3DDEPTH_SET(x) (((uint16_t)(x) << WM8960_3D_3DDEPTH_SHIFT) & WM8960_3D_3DDEPTH_MASK) 738 #define WM8960_3D_3DDEPTH_GET(x) (((uint16_t)(x) & WM8960_3D_3DDEPTH_MASK) >> WM8960_3D_3DDEPTH_SHIFT) 739 740 /* 741 * 3DEN (RW) 742 * 743 * 3D Stereo Enhancement Enable 744 * 0 = Disabled 745 * 1 = Enabled 746 */ 747 #define WM8960_3D_3DEN_MASK (0x1U) 748 #define WM8960_3D_3DEN_SHIFT (0U) 749 #define WM8960_3D_3DEN_SET(x) (((uint16_t)(x) << WM8960_3D_3DEN_SHIFT) & WM8960_3D_3DEN_MASK) 750 #define WM8960_3D_3DEN_GET(x) (((uint16_t)(x) & WM8960_3D_3DEN_MASK) >> WM8960_3D_3DEN_SHIFT) 751 752 /* Bitfield definition for register: ALC1 */ 753 /* 754 * ALCSEL (RW) 755 * 756 * ALC Function Select 757 * 00 = ALC off (PGA gain set by register) 758 * 01 = Right channel only 759 * 10 = Left channel only 760 * 11 = Stereo (PGA registers unused) Note: 761 * ensure that LINVOL and RINVOL settings 762 * (reg. 0 and 1) are the same before entering this mode. 763 */ 764 #define WM8960_ALC1_ALCSEL_MASK (0x180U) 765 #define WM8960_ALC1_ALCSEL_SHIFT (7U) 766 #define WM8960_ALC1_ALCSEL_SET(x) (((uint16_t)(x) << WM8960_ALC1_ALCSEL_SHIFT) & WM8960_ALC1_ALCSEL_MASK) 767 #define WM8960_ALC1_ALCSEL_GET(x) (((uint16_t)(x) & WM8960_ALC1_ALCSEL_MASK) >> WM8960_ALC1_ALCSEL_SHIFT) 768 769 /* 770 * MAXGAIN (RW) 771 * 772 * Set Maximum Gain of PGA (During ALC 773 * operation) 774 * 111 : +30dB 775 * 110 : +24dB 776 * ….(-6dB steps) 777 * 001 : -6dB 778 * 000 : -12dB 779 */ 780 #define WM8960_ALC1_MAXGAIN_MASK (0x70U) 781 #define WM8960_ALC1_MAXGAIN_SHIFT (4U) 782 #define WM8960_ALC1_MAXGAIN_SET(x) (((uint16_t)(x) << WM8960_ALC1_MAXGAIN_SHIFT) & WM8960_ALC1_MAXGAIN_MASK) 783 #define WM8960_ALC1_MAXGAIN_GET(x) (((uint16_t)(x) & WM8960_ALC1_MAXGAIN_MASK) >> WM8960_ALC1_MAXGAIN_SHIFT) 784 785 /* 786 * ALCL (RW) 787 * 788 * ALC Target (Sets signal level at ADC input) 789 * 0000 = -22.5dB FS 790 * 0001 = -21.0dB FS 791 * … (1.5dB steps) 792 * 1101 = -3.0dB FS 793 * 1110 = -1.5dB FS 794 * 1111 = -1.5dB FS 795 */ 796 #define WM8960_ALC1_ALCL_MASK (0xFU) 797 #define WM8960_ALC1_ALCL_SHIFT (0U) 798 #define WM8960_ALC1_ALCL_SET(x) (((uint16_t)(x) << WM8960_ALC1_ALCL_SHIFT) & WM8960_ALC1_ALCL_MASK) 799 #define WM8960_ALC1_ALCL_GET(x) (((uint16_t)(x) & WM8960_ALC1_ALCL_MASK) >> WM8960_ALC1_ALCL_SHIFT) 800 801 /* Bitfield definition for register: ALC2 */ 802 /* 803 * MINGAIN (RW) 804 * 805 * Set Minimum Gain of PGA (During ALC 806 * operation) 807 * 000 = -17.25dB 808 * 001 = -11.25dB 809 * 010 = -5.25dB 810 * 011 = +0.75dB 811 * 100 = +6.75dB 812 * 101 = +12.75dB 813 * 110 = +18.75dB 814 * 111 = +24.75dB 815 */ 816 #define WM8960_ALC2_MINGAIN_MASK (0x70U) 817 #define WM8960_ALC2_MINGAIN_SHIFT (4U) 818 #define WM8960_ALC2_MINGAIN_SET(x) (((uint16_t)(x) << WM8960_ALC2_MINGAIN_SHIFT) & WM8960_ALC2_MINGAIN_MASK) 819 #define WM8960_ALC2_MINGAIN_GET(x) (((uint16_t)(x) & WM8960_ALC2_MINGAIN_MASK) >> WM8960_ALC2_MINGAIN_SHIFT) 820 821 /* 822 * HLD (RW) 823 * 824 * ALC hold time before gain is increased. 825 * 0000 = 0ms 826 * 0001 = 2.67ms 827 * 0010 = 5.33ms 828 * … (time doubles with every step) 829 * 1111 = 43.691s 830 */ 831 #define WM8960_ALC2_HLD_MASK (0xFU) 832 #define WM8960_ALC2_HLD_SHIFT (0U) 833 #define WM8960_ALC2_HLD_SET(x) (((uint16_t)(x) << WM8960_ALC2_HLD_SHIFT) & WM8960_ALC2_HLD_MASK) 834 #define WM8960_ALC2_HLD_GET(x) (((uint16_t)(x) & WM8960_ALC2_HLD_MASK) >> WM8960_ALC2_HLD_SHIFT) 835 836 /* Bitfield definition for register: ALC3 */ 837 /* 838 * ALCMODE (RW) 839 * 840 * Determines the ALC mode of operation: 841 * 0 = ALC mode 842 * 1 = Limiter mode 843 */ 844 #define WM8960_ALC3_ALCMODE_MASK (0x100U) 845 #define WM8960_ALC3_ALCMODE_SHIFT (8U) 846 #define WM8960_ALC3_ALCMODE_SET(x) (((uint16_t)(x) << WM8960_ALC3_ALCMODE_SHIFT) & WM8960_ALC3_ALCMODE_MASK) 847 #define WM8960_ALC3_ALCMODE_GET(x) (((uint16_t)(x) & WM8960_ALC3_ALCMODE_MASK) >> WM8960_ALC3_ALCMODE_SHIFT) 848 849 /* 850 * DCY (RW) 851 * 852 * ALC decay (gain ramp-up) time 853 * 0000 = 24ms 854 * 0001 = 48ms 855 * 0010 = 96ms 856 * … (time doubles with every step) 857 * 1010 or higher = 24.58s 858 */ 859 #define WM8960_ALC3_DCY_MASK (0xF0U) 860 #define WM8960_ALC3_DCY_SHIFT (4U) 861 #define WM8960_ALC3_DCY_SET(x) (((uint16_t)(x) << WM8960_ALC3_DCY_SHIFT) & WM8960_ALC3_DCY_MASK) 862 #define WM8960_ALC3_DCY_GET(x) (((uint16_t)(x) & WM8960_ALC3_DCY_MASK) >> WM8960_ALC3_DCY_SHIFT) 863 864 /* 865 * ATK (RW) 866 * 867 * ALC attack (gain ramp-down) time 868 * 0000 = 6ms 869 * 0001 = 12ms 870 * 0010 = 24ms 871 * … (time doubles with every step) 872 * 1010 or higher = 6.14s 873 */ 874 #define WM8960_ALC3_ATK_MASK (0xFU) 875 #define WM8960_ALC3_ATK_SHIFT (0U) 876 #define WM8960_ALC3_ATK_SET(x) (((uint16_t)(x) << WM8960_ALC3_ATK_SHIFT) & WM8960_ALC3_ATK_MASK) 877 #define WM8960_ALC3_ATK_GET(x) (((uint16_t)(x) & WM8960_ALC3_ATK_MASK) >> WM8960_ALC3_ATK_SHIFT) 878 879 /* Bitfield definition for register: NOISEG */ 880 /* 881 * NGTH (RW) 882 * 883 * Noise gate threshold 884 * 00000 -76.5dBfs 885 * 00001 -75dBfs 886 * … 1.5 dB steps 887 * 11110 -31.5dBfs 888 * 11111 -30dBfs 889 */ 890 #define WM8960_NOISEG_NGTH_MASK (0xF8U) 891 #define WM8960_NOISEG_NGTH_SHIFT (3U) 892 #define WM8960_NOISEG_NGTH_SET(x) (((uint16_t)(x) << WM8960_NOISEG_NGTH_SHIFT) & WM8960_NOISEG_NGTH_MASK) 893 #define WM8960_NOISEG_NGTH_GET(x) (((uint16_t)(x) & WM8960_NOISEG_NGTH_MASK) >> WM8960_NOISEG_NGTH_SHIFT) 894 895 /* 896 * NGAT (RW) 897 * 898 * Noise gate function enable 899 * 0 = disable 900 * 1 = enable 901 */ 902 #define WM8960_NOISEG_NGAT_MASK (0x1U) 903 #define WM8960_NOISEG_NGAT_SHIFT (0U) 904 #define WM8960_NOISEG_NGAT_SET(x) (((uint16_t)(x) << WM8960_NOISEG_NGAT_SHIFT) & WM8960_NOISEG_NGAT_MASK) 905 #define WM8960_NOISEG_NGAT_GET(x) (((uint16_t)(x) & WM8960_NOISEG_NGAT_MASK) >> WM8960_NOISEG_NGAT_SHIFT) 906 907 /* Bitfield definition for register: LADC */ 908 /* 909 * ADCVU (RW) 910 * 911 * ADC Volume Update 912 * Writing a 1 to this bit will cause left and right 913 * ADC volumes to be updated (LADCVOL and 914 * RADCVOL) 915 */ 916 #define WM8960_LADC_ADCVU_MASK (0x100U) 917 #define WM8960_LADC_ADCVU_SHIFT (8U) 918 #define WM8960_LADC_ADCVU_SET(x) (((uint16_t)(x) << WM8960_LADC_ADCVU_SHIFT) & WM8960_LADC_ADCVU_MASK) 919 #define WM8960_LADC_ADCVU_GET(x) (((uint16_t)(x) & WM8960_LADC_ADCVU_MASK) >> WM8960_LADC_ADCVU_SHIFT) 920 921 /* 922 * LADCVOL (RW) 923 * 924 * Left ADC Digital Volume Control 925 * 0000 0000 = Digital Mute 926 * 0000 0001 = -97dB 927 * 0000 0010 = -96.5dB 928 * ... 0.5dB steps up to 929 * 1111 1111 = +30dB 930 */ 931 #define WM8960_LADC_LADCVOL_MASK (0xFFU) 932 #define WM8960_LADC_LADCVOL_SHIFT (0U) 933 #define WM8960_LADC_LADCVOL_SET(x) (((uint16_t)(x) << WM8960_LADC_LADCVOL_SHIFT) & WM8960_LADC_LADCVOL_MASK) 934 #define WM8960_LADC_LADCVOL_GET(x) (((uint16_t)(x) & WM8960_LADC_LADCVOL_MASK) >> WM8960_LADC_LADCVOL_SHIFT) 935 936 /* Bitfield definition for register: RADC */ 937 /* 938 * ADCVU (RW) 939 * 940 * ADC Volume Update 941 * Writing a 1 to this bit will cause left and right 942 * ADC volumes to be updated (LADCVOL and RADCVOL) 943 */ 944 #define WM8960_RADC_ADCVU_MASK (0x100U) 945 #define WM8960_RADC_ADCVU_SHIFT (8U) 946 #define WM8960_RADC_ADCVU_SET(x) (((uint16_t)(x) << WM8960_RADC_ADCVU_SHIFT) & WM8960_RADC_ADCVU_MASK) 947 #define WM8960_RADC_ADCVU_GET(x) (((uint16_t)(x) & WM8960_RADC_ADCVU_MASK) >> WM8960_RADC_ADCVU_SHIFT) 948 949 /* 950 * RADCVOL (RW) 951 * 952 * Right ADC Digital Volume Control 953 * 0000 0000 = Digital Mute 954 * 0000 0001 = -97dB 955 * 0000 0010 = -96.5dB 956 * ... 0.5dB steps up to 957 * 1111 1111 = +30dB 958 */ 959 #define WM8960_RADC_RADCVOL_MASK (0xFFU) 960 #define WM8960_RADC_RADCVOL_SHIFT (0U) 961 #define WM8960_RADC_RADCVOL_SET(x) (((uint16_t)(x) << WM8960_RADC_RADCVOL_SHIFT) & WM8960_RADC_RADCVOL_MASK) 962 #define WM8960_RADC_RADCVOL_GET(x) (((uint16_t)(x) & WM8960_RADC_RADCVOL_MASK) >> WM8960_RADC_RADCVOL_SHIFT) 963 964 /* Bitfield definition for register: ADDCTL1 */ 965 /* 966 * TSDEN (RW) 967 * 968 * Thermal Shutdown Enable 969 * 0 = Thermal shutdown disabled 970 * 1 = Thermal shutdown enabled 971 * (TSENSEN must be enabled for this function to work) 972 */ 973 #define WM8960_ADDCTL1_TSDEN_MASK (0x100U) 974 #define WM8960_ADDCTL1_TSDEN_SHIFT (8U) 975 #define WM8960_ADDCTL1_TSDEN_SET(x) (((uint16_t)(x) << WM8960_ADDCTL1_TSDEN_SHIFT) & WM8960_ADDCTL1_TSDEN_MASK) 976 #define WM8960_ADDCTL1_TSDEN_GET(x) (((uint16_t)(x) & WM8960_ADDCTL1_TSDEN_MASK) >> WM8960_ADDCTL1_TSDEN_SHIFT) 977 978 /* 979 * VSEL (RW) 980 * 981 * Analogue Bias Optimisation 982 * 00 = Reserved 983 * 01 = Increased bias current optimized for 984 * AVDD=2.7V 985 * 1X = Lowest bias current, optimized for 986 * AVDD=3.3V 987 */ 988 #define WM8960_ADDCTL1_VSEL_MASK (0xC0U) 989 #define WM8960_ADDCTL1_VSEL_SHIFT (6U) 990 #define WM8960_ADDCTL1_VSEL_SET(x) (((uint16_t)(x) << WM8960_ADDCTL1_VSEL_SHIFT) & WM8960_ADDCTL1_VSEL_MASK) 991 #define WM8960_ADDCTL1_VSEL_GET(x) (((uint16_t)(x) & WM8960_ADDCTL1_VSEL_MASK) >> WM8960_ADDCTL1_VSEL_SHIFT) 992 993 /* 994 * DMONOMIX (RW) 995 * 996 * DAC Mono Mix 997 * 0 = Stereo 998 * 1 = Mono (Mono MIX output on enabled DACs 999 */ 1000 #define WM8960_ADDCTL1_DMONOMIX_MASK (0x10U) 1001 #define WM8960_ADDCTL1_DMONOMIX_SHIFT (4U) 1002 #define WM8960_ADDCTL1_DMONOMIX_SET(x) (((uint16_t)(x) << WM8960_ADDCTL1_DMONOMIX_SHIFT) & WM8960_ADDCTL1_DMONOMIX_MASK) 1003 #define WM8960_ADDCTL1_DMONOMIX_GET(x) (((uint16_t)(x) & WM8960_ADDCTL1_DMONOMIX_MASK) >> WM8960_ADDCTL1_DMONOMIX_SHIFT) 1004 1005 /* 1006 * DATSEL (RW) 1007 * 1008 * ADC Data Output Select 1009 * 00: left data = left ADC; right data =right ADC 1010 * 01: left data = left ADC; right data = left ADC 1011 * 10: left data = right ADC; right data =right ADC 1012 * 11: left data = right ADC; right data = left ADC 1013 */ 1014 #define WM8960_ADDCTL1_DATSEL_MASK (0xCU) 1015 #define WM8960_ADDCTL1_DATSEL_SHIFT (2U) 1016 #define WM8960_ADDCTL1_DATSEL_SET(x) (((uint16_t)(x) << WM8960_ADDCTL1_DATSEL_SHIFT) & WM8960_ADDCTL1_DATSEL_MASK) 1017 #define WM8960_ADDCTL1_DATSEL_GET(x) (((uint16_t)(x) & WM8960_ADDCTL1_DATSEL_MASK) >> WM8960_ADDCTL1_DATSEL_SHIFT) 1018 1019 /* 1020 * TOCLKSEL (RW) 1021 * 1022 * Slow Clock Select (Used for volume update 1023 * timeouts and for jack detect debounce) 1024 * 0 = SYSCLK / 221 (Slower Response) 1025 * 1 = SYSCLK / 219 (Faster Response) 1026 */ 1027 #define WM8960_ADDCTL1_TOCLKSEL_MASK (0x2U) 1028 #define WM8960_ADDCTL1_TOCLKSEL_SHIFT (1U) 1029 #define WM8960_ADDCTL1_TOCLKSEL_SET(x) (((uint16_t)(x) << WM8960_ADDCTL1_TOCLKSEL_SHIFT) & WM8960_ADDCTL1_TOCLKSEL_MASK) 1030 #define WM8960_ADDCTL1_TOCLKSEL_GET(x) (((uint16_t)(x) & WM8960_ADDCTL1_TOCLKSEL_MASK) >> WM8960_ADDCTL1_TOCLKSEL_SHIFT) 1031 1032 /* 1033 * TOEN (RW) 1034 * 1035 * Enables Slow Clock for Volume Update Timeout 1036 * and Jack Detect Debounce 1037 * 0 = Slow clock disabled 1038 * 1 = Slow clock enabled 1039 */ 1040 #define WM8960_ADDCTL1_TOEN_MASK (0x1U) 1041 #define WM8960_ADDCTL1_TOEN_SHIFT (0U) 1042 #define WM8960_ADDCTL1_TOEN_SET(x) (((uint16_t)(x) << WM8960_ADDCTL1_TOEN_SHIFT) & WM8960_ADDCTL1_TOEN_MASK) 1043 #define WM8960_ADDCTL1_TOEN_GET(x) (((uint16_t)(x) & WM8960_ADDCTL1_TOEN_MASK) >> WM8960_ADDCTL1_TOEN_SHIFT) 1044 1045 /* Bitfield definition for register: ADDCTL2 */ 1046 /* 1047 * HPSWEN (RW) 1048 * 1049 * Headphone Switch Enable 1050 * 0 = Headphone switch disabled 1051 * 1 = Headphone switch enabled 1052 */ 1053 #define WM8960_ADDCTL2_HPSWEN_MASK (0x40U) 1054 #define WM8960_ADDCTL2_HPSWEN_SHIFT (6U) 1055 #define WM8960_ADDCTL2_HPSWEN_SET(x) (((uint16_t)(x) << WM8960_ADDCTL2_HPSWEN_SHIFT) & WM8960_ADDCTL2_HPSWEN_MASK) 1056 #define WM8960_ADDCTL2_HPSWEN_GET(x) (((uint16_t)(x) & WM8960_ADDCTL2_HPSWEN_MASK) >> WM8960_ADDCTL2_HPSWEN_SHIFT) 1057 1058 /* 1059 * HPSWPOL (RW) 1060 * 1061 * Headphone Switch Polarity 1062 * 0 = HPDETECT high = headphone 1063 * 1 = HPDETECT high = speaker 1064 */ 1065 #define WM8960_ADDCTL2_HPSWPOL_MASK (0x20U) 1066 #define WM8960_ADDCTL2_HPSWPOL_SHIFT (5U) 1067 #define WM8960_ADDCTL2_HPSWPOL_SET(x) (((uint16_t)(x) << WM8960_ADDCTL2_HPSWPOL_SHIFT) & WM8960_ADDCTL2_HPSWPOL_MASK) 1068 #define WM8960_ADDCTL2_HPSWPOL_GET(x) (((uint16_t)(x) & WM8960_ADDCTL2_HPSWPOL_MASK) >> WM8960_ADDCTL2_HPSWPOL_SHIFT) 1069 1070 /* 1071 * TRIS (RW) 1072 * 1073 * Tristates ADCDAT and switches ADCLRC, 1074 * DACLRC and BCLK to inputs. 1075 * 0 = ADCDAT is an output; ADCLRC, DACLRC 1076 * and BCLK are inputs (slave mode) or outputs 1077 * (master mode) 1078 * 1 = ADCDAT is tristated; DACLRC and BCLK 1079 * are inputs; ADCLRC is an input (when not 1080 * configured as a GPIO) 1081 */ 1082 #define WM8960_ADDCTL2_TRIS_MASK (0x8U) 1083 #define WM8960_ADDCTL2_TRIS_SHIFT (3U) 1084 #define WM8960_ADDCTL2_TRIS_SET(x) (((uint16_t)(x) << WM8960_ADDCTL2_TRIS_SHIFT) & WM8960_ADDCTL2_TRIS_MASK) 1085 #define WM8960_ADDCTL2_TRIS_GET(x) (((uint16_t)(x) & WM8960_ADDCTL2_TRIS_MASK) >> WM8960_ADDCTL2_TRIS_SHIFT) 1086 1087 /* 1088 * LRCM (RW) 1089 * 1090 * Selects disable mode for ADCLRC and DACLRC 1091 * (Master mode) 1092 * 0 = ADCLRC disabled when ADC (Left and 1093 * Right) disabled; DACLRC disabled when 1094 * DAC (Left and Right) disabled. 1095 * 1 = ADCLRC and DACLRC disabled only when 1096 * ADC (Left and Right) and DAC (Left and Right) 1097 * are disabled. 1098 */ 1099 #define WM8960_ADDCTL2_LRCM_MASK (0x4U) 1100 #define WM8960_ADDCTL2_LRCM_SHIFT (2U) 1101 #define WM8960_ADDCTL2_LRCM_SET(x) (((uint16_t)(x) << WM8960_ADDCTL2_LRCM_SHIFT) & WM8960_ADDCTL2_LRCM_MASK) 1102 #define WM8960_ADDCTL2_LRCM_GET(x) (((uint16_t)(x) & WM8960_ADDCTL2_LRCM_MASK) >> WM8960_ADDCTL2_LRCM_SHIFT) 1103 1104 /* Bitfield definition for register: POWER1 */ 1105 /* 1106 * VMIDSEL (RW) 1107 * 1108 * Vmid Divider Enable and Select 1109 * 00 = Vmid disabled (for OFF mode) 1110 * 01 = 2 x 50k divider enabled (for playback / 1111 * record) 1112 * 10 = 2 x 250k divider enabled (for low-power 1113 * standby) 1114 * 11 = 2 x 5k divider enabled (for fast start-up) 1115 */ 1116 #define WM8960_POWER1_VMIDSEL_MASK (0x180U) 1117 #define WM8960_POWER1_VMIDSEL_SHIFT (7U) 1118 #define WM8960_POWER1_VMIDSEL_SET(x) (((uint16_t)(x) << WM8960_POWER1_VMIDSEL_SHIFT) & WM8960_POWER1_VMIDSEL_MASK) 1119 #define WM8960_POWER1_VMIDSEL_GET(x) (((uint16_t)(x) & WM8960_POWER1_VMIDSEL_MASK) >> WM8960_POWER1_VMIDSEL_SHIFT) 1120 1121 /* 1122 * VREF (RW) 1123 * 1124 * VREF (necessary for all other functions) 1125 * 0 = Power down 1126 * 1 = Power up 1127 */ 1128 #define WM8960_POWER1_VREF_MASK (0x40U) 1129 #define WM8960_POWER1_VREF_SHIFT (6U) 1130 #define WM8960_POWER1_VREF_SET(x) (((uint16_t)(x) << WM8960_POWER1_VREF_SHIFT) & WM8960_POWER1_VREF_MASK) 1131 #define WM8960_POWER1_VREF_GET(x) (((uint16_t)(x) & WM8960_POWER1_VREF_MASK) >> WM8960_POWER1_VREF_SHIFT) 1132 1133 /* 1134 * AINL (RW) 1135 * 1136 * Analogue in PGA Left 1137 * 0 = Power down 1138 * 1 = Power up 1139 */ 1140 #define WM8960_POWER1_AINL_MASK (0x20U) 1141 #define WM8960_POWER1_AINL_SHIFT (5U) 1142 #define WM8960_POWER1_AINL_SET(x) (((uint16_t)(x) << WM8960_POWER1_AINL_SHIFT) & WM8960_POWER1_AINL_MASK) 1143 #define WM8960_POWER1_AINL_GET(x) (((uint16_t)(x) & WM8960_POWER1_AINL_MASK) >> WM8960_POWER1_AINL_SHIFT) 1144 1145 /* 1146 * AINR (RW) 1147 * 1148 * Analogue in PGA Right 1149 * 0 = Power down 1150 * 1 = Power up 1151 */ 1152 #define WM8960_POWER1_AINR_MASK (0x10U) 1153 #define WM8960_POWER1_AINR_SHIFT (4U) 1154 #define WM8960_POWER1_AINR_SET(x) (((uint16_t)(x) << WM8960_POWER1_AINR_SHIFT) & WM8960_POWER1_AINR_MASK) 1155 #define WM8960_POWER1_AINR_GET(x) (((uint16_t)(x) & WM8960_POWER1_AINR_MASK) >> WM8960_POWER1_AINR_SHIFT) 1156 1157 /* 1158 * ADCL (RW) 1159 * 1160 * ADC Left 1161 * 0 = Power down 1162 * 1 = Power up 1163 */ 1164 #define WM8960_POWER1_ADCL_MASK (0x8U) 1165 #define WM8960_POWER1_ADCL_SHIFT (3U) 1166 #define WM8960_POWER1_ADCL_SET(x) (((uint16_t)(x) << WM8960_POWER1_ADCL_SHIFT) & WM8960_POWER1_ADCL_MASK) 1167 #define WM8960_POWER1_ADCL_GET(x) (((uint16_t)(x) & WM8960_POWER1_ADCL_MASK) >> WM8960_POWER1_ADCL_SHIFT) 1168 1169 /* 1170 * ADCR (RW) 1171 * 1172 * ADC Right 1173 * 0 = Power down 1174 * 1 = Power up 1175 */ 1176 #define WM8960_POWER1_ADCR_MASK (0x4U) 1177 #define WM8960_POWER1_ADCR_SHIFT (2U) 1178 #define WM8960_POWER1_ADCR_SET(x) (((uint16_t)(x) << WM8960_POWER1_ADCR_SHIFT) & WM8960_POWER1_ADCR_MASK) 1179 #define WM8960_POWER1_ADCR_GET(x) (((uint16_t)(x) & WM8960_POWER1_ADCR_MASK) >> WM8960_POWER1_ADCR_SHIFT) 1180 1181 /* 1182 * MICB (RW) 1183 * 1184 * MICBIAS 1185 * 0 = Power down 1186 * 1 = Power up 1187 */ 1188 #define WM8960_POWER1_MICB_MASK (0x2U) 1189 #define WM8960_POWER1_MICB_SHIFT (1U) 1190 #define WM8960_POWER1_MICB_SET(x) (((uint16_t)(x) << WM8960_POWER1_MICB_SHIFT) & WM8960_POWER1_MICB_MASK) 1191 #define WM8960_POWER1_MICB_GET(x) (((uint16_t)(x) & WM8960_POWER1_MICB_MASK) >> WM8960_POWER1_MICB_SHIFT) 1192 1193 /* 1194 * DIGENB (RW) 1195 * 1196 * Master Clock Disable 1197 * 0 = Master clock enabled 1198 * 1 = Master clock disabled 1199 */ 1200 #define WM8960_POWER1_DIGENB_MASK (0x1U) 1201 #define WM8960_POWER1_DIGENB_SHIFT (0U) 1202 #define WM8960_POWER1_DIGENB_SET(x) (((uint16_t)(x) << WM8960_POWER1_DIGENB_SHIFT) & WM8960_POWER1_DIGENB_MASK) 1203 #define WM8960_POWER1_DIGENB_GET(x) (((uint16_t)(x) & WM8960_POWER1_DIGENB_MASK) >> WM8960_POWER1_DIGENB_SHIFT) 1204 1205 /* Bitfield definition for register: POWER2 */ 1206 /* 1207 * DACL (RW) 1208 * 1209 * DAC Left 1210 * 0 = Power down 1211 * 1 = Power up 1212 */ 1213 #define WM8960_POWER2_DACL_MASK (0x100U) 1214 #define WM8960_POWER2_DACL_SHIFT (8U) 1215 #define WM8960_POWER2_DACL_SET(x) (((uint16_t)(x) << WM8960_POWER2_DACL_SHIFT) & WM8960_POWER2_DACL_MASK) 1216 #define WM8960_POWER2_DACL_GET(x) (((uint16_t)(x) & WM8960_POWER2_DACL_MASK) >> WM8960_POWER2_DACL_SHIFT) 1217 1218 /* 1219 * DACR (RW) 1220 * 1221 * DAC Right 1222 * 0 = Power down 1223 * 1 = Power up 1224 */ 1225 #define WM8960_POWER2_DACR_MASK (0x80U) 1226 #define WM8960_POWER2_DACR_SHIFT (7U) 1227 #define WM8960_POWER2_DACR_SET(x) (((uint16_t)(x) << WM8960_POWER2_DACR_SHIFT) & WM8960_POWER2_DACR_MASK) 1228 #define WM8960_POWER2_DACR_GET(x) (((uint16_t)(x) & WM8960_POWER2_DACR_MASK) >> WM8960_POWER2_DACR_SHIFT) 1229 1230 /* 1231 * LOUT1 (RW) 1232 * 1233 * LOUT1 Output Buffer 1234 * 0 = Power down 1235 * 1 = Power up 1236 */ 1237 #define WM8960_POWER2_LOUT1_MASK (0x40U) 1238 #define WM8960_POWER2_LOUT1_SHIFT (6U) 1239 #define WM8960_POWER2_LOUT1_SET(x) (((uint16_t)(x) << WM8960_POWER2_LOUT1_SHIFT) & WM8960_POWER2_LOUT1_MASK) 1240 #define WM8960_POWER2_LOUT1_GET(x) (((uint16_t)(x) & WM8960_POWER2_LOUT1_MASK) >> WM8960_POWER2_LOUT1_SHIFT) 1241 1242 /* 1243 * ROUT1 (RW) 1244 * 1245 * ROUT1 Output Buffer 1246 * 0 = Power down 1247 * 1 = Power up 1248 */ 1249 #define WM8960_POWER2_ROUT1_MASK (0x20U) 1250 #define WM8960_POWER2_ROUT1_SHIFT (5U) 1251 #define WM8960_POWER2_ROUT1_SET(x) (((uint16_t)(x) << WM8960_POWER2_ROUT1_SHIFT) & WM8960_POWER2_ROUT1_MASK) 1252 #define WM8960_POWER2_ROUT1_GET(x) (((uint16_t)(x) & WM8960_POWER2_ROUT1_MASK) >> WM8960_POWER2_ROUT1_SHIFT) 1253 1254 /* 1255 * SPKL (RW) 1256 * 1257 * SPK_LP/SPK_LN Output Buffers 1258 * 0 = Power down 1259 * 1 = Power up 1260 */ 1261 #define WM8960_POWER2_SPKL_MASK (0x10U) 1262 #define WM8960_POWER2_SPKL_SHIFT (4U) 1263 #define WM8960_POWER2_SPKL_SET(x) (((uint16_t)(x) << WM8960_POWER2_SPKL_SHIFT) & WM8960_POWER2_SPKL_MASK) 1264 #define WM8960_POWER2_SPKL_GET(x) (((uint16_t)(x) & WM8960_POWER2_SPKL_MASK) >> WM8960_POWER2_SPKL_SHIFT) 1265 1266 /* 1267 * SPKR (RW) 1268 * 1269 * SPK_RP/SPK_RN Output Buffers 1270 * 0 = Power down 1271 * 1 = Power up 1272 */ 1273 #define WM8960_POWER2_SPKR_MASK (0x8U) 1274 #define WM8960_POWER2_SPKR_SHIFT (3U) 1275 #define WM8960_POWER2_SPKR_SET(x) (((uint16_t)(x) << WM8960_POWER2_SPKR_SHIFT) & WM8960_POWER2_SPKR_MASK) 1276 #define WM8960_POWER2_SPKR_GET(x) (((uint16_t)(x) & WM8960_POWER2_SPKR_MASK) >> WM8960_POWER2_SPKR_SHIFT) 1277 1278 /* 1279 * OUT3 (RW) 1280 * 1281 * OUT3 Output Buffer 1282 * 0 = Power down 1283 * 1 = Power up 1284 */ 1285 #define WM8960_POWER2_OUT3_MASK (0x2U) 1286 #define WM8960_POWER2_OUT3_SHIFT (1U) 1287 #define WM8960_POWER2_OUT3_SET(x) (((uint16_t)(x) << WM8960_POWER2_OUT3_SHIFT) & WM8960_POWER2_OUT3_MASK) 1288 #define WM8960_POWER2_OUT3_GET(x) (((uint16_t)(x) & WM8960_POWER2_OUT3_MASK) >> WM8960_POWER2_OUT3_SHIFT) 1289 1290 /* 1291 * PLL_EN (RW) 1292 * 1293 * PLL Enable 1294 * 0 = Power down 1295 * 1 = Power up 1296 */ 1297 #define WM8960_POWER2_PLL_EN_MASK (0x1U) 1298 #define WM8960_POWER2_PLL_EN_SHIFT (0U) 1299 #define WM8960_POWER2_PLL_EN_SET(x) (((uint16_t)(x) << WM8960_POWER2_PLL_EN_SHIFT) & WM8960_POWER2_PLL_EN_MASK) 1300 #define WM8960_POWER2_PLL_EN_GET(x) (((uint16_t)(x) & WM8960_POWER2_PLL_EN_MASK) >> WM8960_POWER2_PLL_EN_SHIFT) 1301 1302 /* Bitfield definition for register: ADDCTL3 */ 1303 /* 1304 * VROI (RW) 1305 * 1306 * VREF to Analogue Output Resistance (Disabled 1307 * Outputs) 1308 * 0 = 500 VMID to output 1309 * 1 = 20k VMID to output 1310 */ 1311 #define WM8960_ADDCTL3_VROI_MASK (0x40U) 1312 #define WM8960_ADDCTL3_VROI_SHIFT (6U) 1313 #define WM8960_ADDCTL3_VROI_SET(x) (((uint16_t)(x) << WM8960_ADDCTL3_VROI_SHIFT) & WM8960_ADDCTL3_VROI_MASK) 1314 #define WM8960_ADDCTL3_VROI_GET(x) (((uint16_t)(x) & WM8960_ADDCTL3_VROI_MASK) >> WM8960_ADDCTL3_VROI_SHIFT) 1315 1316 /* 1317 * OUT3CAP (RW) 1318 * 1319 * Capless Mode Headphone Switch Enable 1320 * 0 = OUT3 unaffected by jack detect events 1321 * 1 = OUT3 enabled and disabled together with 1322 * HP_L and HP_R in response to jack detect 1323 * events 1324 */ 1325 #define WM8960_ADDCTL3_OUT3CAP_MASK (0x8U) 1326 #define WM8960_ADDCTL3_OUT3CAP_SHIFT (3U) 1327 #define WM8960_ADDCTL3_OUT3CAP_SET(x) (((uint16_t)(x) << WM8960_ADDCTL3_OUT3CAP_SHIFT) & WM8960_ADDCTL3_OUT3CAP_MASK) 1328 #define WM8960_ADDCTL3_OUT3CAP_GET(x) (((uint16_t)(x) & WM8960_ADDCTL3_OUT3CAP_MASK) >> WM8960_ADDCTL3_OUT3CAP_SHIFT) 1329 1330 /* 1331 * ADC_ALC_SR (RW) 1332 * 1333 * ALC Sample Rate 1334 * 000 = 44.1k / 48k 1335 * 001 = 32k 1336 * 010 = 22.05k / 24k 1337 * 011 = 16k 1338 * 100 = 11.25k / 12k 1339 * 101 = 8k 1340 * 110 and 111 = Reserved 1341 */ 1342 #define WM8960_ADDCTL3_ADC_ALC_SR_MASK (0x7U) 1343 #define WM8960_ADDCTL3_ADC_ALC_SR_SHIFT (0U) 1344 #define WM8960_ADDCTL3_ADC_ALC_SR_SET(x) (((uint16_t)(x) << WM8960_ADDCTL3_ADC_ALC_SR_SHIFT) & WM8960_ADDCTL3_ADC_ALC_SR_MASK) 1345 #define WM8960_ADDCTL3_ADC_ALC_SR_GET(x) (((uint16_t)(x) & WM8960_ADDCTL3_ADC_ALC_SR_MASK) >> WM8960_ADDCTL3_ADC_ALC_SR_SHIFT) 1346 1347 /* Bitfield definition for register: APOP1 */ 1348 /* 1349 * POBCTRL (RW) 1350 * 1351 * Selects the bias current source for output 1352 * amplifiers and VMID buffer 1353 * 0 = VMID / R bias 1354 * 1 = VGS / R bias 1355 */ 1356 #define WM8960_APOP1_POBCTRL_MASK (0x80U) 1357 #define WM8960_APOP1_POBCTRL_SHIFT (7U) 1358 #define WM8960_APOP1_POBCTRL_SET(x) (((uint16_t)(x) << WM8960_APOP1_POBCTRL_SHIFT) & WM8960_APOP1_POBCTRL_MASK) 1359 #define WM8960_APOP1_POBCTRL_GET(x) (((uint16_t)(x) & WM8960_APOP1_POBCTRL_MASK) >> WM8960_APOP1_POBCTRL_SHIFT) 1360 1361 /* 1362 * BUFDCOPEN (RW) 1363 * 1364 * Enables the VGS / R current generator 1365 * 0 = Disabled 1366 * 1 = Enabled 1367 */ 1368 #define WM8960_APOP1_BUFDCOPEN_MASK (0x10U) 1369 #define WM8960_APOP1_BUFDCOPEN_SHIFT (4U) 1370 #define WM8960_APOP1_BUFDCOPEN_SET(x) (((uint16_t)(x) << WM8960_APOP1_BUFDCOPEN_SHIFT) & WM8960_APOP1_BUFDCOPEN_MASK) 1371 #define WM8960_APOP1_BUFDCOPEN_GET(x) (((uint16_t)(x) & WM8960_APOP1_BUFDCOPEN_MASK) >> WM8960_APOP1_BUFDCOPEN_SHIFT) 1372 1373 /* 1374 * BUFIOEN (RW) 1375 * 1376 * Enables the VGS / R current generator and the 1377 * analogue input and output bias 1378 * 0 = Disabled 1379 * 1 = Enabled 1380 */ 1381 #define WM8960_APOP1_BUFIOEN_MASK (0x8U) 1382 #define WM8960_APOP1_BUFIOEN_SHIFT (3U) 1383 #define WM8960_APOP1_BUFIOEN_SET(x) (((uint16_t)(x) << WM8960_APOP1_BUFIOEN_SHIFT) & WM8960_APOP1_BUFIOEN_MASK) 1384 #define WM8960_APOP1_BUFIOEN_GET(x) (((uint16_t)(x) & WM8960_APOP1_BUFIOEN_MASK) >> WM8960_APOP1_BUFIOEN_SHIFT) 1385 1386 /* 1387 * SOFT_ST (RW) 1388 * 1389 * Enables VMID soft start 1390 * 0 = Disabled 1391 * 1 = Enabled 1392 */ 1393 #define WM8960_APOP1_SOFT_ST_MASK (0x4U) 1394 #define WM8960_APOP1_SOFT_ST_SHIFT (2U) 1395 #define WM8960_APOP1_SOFT_ST_SET(x) (((uint16_t)(x) << WM8960_APOP1_SOFT_ST_SHIFT) & WM8960_APOP1_SOFT_ST_MASK) 1396 #define WM8960_APOP1_SOFT_ST_GET(x) (((uint16_t)(x) & WM8960_APOP1_SOFT_ST_MASK) >> WM8960_APOP1_SOFT_ST_SHIFT) 1397 1398 /* 1399 * HPSTBY (RW) 1400 * 1401 * Headphone Amplifier Standby 1402 * 0 = Standby mode disabled (Normal operation) 1403 * 1 = Standby mode enabled 1404 */ 1405 #define WM8960_APOP1_HPSTBY_MASK (0x1U) 1406 #define WM8960_APOP1_HPSTBY_SHIFT (0U) 1407 #define WM8960_APOP1_HPSTBY_SET(x) (((uint16_t)(x) << WM8960_APOP1_HPSTBY_SHIFT) & WM8960_APOP1_HPSTBY_MASK) 1408 #define WM8960_APOP1_HPSTBY_GET(x) (((uint16_t)(x) & WM8960_APOP1_HPSTBY_MASK) >> WM8960_APOP1_HPSTBY_SHIFT) 1409 1410 /* Bitfield definition for register: APOP2 */ 1411 /* 1412 * DISOP (RW) 1413 * 1414 * Discharges the DC-blocking headphone 1415 * capacitors on HP_L and HP_R 1416 * 0 = Disabled 1417 * 1 = Enabled 1418 */ 1419 #define WM8960_APOP2_DISOP_MASK (0x40U) 1420 #define WM8960_APOP2_DISOP_SHIFT (6U) 1421 #define WM8960_APOP2_DISOP_SET(x) (((uint16_t)(x) << WM8960_APOP2_DISOP_SHIFT) & WM8960_APOP2_DISOP_MASK) 1422 #define WM8960_APOP2_DISOP_GET(x) (((uint16_t)(x) & WM8960_APOP2_DISOP_MASK) >> WM8960_APOP2_DISOP_SHIFT) 1423 1424 /* 1425 * DRES (RW) 1426 * 1427 * DRES determines the value of the resistors used 1428 * to discharge the DC-blocking headphone 1429 * capacitors when DISOP=1 1430 * DRES[1:0] Resistance (Ohms) 1431 * 0 0 400 1432 * 0 1 200 1433 * 1 0 600 1434 * 1 1 150 1435 */ 1436 #define WM8960_APOP2_DRES_MASK (0x30U) 1437 #define WM8960_APOP2_DRES_SHIFT (4U) 1438 #define WM8960_APOP2_DRES_SET(x) (((uint16_t)(x) << WM8960_APOP2_DRES_SHIFT) & WM8960_APOP2_DRES_MASK) 1439 #define WM8960_APOP2_DRES_GET(x) (((uint16_t)(x) & WM8960_APOP2_DRES_MASK) >> WM8960_APOP2_DRES_SHIFT) 1440 1441 /* Bitfield definition for register: LINPATH */ 1442 /* 1443 * LMN1 (RW) 1444 * 1445 * Connect LINPUT1 to inverting input of Left Input 1446 * PGA 1447 * 0 = LINPUT1 not connected to PGA 1448 * 1 = LINPUT1 connected to PGA 1449 */ 1450 #define WM8960_LINPATH_LMN1_MASK (0x100U) 1451 #define WM8960_LINPATH_LMN1_SHIFT (8U) 1452 #define WM8960_LINPATH_LMN1_SET(x) (((uint16_t)(x) << WM8960_LINPATH_LMN1_SHIFT) & WM8960_LINPATH_LMN1_MASK) 1453 #define WM8960_LINPATH_LMN1_GET(x) (((uint16_t)(x) & WM8960_LINPATH_LMN1_MASK) >> WM8960_LINPATH_LMN1_SHIFT) 1454 1455 /* 1456 * LMP3 (RW) 1457 * 1458 * Connect LINPUT3 to non-inverting input of Left 1459 * Input PGA 1460 * 0 = LINPUT3 not connected to PGA 1461 * 1 = LINPUT3 connected to PGA (Constant input 1462 * impedance) 1463 */ 1464 #define WM8960_LINPATH_LMP3_MASK (0x80U) 1465 #define WM8960_LINPATH_LMP3_SHIFT (7U) 1466 #define WM8960_LINPATH_LMP3_SET(x) (((uint16_t)(x) << WM8960_LINPATH_LMP3_SHIFT) & WM8960_LINPATH_LMP3_MASK) 1467 #define WM8960_LINPATH_LMP3_GET(x) (((uint16_t)(x) & WM8960_LINPATH_LMP3_MASK) >> WM8960_LINPATH_LMP3_SHIFT) 1468 1469 /* 1470 * LMP2 (RW) 1471 * 1472 * Connect LINPUT2 to non-inverting input of Left 1473 * Input PGA 1474 * 0 = LINPUT2 not connected to PGA 1475 * 1 = LINPUT2 connected to PGA (Constant input impedance) 1476 */ 1477 #define WM8960_LINPATH_LMP2_MASK (0x40U) 1478 #define WM8960_LINPATH_LMP2_SHIFT (6U) 1479 #define WM8960_LINPATH_LMP2_SET(x) (((uint16_t)(x) << WM8960_LINPATH_LMP2_SHIFT) & WM8960_LINPATH_LMP2_MASK) 1480 #define WM8960_LINPATH_LMP2_GET(x) (((uint16_t)(x) & WM8960_LINPATH_LMP2_MASK) >> WM8960_LINPATH_LMP2_SHIFT) 1481 1482 /* 1483 * LMICBOOST (RW) 1484 * 1485 * Left Channel Input PGA Boost Gain 1486 * 00 = +0dB 1487 * 01 = +13dB 1488 * 10 = +20dB 1489 * 11 = +29dB 1490 */ 1491 #define WM8960_LINPATH_LMICBOOST_MASK (0x30U) 1492 #define WM8960_LINPATH_LMICBOOST_SHIFT (4U) 1493 #define WM8960_LINPATH_LMICBOOST_SET(x) (((uint16_t)(x) << WM8960_LINPATH_LMICBOOST_SHIFT) & WM8960_LINPATH_LMICBOOST_MASK) 1494 #define WM8960_LINPATH_LMICBOOST_GET(x) (((uint16_t)(x) & WM8960_LINPATH_LMICBOOST_MASK) >> WM8960_LINPATH_LMICBOOST_SHIFT) 1495 1496 /* 1497 * LMIC2B (RW) 1498 * 1499 * Connect Left Input PGA to Left Input Boost Mixer 1500 * 0 = Not connected 1501 * 1 = Connected 1502 */ 1503 #define WM8960_LINPATH_LMIC2B_MASK (0x8U) 1504 #define WM8960_LINPATH_LMIC2B_SHIFT (3U) 1505 #define WM8960_LINPATH_LMIC2B_SET(x) (((uint16_t)(x) << WM8960_LINPATH_LMIC2B_SHIFT) & WM8960_LINPATH_LMIC2B_MASK) 1506 #define WM8960_LINPATH_LMIC2B_GET(x) (((uint16_t)(x) & WM8960_LINPATH_LMIC2B_MASK) >> WM8960_LINPATH_LMIC2B_SHIFT) 1507 1508 /* Bitfield definition for register: RINPATH */ 1509 /* 1510 * RMN1 (RW) 1511 * 1512 * Connect RINPUT1 to inverting input of Right 1513 * Input PGA 1514 * 0 = RINPUT1 not connected to PGA 1515 * 1 = RINPUT1 connected to PGA 1516 */ 1517 #define WM8960_RINPATH_RMN1_MASK (0x100U) 1518 #define WM8960_RINPATH_RMN1_SHIFT (8U) 1519 #define WM8960_RINPATH_RMN1_SET(x) (((uint16_t)(x) << WM8960_RINPATH_RMN1_SHIFT) & WM8960_RINPATH_RMN1_MASK) 1520 #define WM8960_RINPATH_RMN1_GET(x) (((uint16_t)(x) & WM8960_RINPATH_RMN1_MASK) >> WM8960_RINPATH_RMN1_SHIFT) 1521 1522 /* 1523 * RMP3 (RW) 1524 * 1525 * Connect RINPUT3 to non-inverting input of Right 1526 * Input PGA 1527 * 0 = RINPUT3 not connected to PGA 1528 * 1 = RINPUT3 connected to PGA (Constant input impedance) 1529 */ 1530 #define WM8960_RINPATH_RMP3_MASK (0x80U) 1531 #define WM8960_RINPATH_RMP3_SHIFT (7U) 1532 #define WM8960_RINPATH_RMP3_SET(x) (((uint16_t)(x) << WM8960_RINPATH_RMP3_SHIFT) & WM8960_RINPATH_RMP3_MASK) 1533 #define WM8960_RINPATH_RMP3_GET(x) (((uint16_t)(x) & WM8960_RINPATH_RMP3_MASK) >> WM8960_RINPATH_RMP3_SHIFT) 1534 1535 /* 1536 * RMP2 (RW) 1537 * 1538 * Connect RINPUT2 to non-inverting input of Right 1539 * Input PGA 1540 * 0 = RINPUT2 not connected to PGA 1541 * 1 = RINPUT2 connected to PGA (Constant input 1542 * impedance) 1543 */ 1544 #define WM8960_RINPATH_RMP2_MASK (0x40U) 1545 #define WM8960_RINPATH_RMP2_SHIFT (6U) 1546 #define WM8960_RINPATH_RMP2_SET(x) (((uint16_t)(x) << WM8960_RINPATH_RMP2_SHIFT) & WM8960_RINPATH_RMP2_MASK) 1547 #define WM8960_RINPATH_RMP2_GET(x) (((uint16_t)(x) & WM8960_RINPATH_RMP2_MASK) >> WM8960_RINPATH_RMP2_SHIFT) 1548 1549 /* 1550 * RMICBOOST (RW) 1551 * 1552 * Right Channel Input PGA Boost Gain 1553 * 00 = +0dB 1554 * 01 = +13dB 1555 * 10 = +20dB 1556 * 11 = +29dB 1557 */ 1558 #define WM8960_RINPATH_RMICBOOST_MASK (0x30U) 1559 #define WM8960_RINPATH_RMICBOOST_SHIFT (4U) 1560 #define WM8960_RINPATH_RMICBOOST_SET(x) (((uint16_t)(x) << WM8960_RINPATH_RMICBOOST_SHIFT) & WM8960_RINPATH_RMICBOOST_MASK) 1561 #define WM8960_RINPATH_RMICBOOST_GET(x) (((uint16_t)(x) & WM8960_RINPATH_RMICBOOST_MASK) >> WM8960_RINPATH_RMICBOOST_SHIFT) 1562 1563 /* 1564 * RMIC2B (RW) 1565 * 1566 * Connect Right Input PGA to Right Input Boost 1567 * Mixer 1568 * 0 = Not connected 1569 * 1 = Connected 1570 */ 1571 #define WM8960_RINPATH_RMIC2B_MASK (0x8U) 1572 #define WM8960_RINPATH_RMIC2B_SHIFT (3U) 1573 #define WM8960_RINPATH_RMIC2B_SET(x) (((uint16_t)(x) << WM8960_RINPATH_RMIC2B_SHIFT) & WM8960_RINPATH_RMIC2B_MASK) 1574 #define WM8960_RINPATH_RMIC2B_GET(x) (((uint16_t)(x) & WM8960_RINPATH_RMIC2B_MASK) >> WM8960_RINPATH_RMIC2B_SHIFT) 1575 1576 /* Bitfield definition for register: LOUTMIX */ 1577 /* 1578 * LD2LO (RW) 1579 * 1580 * Left DAC to Left Output Mixer 1581 * 0 = Disable (Mute) 1582 * 1 = Enable Path 1583 */ 1584 #define WM8960_LOUTMIX_LD2LO_MASK (0x100U) 1585 #define WM8960_LOUTMIX_LD2LO_SHIFT (8U) 1586 #define WM8960_LOUTMIX_LD2LO_SET(x) (((uint16_t)(x) << WM8960_LOUTMIX_LD2LO_SHIFT) & WM8960_LOUTMIX_LD2LO_MASK) 1587 #define WM8960_LOUTMIX_LD2LO_GET(x) (((uint16_t)(x) & WM8960_LOUTMIX_LD2LO_MASK) >> WM8960_LOUTMIX_LD2LO_SHIFT) 1588 1589 /* 1590 * LI2LO (RW) 1591 * 1592 * LINPUT3 to Left Output Mixer 1593 * 0 = Disable (Mute) 1594 * 1 = Enable Path 1595 */ 1596 #define WM8960_LOUTMIX_LI2LO_MASK (0x80U) 1597 #define WM8960_LOUTMIX_LI2LO_SHIFT (7U) 1598 #define WM8960_LOUTMIX_LI2LO_SET(x) (((uint16_t)(x) << WM8960_LOUTMIX_LI2LO_SHIFT) & WM8960_LOUTMIX_LI2LO_MASK) 1599 #define WM8960_LOUTMIX_LI2LO_GET(x) (((uint16_t)(x) & WM8960_LOUTMIX_LI2LO_MASK) >> WM8960_LOUTMIX_LI2LO_SHIFT) 1600 1601 /* 1602 * LI2LOVOL (RW) 1603 * 1604 * LINPUT3 to Left Output Mixer Volume 1605 * 000 = 0dB 1606 * ...(3dB steps) 1607 * 111 = -21dB 1608 */ 1609 #define WM8960_LOUTMIX_LI2LOVOL_MASK (0x70U) 1610 #define WM8960_LOUTMIX_LI2LOVOL_SHIFT (4U) 1611 #define WM8960_LOUTMIX_LI2LOVOL_SET(x) (((uint16_t)(x) << WM8960_LOUTMIX_LI2LOVOL_SHIFT) & WM8960_LOUTMIX_LI2LOVOL_MASK) 1612 #define WM8960_LOUTMIX_LI2LOVOL_GET(x) (((uint16_t)(x) & WM8960_LOUTMIX_LI2LOVOL_MASK) >> WM8960_LOUTMIX_LI2LOVOL_SHIFT) 1613 1614 /* Bitfield definition for register: ROUTMIX */ 1615 /* 1616 * RD2RO (RW) 1617 * 1618 * Right DAC to Right Output Mixer 1619 * 0 = Disable (Mute) 1620 * 1 = Enable Path 1621 */ 1622 #define WM8960_ROUTMIX_RD2RO_MASK (0x100U) 1623 #define WM8960_ROUTMIX_RD2RO_SHIFT (8U) 1624 #define WM8960_ROUTMIX_RD2RO_SET(x) (((uint16_t)(x) << WM8960_ROUTMIX_RD2RO_SHIFT) & WM8960_ROUTMIX_RD2RO_MASK) 1625 #define WM8960_ROUTMIX_RD2RO_GET(x) (((uint16_t)(x) & WM8960_ROUTMIX_RD2RO_MASK) >> WM8960_ROUTMIX_RD2RO_SHIFT) 1626 1627 /* 1628 * RI2RO (RW) 1629 * 1630 * RINPUT3 to Right Output Mixer 1631 * 0 = Disable (Mute) 1632 * 1 = Enable Path 1633 */ 1634 #define WM8960_ROUTMIX_RI2RO_MASK (0x80U) 1635 #define WM8960_ROUTMIX_RI2RO_SHIFT (7U) 1636 #define WM8960_ROUTMIX_RI2RO_SET(x) (((uint16_t)(x) << WM8960_ROUTMIX_RI2RO_SHIFT) & WM8960_ROUTMIX_RI2RO_MASK) 1637 #define WM8960_ROUTMIX_RI2RO_GET(x) (((uint16_t)(x) & WM8960_ROUTMIX_RI2RO_MASK) >> WM8960_ROUTMIX_RI2RO_SHIFT) 1638 1639 /* 1640 * RI2ROVOL (RW) 1641 * 1642 * RINPUT3 to Right Output Mixer Volume 1643 * 000 = 0dB 1644 * ...(3dB steps) 1645 * 111 = -21dB 1646 */ 1647 #define WM8960_ROUTMIX_RI2ROVOL_MASK (0x70U) 1648 #define WM8960_ROUTMIX_RI2ROVOL_SHIFT (4U) 1649 #define WM8960_ROUTMIX_RI2ROVOL_SET(x) (((uint16_t)(x) << WM8960_ROUTMIX_RI2ROVOL_SHIFT) & WM8960_ROUTMIX_RI2ROVOL_MASK) 1650 #define WM8960_ROUTMIX_RI2ROVOL_GET(x) (((uint16_t)(x) & WM8960_ROUTMIX_RI2ROVOL_MASK) >> WM8960_ROUTMIX_RI2ROVOL_SHIFT) 1651 1652 /* Bitfield definition for register: MONOMIX1 */ 1653 /* 1654 * L2MO (RW) 1655 * 1656 * Left Output Mixer to Mono Output Mixer Control 1657 * 0 = Left channel mix disabled 1658 * 1 = Left channel mix enabled 1659 */ 1660 #define WM8960_MONOMIX1_L2MO_MASK (0x80U) 1661 #define WM8960_MONOMIX1_L2MO_SHIFT (7U) 1662 #define WM8960_MONOMIX1_L2MO_SET(x) (((uint16_t)(x) << WM8960_MONOMIX1_L2MO_SHIFT) & WM8960_MONOMIX1_L2MO_MASK) 1663 #define WM8960_MONOMIX1_L2MO_GET(x) (((uint16_t)(x) & WM8960_MONOMIX1_L2MO_MASK) >> WM8960_MONOMIX1_L2MO_SHIFT) 1664 1665 /* Bitfield definition for register: MONOMIX2 */ 1666 /* 1667 * R2MO (RW) 1668 * 1669 * Right Output Mixer to Mono Output Mixer Control 1670 * 0 = Right channel mix disabled 1671 * 1 = Right channel mix enabled 1672 */ 1673 #define WM8960_MONOMIX2_R2MO_MASK (0x80U) 1674 #define WM8960_MONOMIX2_R2MO_SHIFT (7U) 1675 #define WM8960_MONOMIX2_R2MO_SET(x) (((uint16_t)(x) << WM8960_MONOMIX2_R2MO_SHIFT) & WM8960_MONOMIX2_R2MO_MASK) 1676 #define WM8960_MONOMIX2_R2MO_GET(x) (((uint16_t)(x) & WM8960_MONOMIX2_R2MO_MASK) >> WM8960_MONOMIX2_R2MO_SHIFT) 1677 1678 /* Bitfield definition for register: LOUT2 */ 1679 /* 1680 * SPKVU (RW) 1681 * 1682 * Speaker Volume Update 1683 * Writing a 1 to this bit will cause left and right speaker volumes to be updated (SPKLVOL and SPKRVOL) 1684 */ 1685 #define WM8960_LOUT2_SPKVU_MASK (0x100U) 1686 #define WM8960_LOUT2_SPKVU_SHIFT (8U) 1687 #define WM8960_LOUT2_SPKVU_SET(x) (((uint16_t)(x) << WM8960_LOUT2_SPKVU_SHIFT) & WM8960_LOUT2_SPKVU_MASK) 1688 #define WM8960_LOUT2_SPKVU_GET(x) (((uint16_t)(x) & WM8960_LOUT2_SPKVU_MASK) >> WM8960_LOUT2_SPKVU_SHIFT) 1689 1690 /* 1691 * SPKLZC (RW) 1692 * 1693 * Left Speaker Zero Cross Enable 1694 * 1 = Change gain on zero cross only 1695 * 0 = Change gain immediately 1696 */ 1697 #define WM8960_LOUT2_SPKLZC_MASK (0x80U) 1698 #define WM8960_LOUT2_SPKLZC_SHIFT (7U) 1699 #define WM8960_LOUT2_SPKLZC_SET(x) (((uint16_t)(x) << WM8960_LOUT2_SPKLZC_SHIFT) & WM8960_LOUT2_SPKLZC_MASK) 1700 #define WM8960_LOUT2_SPKLZC_GET(x) (((uint16_t)(x) & WM8960_LOUT2_SPKLZC_MASK) >> WM8960_LOUT2_SPKLZC_SHIFT) 1701 1702 /* 1703 * SPKLVOL (RW) 1704 * 1705 * SPK_LP/SPK_LN Volume 1706 * 1111111 = +6dB 1707 * … 1dB steps down to 1708 * 0110000 = -73dB 1709 * 0101111 to 0000000 = Analogue MUTE 1710 */ 1711 #define WM8960_LOUT2_SPKLVOL_MASK (0x7FU) 1712 #define WM8960_LOUT2_SPKLVOL_SHIFT (0U) 1713 #define WM8960_LOUT2_SPKLVOL_SET(x) (((uint16_t)(x) << WM8960_LOUT2_SPKLVOL_SHIFT) & WM8960_LOUT2_SPKLVOL_MASK) 1714 #define WM8960_LOUT2_SPKLVOL_GET(x) (((uint16_t)(x) & WM8960_LOUT2_SPKLVOL_MASK) >> WM8960_LOUT2_SPKLVOL_SHIFT) 1715 1716 /* Bitfield definition for register: ROUT2 */ 1717 /* 1718 * SPKVU (RW) 1719 * 1720 * Speaker Volume Update 1721 * Writing a 1 to this bit will cause left and right 1722 * speaker volumes to be updated (SPKLVOL and SPKRVOL) 1723 */ 1724 #define WM8960_ROUT2_SPKVU_MASK (0x100U) 1725 #define WM8960_ROUT2_SPKVU_SHIFT (8U) 1726 #define WM8960_ROUT2_SPKVU_SET(x) (((uint16_t)(x) << WM8960_ROUT2_SPKVU_SHIFT) & WM8960_ROUT2_SPKVU_MASK) 1727 #define WM8960_ROUT2_SPKVU_GET(x) (((uint16_t)(x) & WM8960_ROUT2_SPKVU_MASK) >> WM8960_ROUT2_SPKVU_SHIFT) 1728 1729 /* 1730 * SPKRZC (RW) 1731 * 1732 * Right Speaker Zero Cross Enable 1733 * 1 = Change gain on zero cross only 1734 * 0 = Change gain immediately 1735 */ 1736 #define WM8960_ROUT2_SPKRZC_MASK (0x80U) 1737 #define WM8960_ROUT2_SPKRZC_SHIFT (7U) 1738 #define WM8960_ROUT2_SPKRZC_SET(x) (((uint16_t)(x) << WM8960_ROUT2_SPKRZC_SHIFT) & WM8960_ROUT2_SPKRZC_MASK) 1739 #define WM8960_ROUT2_SPKRZC_GET(x) (((uint16_t)(x) & WM8960_ROUT2_SPKRZC_MASK) >> WM8960_ROUT2_SPKRZC_SHIFT) 1740 1741 /* 1742 * SPKRVOL (RW) 1743 * 1744 * SPK_RP/SPK_RN Volume 1745 * 1111111 = +6dB 1746 * … 1dB steps down to 1747 * 0110000 = -73dB 1748 * 0101111 to 0000000 = Analogue MUTE 1749 */ 1750 #define WM8960_ROUT2_SPKRVOL_MASK (0x7FU) 1751 #define WM8960_ROUT2_SPKRVOL_SHIFT (0U) 1752 #define WM8960_ROUT2_SPKRVOL_SET(x) (((uint16_t)(x) << WM8960_ROUT2_SPKRVOL_SHIFT) & WM8960_ROUT2_SPKRVOL_MASK) 1753 #define WM8960_ROUT2_SPKRVOL_GET(x) (((uint16_t)(x) & WM8960_ROUT2_SPKRVOL_MASK) >> WM8960_ROUT2_SPKRVOL_SHIFT) 1754 1755 /* Bitfield definition for register: MONO */ 1756 /* 1757 * MOUTVOL (RW) 1758 * 1759 * Mono Output Mixer Volume Control 1760 * 0 = 0dB 1761 * 1 = -6dB 1762 */ 1763 #define WM8960_MONO_MOUTVOL_MASK (0x40U) 1764 #define WM8960_MONO_MOUTVOL_SHIFT (6U) 1765 #define WM8960_MONO_MOUTVOL_SET(x) (((uint16_t)(x) << WM8960_MONO_MOUTVOL_SHIFT) & WM8960_MONO_MOUTVOL_MASK) 1766 #define WM8960_MONO_MOUTVOL_GET(x) (((uint16_t)(x) & WM8960_MONO_MOUTVOL_MASK) >> WM8960_MONO_MOUTVOL_SHIFT) 1767 1768 /* Bitfield definition for register: INBMIX1 */ 1769 /* 1770 * LIN3BOOST (RW) 1771 * 1772 * LINPUT3 to Boost Mixer Gain 1773 * 000 = Mute 1774 * 001 = -12dB 1775 * ...3dB steps up to 1776 * 111 = +6dB 1777 */ 1778 #define WM8960_INBMIX1_LIN3BOOST_MASK (0x70U) 1779 #define WM8960_INBMIX1_LIN3BOOST_SHIFT (4U) 1780 #define WM8960_INBMIX1_LIN3BOOST_SET(x) (((uint16_t)(x) << WM8960_INBMIX1_LIN3BOOST_SHIFT) & WM8960_INBMIX1_LIN3BOOST_MASK) 1781 #define WM8960_INBMIX1_LIN3BOOST_GET(x) (((uint16_t)(x) & WM8960_INBMIX1_LIN3BOOST_MASK) >> WM8960_INBMIX1_LIN3BOOST_SHIFT) 1782 1783 /* 1784 * LIN2BOOST (RW) 1785 * 1786 * LINPUT2 to Boost Mixer Gain 1787 * 000 = Mute 1788 * 001 = -12dB 1789 * ...3dB steps up to 1790 * 111 = +6dB 1791 */ 1792 #define WM8960_INBMIX1_LIN2BOOST_MASK (0xEU) 1793 #define WM8960_INBMIX1_LIN2BOOST_SHIFT (1U) 1794 #define WM8960_INBMIX1_LIN2BOOST_SET(x) (((uint16_t)(x) << WM8960_INBMIX1_LIN2BOOST_SHIFT) & WM8960_INBMIX1_LIN2BOOST_MASK) 1795 #define WM8960_INBMIX1_LIN2BOOST_GET(x) (((uint16_t)(x) & WM8960_INBMIX1_LIN2BOOST_MASK) >> WM8960_INBMIX1_LIN2BOOST_SHIFT) 1796 1797 /* Bitfield definition for register: INBMIX2 */ 1798 /* 1799 * RIN3BOOST (RW) 1800 * 1801 * RINPUT3 to Boost Mixer Gain 1802 * 000 = Mute 1803 * 001 = -12dB 1804 * ...3dB steps up to 1805 * 111 = +6dB 1806 */ 1807 #define WM8960_INBMIX2_RIN3BOOST_MASK (0x70U) 1808 #define WM8960_INBMIX2_RIN3BOOST_SHIFT (4U) 1809 #define WM8960_INBMIX2_RIN3BOOST_SET(x) (((uint16_t)(x) << WM8960_INBMIX2_RIN3BOOST_SHIFT) & WM8960_INBMIX2_RIN3BOOST_MASK) 1810 #define WM8960_INBMIX2_RIN3BOOST_GET(x) (((uint16_t)(x) & WM8960_INBMIX2_RIN3BOOST_MASK) >> WM8960_INBMIX2_RIN3BOOST_SHIFT) 1811 1812 /* 1813 * RIN2BOOST (RW) 1814 * 1815 * RINPUT2 to Boost Mixer Gain 1816 * 000 = Mute 1817 * 001 = -12dB 1818 * ...3dB steps up to 1819 * 111 = +6dB 1820 */ 1821 #define WM8960_INBMIX2_RIN2BOOST_MASK (0xEU) 1822 #define WM8960_INBMIX2_RIN2BOOST_SHIFT (1U) 1823 #define WM8960_INBMIX2_RIN2BOOST_SET(x) (((uint16_t)(x) << WM8960_INBMIX2_RIN2BOOST_SHIFT) & WM8960_INBMIX2_RIN2BOOST_MASK) 1824 #define WM8960_INBMIX2_RIN2BOOST_GET(x) (((uint16_t)(x) & WM8960_INBMIX2_RIN2BOOST_MASK) >> WM8960_INBMIX2_RIN2BOOST_SHIFT) 1825 1826 /* Bitfield definition for register: BYPASS1 */ 1827 /* 1828 * LB2LO (RW) 1829 * 1830 * Left Input Boost Mixer to Left Output Mixer 1831 * 0 = Disable (Mute) 1832 * 1 = Enable Path 1833 */ 1834 #define WM8960_BYPASS1_LB2LO_MASK (0x80U) 1835 #define WM8960_BYPASS1_LB2LO_SHIFT (7U) 1836 #define WM8960_BYPASS1_LB2LO_SET(x) (((uint16_t)(x) << WM8960_BYPASS1_LB2LO_SHIFT) & WM8960_BYPASS1_LB2LO_MASK) 1837 #define WM8960_BYPASS1_LB2LO_GET(x) (((uint16_t)(x) & WM8960_BYPASS1_LB2LO_MASK) >> WM8960_BYPASS1_LB2LO_SHIFT) 1838 1839 /* 1840 * LB2LOVOL (RW) 1841 * 1842 * Left Input Boost Mixer to Left Output Mixer 1843 * Volume 1844 * 000 = 0dB 1845 * ...(3dB steps) 1846 * 111 = -21dB 1847 */ 1848 #define WM8960_BYPASS1_LB2LOVOL_MASK (0x70U) 1849 #define WM8960_BYPASS1_LB2LOVOL_SHIFT (4U) 1850 #define WM8960_BYPASS1_LB2LOVOL_SET(x) (((uint16_t)(x) << WM8960_BYPASS1_LB2LOVOL_SHIFT) & WM8960_BYPASS1_LB2LOVOL_MASK) 1851 #define WM8960_BYPASS1_LB2LOVOL_GET(x) (((uint16_t)(x) & WM8960_BYPASS1_LB2LOVOL_MASK) >> WM8960_BYPASS1_LB2LOVOL_SHIFT) 1852 1853 /* Bitfield definition for register: BYPASS2 */ 1854 /* 1855 * RB2RO (RW) 1856 * 1857 * Right Input Boost Mixer to Right Output Mixer 1858 * 0 = Disable (Mute) 1859 * 1 = Enable Path 1860 */ 1861 #define WM8960_BYPASS2_RB2RO_MASK (0x80U) 1862 #define WM8960_BYPASS2_RB2RO_SHIFT (7U) 1863 #define WM8960_BYPASS2_RB2RO_SET(x) (((uint16_t)(x) << WM8960_BYPASS2_RB2RO_SHIFT) & WM8960_BYPASS2_RB2RO_MASK) 1864 #define WM8960_BYPASS2_RB2RO_GET(x) (((uint16_t)(x) & WM8960_BYPASS2_RB2RO_MASK) >> WM8960_BYPASS2_RB2RO_SHIFT) 1865 1866 /* 1867 * RB2ROVOL (RW) 1868 * 1869 * Right Input Boost Mixer to Right Output Mixer 1870 * Volume 1871 * 000 = 0dB 1872 * ...(3dB steps) 1873 * 111 = -21dB 1874 */ 1875 #define WM8960_BYPASS2_RB2ROVOL_MASK (0x70U) 1876 #define WM8960_BYPASS2_RB2ROVOL_SHIFT (4U) 1877 #define WM8960_BYPASS2_RB2ROVOL_SET(x) (((uint16_t)(x) << WM8960_BYPASS2_RB2ROVOL_SHIFT) & WM8960_BYPASS2_RB2ROVOL_MASK) 1878 #define WM8960_BYPASS2_RB2ROVOL_GET(x) (((uint16_t)(x) & WM8960_BYPASS2_RB2ROVOL_MASK) >> WM8960_BYPASS2_RB2ROVOL_SHIFT) 1879 1880 /* Bitfield definition for register: POWER3 */ 1881 /* 1882 * LMIC (RW) 1883 * 1884 * Left Channel Input PGA Enable 1885 * 0 = PGA disabled 1886 * 1 = PGA enabled (if AINL = 1) 1887 */ 1888 #define WM8960_POWER3_LMIC_MASK (0x20U) 1889 #define WM8960_POWER3_LMIC_SHIFT (5U) 1890 #define WM8960_POWER3_LMIC_SET(x) (((uint16_t)(x) << WM8960_POWER3_LMIC_SHIFT) & WM8960_POWER3_LMIC_MASK) 1891 #define WM8960_POWER3_LMIC_GET(x) (((uint16_t)(x) & WM8960_POWER3_LMIC_MASK) >> WM8960_POWER3_LMIC_SHIFT) 1892 1893 /* 1894 * RMIC (RW) 1895 * 1896 * Right Channel Input PGA Enable 1897 * 0 = PGA disabled 1898 * 1 = PGA enabled (if AINR = 1) 1899 */ 1900 #define WM8960_POWER3_RMIC_MASK (0x10U) 1901 #define WM8960_POWER3_RMIC_SHIFT (4U) 1902 #define WM8960_POWER3_RMIC_SET(x) (((uint16_t)(x) << WM8960_POWER3_RMIC_SHIFT) & WM8960_POWER3_RMIC_MASK) 1903 #define WM8960_POWER3_RMIC_GET(x) (((uint16_t)(x) & WM8960_POWER3_RMIC_MASK) >> WM8960_POWER3_RMIC_SHIFT) 1904 1905 /* 1906 * LOMIX (RW) 1907 * 1908 * Left Output Mixer Enable Control 1909 * 0 = Disabled 1910 * 1 = Enabled 1911 */ 1912 #define WM8960_POWER3_LOMIX_MASK (0x8U) 1913 #define WM8960_POWER3_LOMIX_SHIFT (3U) 1914 #define WM8960_POWER3_LOMIX_SET(x) (((uint16_t)(x) << WM8960_POWER3_LOMIX_SHIFT) & WM8960_POWER3_LOMIX_MASK) 1915 #define WM8960_POWER3_LOMIX_GET(x) (((uint16_t)(x) & WM8960_POWER3_LOMIX_MASK) >> WM8960_POWER3_LOMIX_SHIFT) 1916 1917 /* 1918 * ROMIX (RW) 1919 * 1920 * Right Output Mixer Enable Control 1921 * 0 = Disabled 1922 * 1 = Enabled 1923 */ 1924 #define WM8960_POWER3_ROMIX_MASK (0x4U) 1925 #define WM8960_POWER3_ROMIX_SHIFT (2U) 1926 #define WM8960_POWER3_ROMIX_SET(x) (((uint16_t)(x) << WM8960_POWER3_ROMIX_SHIFT) & WM8960_POWER3_ROMIX_MASK) 1927 #define WM8960_POWER3_ROMIX_GET(x) (((uint16_t)(x) & WM8960_POWER3_ROMIX_MASK) >> WM8960_POWER3_ROMIX_SHIFT) 1928 1929 /* Bitfield definition for register: ADDCTL4 */ 1930 /* 1931 * GPIOPOL (RW) 1932 * 1933 * GPIO Polarity Invert 1934 * 0 = Non inverted 1935 * 1 = Inverted 1936 */ 1937 #define WM8960_ADDCTL4_GPIOPOL_MASK (0x80U) 1938 #define WM8960_ADDCTL4_GPIOPOL_SHIFT (7U) 1939 #define WM8960_ADDCTL4_GPIOPOL_SET(x) (((uint16_t)(x) << WM8960_ADDCTL4_GPIOPOL_SHIFT) & WM8960_ADDCTL4_GPIOPOL_MASK) 1940 #define WM8960_ADDCTL4_GPIOPOL_GET(x) (((uint16_t)(x) & WM8960_ADDCTL4_GPIOPOL_MASK) >> WM8960_ADDCTL4_GPIOPOL_SHIFT) 1941 1942 /* 1943 * GPIOSEL (RW) 1944 * 1945 * ADCLRC/GPIO1 GPIO Function Select: 1946 * 000 = Jack detect input 1947 * 001 = Reserved 1948 * 010 = Temperature ok 1949 * 011 = Debounced jack detect output 1950 * 100 = SYSCLK output 1951 * 101 = PLL lock 1952 * 110 = Logic 0 1953 * 111 = Logic 1 1954 */ 1955 #define WM8960_ADDCTL4_GPIOSEL_MASK (0x70U) 1956 #define WM8960_ADDCTL4_GPIOSEL_SHIFT (4U) 1957 #define WM8960_ADDCTL4_GPIOSEL_SET(x) (((uint16_t)(x) << WM8960_ADDCTL4_GPIOSEL_SHIFT) & WM8960_ADDCTL4_GPIOSEL_MASK) 1958 #define WM8960_ADDCTL4_GPIOSEL_GET(x) (((uint16_t)(x) & WM8960_ADDCTL4_GPIOSEL_MASK) >> WM8960_ADDCTL4_GPIOSEL_SHIFT) 1959 1960 /* 1961 * HPSEL (RW) 1962 * 1963 * Headphone Switch Input Select 1964 * 0X = GPIO1 used for jack detect input (Requires 1965 * ADCLRC pin to be configured as a GPIO) 1966 * 10 = JD2 used for jack detect input 1967 * 11 = JD3 used for jack detect input 1968 */ 1969 #define WM8960_ADDCTL4_HPSEL_MASK (0xCU) 1970 #define WM8960_ADDCTL4_HPSEL_SHIFT (2U) 1971 #define WM8960_ADDCTL4_HPSEL_SET(x) (((uint16_t)(x) << WM8960_ADDCTL4_HPSEL_SHIFT) & WM8960_ADDCTL4_HPSEL_MASK) 1972 #define WM8960_ADDCTL4_HPSEL_GET(x) (((uint16_t)(x) & WM8960_ADDCTL4_HPSEL_MASK) >> WM8960_ADDCTL4_HPSEL_SHIFT) 1973 1974 /* 1975 * TSENSEN (RW) 1976 * 1977 * Temperature Sensor Enable 1978 * 0 = Temperature sensor disabled 1979 * 1 = Temperature sensor enabled 1980 */ 1981 #define WM8960_ADDCTL4_TSENSEN_MASK (0x2U) 1982 #define WM8960_ADDCTL4_TSENSEN_SHIFT (1U) 1983 #define WM8960_ADDCTL4_TSENSEN_SET(x) (((uint16_t)(x) << WM8960_ADDCTL4_TSENSEN_SHIFT) & WM8960_ADDCTL4_TSENSEN_MASK) 1984 #define WM8960_ADDCTL4_TSENSEN_GET(x) (((uint16_t)(x) & WM8960_ADDCTL4_TSENSEN_MASK) >> WM8960_ADDCTL4_TSENSEN_SHIFT) 1985 1986 /* 1987 * MBSEL (RW) 1988 * 1989 * Microphone Bias Voltage Control 1990 * 0 = 0.9 * AVDD 1991 * 1 = 0.65 * AVDD 1992 */ 1993 #define WM8960_ADDCTL4_MBSEL_MASK (0x1U) 1994 #define WM8960_ADDCTL4_MBSEL_SHIFT (0U) 1995 #define WM8960_ADDCTL4_MBSEL_SET(x) (((uint16_t)(x) << WM8960_ADDCTL4_MBSEL_SHIFT) & WM8960_ADDCTL4_MBSEL_MASK) 1996 #define WM8960_ADDCTL4_MBSEL_GET(x) (((uint16_t)(x) & WM8960_ADDCTL4_MBSEL_MASK) >> WM8960_ADDCTL4_MBSEL_SHIFT) 1997 1998 /* Bitfield definition for register: CLASSD1 */ 1999 /* 2000 * SPK_OP_EN (RW) 2001 * 2002 * Enable Class D Speaker Outputs 2003 * 00 = Off 2004 * 01 = Left speaker only 2005 * 10 = Right speaker only 2006 * 11 = Left and right speakers enabled 2007 */ 2008 #define WM8960_CLASSD1_SPK_OP_EN_MASK (0xC0U) 2009 #define WM8960_CLASSD1_SPK_OP_EN_SHIFT (6U) 2010 #define WM8960_CLASSD1_SPK_OP_EN_SET(x) (((uint16_t)(x) << WM8960_CLASSD1_SPK_OP_EN_SHIFT) & WM8960_CLASSD1_SPK_OP_EN_MASK) 2011 #define WM8960_CLASSD1_SPK_OP_EN_GET(x) (((uint16_t)(x) & WM8960_CLASSD1_SPK_OP_EN_MASK) >> WM8960_CLASSD1_SPK_OP_EN_SHIFT) 2012 2013 /* Bitfield definition for register: CLASSD3 */ 2014 /* 2015 * DCGAIN (RW) 2016 * 2017 * DC Speaker Boost (Boosts speaker DC output 2018 * level by up to 1.8 x on left and right channels) 2019 * 000 = 1.00x boost (+0dB) 2020 * 001 = 1.27x boost (+2.1dB) 2021 * 010 = 1.40x boost (+2.9dB) 2022 * 011 = 1.52x boost (+3.6dB) 2023 * 100 = 1.67x boost (+4.5dB) 2024 * 101 = 1.8x boost (+5.1dB) 2025 * 110 to 111 = Reserved 2026 */ 2027 #define WM8960_CLASSD3_DCGAIN_MASK (0x38U) 2028 #define WM8960_CLASSD3_DCGAIN_SHIFT (3U) 2029 #define WM8960_CLASSD3_DCGAIN_SET(x) (((uint16_t)(x) << WM8960_CLASSD3_DCGAIN_SHIFT) & WM8960_CLASSD3_DCGAIN_MASK) 2030 #define WM8960_CLASSD3_DCGAIN_GET(x) (((uint16_t)(x) & WM8960_CLASSD3_DCGAIN_MASK) >> WM8960_CLASSD3_DCGAIN_SHIFT) 2031 2032 /* 2033 * ACGAIN (RW) 2034 * 2035 * AC Speaker Boost (Boosts speaker AC output 2036 * signal by up to 1.8 x on left and right channels) 2037 * 000 = 1.00x boost (+0dB) 2038 * 001 = 1.27x boost (+2.1dB) 2039 * 010 = 1.40x boost (+2.9dB) 2040 * 011 = 1.52x boost (+3.6dB) 2041 * 100 = 1.67x boost (+4.5dB) 2042 * 101 = 1.8x boost (+5.1dB) 2043 * 110 to 111 = Reserved 2044 */ 2045 #define WM8960_CLASSD3_ACGAIN_MASK (0x7U) 2046 #define WM8960_CLASSD3_ACGAIN_SHIFT (0U) 2047 #define WM8960_CLASSD3_ACGAIN_SET(x) (((uint16_t)(x) << WM8960_CLASSD3_ACGAIN_SHIFT) & WM8960_CLASSD3_ACGAIN_MASK) 2048 #define WM8960_CLASSD3_ACGAIN_GET(x) (((uint16_t)(x) & WM8960_CLASSD3_ACGAIN_MASK) >> WM8960_CLASSD3_ACGAIN_SHIFT) 2049 2050 /* Bitfield definition for register: PLL1 */ 2051 /* 2052 * OPCLKDIV (RW) 2053 * 2054 * SYSCLK Output to GPIO Clock Division ratio 2055 * 000 = SYSCLK 2056 * 001 = SYSCLK / 2 2057 * 010 = SYSCLK / 3 2058 * 011 = SYSCLK / 4 2059 * 100 = SYSCLK / 5.5 2060 * 101 = SYSCLK / 6 2061 */ 2062 #define WM8960_PLL1_OPCLKDIV_MASK (0x1C0U) 2063 #define WM8960_PLL1_OPCLKDIV_SHIFT (6U) 2064 #define WM8960_PLL1_OPCLKDIV_SET(x) (((uint16_t)(x) << WM8960_PLL1_OPCLKDIV_SHIFT) & WM8960_PLL1_OPCLKDIV_MASK) 2065 #define WM8960_PLL1_OPCLKDIV_GET(x) (((uint16_t)(x) & WM8960_PLL1_OPCLKDIV_MASK) >> WM8960_PLL1_OPCLKDIV_SHIFT) 2066 2067 /* 2068 * SDM (RW) 2069 * 2070 * Enable Integer Mode 2071 * 0 = Integer mode 2072 * 1 = Fractional mode 2073 */ 2074 #define WM8960_PLL1_SDM_MASK (0x20U) 2075 #define WM8960_PLL1_SDM_SHIFT (5U) 2076 #define WM8960_PLL1_SDM_SET(x) (((uint16_t)(x) << WM8960_PLL1_SDM_SHIFT) & WM8960_PLL1_SDM_MASK) 2077 #define WM8960_PLL1_SDM_GET(x) (((uint16_t)(x) & WM8960_PLL1_SDM_MASK) >> WM8960_PLL1_SDM_SHIFT) 2078 2079 /* 2080 * PLLPRESCALE (RW) 2081 * 2082 * Divide MCLK by 2 before input to PLL 2083 * 0 = Divide by 1 2084 * 1 = Divide by 2 2085 */ 2086 #define WM8960_PLL1_PLLPRESCALE_MASK (0x10U) 2087 #define WM8960_PLL1_PLLPRESCALE_SHIFT (4U) 2088 #define WM8960_PLL1_PLLPRESCALE_SET(x) (((uint16_t)(x) << WM8960_PLL1_PLLPRESCALE_SHIFT) & WM8960_PLL1_PLLPRESCALE_MASK) 2089 #define WM8960_PLL1_PLLPRESCALE_GET(x) (((uint16_t)(x) & WM8960_PLL1_PLLPRESCALE_MASK) >> WM8960_PLL1_PLLPRESCALE_SHIFT) 2090 2091 /* 2092 * PLLN (RW) 2093 * 2094 * Integer (N) part of PLL input/output frequency 2095 * ratio. Use values greater than 5 and less than 13 2096 */ 2097 #define WM8960_PLL1_PLLN_MASK (0xFU) 2098 #define WM8960_PLL1_PLLN_SHIFT (0U) 2099 #define WM8960_PLL1_PLLN_SET(x) (((uint16_t)(x) << WM8960_PLL1_PLLN_SHIFT) & WM8960_PLL1_PLLN_MASK) 2100 #define WM8960_PLL1_PLLN_GET(x) (((uint16_t)(x) & WM8960_PLL1_PLLN_MASK) >> WM8960_PLL1_PLLN_SHIFT) 2101 2102 /* Bitfield definition for register: PLL2 */ 2103 /* 2104 * PLLK (RW) 2105 * 2106 * Fractional (K) part of PLL1 input/output 2107 * frequency ratio (treat as one 24-digit binary number). 2108 */ 2109 #define WM8960_PLL2_PLLK_MASK (0xFFU) 2110 #define WM8960_PLL2_PLLK_SHIFT (0U) 2111 #define WM8960_PLL2_PLLK_SET(x) (((uint16_t)(x) << WM8960_PLL2_PLLK_SHIFT) & WM8960_PLL2_PLLK_MASK) 2112 #define WM8960_PLL2_PLLK_GET(x) (((uint16_t)(x) & WM8960_PLL2_PLLK_MASK) >> WM8960_PLL2_PLLK_SHIFT) 2113 2114 /* Bitfield definition for register: PLL3 */ 2115 /* 2116 * PLLK (RW) 2117 * 2118 * Fractional (K) part of PLL1 input/output 2119 * frequency ratio (treat as one 24-digit binary number). 2120 */ 2121 #define WM8960_PLL3_PLLK_MASK (0xFFU) 2122 #define WM8960_PLL3_PLLK_SHIFT (0U) 2123 #define WM8960_PLL3_PLLK_SET(x) (((uint16_t)(x) << WM8960_PLL3_PLLK_SHIFT) & WM8960_PLL3_PLLK_MASK) 2124 #define WM8960_PLL3_PLLK_GET(x) (((uint16_t)(x) & WM8960_PLL3_PLLK_MASK) >> WM8960_PLL3_PLLK_SHIFT) 2125 2126 /* Bitfield definition for register: PLL4 */ 2127 /* 2128 * PLLK (RW) 2129 * 2130 * Fractional (K) part of PLL1 input/output 2131 * frequency ratio (treat as one 24-digit binary number). 2132 */ 2133 #define WM8960_PLL4_PLLK_MASK (0xFFU) 2134 #define WM8960_PLL4_PLLK_SHIFT (0U) 2135 #define WM8960_PLL4_PLLK_SET(x) (((uint16_t)(x) << WM8960_PLL4_PLLK_SHIFT) & WM8960_PLL4_PLLK_MASK) 2136 #define WM8960_PLL4_PLLK_GET(x) (((uint16_t)(x) & WM8960_PLL4_PLLK_MASK) >> WM8960_PLL4_PLLK_SHIFT) 2137 2138 2139 #endif /* _HPM_WM8960_REG_H_ */ 2140