1 /* 2 * Copyright (c) 2022 HPMicro 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 */ 7 8 #ifndef HPM_DMA_MGR_H 9 #define HPM_DMA_MGR_H 10 11 #include "hpm_common.h" 12 #include "hpm_dmamux_drv.h" 13 #include "hpm_dmamux_src.h" 14 #ifdef HPMSOC_HAS_HPMSDK_DMAV2 15 #include "hpm_dmav2_drv.h" 16 #else 17 #include "hpm_dma_drv.h" 18 #endif 19 #include "hpm_soc_feature.h" 20 21 #ifdef HPMSOC_HAS_HPMSDK_DMAV2 22 #define DMA_MGR_HAS_INFINITE_LOOP (1U) 23 #define DMA_MGR_HAS_HALF_TC_INT (1U) 24 #define DMA_MGR_HAS_HANDSHAKE_OPT (1U) 25 #define DMA_MGR_HAS_BURST_OPT (1U) 26 #endif 27 28 #define DMA_MGR_CHANNEL_PRIORITY_LOW DMA_CHANNEL_PRIORITY_LOW 29 #define DMA_MGR_CHANNEL_PRIORITY_HIGH DMA_CHANNEL_PRIORITY_HIGH 30 31 #define DMA_MGR_NUM_TRANSFER_PER_BURST_1T DMA_NUM_TRANSFER_PER_BURST_1T 32 #define DMA_MGR_NUM_TRANSFER_PER_BURST_2T DMA_NUM_TRANSFER_PER_BURST_2T 33 #define DMA_MGR_NUM_TRANSFER_PER_BURST_4T DMA_NUM_TRANSFER_PER_BURST_4T 34 #define DMA_MGR_NUM_TRANSFER_PER_BURST_8T DMA_NUM_TRANSFER_PER_BURST_8T 35 #define DMA_MGR_NUM_TRANSFER_PER_BURST_16T DMA_NUM_TRANSFER_PER_BURST_16T 36 #define DMA_MGR_NUM_TRANSFER_PER_BURST_32T DMA_NUM_TRANSFER_PER_BURST_32T 37 #define DMA_MGR_NUM_TRANSFER_PER_BURST_64T DMA_NUM_TRANSFER_PER_BURST_64T 38 #define DMA_MGR_NUM_TRANSFER_PER_BURST_128T DMA_NUM_TRANSFER_PER_BURST_128T 39 #define DMA_MGR_NUM_TRANSFER_PER_BURST_256T DMA_NUM_TRANSFER_PER_BURST_256T 40 #define DMA_MGR_NUM_TRANSFER_PER_BURST_512T DMA_NUM_TRANSFER_PER_BURST_512T 41 #define DMA_MGR_NUM_TRANSFER_PER_BURST_1024T DMA_NUM_TRANSFER_PER_BURST_1024T 42 43 #define DMA_MGR_TRANSFER_WIDTH_BYTE DMA_TRANSFER_WIDTH_BYTE 44 #define DMA_MGR_TRANSFER_WIDTH_HALF_WORD DMA_TRANSFER_WIDTH_HALF_WORD 45 #define DMA_MGR_TRANSFER_WIDTH_WORD DMA_TRANSFER_WIDTH_WORD 46 #define DMA_MGR_TRANSFER_WIDTH_DOUBLE_WORD DMA_TRANSFER_WIDTH_DOUBLE_WORD 47 48 #define DMA_MGR_HANDSHAKE_MODE_NORMAL DMA_HANDSHAKE_MODE_NORMAL 49 #define DMA_MGR_HANDSHAKE_MODE_HANDSHAKE DMA_HANDSHAKE_MODE_HANDSHAKE 50 51 #define DMA_MGR_ADDRESS_CONTROL_INCREMENT DMA_ADDRESS_CONTROL_INCREMENT 52 #define DMA_MGR_ADDRESS_CONTROL_DECREMENT DMA_ADDRESS_CONTROL_DECREMENT 53 #define DMA_MGR_ADDRESS_CONTROL_FIXED DMA_ADDRESS_CONTROL_FIXED 54 55 #ifdef DMA_MGR_HAS_BURST_OPT 56 #define DMA_MGR_SRC_BURST_OPT_STANDAND_SIZE DMA_SRC_BURST_OPT_STANDAND_SIZE 57 #define DMA_MGR_SRC_BURST_OPT_CUSTOM_SIZE DMA_SRC_BURST_OPT_CUSTOM_SIZE 58 #else 59 #define DMA_MGR_SRC_BURST_OPT_STANDAND_SIZE 0 60 #define DMA_MGR_SRC_BURST_OPT_CUSTOM_SIZE 0 61 #endif 62 63 #ifdef DMA_MGR_HAS_HANDSHAKE_OPT 64 #define DMA_MGR_HANDSHAKE_OPT_ONE_BURST DMA_HANDSHAKE_OPT_ONE_BURST 65 #define DMA_MGR_HANDSHAKE_OPT_ALL_TRANSIZE DMA_HANDSHAKE_OPT_ALL_TRANSIZE 66 #else 67 #define DMA_MGR_HANDSHAKE_OPT_ONE_BURST 0 68 #define DMA_MGR_HANDSHAKE_OPT_ALL_TRANSIZE 0 69 #endif 70 71 #define DMA_MGR_CHANNEL_STATUS_ONGOING DMA_CHANNEL_STATUS_ONGOING 72 #define DMA_MGR_CHANNEL_STATUS_ERROR DMA_CHANNEL_STATUS_ERROR 73 #define DMA_MGR_CHANNEL_STATUS_ABORT DMA_CHANNEL_STATUS_ABORT 74 #define DMA_MGR_CHANNEL_STATUS_TC DMA_CHANNEL_STATUS_TC 75 #ifdef DMA_MGR_HAS_HALF_TC_INT 76 #define DMA_MGR_CHANNEL_STATUS_HALF_TC DMA_CHANNEL_STATUS_HALF_TC 77 #else 78 #define DMA_MGR_CHANNEL_STATUS_HALF_TC 0 79 #endif 80 #define DMA_MGR_INTERRUPT_MASK_NONE DMA_INTERRUPT_MASK_NONE 81 #define DMA_MGR_INTERRUPT_MASK_ERROR DMA_INTERRUPT_MASK_ERROR 82 #define DMA_MGR_INTERRUPT_MASK_ABORT DMA_INTERRUPT_MASK_ABORT 83 #define DMA_MGR_INTERRUPT_MASK_TC DMA_INTERRUPT_MASK_TERMINAL_COUNT 84 #ifdef DMA_MGR_HAS_HALF_TC_INT 85 #define DMA_MGR_INTERRUPT_MASK_HALF_TC DMA_INTERRUPT_MASK_HALF_TC 86 #else 87 #define DMA_MGR_INTERRUPT_MASK_HALF_TC 0 88 #endif 89 #define DMA_MGR_INTERRUPT_MASK_ALL DMA_INTERRUPT_MASK_ALL 90 91 #ifdef __cplusplus 92 93 extern "C" { 94 #endif 95 96 /** 97 * @brief DMA Manager status codes 98 */ 99 enum { 100 status_dma_mgr_no_resource = MAKE_STATUS(status_group_dma_manager, 0), /**< No DMA resource available */ 101 }; 102 103 /** 104 * @brief DMA Channel Interrupt callback 105 * 106 * @param [in] DMA base address 107 * @param [in] channel DMA channel index 108 * @param [in/out] cb_data_ptr callback Data pointer 109 */ 110 typedef void (*dma_mgr_chn_cb_t)(DMA_Type *base, uint32_t channel, void *cb_data_ptr); 111 112 /** 113 * @brief DMA Resource Structure 114 */ 115 typedef struct _dma_resource { 116 DMA_Type *base; /**< The DMA intance that the allocated channel belongs to */ 117 uint32_t channel; /**< Channel index */ 118 int32_t irq_num; /**< DMA IRQ number */ 119 } dma_resource_t; 120 121 typedef struct hpm_dma_mgr_chn_conf { 122 bool en_dmamux; /**< DMAMUX enable */ 123 uint8_t dmamux_src; /**< DMAMUX source */ 124 uint8_t priority; /**< Channel priority */ 125 uint8_t src_burst_size; /**< Source burst size */ 126 uint8_t src_mode; /**< Source work mode: 0-Normal, 1-Handshake */ 127 uint8_t dst_mode; /**< Destination work mode: 0-Normal, 1-Handshake */ 128 uint8_t src_width; /**< Source width */ 129 uint8_t dst_width; /**< Destination width */ 130 uint8_t src_addr_ctrl; /**< Source address control: 0-inc, 1-dec, 2-fix */ 131 uint8_t dst_addr_ctrl; /**< Destination address control: 0-inc, 1-dec, 2-fix */ 132 uint16_t interrupt_mask; /**< Interrupt mask */ 133 uint32_t src_addr; /**< Source address */ 134 uint32_t dst_addr; /**< Destination address */ 135 uint32_t linked_ptr; /**< Next linked descriptor */ 136 uint32_t size_in_byte; /**< Total size to be transferred in byte */ 137 bool en_infiniteloop; /**< Infinite loop transfer enable. Attention: only DMAV2 support */ 138 uint8_t handshake_opt; /**< Handshake transfer option. Attention: only DMAV2 support */ 139 uint8_t burst_opt; /**< Burst size option. Attention: only DMAV2 support */ 140 } dma_mgr_chn_conf_t; 141 142 typedef struct hpm_dma_mgr_linked_descriptor { 143 uint32_t descriptor[8]; 144 } dma_mgr_linked_descriptor_t; 145 146 /** 147 * @brief Initialize DMA Manager Context 148 */ 149 void dma_mgr_init(void); 150 151 /** 152 * @brief Request DMA resource from DMA Manager 153 * 154 * @param [out] resource DMA resource 155 * @retval status_success if no error occurred 156 * @retval status_invalid_argument if the parameter is invalid 157 * @retval status_dma_mgr_no_resource if all DMA channels are occupied; 158 */ 159 hpm_stat_t dma_mgr_request_resource(dma_resource_t *resource); 160 161 /** 162 * @brief Release DMA resource 163 * 164 * @param [in] resource DMA resource 165 * 166 * @retval status_success if no error occurred 167 * @retval status_invalid_argument if the parameter is invalid 168 */ 169 hpm_stat_t dma_mgr_release_resource(const dma_resource_t *resource); 170 171 /** 172 * @brief Enable DMA interrupt with priority 173 * @param [in] resource DMA resource 174 * @param [in] priority Interrupt Priority 175 * 176 * @retval status_success if no error occurred 177 * @retval status_invalid_argument if any parameters are invalid 178 */ 179 hpm_stat_t dma_mgr_enable_dma_irq_with_priority(const dma_resource_t *resource, uint32_t priority); 180 181 /** 182 * @brief Disable DMA interrupt 183 * NOTE: Each DMA instance consists of several DMA channels, disabling the DMA interrupt 184 * will disable the global DMA interrupt for all DMA channels. Please be aware of the 185 * impact 186 * @param [in] resource DMA resource 187 * 188 * @retval status_success if no error occurred 189 * @retval status_invalid_argument if any parameters are invalid 190 */ 191 hpm_stat_t dma_mgr_disable_dma_irq(const dma_resource_t *resource); 192 193 /** 194 * @brief Install Interrupt Callback for DMA channel transfer complete 195 * 196 * @param [in] resource DMA resource 197 * @param [in] callback Interrupt callback for DMA resource 198 * @param [in] user_data User data used in the callback 199 * 200 * @retval status_success if no error occurred 201 * @retval status_invalid_argument if any parameters are invalid 202 */ 203 hpm_stat_t dma_mgr_install_chn_tc_callback(const dma_resource_t *resource, dma_mgr_chn_cb_t callback, void *user_data); 204 205 /** 206 * @brief Install Interrupt Callback for DMA channel half transfer complete 207 * 208 * @param [in] resource DMA resource 209 * @param [in] callback Interrupt callback for DMA resource 210 * @param [in] user_data User data used in the callback 211 * 212 * @retval status_success if no error occurred 213 * @retval status_invalid_argument if any parameters are invalid 214 */ 215 hpm_stat_t dma_mgr_install_chn_half_tc_callback(const dma_resource_t *resource, dma_mgr_chn_cb_t callback, void *user_data); 216 217 /** 218 * @brief Install Interrupt Callback for DMA channel transfer error 219 * 220 * @param [in] resource DMA resource 221 * @param [in] callback Interrupt callback for DMA resource 222 * @param [in] user_data User data used in the callback 223 * 224 * @retval status_success if no error occurred 225 * @retval status_invalid_argument if any parameters are invalid 226 */ 227 hpm_stat_t dma_mgr_install_chn_error_callback(const dma_resource_t *resource, dma_mgr_chn_cb_t callback, void *user_data); 228 229 /** 230 * @brief Install Interrupt Callback for DMA channel transfer abort 231 * 232 * @param [in] resource DMA resource 233 * @param [in] callback Interrupt callback for DMA resource 234 * @param [in] user_data User data used in the callback 235 * 236 * @retval status_success if no error occurred 237 * @retval status_invalid_argument if any parameters are invalid 238 */ 239 hpm_stat_t dma_mgr_install_chn_abort_callback(const dma_resource_t *resource, dma_mgr_chn_cb_t callback, void *user_data); 240 241 /** 242 * @brief Get DMA channel default config 243 * 244 * @param [out] config config data pointer 245 */ 246 void dma_mgr_get_default_chn_config(dma_mgr_chn_conf_t *config); 247 248 /** 249 * @brief Setup channel config 250 * 251 * @param [in] resource DMA resource 252 * @param [in] config DMA channel config 253 * 254 * @retval status_success if no error occurred 255 * @retval status_invalid_argument if any parameters are invalid 256 */ 257 hpm_stat_t dma_mgr_setup_channel(const dma_resource_t *resource, dma_mgr_chn_conf_t *config); 258 259 /** 260 * @brief Setup chain linked descriptor config 261 * 262 * @param [in] resource DMA resource 263 * @param [in] config DMA channel config 264 * @param [out] descriptor linked descriptor config data pointer 265 * 266 * @retval status_success if no error occurred 267 * @retval status_invalid_argument if any parameters are invalid 268 */ 269 hpm_stat_t dma_mgr_config_linked_descriptor(const dma_resource_t *resource, dma_mgr_chn_conf_t *config, dma_mgr_linked_descriptor_t *descriptor); 270 271 /** 272 * @brief Enable DMA channel, start transfer 273 * 274 * @param [in] resource DMA resource 275 * 276 * @retval status_success if no error occurred 277 * @retval status_invalid_argument if any parameters are invalid 278 */ 279 hpm_stat_t dma_mgr_enable_channel(const dma_resource_t *resource); 280 281 /** 282 * @brief Disable DMA channel 283 * 284 * @param [in] resource DMA resource 285 * 286 * @retval status_success if no error occurred 287 * @retval status_invalid_argument if any parameters are invalid 288 */ 289 hpm_stat_t dma_mgr_disable_channel(const dma_resource_t *resource); 290 291 /** 292 * @brief Check DMA channel enable status 293 * 294 * @param [in] resource DMA resource 295 * @param [out] enable enable status 296 * 297 * @retval status_success if no error occurred 298 * @retval status_invalid_argument if any parameters are invalid 299 */ 300 hpm_stat_t dma_mgr_check_chn_enable(const dma_resource_t *resource, bool *enable); 301 302 /** 303 * @brief Enable DMA channel interrupt 304 * @param [in] resource DMA resource 305 * 306 * @retval status_success if no error occurred 307 * @retval status_invalid_argument if any parameters are invalid 308 */ 309 hpm_stat_t dma_mgr_enable_chn_irq(const dma_resource_t *resource, uint32_t irq_mask); 310 311 /** 312 * @brief Disable DMA channel interrupt 313 * @param [in] resource DMA resource 314 * 315 * @retval status_success if no error occurred 316 * @retval status_invalid_argument if any parameters are invalid 317 */ 318 hpm_stat_t dma_mgr_disable_chn_irq(const dma_resource_t *resource, uint32_t irq_mask); 319 320 /** 321 * @brief Set DMA channel priority 322 * 323 * @param [in] resource DMA resource 324 * @param [in] priority DMA channel priority 325 * @arg @ref DMA_MGR_PRIORITY_LOW 326 * @arg @ref DMA_MGR_PRIORITY_HIGH 327 * 328 * @retval status_success if no error occurred 329 * @retval status_invalid_argument if any parameters are invalid 330 */ 331 hpm_stat_t dma_mgr_set_chn_priority(const dma_resource_t *resource, uint8_t priority); 332 333 /** 334 * @brief Set DMA channel source work mode 335 * 336 * @param [in] resource DMA resource 337 * @param [in] mode DMA source work mode 338 * @arg @ref DMA_MGR_HANDSHAKE_MODE_NORMAL 339 * @arg @ref DMA_MGR_HANDSHAKE_MODE_HANDSHAKE 340 * 341 * @retval status_success if no error occurred 342 * @retval status_invalid_argument if any parameters are invalid 343 */ 344 hpm_stat_t dma_mgr_set_chn_src_work_mode(const dma_resource_t *resource, uint8_t mode); 345 346 /** 347 * @brief Set DMA channel destination work mode 348 * 349 * @param [in] resource DMA resource 350 * @param [in] mode DMA destination work mode 351 * @arg @ref DMA_MGR_HANDSHAKE_MODE_NORMAL 352 * @arg @ref DMA_MGR_HANDSHAKE_MODE_HANDSHAKE 353 * 354 * @retval status_success if no error occurred 355 * @retval status_invalid_argument if any parameters are invalid 356 */ 357 hpm_stat_t dma_mgr_set_chn_dst_work_mode(const dma_resource_t *resource, uint8_t mode); 358 359 /** 360 * @brief Set DMA channel source burst size 361 * 362 * @param [in] resource DMA resource 363 * @param [in] burstsize DMA source burst size 364 * when BURSTOPT is 0, please reference follows: 365 * @arg @ref DMA_MGR_NUM_TRANSFER_PER_BURST_1T 366 * @arg @ref DMA_MGR_NUM_TRANSFER_PER_BURST_2T 367 * @arg @ref DMA_MGR_NUM_TRANSFER_PER_BURST_4T 368 * @arg @ref DMA_MGR_NUM_TRANSFER_PER_BURST_8T 369 * @arg @ref DMA_MGR_NUM_TRANSFER_PER_BURST_16T 370 * @arg @ref DMA_MGR_NUM_TRANSFER_PER_BURST_32T 371 * @arg @ref DMA_MGR_NUM_TRANSFER_PER_BURST_64T 372 * @arg @ref DMA_MGR_NUM_TRANSFER_PER_BURST_128T 373 * @arg @ref DMA_MGR_NUM_TRANSFER_PER_BURST_256T 374 * @arg @ref DMA_MGR_NUM_TRANSFER_PER_BURST_512T 375 * @arg @ref DMA_MGR_NUM_TRANSFER_PER_BURST_1024T 376 * when BURSTOPT is 1, burst size is (burstsize + 1). Attention: only DMAV2 support 377 * 378 * @retval status_success if no error occurred 379 * @retval status_invalid_argument if any parameters are invalid 380 */ 381 hpm_stat_t dma_mgr_set_chn_src_burst_size(const dma_resource_t *resource, uint8_t burstsize); 382 383 /** 384 * @brief Get DMA channel remaining transfer size 385 * 386 * @param [in] resource DMA resource 387 * @param [out] size remaining transfer size of the channel. 388 * 389 * @retval status_success if no error occurred 390 * @retval status_invalid_argument if any parameters are invalid 391 */ 392 hpm_stat_t dma_mgr_get_chn_remaining_transize(const dma_resource_t *resource, uint32_t *size); 393 394 /** 395 * @brief Set DMA channel transfer size 396 * 397 * @param [in] resource DMA resource 398 * @param [in] size transfer size of the channel. 399 * 400 * @retval status_success if no error occurred 401 * @retval status_invalid_argument if any parameters are invalid 402 */ 403 hpm_stat_t dma_mgr_set_chn_transize(const dma_resource_t *resource, uint32_t size); 404 405 /** 406 * @brief Set DMA channel source width 407 * 408 * @param [in] resource DMA resource 409 * @param [in] width transfer source width of the channel 410 * @arg @ref DMA_MGR_TRANSFER_WIDTH_BYTE 411 * @arg @ref DMA_MGR_TRANSFER_WIDTH_HALF_WORD 412 * @arg @ref DMA_MGR_TRANSFER_WIDTH_WORD 413 * @arg @ref DMA_MGR_TRANSFER_WIDTH_DOUBLE_WORD 414 * 415 * @retval status_success if no error occurred 416 * @retval status_invalid_argument if any parameters are invalid 417 */ 418 hpm_stat_t dma_mgr_set_chn_src_width(const dma_resource_t *resource, uint8_t width); 419 420 /** 421 * @brief Set DMA channel destination width 422 * 423 * @param [in] resource DMA resource 424 * @param [in] width transfer destination width of the channel 425 * @arg @ref DMA_MGR_TRANSFER_WIDTH_BYTE 426 * @arg @ref DMA_MGR_TRANSFER_WIDTH_HALF_WORD 427 * @arg @ref DMA_MGR_TRANSFER_WIDTH_WORD 428 * @arg @ref DMA_MGR_TRANSFER_WIDTH_DOUBLE_WORD 429 * 430 * @retval status_success if no error occurred 431 * @retval status_invalid_argument if any parameters are invalid 432 */ 433 hpm_stat_t dma_mgr_set_chn_dst_width(const dma_resource_t *resource, uint8_t width); 434 435 /** 436 * @brief Set DMA channel source address 437 * 438 * @param [in] resource DMA resource 439 * @param [in] addr source address 440 * 441 * @retval status_success if no error occurred 442 * @retval status_invalid_argument if any parameters are invalid 443 */ 444 hpm_stat_t dma_mgr_set_chn_src_addr(const dma_resource_t *resource, uint32_t addr); 445 446 /** 447 * @brief Set DMA channel destination address 448 * 449 * @param [in] resource DMA resource 450 * @param [in] addr destination address 451 * 452 * @retval status_success if no error occurred 453 * @retval status_invalid_argument if any parameters are invalid 454 */ 455 hpm_stat_t dma_mgr_set_chn_dst_addr(const dma_resource_t *resource, uint32_t addr); 456 457 /** 458 * @brief Set DMA channel source address control mode 459 * 460 * @param [in] resource DMA resource 461 * @param [in] addr_ctrl source address control mode 462 * @arg @ref DMA_MGR_ADDRESS_CONTROL_INCREMENT 463 * @arg @ref DMA_MGR_ADDRESS_CONTROL_DECREMENT 464 * @arg @ref DMA_MGR_ADDRESS_CONTROL_FIXED 465 * 466 * @retval status_success if no error occurred 467 * @retval status_invalid_argument if any parameters are invalid 468 */ 469 hpm_stat_t dma_mgr_set_chn_src_addr_ctrl(const dma_resource_t *resource, uint8_t addr_ctrl); 470 471 /** 472 * @brief Set DMA channel destination address control mode 473 * 474 * @param [in] resource DMA resource 475 * @param [in] addr_ctrl destination address control mode 476 * @arg @ref DMA_MGR_ADDRESS_CONTROL_INCREMENT 477 * @arg @ref DMA_MGR_ADDRESS_CONTROL_DECREMENT 478 * @arg @ref DMA_MGR_ADDRESS_CONTROL_FIXED 479 * 480 * @retval status_success if no error occurred 481 * @retval status_invalid_argument if any parameters are invalid 482 */ 483 hpm_stat_t dma_mgr_set_chn_dst_addr_ctrl(const dma_resource_t *resource, uint8_t addr_ctrl); 484 485 /** 486 * @brief Set DMA channel infinite loop mode. Attention: only DMAV2 support 487 * 488 * @param [in] resource DMA resource 489 * @param [in] infinite_loop false - normal mode(single times mode); true - infinite loop mode(cycle mode) 490 * 491 * @retval status_success if no error occurred 492 * @retval status_invalid_argument if any parameters are invalid 493 */ 494 hpm_stat_t dma_mgr_set_chn_infinite_loop_mode(const dma_resource_t *resource, bool infinite_loop); 495 496 /** 497 * @brief Set DMA channel source burst option. Attention: only DMAV2 support 498 * 499 * @param [in] resource DMA resource 500 * @param [in] burst_opt burst option 501 * @arg @ref DMA_MGR_SRC_BURST_OPT_STANDAND_SIZE 502 * @arg @ref DMA_MGR_SRC_BURST_OPT_CUSTOM_SIZE 503 * 504 * @retval status_success if no error occurred 505 * @retval status_invalid_argument if any parameters are invalid 506 */ 507 hpm_stat_t dma_mgr_set_chn_src_busrt_option(const dma_resource_t *resource, uint8_t burst_opt); 508 509 /** 510 * @brief Set DMA channel handshake option. Attention: only DMAV2 support 511 * 512 * @param [in] resource DMA resource 513 * @param [in] handshake_opt handshake option 514 * @arg @ref DMA_HANDSHAKE_OPT_ONE_BURST 515 * @arg @ref DMA_HANDSHAKE_OPT_ALL_TRANSIZE 516 * 517 * @retval status_success if no error occurred 518 * @retval status_invalid_argument if any parameters are invalid 519 */ 520 hpm_stat_t dma_mgr_set_chn_handshake_option(const dma_resource_t *resource, uint8_t handshake_opt); 521 522 /** 523 * @brief Abort DMA channel transfer 524 * 525 * @param [in] resource DMA resource 526 * 527 * @retval status_success if no error occurred 528 * @retval status_invalid_argument if any parameters are invalid 529 */ 530 hpm_stat_t dma_mgr_abort_chn_transfer(const dma_resource_t *resource); 531 532 /** 533 * @brief Check DMA channel transfer status 534 * 535 * @param [in] resource DMA resource 536 * @param [out] sts transfer status 537 * DMA_MGR_CHANNEL_STATUS_ONGOING if transfer is still ongoing 538 * DMA_MGR_CHANNEL_STATUS_ERROR if any error occurred during transferring 539 * DMA_MGR_CHANNEL_STATUS_ABORT if transfer is aborted 540 * DMA_MGR_CHANNEL_STATUS_TC if transfer is finished without error 541 * DMA_MGR_CHANNEL_STATUS_HALF_TC if half transfer complete without error. Attention: only DMAV2 support 542 * 543 * @retval status_success if no error occurred 544 * @retval status_invalid_argument if any parameters are invalid 545 */ 546 hpm_stat_t dma_mgr_check_chn_transfer_status(const dma_resource_t *resource, uint32_t *status); 547 548 #ifdef __cplusplus 549 } 550 #endif 551 552 #endif /* HPM_DMA_MGR_H */ 553