1 /* 2 * Copyright (c) 2021-2023 HPMicro 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 */ 7 8 #ifndef HPM_ENET_DRV_H 9 #define HPM_ENET_DRV_H 10 11 /*--------------------------------------------------------------------- 12 * Includes 13 *--------------------------------------------------------------------- 14 */ 15 #include "hpm_common.h" 16 #include "hpm_enet_regs.h" 17 #include "hpm_soc_feature.h" 18 #include "hpm_enet_soc_drv.h" 19 20 /** 21 * @brief Enet driver APIs 22 * @defgroup enet_interface Enet driver APIs 23 * @ingroup communication_interfaces 24 * @{ 25 */ 26 27 /*--------------------------------------------------------------------- 28 * Macro Constant Declarations 29 *--------------------------------------------------------------------- 30 */ 31 #define ENET_HEADER (14U) /**< 6-byte Dest addr, 6-byte Src addr, 2-byte type */ 32 #define ENET_EXTRA (2U) /**< Extra bytes in some cases */ 33 #define ENET_VLAN_TAG (4U) /**< optional 802.1q VLAN Tag */ 34 #define ENET_CRC (4U) /**< Ethernet CRC */ 35 #define ENET_MIN_PAYLOAD (46U) /**< Minimum Ethernet payload size */ 36 #define ENET_MAX_PAYLOAD (1500U) /**< Maximum Ethernet payload size */ 37 #define ENET_MAX_FRAME_SIZE (1524U) /**< ENET_HEADER + ENET_EXTRA + VLAN_TAG + MAX_ENET_PAYLOAD + ENET_CRC */ 38 #define ENET_JUMBO_FRAME_PAYLOAD (9000U) /**< Jumbo frame payload size */ 39 #define ENET_MAC (6) /**< Ethernet MAC size */ 40 #define ENET_ERROR (0) /**< ENET error */ 41 #define ENET_SUCCESS (1) /**< ENET success */ 42 43 #define ENET_ADJ_FREQ_BASE_ADDEND (0x80000000UL) /**< PTP base adjustment addend */ 44 #define ENET_ONE_SEC_IN_NANOSEC (1000000000UL) /**< one second in nanoseconds */ 45 46 #define ENET_PPS_CMD_MASK (0x07UL) /**< Enet PPS CMD Mask */ 47 #define ENET_PPS_CMD_OFS_FAC (3U) /**< Enet PPS CMD OFS Factor */ 48 49 #ifndef ENET_RETRY_CNT 50 #define ENET_RETRY_CNT (10000UL) /**< Enet retry count for PTP */ 51 #endif 52 53 /*--------------------------------------------------------------------- 54 * Typedef Enum Declarations 55 *--------------------------------------------------------------------- 56 */ 57 58 /** @brief interrupt enable type */ 59 typedef enum { 60 enet_normal_int_sum_en = ENET_DMA_INTR_EN_NIE_MASK, 61 enet_aboarmal_int_sum_en = ENET_DMA_INTR_EN_AIE_MASK, 62 enet_receive_int_en = ENET_DMA_INTR_EN_RIE_MASK 63 } enet_interrupt_enable_t; 64 65 /** @brief interrupt mask type */ 66 typedef enum { 67 enet_lpi_int_mask = ENET_INTR_MASK_LPIIM_MASK, 68 enet_rgsmii_int_mask = ENET_INTR_MASK_RGSMIIIM_MASK 69 } enet_interrupt_mask_t; 70 71 72 /** @brief Programmable burst length selections */ 73 typedef enum { 74 enet_pbl_1 = 1, 75 enet_pbl_2 = 2, 76 enet_pbl_4 = 4, 77 enet_pbl_8 = 8, 78 enet_pbl_16 = 16, 79 enet_pbl_32 = 32 80 } enet_pbl_t; 81 82 /** @brief Checksum insertion control selections */ 83 typedef enum { 84 enet_cic_disable = 0, 85 enet_cic_ip = 1, 86 enet_cic_ip_no_pseudoheader = 2, 87 enet_cic_ip_pseudoheader = 3 88 } enet_cic_insertion_control_t; 89 90 /** @brief VLAN insertion control selections */ 91 typedef enum { 92 enet_vlic_disable = 0, 93 enet_vlic_remove_vlan_tag = 1, 94 enet_vlic_insert_vlan_tag = 2, 95 enet_vlic_replace_vlan_tag = 3 96 } enet_vlan_insertion_control_t; 97 98 /** @brief SA insertion or replacement control selections for any selective frames */ 99 typedef enum { 100 enet_saic_disable = 0, 101 enet_saic_insert_mac0 = 1, 102 enet_saic_replace_mac0 = 2, 103 enet_saic_insert_mac1 = 5, 104 enet_saic_replace_mac1 = 6 105 } enet_saic_insertion_replacement_control_t; 106 107 /** @brief SA insertion or replacement control selections for all transmit frames */ 108 typedef enum { 109 enet_sarc_disable = 0, 110 enet_sarc_insert_mac0 = 2, 111 enet_sarc_replace_mac0 = 3, 112 enet_sarc_insert_mac1 = 6, 113 enet_sarc_replace_mac1 = 7 114 } enet_sarc_insertion_replacement_control_t; 115 116 /** @brief PHY operation selections */ 117 typedef enum { 118 enet_phy_op_read = 0, 119 enet_phy_op_write 120 } enet_phy_op_t; 121 122 123 /** @brief PHY status */ 124 typedef enum { 125 enet_gmii_idle = 0, 126 enet_gmii_busy 127 } enet_gmii_status_t; 128 129 /** @brief CSR clock range and MDC clock selections */ 130 /** @note The suggested range of CSR clock is approximately 131 * between the frequency range 1.0MHz-2.5MHz. 132 * You can achieve higher frequency of the MDC clock than the frequency limit of 2.5MHz(specified in the IEEE Std 802.3) 133 * and program a clock divider of lower value. Program the value which is no less than enet_csr_60m_to_100m_mdc_csr_div_4 134 * only if the interfacing chips support faster MDC clocks. 135 */ 136 typedef enum { 137 enet_csr_60m_to_100m_mdc_csr_div_42 = 0, /**< CSR clock range: 60-100MHz <==> MDC clock: CSR clock / 42 */ 138 enet_csr_100m_to_150m_mdc_csr_div_62, /**< CSR clock range: 100-150MHz <==> MDC clock: CSR clock / 62 */ 139 enet_csr_20m_to_35m_mdc_csr_div_16, /**< CSR clock range: 20-35MHz <==> MDC clock: CSR clock / 16 */ 140 enet_csr_35m_to_60m_mdc_csr_div_26, /**< CSR clock range: 35-60MHz <==> MDC clock: CSR clock / 26 */ 141 enet_csr_150m_to_250m_mdc_csr_div_102, /**< CSR clock range: 150-250MHz <==> MDC clock: CSR clock / 102 */ 142 enet_csr_250m_to_300m_mdc_csr_div_124, /**< CSR clock range: 250-300MHz <==> MDC clock: CSR clock / 124 */ 143 144 enet_csr_60m_to_100m_mdc_csr_div_4 = 8, /**< CSR clock / 4 */ 145 enet_csr_60m_to_100m_mdc_csr_div_6, /**< CSR clock / 6 */ 146 enet_csr_60m_to_100m_mdc_csr_div_8, /**< CSR clock / 8 */ 147 enet_csr_60m_to_100m_mdc_csr_div_10, /**< CSR clock / 10 */ 148 enet_csr_60m_to_100m_mdc_csr_div_12, /**< CSR clock / 12 */ 149 enet_csr_60m_to_100m_mdc_csr_div_14, /**< CSR clock / 14 */ 150 enet_csr_60m_to_100m_mdc_csr_div_16, /**< CSR clock / 16 */ 151 enet_csr_60m_to_100m_mdc_csr_div_18 /**< CSR clock / 18 */ 152 } enet_csr_clk_range_t; 153 154 /** @brief enet interface selections */ 155 typedef enum { 156 enet_inf_rmii = 4, 157 enet_inf_rgmii = 1 158 } enet_inf_type_t; 159 160 /** @brief enet line speed */ 161 typedef enum { 162 enet_line_speed_1000mbps = 0, 163 enet_line_speed_10mbps = 2, 164 enet_line_speed_100mbps = 3 165 } enet_line_speed_t; 166 167 /** @brief enet duplex mode */ 168 typedef enum { 169 enet_half_duplex = 0, 170 enet_full_duplex 171 } enet_duplex_mode_t; 172 173 /** @brief enet timestamp update methods */ 174 typedef enum { 175 enet_ptp_time_coarse_update = 0, 176 enet_ptp_time_fine_update 177 } enet_ptp_time_update_method_t; 178 179 /** @brief PTP versions */ 180 typedef enum { 181 enet_ptp_v1 = 0, 182 enet_ptp_v2 183 } enet_ptp_version_t; 184 185 /** @brief PTP frame types */ 186 typedef enum { 187 enet_ptp_frame_ipv4 = 0, 188 enet_ptp_frame_ipv6, 189 enet_ptp_frame_ethernet 190 } enet_ptp_frame_type_t; 191 192 /** @brief PTP message type for snapshots */ 193 typedef enum { 194 enet_ts_ss_ptp_msg_0 = 0, /* SYNC, Follow_Up, Delay_Req, Delay_Resp */ 195 enet_ts_ss_ptp_msg_1 = 1, /* SYNC */ 196 enet_ts_ss_ptp_msg_2 = 3, /* Delay_Req */ 197 enet_ts_ss_ptp_msg_3 = 4, /* SYNC, Follow_Up, Delay_Req, Delay_Resp, Pdelay_Req, Pdelay_Resp, Pdelay_Resp_Follow_Up */ 198 enet_ts_ss_ptp_msg_4 = 5, /* SYNC, Pdelay_Req, Pdelay_Resp */ 199 enet_ts_ss_ptp_msg_5 = 7, /* Delay_Req, Pdelay_Req, Pdelay_Resp */ 200 enet_ts_ss_ptp_msg_6 = 8, /* SYNC, Delay_Req */ 201 enet_ts_ss_ptp_msg_7 = 12 /* Pdelay_Req, Pdelay_Resp */ 202 } enet_ts_ss_ptp_msg_t; 203 204 /** @brief PTP timer rollover modes */ 205 typedef enum { 206 enet_ts_bin_rollover_control = 0, /* timestamp rolls over after 0x7fffffff */ 207 enet_ts_dig_rollover_control /* timestamp rolls over after 0x3b9ac9ff */ 208 } enet_ts_rollover_control_t; 209 210 /** @brief PPS indexes */ 211 typedef enum { 212 enet_pps_0 = -1, 213 enet_pps_1 = 0, 214 enet_pps_2 = 1, 215 enet_pps_3 = 2 216 } enet_pps_idx_t; 217 218 /** @brief PPS0 control for output frequency selections */ 219 typedef enum { 220 enet_pps_ctrl_pps = 0, 221 enet_pps_ctrl_bin_2hz_digital_1hz, 222 enet_pps_ctrl_bin_4hz_digital_2hz, 223 enet_pps_ctrl_bin_8hz_digital_4hz, 224 enet_pps_ctrl_bin_16hz_digital_8hz, 225 enet_pps_ctrl_bin_32hz_digital_16hz, 226 enet_pps_ctrl_bin_64hz_digital_32hz, 227 enet_pps_ctrl_bin_128hz_digital_64hz, 228 enet_pps_ctrl_bin_256hz_digital_128hz, 229 enet_pps_ctrl_bin_512hz_digital_256hz, 230 enet_pps_ctrl_bin_1024hz_digital_512hz, 231 enet_pps_ctrl_bin_2048hz_digital_1024hz, 232 enet_pps_ctrl_bin_4096hz_digital_2048hz, 233 enet_pps_ctrl_bin_8192hz_digital_4096hz, 234 enet_pps_ctrl_bin_16384hz_digital_8192hz, 235 enet_pps_ctrl_bin_32867hz_digital_16384hz 236 } enet_pps_ctrl_t; 237 238 /** @brief PPS0 commands */ 239 typedef enum { 240 enet_pps_cmd_no_command = 0, 241 enet_pps_cmd_start_single_pulse, 242 enet_pps_cmd_start_pulse_train, 243 enet_pps_cmd_cancel_start, 244 enet_pps_cmd_stop_pulse_train_at_time, 245 enet_pps_cmd_stop_pulse_train_immediately, 246 enet_pps_cmd_cancel_stop_pulse_train 247 } enet_pps_cmd_t; 248 249 /*--------------------------------------------------------------------- 250 * Typedef Struct Declarations 251 *--------------------------------------------------------------------- 252 */ 253 /** @brief enet buffer config struct */ 254 typedef struct { 255 uint32_t buffer; 256 uint32_t count; 257 uint16_t size; 258 } enet_buff_config_t; 259 260 /** @brief enet mac config struct */ 261 typedef struct { 262 uint32_t mac_addr_high[ENET_SOC_ADDR_MAX_COUNT]; 263 uint32_t mac_addr_low[ENET_SOC_ADDR_MAX_COUNT]; 264 uint8_t valid_max_count; 265 uint8_t dma_pbl; 266 uint8_t sarc; 267 } enet_mac_config_t; 268 269 /** @brief transmission descriptor struct */ 270 typedef struct { 271 union { 272 uint32_t tdes0; 273 struct { 274 uint32_t db: 1; /**< * Deferred Bit*/ 275 uint32_t uf: 1; /**< * Underflow Error */ 276 uint32_t ed: 1; /**< * Excessive Deferral */ 277 uint32_t cc: 4; /**< * Collision Count */ 278 uint32_t vf: 1; /**< * VLAN Frame */ 279 uint32_t ec: 1; /**< * Excessive Collision */ 280 uint32_t lc: 1; /**< * Late Collision */ 281 uint32_t nc: 1; /**< * No Carrier */ 282 uint32_t loc: 1; /**< * Loss of Carrier */ 283 uint32_t ipe: 1; /**< * IP Payload Error */ 284 uint32_t ff: 1; /**< * Frame Flushed */ 285 uint32_t jt: 1; /**< * Jabber Timeout */ 286 uint32_t es: 1; /**< * Error Summary */ 287 uint32_t ihe: 1; /**< * IP Header Error */ 288 uint32_t ttss: 1; /**< * Transmit Timestamp Status */ 289 uint32_t vlic: 2; /**< * VLAN Insertion Control */ 290 uint32_t tch: 1; /**< * Second Address Chained */ 291 uint32_t ter: 1; /**< * Transmit End of Ring */ 292 uint32_t cic: 2; /**< * Checksum Insertion Control */ 293 uint32_t crcr: 1; /**< * CRC Replacement Control */ 294 uint32_t ttse: 1; /**< * Transmit Timestamp Enable */ 295 uint32_t dp: 1; /**< * Disable Pad */ 296 uint32_t dc: 1; /**< * Disable CRC */ 297 uint32_t fs: 1; /**< * First Segment */ 298 uint32_t ls: 1; /**< * Last Segment */ 299 uint32_t ic: 1; /**< * Interrupt on Completion */ 300 uint32_t own: 1; /**< * Own Bit */ 301 } tdes0_bm; 302 }; 303 304 union { 305 uint32_t tdes1; 306 struct { 307 uint32_t tbs1 : 13; /**< Transmit Buffer 1 Size */ 308 uint32_t reserved: 3; /**< Reserved */ 309 uint32_t tbs2 : 13; /**< Transmit Buffer 2 Size */ 310 uint32_t saic : 3; /**< SA Insertion Control */ 311 } tdes1_bm; 312 }; 313 314 union { 315 uint32_t tdes2; 316 struct { 317 uint32_t buffer1; /**< Buffer 1 Address */ 318 } tdes2_bm; 319 }; 320 321 union { 322 uint32_t tdes3; 323 union { 324 uint32_t buffer2; /**< Buffer 2 Address */ 325 uint32_t next_desc; /**< Next Descriptor Address */ 326 } tdes3_bm; 327 }; 328 329 #if ENET_SOC_ALT_EHD_DES_LEN == ENET_SOC_ALT_EHD_DES_MAX_LEN 330 struct { 331 uint32_t reserved; 332 } tdes4_bm; 333 334 struct { 335 uint32_t reserved; 336 } tdes5_bm; 337 338 struct { 339 uint32_t ttsl; /**< Transmit Frame Timestamp Low */ 340 } tdes6_bm; 341 342 struct { 343 uint32_t ttsh; /**< Transmit Frame Timestamp High */ 344 } tdes7_bm; 345 #endif 346 } enet_tx_desc_t; 347 348 /** @brief reception descriptor struct */ 349 typedef struct { 350 union { 351 uint32_t rdes0; 352 353 struct { 354 uint32_t ex_sta_rx_addr : 1; /**< Extended Status Available or Rx MAC Address*/ 355 uint32_t ce : 1; /**< CRC Error */ 356 uint32_t dbe : 1; /**< Dribble Bit Error */ 357 uint32_t re : 1; /**< Receive Error */ 358 uint32_t rwt : 1; /**< Receive Watchdog Timeout */ 359 uint32_t ft : 1; /**< Frame Type */ 360 uint32_t lc : 1; /**< Late Collision */ 361 uint32_t ts_ip_gf : 1; /**< Timestamp Available, IP Checksum Error or Giant Frame*/ 362 uint32_t ls : 1; /**< Last Descriptor */ 363 uint32_t fs : 1; /**< First Descriptor */ 364 uint32_t vlan : 1; /**< VLAN Tag */ 365 uint32_t oe : 1; /**< Overflow Error */ 366 uint32_t le : 1; /**< Length Error */ 367 uint32_t saf : 1; /**< Source Address Filter Fail */ 368 uint32_t dse : 1; /**< Descriptor Error */ 369 uint32_t es : 1; /**< Error Summary */ 370 uint32_t fl : 14; /**< Frame Length */ 371 uint32_t afm : 1; /**< Destination Address Filter Fail */ 372 uint32_t own : 1; /**< Own Bit */ 373 } rdes0_bm; 374 }; 375 376 union { 377 uint32_t rdes1; 378 struct { 379 uint32_t rbs1 : 13; /**< Receive Buffer 1 Size */ 380 uint32_t reserved0: 1; /**< Reserved */ 381 uint32_t rch : 1; /**< Second Address Chained */ 382 uint32_t rer : 1; /**< Receive End of Ring */ 383 uint32_t rbs2 : 13; /**< Receive Buffer 2 Size */ 384 uint32_t reserved1: 2; /**< Reserved */ 385 uint32_t dic : 1; /**< Disable Interrupt on Completion */ 386 } rdes1_bm; 387 }; 388 389 union { 390 uint32_t rdes2; 391 struct { 392 uint32_t buffer1; /**< Buffer 1 Address */ 393 } rdes2_bm; 394 }; 395 396 union { 397 uint32_t rdes3; 398 union { 399 uint32_t buffer2; /**< Buffer 2 Address */ 400 uint32_t next_desc; /**< Next Descriptor Address */ 401 } rdes3_bm; 402 }; 403 404 #if ENET_SOC_ALT_EHD_DES_LEN == ENET_SOC_ALT_EHD_DES_MAX_LEN 405 union { 406 uint32_t rdes4; 407 struct { 408 uint32_t ip_payload_type : 3; /**< IP Payload Type */ 409 uint32_t ip_header_err : 1; /**< IP Header Error */ 410 uint32_t ip_payload_err : 1; /**< IP Payload Error */ 411 uint32_t ip_chksum_bypassed : 1; /**< IP Checksum Bypassed */ 412 uint32_t ipv4_pkt_received : 1; /**< IPv4 Packet Received */ 413 uint32_t ipv6_pkt_received : 1; /**< IPv6 Packet Received */ 414 uint32_t msg_type : 4; /**< Message Type */ 415 uint32_t ptp_frame_type : 1; /**< PTP Frame Type */ 416 uint32_t ptp_version : 1; /**< PTP Version */ 417 uint32_t ts_dp : 1; /**< Timestamp Dropped */ 418 uint32_t reserved0 : 1; /**< Reserved */ 419 uint32_t av_pkt_recv : 1; /**< AV Packet Received */ 420 uint32_t av_tagged_pkt_recv : 1; /**< AV Tagged Packet Received */ 421 uint32_t vlan_tag_pri_value : 3; /**< VLAN Tag Priority Value */ 422 uint32_t reserved1 : 3; /**< Reserved */ 423 uint32_t l3_fm : 1; /**< Layer 3 Filter Matched */ 424 uint32_t l4_fm : 1; /**< Layer 4 Filter Matched */ 425 uint32_t l3_l4_fnl : 2; /**< Layer 3 and Layer 4 Filter Number Matched */ 426 uint32_t reserved2 : 4; /**< Reserved */ 427 } rdes4_bm; 428 }; 429 430 struct { 431 uint32_t reserved; 432 } rdes5_bm; 433 434 struct { 435 uint32_t rtsl; /**< Receive Frame Timestamp Low */ 436 } rdes6_bm; 437 438 struct { 439 uint32_t rtsh; /**< Receive Frame Timestamp High */ 440 } rdes7_bm; 441 #endif 442 } enet_rx_desc_t; 443 444 /** @brief enet frame struct */ 445 typedef struct{ 446 uint32_t length; 447 uint32_t buffer; 448 enet_rx_desc_t *rx_desc; 449 } enet_frame_t; 450 451 /** @brief enet reception frame info struct */ 452 typedef struct { 453 enet_rx_desc_t *fs_rx_desc; 454 enet_rx_desc_t *ls_rx_desc; 455 uint32_t seg_count; 456 } enet_rx_frame_info_t; 457 458 /** @brief enet control config struct for transmission */ 459 typedef struct { 460 bool enable_ioc; /* interrupt on completion */ 461 bool disable_crc; /* disable CRC */ 462 bool disable_pad; /* disable Pad */ 463 bool enable_ttse; /* enable transmit timestamp */ 464 bool enable_crcr; /* CRC replacement control */ 465 uint8_t cic; /* checksum insertion control */ 466 uint8_t vlic; /* VLAN insertion control */ 467 uint8_t saic; /* SA insertion control */ 468 } enet_tx_control_config_t; 469 470 /** @brief enet description struct */ 471 typedef struct { 472 enet_tx_desc_t *tx_desc_list_head; 473 enet_rx_desc_t *rx_desc_list_head; 474 enet_tx_desc_t *tx_desc_list_cur; 475 enet_rx_desc_t *rx_desc_list_cur; 476 enet_buff_config_t tx_buff_cfg; 477 enet_buff_config_t rx_buff_cfg; 478 enet_rx_frame_info_t rx_frame_info; 479 enet_tx_control_config_t tx_control_config; 480 } enet_desc_t; 481 482 /** @brief PTP system timestamp struct */ 483 typedef struct { 484 uint32_t sec; 485 uint32_t nsec; 486 } enet_ptp_ts_system_t; 487 488 /** @brief PTP update timestamp struct */ 489 typedef struct { 490 uint32_t sec; 491 uint32_t nsec; 492 uint8_t sign; 493 } enet_ptp_ts_update_t; 494 495 /** @brief PTP target timestamp struct */ 496 typedef struct { 497 uint32_t sec; 498 uint32_t nsec; 499 } enet_ptp_ts_target_t; 500 501 /** @brief PTP config strcut */ 502 typedef struct { 503 uint8_t ssinc; 504 uint8_t timestamp_rollover_mode; 505 uint8_t update_method; 506 uint32_t addend; 507 } enet_ptp_config_t; 508 509 /** @brief PTP PPS command output config strcut */ 510 typedef struct { 511 uint32_t pps_interval; 512 uint32_t pps_width; 513 uint32_t target_sec; 514 uint32_t target_nsec; 515 } enet_pps_cmd_config_t; 516 517 /** @brief Enet interrupt config struct */ 518 typedef struct { 519 uint32_t int_enable; /* DMA_INTR_EN */ 520 uint32_t int_mask; /* INTR MASK */ 521 uint32_t mmc_intr_rx; 522 uint32_t mmc_intr_mask_rx; 523 uint32_t mmc_intr_tx; 524 uint32_t mmc_intr_mask_tx; 525 } enet_int_config_t; 526 527 /* 528 * @brief Bit definition of TDES1 529 */ 530 #define ENET_DMATxDesc_TBS2 ((uint32_t)0x1FFF0000) /**< Transmit Buffer2 Size */ 531 #define ENET_DMATxDesc_TBS1 ((uint32_t)0x00001FFF) /**< Transmit Buffer1 Size */ 532 533 #if defined __cplusplus 534 extern "C" { 535 #endif /* __cplusplus */ 536 /*--------------------------------------------------------------------- 537 * Exported Functions 538 *--------------------------------------------------------------------- 539 */ 540 /** 541 * @brief Get a default control config for tranmission 542 * 543 * @param[in] ptr An Ethernet peripheral base address 544 * @param[in] config A pointer to a control config structure for tranmission 545 */ 546 void enet_get_default_tx_control_config(ENET_Type *ptr, enet_tx_control_config_t *config); 547 548 /** 549 * @brief Get interrupt status 550 * 551 * @param[in] ptr An Ethernet peripheral base address 552 * @return A result of interrupt status 553 */ 554 uint32_t enet_get_interrupt_status(ENET_Type *ptr); 555 556 /** 557 * @brief Mask the specified mmc interrupt evenets of received frames 558 * 559 * @param[in] ptr An Ethernet peripheral base address 560 * @param[in] config A mask of the specified evenets 561 */ 562 void enet_mask_mmc_rx_interrupt_event(ENET_Type *ptr, uint32_t mask); 563 564 /** 565 * @brief Mask the specified mmc interrupt evenets of transmitted frames 566 * 567 * @param[in] ptr An Ethernet peripheral base address 568 * @param[in] config A mask of the specified evenets 569 */ 570 void enet_mask_mmc_tx_interrupt_event(ENET_Type *ptr, uint32_t mask); 571 572 /** 573 * @brief Get a staus of mmc receive interrupt events 574 * 575 * @param[in] ptr An Ethernet peripheral base address 576 * @return A result of interrupt status 577 */ 578 uint32_t enet_get_mmc_rx_interrupt_status(ENET_Type *ptr); 579 /** 580 * @brief et a staus of mmc transmission interrupt events 581 * 582 * @param[in] ptr An Ethernet peripheral base address 583 * @return A result of interrupt status 584 */ 585 uint32_t enet_get_mmc_tx_interrupt_status(ENET_Type *ptr); 586 587 /** 588 * @brief Initialize controller 589 * 590 * @param[in] ptr An Ethernet peripheral base address 591 * @param[in] inf_type the specified interface 592 * @param[in] desc A pointer to descriptor config 593 * @param[in] cfg A pointer to mac config 594 * @param[in] int_cfg A pointer to the masks of the specified enabled interrupts and the specified masked interrupts 595 * @return A result of the specified controller initialization 596 */ 597 hpm_stat_t enet_controller_init(ENET_Type *ptr, enet_inf_type_t inf_type, enet_desc_t *desc, enet_mac_config_t *cfg, enet_int_config_t *int_config); 598 599 /** 600 * @brief Set port line speed 601 * 602 * @param[in] ptr An Ethernet peripheral base address 603 * @param[in] line_speed An enum variable of @ref enet_line_speed_t 604 */ 605 void enet_set_line_speed(ENET_Type *ptr, enet_line_speed_t speed); 606 607 /** 608 * @brief Set duplex mode 609 * 610 * @param[in] ptr An Ethernet peripheral base address 611 * @param[in] mode An enum variable of @ref enet_duplex_mode_t 612 */ 613 void enet_set_duplex_mode(ENET_Type *ptr, enet_duplex_mode_t mode); 614 615 /** 616 * @brief Read phy 617 * 618 * @param[in] ptr An Ethernet peripheral base address 619 * @param[in] phy_addr the specified address of phy 620 * @param[in] addr the specified address of register 621 * @retval A value corresponding to the specified register address 622 */ 623 uint16_t enet_read_phy(ENET_Type *ptr, uint32_t phy_addr, uint32_t addr); 624 625 /** 626 * @brief Write phy 627 * 628 * @param[in] ptr An Ethernet peripheral base address 629 * @param[in] phy_addr a specified address of phy 630 * @param[in] addr a specified address of the register 631 * @param[in] data a specified data to be written 632 */ 633 void enet_write_phy(ENET_Type *ptr, uint32_t phy_addr, uint32_t addr, uint32_t data); 634 635 /** 636 * @brief Resume reception process 637 * 638 * @param[in] ptr An Ethernet peripheral base address 639 * 640 */ 641 void enet_rx_resume(ENET_Type *ptr); 642 643 /** 644 * @brief Check if there is a received frame 645 * 646 * @param[out] parent_rx_desc_list_cur a parent pointer to the current reception description list 647 * @param[in] rx_frame_info A pointer to the information of the reception frames 648 * @retval A result of reception frame. 649 * 1 means that a reception of frame is successful. 650 * 0 means that a reception of frame is unsuccessful. 651 */ 652 uint32_t enet_check_received_frame(enet_rx_desc_t **parent_rx_desc_list_cur, enet_rx_frame_info_t *rx_frame_info); 653 654 /** 655 * @brief get a received frame 656 * 657 * @param[out] parent_rx_desc_list_cur A parent pointer to the current reception description list 658 * @param[in] rx_frame_info A pointer to the information of the reception frames 659 * @retval A struct of the current reception frame 660 */ 661 enet_frame_t enet_get_received_frame(enet_rx_desc_t **parent_rx_desc_list_cur, enet_rx_frame_info_t *rx_frame_info); 662 663 /** 664 * @brief get a received frame from interrupt 665 * 666 * @param[out] parent_rx_desc_list_cur the parent pointer to the current reception description list 667 * @param[in] rx_frame_info A pointer to the information of the reception frames 668 * @param[in] rx_desc_count A total count of the reception descriptors 669 * @retval A struct of the current reception frame 670 */ 671 enet_frame_t enet_get_received_frame_interrupt(enet_rx_desc_t **parent_rx_desc_list_cur, enet_rx_frame_info_t *rx_frame_info, uint32_t rx_desc_count); 672 673 /** 674 * @brief prepare for the transmission descriptors (It will be deprecated.) 675 * 676 * @param[in] ptr An Ethernet peripheral base address 677 * @param[out] parent_tx_desc_list_cur a pointer to the information of the reception frames 678 * @param[in] frame_length the length of the transmission 679 * @param[in] tx_buff_size the size of the transmission buffer 680 * @retval a result of the transmission preparation. 681 * 1 means that the preparation is successful. 682 * 0 means that the preparation is unsuccessful. 683 */ 684 uint32_t enet_prepare_transmission_descriptors(ENET_Type *ptr, enet_tx_desc_t **parent_tx_desc_list_cur, uint16_t frame_length, uint16_t tx_buff_size); 685 686 /** 687 * @brief prepare for the transmission descriptors 688 * 689 * @param[in] ptr An Ethernet peripheral base address 690 * @param[out] parent_tx_desc_list_cur a pointer to the information of the reception frames 691 * @param[in] config a pointer to the control configuration for the transmission frames 692 * @param[in] frame_length the length of the transmission 693 * @param[in] tx_buff_size the size of the transmission buffer 694 * @retval a result of the transmission preparation. 695 * 1 means that the preparation is successful. 696 * 0 means that the preparation is unsuccessful. 697 */ 698 uint32_t enet_prepare_tx_desc(ENET_Type *ptr, enet_tx_desc_t **parent_tx_desc_list_cur, enet_tx_control_config_t *config, uint16_t frame_length, uint16_t tx_buff_size); 699 700 /** 701 * @brief prepare for the transmission descriptors with a timestamp record 702 * 703 * @param[in] ptr An Ethernet peripheral base address 704 * @param[out] parent_tx_desc_list_cur a pointer to the information of the reception frames 705 * @param[in] config a pointer to the control configuration for the transmission frames 706 * @param[in] frame_length the length of the transmission 707 * @param[in] tx_buff_size the size of the transmission buffer 708 * @param[out] timestamp a pointer to the timestamp record of a transmitted frame 709 * @retval a result of the transmission preparation. 710 * 1 means that the preparation is successful. 711 * 0 means that the preparation is unsuccessful. 712 */ 713 uint32_t enet_prepare_tx_desc_with_ts_record(ENET_Type *ptr, 714 enet_tx_desc_t **parent_tx_desc_list_cur, 715 enet_tx_control_config_t *config, 716 uint16_t frame_length, uint16_t tx_buff_size, 717 enet_ptp_ts_system_t *timestamp); 718 719 /** 720 * @brief Initialize DMA transmission descriptors in chain mode 721 * 722 * @param[in] ptr An Ethernet peripheral base address 723 * @param[in] desc A pointer to transmission descriptors 724 */ 725 void enet_dma_tx_desc_chain_init(ENET_Type *ptr, enet_desc_t *desc); 726 727 /** 728 * @brief Initialize DMA reception descriptors in chain mode 729 * 730 * @param[in] ptr An Ethernet peripheral base address 731 * @param[in] desc A pointer to reception descriptors 732 */ 733 void enet_dma_rx_desc_chain_init(ENET_Type *ptr, enet_desc_t *desc); 734 735 /** 736 * @brief Flush DMA 737 * 738 * @param[in] ptr An Ethernet peripheral base address 739 */ 740 void enet_dma_flush(ENET_Type *ptr); 741 742 /** 743 * @brief Initialize a PTP timer 744 * 745 * @param[in] ptr An Ethernet peripheral base address 746 * @param[in] config A pointer to an enet_ptp_config struct instance 747 */ 748 void enet_init_ptp(ENET_Type *ptr, enet_ptp_config_t *config); 749 750 /** 751 * @brief Set a timestamp to the PTP timer 752 * 753 * @param[in] ptr An Ethernet peripheral base address 754 * @param[in] timestamp A pointer to a update timestamp structure instance 755 */ 756 void enet_set_ptp_timestamp(ENET_Type *ptr, enet_ptp_ts_update_t *timestamp); 757 758 /** 759 * @brief Get a timestamp from the PTP timer 760 * 761 * @param[in] ptr An Ethernet peripheral base address 762 * @param[out] timestamp A pointer to a system timestamp structure instance 763 */ 764 void enet_get_ptp_timestamp(ENET_Type *ptr, enet_ptp_ts_system_t *timestamp); 765 766 /** 767 * @brief Update a timestamp to the PTP timer 768 * 769 * @param[in] ptr An Ethernet peripheral base address 770 * @param[in] timeoffset A pointer to a update timestamp structure instance 771 */ 772 void enet_update_ptp_timeoffset(ENET_Type *ptr, enet_ptp_ts_update_t *timeoffset); 773 774 /** 775 * @brief Adjust the count frequency of the PTP timer 776 * 777 * @param[in] ptr An Ethernet peripheral base address 778 * @param[in] adj An adjustment value for the count frequency of the PTP timer 779 */ 780 void enet_adjust_ptp_time_freq(ENET_Type *ptr, int32_t adj); 781 782 /** 783 * @brief Set the PTP version 784 * 785 * @param[in] ptr An Ethernet peripheral base address 786 * @param[in] ptp_ver An enum value indicating the PTP protocol 787 */ 788 void enet_set_ptp_version(ENET_Type *ptr, enet_ptp_version_t ptp_ver); 789 790 /** 791 * @brief Enable the specified ptp frame type for MAC process 792 * 793 * @param[in] ptr An Ethernet peripheral base address 794 * @param[in] ptp_frame_type An enum value indicating the transport protocol of PTP frames 795 * @param[in] enable A value to enable or disable the transport protocol of PTP frames which is specified by ptp_frame_type parameter 796 * @retval hpm_stat_t @ref status_invalid_argument or @ref status_success 797 */ 798 hpm_stat_t enet_enable_ptp_frame_type(ENET_Type *ptr, enet_ptp_frame_type_t ptp_frame_type, bool enable); 799 800 /** 801 * @brief Set the ptp message type for snapshots 802 * 803 * @param[in] ptr An Ethernet peripheral base address 804 * @param[in] ts_ss_ptp_msg An enum value indicating the specified ptp message type for snapshots 805 */ 806 void enet_set_snapshot_ptp_message_type(ENET_Type *ptr, enet_ts_ss_ptp_msg_t ts_ss_ptp_msg); 807 808 /** 809 * @brief Set the pps0 control output 810 * 811 * @param[in] ptr An Ethernet peripheral base address 812 * @param[in] enet_pps_ctrl_t An enum value indicating the specified pps frequency 813 */ 814 void enet_set_pps0_control_output(ENET_Type *ptr, enet_pps_ctrl_t freq); 815 816 /** 817 * @brief Set a pps command for ppsx 818 * 819 * @param[in] ptr An Ethernet peripheral base address 820 * @param[in] cmd An enum value indicating the specified pps command 821 * @param[in] idx An enum value indicating the index of pps instance 822 * @retval hpm_stat_t @ref status_invalid_argument or @ref status_success 823 */ 824 hpm_stat_t enet_set_ppsx_command(ENET_Type *ptr, enet_pps_cmd_t cmd, enet_pps_idx_t idx); 825 826 /** 827 * @brief Set a pps config for ppsx 828 * 829 * @param[in] ptr An Ethernet peripheral base address 830 * @param[in] cmd An enum value indicating the specified pps config 831 * @param[in] idx An enum value indicating the index of pps instance 832 * @retval hpm_stat_t @ref status_invalid_argument or @ref status_success 833 */ 834 hpm_stat_t enet_set_ppsx_config(ENET_Type *ptr, enet_pps_cmd_config_t *cmd_cfg, enet_pps_idx_t idx); 835 836 #if defined __cplusplus 837 } 838 #endif /* __cplusplus */ 839 840 /** @} */ 841 #endif /* HPM_ENET_DRV_H */ 842