1 /*
2 * Copyright (c) 2023 HPMicro
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 *
6 */
7
8 #ifndef HPM_GWC_DRV_H
9 #define HPM_GWC_DRV_H
10
11 /**
12 * @brief GWC APIs
13 * @defgroup gwc_interface GWC driver APIs
14 * @ingroup gwc_interfaces
15 * @{
16 */
17
18 #include "hpm_common.h"
19 #include "hpm_soc.h"
20 #include "hpm_gwc_regs.h"
21
22 /**
23 * @brief gwc channel config
24 *
25 * @note area of channel do not overlap. in other words, eache pixel belongs to a single channel at most.
26 */
27 typedef struct gwc_ch_config {
28 bool freeze; /*!< freeze the channel configuration except reference CRC32 value setting. */
29 uint16_t start_col; /*!< start col is X of upper left corner. Range: 0 to 2^13-1. */
30 uint16_t start_row; /*!< start row is Y of upper left corner. Range: 0 to 2^12-1. */
31 uint16_t end_col; /*!< end col is X of lower right corner. Range: 0 to 2^13-1. */
32 uint16_t end_row; /*!< end row is Y of lower right corner. Range: 0 to 2^12-1. */
33 uint32_t ref_crc; /*!< Reference CRC32 value.*/
34 } gwc_ch_config_t;
35
36 /**
37 * @brief gwc clk polarity
38 */
39 typedef enum gwc_clk_pol {
40 gwc_clk_pol_normal = 0,
41 gwc_clk_pol_invert
42 } gwc_clk_pol_t;
43
44 /**
45 * @brief gwc config
46 */
47 typedef struct gwc_config {
48 gwc_clk_pol_t clk_pol;
49 } gwc_config_t;
50
51 #ifdef __cplusplus
52 extern "C" {
53 #endif
54
55 /**
56 * @brief init the gwc
57 *
58 * @param[in] cfg GWC config @ref gwc_config_t
59 */
60 void gwc_get_default_config(gwc_config_t *cfg);
61
62 /**
63 * @brief init the gwc
64 *
65 * @param[in] ptr GWC base address
66 * @param[in] cfg GWC config @ref gwc_config_t
67 *
68 * @note the function is called while gwc is disable only
69 */
70 void gwc_init(GWC_Type *ptr, gwc_config_t *cfg);
71
72 /**
73 * @brief enable the gwc
74 *
75 * @param[in] ptr GWC base address
76 */
77 void gwc_enable(GWC_Type *ptr);
78
79 /**
80 * @brief disable the gwc
81 *
82 * @param[in] ptr GWC base address
83 */
84 void gwc_disable(GWC_Type *ptr);
85
86 /**
87 * @brief enable interrupts
88 *
89 * @param[in] ptr GWC base address
90 * @param[in] mask Mask of interrupt events that would be enabled
91 * @ref GWC_IRQ_MASK_ERR_MASK_MASK
92 * @ref GWC_IRQ_MASK_FUNC_MASK_MASK
93 */
gwc_enable_interrupt(GWC_Type * ptr,uint32_t mask)94 static inline void gwc_enable_interrupt(GWC_Type *ptr, uint32_t mask)
95 {
96 ptr->IRQ_MASK &= ~mask;
97 }
98
99 /**
100 * @brief disable interrupts.
101 *
102 * @param[in] ptr GWC base address
103 * @param[in] mask mask of interrupt events that would be enabled.
104 * @ref GWC_IRQ_MASK_ERR_MASK_MASK
105 * @ref GWC_IRQ_MASK_FUNC_MASK_MASK
106 */
gwc_disable_interrupt(GWC_Type * ptr,uint32_t mask)107 static inline void gwc_disable_interrupt(GWC_Type *ptr, uint32_t mask)
108 {
109 ptr->IRQ_MASK |= mask;
110 }
111
112 /**
113 * @brief get gwc status flag
114 *
115 * @param[in] ptr GWC base address
116 * @return gwc status
117 */
gwc_get_status(GWC_Type * ptr)118 static inline uint32_t gwc_get_status(GWC_Type *ptr)
119 {
120 return ptr->IRQ_STS;
121 }
122
123 /**
124 * @brief clear gwc status flag
125 *
126 * @param[in] ptr GWC base address
127 * @param[in] mask logical OR'ed of GWC_IRQ_STS_XXX_STS_MASK
128 */
gwc_clear_status(GWC_Type * ptr,uint32_t mask)129 static inline void gwc_clear_status(GWC_Type *ptr, uint32_t mask)
130 {
131 ptr->IRQ_STS = mask;
132 }
133
134 /**
135 * @brief disable change of interrupt masks
136 *
137 * Once this function is called, the interrupt enabled status could not be changed
138 * until reset.
139 *
140 * @param[in] ptr GWC base address
141 */
142 void gwc_freeze_interrupt_control(GWC_Type *ptr);
143
144 /**
145 * @brief init gwc channel
146 *
147 * @param[in] ptr GWC base address
148 * @param[in] ch_index channel index @ref GWC_CHANNEL_CHn
149 * @param[in] cfg config of gwc channel
150 *
151 * @note the function is called while gwc channel is disable only
152 */
153 void gwc_ch_init(GWC_Type *ptr, uint8_t ch_index, gwc_ch_config_t *cfg);
154
155 /**
156 * @brief enable gwc channel
157 *
158 * @param[in] ptr GWC base address
159 * @param[in] ch_index channel index @ref GWC_CHANNEL_CHn
160 */
gwc_ch_enable(GWC_Type * ptr,uint8_t ch_index)161 static inline void gwc_ch_enable(GWC_Type *ptr, uint8_t ch_index)
162 {
163 assert(ch_index <= GWC_CHANNEL_CH15);
164 ptr->CHANNEL[ch_index].CFG0 |= GWC_CHANNEL_CFG0_ENABLE_MASK;
165 }
166
167 /**
168 * @brief disable gwc channel
169 *
170 * @param[in] ptr GWC base address
171 * @param[in] ch_index channel index @ref GWC_CHANNEL_CHn
172 */
gwc_ch_disable(GWC_Type * ptr,uint8_t ch_index)173 static inline void gwc_ch_disable(GWC_Type *ptr, uint8_t ch_index)
174 {
175 assert(ch_index <= GWC_CHANNEL_CH15);
176 ptr->CHANNEL[ch_index].CFG0 &= ~GWC_CHANNEL_CFG0_ENABLE_MASK;
177 }
178
179 /**
180 * @brief get gwc channel calc crc
181 *
182 * @param[in] ptr GWC base address
183 * @param[in] ch_index channel index @ref GWC_CHANNEL_CHn
184 */
gwc_ch_get_crc(GWC_Type * ptr,uint8_t ch_index)185 static inline uint32_t gwc_ch_get_crc(GWC_Type *ptr, uint8_t ch_index)
186 {
187 assert(ch_index <= GWC_CHANNEL_CH15);
188 return ptr->CHANNEL[ch_index].CALCRC;
189 }
190
191 #ifdef __cplusplus
192 }
193 #endif
194
195 /**
196 * @}
197 */
198 #endif /* HPM_GWC_DRV_H */
199