1 /*
2 * Copyright (c) 2021 HPMicro
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 *
6 */
7
8 #ifndef HPM_I2C_DRV_H
9 #define HPM_I2C_DRV_H
10 #include "hpm_common.h"
11 #include "hpm_i2c_regs.h"
12 #include "hpm_soc_feature.h"
13
14 /**
15 * @brief I2C driver APIs
16 * @defgroup i2c_interface I2C driver APIs
17 * @ingroup io_interfaces
18 * @{
19 */
20
21 /**
22 * @brief I2C status
23 */
24 enum {
25 status_i2c_no_ack = MAKE_STATUS(status_group_i2c, 1),
26 status_i2c_invalid_data = MAKE_STATUS(status_group_i2c, 2),
27 status_i2c_no_addr_hit = MAKE_STATUS(status_group_i2c, 3),
28 status_i2c_transmit_not_completed = MAKE_STATUS(status_group_i2c, 4),
29 status_i2c_not_supported = MAKE_STATUS(status_group_i2c, 9),
30 };
31
32 /* convert data count value into register(CTRL[DATACNT] and CTRL[DATACNT_HIGH] if exist) */
33 /* x range from 1 to I2C_SOC_TRANSFER_COUNT_MAX */
34 /* 0 for I2C_SOC_TRANSFER_COUNT_MAX */
35 #define I2C_DATACNT_MAP(x) (((x) == I2C_SOC_TRANSFER_COUNT_MAX) ? 0 : x)
36
37 /**
38 * @brief I2C CMD
39 */
40 #define I2C_CMD_NO_ACTION (I2C_CMD_CMD_SET(0))
41 #define I2C_CMD_ISSUE_DATA_TRANSMISSION (I2C_CMD_CMD_SET(1))
42 #define I2C_CMD_ACK (I2C_CMD_CMD_SET(2))
43 #define I2C_CMD_NACK (I2C_CMD_CMD_SET(3))
44 #define I2C_CMD_CLEAR_FIFO (I2C_CMD_CMD_SET(4))
45 #define I2C_CMD_RESET (I2C_CMD_CMD_SET(5))
46
47 /**
48 * @brief I2C data direction
49 */
50 #define I2C_DIR_MASTER_WRITE (0U)
51 #define I2C_DIR_MASTER_READ (1U)
52 #define I2C_DIR_SLAVE_READ (0U)
53 #define I2C_DIR_SLAVE_WRITE (1U)
54
55 /**
56 * @brief I2C events for interrupt enable and status check
57 */
58 #define I2C_EVENT_TRANSACTION_COMPLETE I2C_INTEN_CMPL_MASK
59 #define I2C_EVENT_BYTE_RECEIVED I2C_INTEN_BYTERECV_MASK
60 #define I2C_EVENT_BYTE_TRANSMIT I2C_INTEN_BYTETRANS_MASK
61 #define I2C_EVENT_START_CONDITION I2C_INTEN_START_MASK
62 #define I2C_EVENT_STOP_CONDITION I2C_INTEN_STOP_MASK
63 #define I2C_EVENT_LOSS_ARBITRATION I2C_INTEN_ARBLOSE_MASK
64 #define I2C_EVENT_ADDRESS_HIT I2C_INTEN_ADDRHIT_MASK
65 #define I2C_EVENT_FIFO_HALF I2C_INTEN_FIFOHALF_MASK
66 #define I2C_EVENT_FIFO_FULL I2C_INTEN_FIFOFULL_MASK
67 #define I2C_EVENT_FIFO_EMPTY I2C_INTEN_FIFOEMPTY_MASK
68
69 #define I2C_EVENT_ALL_MASK (I2C_INTEN_CMPL_MASK \
70 | I2C_INTEN_BYTERECV_MASK \
71 | I2C_INTEN_BYTETRANS_MASK \
72 | I2C_INTEN_START_MASK \
73 | I2C_INTEN_STOP_MASK \
74 | I2C_INTEN_ARBLOSE_MASK \
75 | I2C_INTEN_ADDRHIT_MASK \
76 | I2C_INTEN_FIFOHALF_MASK \
77 | I2C_INTEN_FIFOFULL_MASK \
78 | I2C_INTEN_FIFOEMPTY_MASK)
79 /**
80 * @brief I2C status for status check only
81 */
82 #define I2C_STATUS_LINE_SDA I2C_STATUS_LINESDA_MASK
83 #define I2C_STATUS_LINE_SCL I2C_STATUS_LINESCL_MASK
84 #define I2C_STATUS_GENERAL_CALL I2C_STATUS_GENCALL_MASK
85 #define I2C_STATUS_BUS_BUSY I2C_STATUS_BUSBUSY_MASK
86 #define I2C_STATUS_ACK I2C_STATUS_ACK_MASK
87
88 /**
89 * @brief I2C config
90 */
91 typedef struct {
92 bool is_10bit_addressing;
93 uint8_t i2c_mode;
94 } i2c_config_t;
95
96 /**
97 * @brief I2C mode
98 */
99 typedef enum i2c_mode {
100 i2c_mode_normal,
101 i2c_mode_fast,
102 i2c_mode_fast_plus,
103 } i2c_mode_t;
104
105 /**
106 * @brief I2c sequential transfer options
107 * @arg: i2c_frist_frame: has start signal
108 * @arg: i2c_next_frame: middle transfer
109 * @arg: i2c_last_frame: has stop signal
110 */
111 typedef enum i2c_seq_transfer_opt {
112 i2c_frist_frame = 0,
113 i2c_next_frame,
114 i2c_last_frame,
115 } i2c_seq_transfer_opt_t;
116
117 #ifdef __cplusplus
118 extern "C" {
119 #endif
120
121 /**
122 * @brief respond NACK
123 *
124 * @param [in] ptr I2C base address
125 */
i2c_respond_Nack(I2C_Type * ptr)126 static inline void i2c_respond_Nack(I2C_Type *ptr)
127 {
128 ptr->CMD = I2C_CMD_NACK;
129 }
130
131 /**
132 * @brief respond ACK
133 *
134 * @param [in] ptr I2C base address
135 */
i2c_respond_ack(I2C_Type * ptr)136 static inline void i2c_respond_ack(I2C_Type *ptr)
137 {
138 ptr->CMD = I2C_CMD_ACK;
139 }
140
141 /**
142 * @brief clear I2C fifo
143 *
144 * @param [in] ptr I2C base address
145 */
i2c_clear_fifo(I2C_Type * ptr)146 static inline void i2c_clear_fifo(I2C_Type *ptr)
147 {
148 ptr->CMD = I2C_CMD_CLEAR_FIFO;
149 }
150
151 /**
152 * @brief check data count
153 *
154 * @details It indicates number of bytes to transfer
155 *
156 * @param [in] ptr I2C base address
157 * @retval data count value in byte
158 */
i2c_get_data_count(I2C_Type * ptr)159 static inline uint8_t i2c_get_data_count(I2C_Type *ptr)
160 {
161 return (I2C_CTRL_DATACNT_HIGH_GET(ptr->CTRL) << 8U) + I2C_CTRL_DATACNT_GET(ptr->CTRL);
162 }
163
164 /**
165 * @brief check if I2C FIFO is full
166 *
167 * @param [in] ptr I2C base address
168 * @retval true if FIFO is full
169 */
i2c_fifo_is_full(I2C_Type * ptr)170 static inline bool i2c_fifo_is_full(I2C_Type *ptr)
171 {
172 return ptr->STATUS & I2C_STATUS_FIFOFULL_MASK;
173 }
174
175 /**
176 * @brief check if I2C FIFO is half
177 *
178 * @note When I2C is transmitting data, it indicates if fifo is half-empty;
179 * @note When I2C is receiving data, it indicates if fifo is half full.
180 *
181 * @param [in] ptr I2C base address
182 * @retval true if FIFO is half empty or full
183 */
i2c_fifo_is_half(I2C_Type * ptr)184 static inline bool i2c_fifo_is_half(I2C_Type *ptr)
185 {
186 return ptr->STATUS & I2C_STATUS_FIFOHALF_MASK;
187 }
188
189 /**
190 * @brief check if I2C FIFO is empty
191 *
192 * @param [in] ptr I2C base address
193 * @retval true if FIFO is empty
194 */
i2c_fifo_is_empty(I2C_Type * ptr)195 static inline bool i2c_fifo_is_empty(I2C_Type *ptr)
196 {
197 return ptr->STATUS & I2C_STATUS_FIFOEMPTY_MASK;
198 }
199
200 /**
201 * @brief check if I2C is writing
202 *
203 * @param [in] ptr I2C base address
204 * @retval bool value
205 * @arg true: receive data if master mode, send data in slave mode
206 * @arg false: send data if master mode, reveive data in slave mode
207 *
208 */
i2c_is_writing(I2C_Type * ptr)209 static inline bool i2c_is_writing(I2C_Type *ptr)
210 {
211 return (ptr->CTRL & I2C_CTRL_DIR_MASK);
212 }
213
214 /**
215 * @brief check if I2C is reading
216 *
217 * @param [in] ptr I2C base address
218 * @retval bool value
219 * @arg true: send data if master mode, receive data in slave mode
220 * @arg false: receive data if master mode, send data in slave mode
221 *
222 */
i2c_is_reading(I2C_Type * ptr)223 static inline bool i2c_is_reading(I2C_Type *ptr)
224 {
225 return !i2c_is_writing(ptr);
226 }
227
228 /**
229 * @brief get i2c sda line status
230 *
231 * @param [in] ptr I2C base address
232 * @retval bool value
233 * @arg true: the sda line is high
234 * @arg false: the sda line is low
235 *
236 */
i2c_get_line_sda_status(I2C_Type * ptr)237 static inline bool i2c_get_line_sda_status(I2C_Type *ptr)
238 {
239 return I2C_STATUS_LINESDA_GET(ptr->STATUS);
240 }
241
242 /**
243 * @brief get i2c scl line status
244 *
245 * @param [in] ptr I2C base address
246 * @retval bool value
247 * @arg true: the scl line is high
248 * @arg false: the scl line is low
249 *
250 */
i2c_get_line_scl_status(I2C_Type * ptr)251 static inline bool i2c_get_line_scl_status(I2C_Type *ptr)
252 {
253 return I2C_STATUS_LINESCL_GET(ptr->STATUS);
254 }
255
256 /**
257 * @brief clear status
258 *
259 * @details Clear status based on mask
260 *
261 * @param [in] ptr I2C base address
262 * @param [in] mask mask to clear status
263 */
i2c_clear_status(I2C_Type * ptr,uint32_t mask)264 static inline void i2c_clear_status(I2C_Type *ptr, uint32_t mask)
265 {
266 ptr->STATUS = mask;
267 }
268
269 /**
270 * @brief get status
271 *
272 * @details Get current I2C status bits
273 *
274 * @param [in] ptr I2C base address
275 * @retval current I2C status
276 */
i2c_get_status(I2C_Type * ptr)277 static inline uint32_t i2c_get_status(I2C_Type *ptr)
278 {
279 return ptr->STATUS;
280 }
281
282 /**
283 * @brief i2c get interrupts setting
284 *
285 * @details Get interrupt setting register value
286 *
287 * @param [in] ptr I2C base address
288 * @retval [out] uint32_t interrupt setting register value
289 */
i2c_get_irq_setting(I2C_Type * ptr)290 static inline uint32_t i2c_get_irq_setting(I2C_Type *ptr)
291 {
292 return ptr->INTEN;
293 }
294
295 /**
296 * @brief disable interrupts
297 *
298 * @details Disable interrupts based on given mask
299 *
300 * @param [in] ptr I2C base address
301 * @param [in] mask interrupt mask to be disabled
302 */
i2c_disable_irq(I2C_Type * ptr,uint32_t mask)303 static inline void i2c_disable_irq(I2C_Type *ptr, uint32_t mask)
304 {
305 ptr->INTEN &= ~mask;
306 }
307
308 /**
309 * @brief enable interrupts
310 *
311 * @details Enable interrupts based on given mask
312 *
313 * @param [in] ptr I2C base address
314 * @param [in] mask interrupt mask to be enabled
315 */
i2c_enable_irq(I2C_Type * ptr,uint32_t mask)316 static inline void i2c_enable_irq(I2C_Type *ptr, uint32_t mask)
317 {
318 ptr->INTEN |= mask;
319 }
320
321 /**
322 * @brief disable auto ack
323 *
324 * @details Disable I2C auto generates proper acknowledgements for each byte received
325 *
326 * @param [in] ptr I2C base address
327 */
i2c_disable_auto_ack(I2C_Type * ptr)328 static inline void i2c_disable_auto_ack(I2C_Type *ptr)
329 {
330 ptr->INTEN &= ~I2C_EVENT_BYTE_RECEIVED;
331 }
332
333 /**
334 * @brief enable auto ack
335 *
336 * @details Enable I2C auto generates proper acknowledgements for each byte received
337 *
338 * @param [in] ptr I2C base address
339 */
i2c_enable_auto_ack(I2C_Type * ptr)340 static inline void i2c_enable_auto_ack(I2C_Type *ptr)
341 {
342 ptr->INTEN |= I2C_EVENT_BYTE_RECEIVED;
343 }
344
345 /**
346 * @brief enable 10 bit address mode
347 *
348 * @details enable 10 bit address mode, if not, address is 7 bit mode
349 *
350 * @param [in] ptr I2C base address
351 * @param [in] enable
352 * @arg true: enable 10 bit address mode
353 * @arg false: enable 7 bit address mode
354 */
i2c_enable_10bit_address_mode(I2C_Type * ptr,bool enable)355 static inline void i2c_enable_10bit_address_mode(I2C_Type *ptr, bool enable)
356 {
357 ptr->SETUP |= I2C_SETUP_ADDRESSING_SET(enable);
358 }
359
360 /**
361 * @brief I2C master initialization
362 *
363 * @details Initialized I2C controller working at master mode
364 *
365 * @param [in] ptr I2C base address
366 * @param [in] src_clk_in_hz I2C controller source clock source frequency in Hz
367 * @param [in] config i2c_config_t
368 * @retval hpm_stat_t: status_success if initialization is completed without any error
369 */
370 hpm_stat_t i2c_init_master(I2C_Type *ptr,
371 uint32_t src_clk_in_hz,
372 i2c_config_t *config);
373
374 /**
375 * @brief I2C master write data to specific address of certain slave device
376 *
377 * @details Write to certain I2C device at specific address within that device
378 * @note the sum of addr_size_in_byte and size_in_byte should not not greater than I2C_SOC_TRANSFER_COUNT_MAX
379 *
380 * @param [in] ptr I2C base address
381 * @param [in] device_address I2C slave address
382 * @param [in] addr address in that I2C device
383 * @param [in] addr_size_in_byte I2C address in byte
384 * @param [in] buf pointer of the data to be sent
385 * @param [in] size_in_byte size of data to be sent in bytes
386 * @retval hpm_stat_t: status_success if writing is completed without any error
387 */
388 hpm_stat_t i2c_master_address_write(I2C_Type *ptr,
389 const uint16_t device_address,
390 uint8_t *addr,
391 uint32_t addr_size_in_byte,
392 uint8_t *buf,
393 const uint32_t size_in_byte);
394
395 /**
396 * @brief I2C master read data from specific address of certain slave device
397 *
398 * @details Read fram certain I2C device at specific address within that device
399 * @note both addr_size_in_byte and size_in_byte should not not greater than I2C_SOC_TRANSFER_COUNT_MAX
400 *
401 * @param [in] ptr I2C base address
402 * @param [in] device_address I2C slave address
403 * @param [in] addr address in that I2C device
404 * @param [in] addr_size_in_byte I2C address in byte
405 * @param [out] buf pointer of the buffer to receive data read from the device
406 * @param [in] size_in_byte size of data to be read in bytes
407 * @retval hpm_stat_t: status_success if reading is completed without any error
408 */
409 hpm_stat_t i2c_master_address_read(I2C_Type *ptr,
410 const uint16_t device_address,
411 uint8_t *addr,
412 uint32_t addr_size_in_byte,
413 uint8_t *buf,
414 const uint32_t size_in_byte);
415
416 /**
417 * @brief I2C master write data to certain slave device
418 *
419 * @details Write data to I2C device
420 * @note size should not not greater than I2C_SOC_TRANSFER_COUNT_MAX
421 *
422 * @param [in] ptr I2C base address
423 * @param [in] device_address I2C slave address
424 * @param [in] buf pointer of the data to be sent
425 * @param [in] size size of data to be sent in bytes
426 * @retval hpm_stat_t: status_success if writing is completed without any error
427 */
428 hpm_stat_t i2c_master_write(I2C_Type *ptr,
429 const uint16_t device_address,
430 uint8_t *buf,
431 const uint32_t size);
432
433 /**
434 * @brief I2C master start write data by DMA
435 *
436 * @details Write data to I2C device by DMA
437 * @note size should not not greater than I2C_SOC_TRANSFER_COUNT_MAX
438 *
439 * @param [in] i2c_ptr I2C base address
440 * @param [in] device_address I2C slave address
441 * @param [in] size size of data to be sent in bytes
442 * @retval hpm_stat_t status_success if starting transmission without any error
443 */
444 hpm_stat_t i2c_master_start_dma_write(I2C_Type *i2c_ptr, const uint16_t device_address, uint32_t size);
445
446 /**
447 * @brief I2C master start read data by DMA
448 *
449 * @details Read data to I2C device by DMA
450 * @note size should not not greater than I2C_SOC_TRANSFER_COUNT_MAX
451 *
452 * @param [in] i2c_ptr I2C base address
453 * @param [in] device_address I2C slave address
454 * @param [in] size size of data to be read in bytes
455 * @retval hpm_stat_t status_success if starting transmission without any error
456 */
457 hpm_stat_t i2c_master_start_dma_read(I2C_Type *i2c_ptr, const uint16_t device_address, uint32_t size);
458
459 /**
460 * @brief I2C master read data from certain slave device
461 *
462 * @details Read data from I2C device
463 * @note size should not not greater than I2C_SOC_TRANSFER_COUNT_MAX
464 *
465 * @param [in] ptr I2C base address
466 * @param [in] device_address I2C slave address
467 * @param [out] buf pointer of the buffer to store data read from device
468 * @param [in] size size of data to be read in bytes
469 * @retval hpm_stat_t: status_success if reading is completed without any error
470 */
471 hpm_stat_t i2c_master_read(I2C_Type *ptr,
472 const uint16_t device_address,
473 uint8_t *buf,
474 const uint32_t size);
475 /**
476 * @brief I2C slave initialization
477 *
478 * @details Initialize I2C controller working at slave mode
479 *
480 * @param [in] ptr I2C base address
481 * @param [in] src_clk_in_hz I2C controller source clock source frequency in Hz
482 * @param [in] config I2C configuration structure
483 * @param [in] slave_address I2C address to be used at slave mode
484 * @retval hpm_stat_t: status_success if initialization is completed without any error
485 */
486 hpm_stat_t i2c_init_slave(I2C_Type *ptr, uint32_t src_clk_in_hz,
487 i2c_config_t *config, const uint16_t slave_address);
488
489 /**
490 * @brief I2C slave read data
491 *
492 * @details Read data at slave mode
493 * @note size should not not greater than I2C_SOC_TRANSFER_COUNT_MAX
494 *
495 * @param [in] ptr I2C base address
496 * @param [in] buf pointer of the buffer to store data read from device
497 * @param [in] size size of data to be read in bytes
498 * @retval hpm_stat_t: status_success if reading is completed without any error
499 */
500 hpm_stat_t i2c_slave_read(I2C_Type *ptr, uint8_t *buf, const uint32_t size);
501
502 /**
503 * @brief I2C slave write data
504 *
505 * @details Write data at slave mode.
506 * @note size should not not greater than I2C_SOC_TRANSFER_COUNT_MAX
507 *
508 * @param [in] ptr I2C base address
509 * @param [in] buf pointer of the buffer to store data sent from device
510 * @param [in] size size of data to be sent in bytes
511 * @retval hpm_stat_t status_success if writing is completed without any error
512 */
513 hpm_stat_t i2c_slave_write(I2C_Type *ptr, uint8_t *buf, const uint32_t size);
514
515 /**
516 * @brief reset I2C
517 *
518 * @param [in] ptr I2C base address
519 */
520 void i2c_reset(I2C_Type *ptr);
521
522 /**
523 * @brief Enable i2c DMA
524 *
525 * @param [in] ptr I2C base address
526 */
i2c_dma_enable(I2C_Type * ptr)527 static inline void i2c_dma_enable(I2C_Type *ptr)
528 {
529 ptr->SETUP |= I2C_SETUP_DMAEN_MASK;
530 }
531
532 /**
533 * @brief Disable i2c DMA
534 *
535 * @param [in] ptr I2C base address
536 */
i2c_dma_disable(I2C_Type * ptr)537 static inline void i2c_dma_disable(I2C_Type *ptr)
538 {
539 ptr->SETUP &= ~I2C_SETUP_DMAEN_MASK;
540 }
541
542 /**
543 * @brief I2C slave dma transfer data
544 *
545 * @note The direction of data transmission depends on Master setting
546 *
547 * @param [in] ptr I2C base address
548 * @param [in] size size of data in bytes
549 * @retval hpm_stat_t status_success if configuring transmission without any error
550 */
551 hpm_stat_t i2c_slave_dma_transfer(I2C_Type *ptr, const uint32_t size);
552
553 /**
554 * @brief I2C write byte into FIFO
555 *
556 * @param ptr [in] ptr I2C base address
557 * @param data [in] byte to ne sent
558 */
i2c_write_byte(I2C_Type * ptr,uint8_t data)559 static inline void i2c_write_byte(I2C_Type *ptr, uint8_t data)
560 {
561 ptr->DATA = I2C_DATA_DATA_SET(data);
562 }
563
564 /**
565 * @brief I2C read byte into FIFO
566 *
567 * @param ptr [in] ptr I2C base address
568 * @return uint8_t read byte
569 */
i2c_read_byte(I2C_Type * ptr)570 static inline uint8_t i2c_read_byte(I2C_Type *ptr)
571 {
572 return (uint8_t)I2C_DATA_DATA_GET(ptr->DATA);
573 }
574
575 /**
576 * @brief I2C get direction
577 *
578 * @note The same value has different meanings in master and slave modes
579 *
580 * @param ptr [in] ptr I2C base address
581 * @return uint8_t direction value
582 */
i2c_get_direction(I2C_Type * ptr)583 static inline uint8_t i2c_get_direction(I2C_Type *ptr)
584 {
585 return (uint8_t)I2C_CTRL_DIR_GET(ptr->CTRL);
586 }
587
588 /**
589 * @brief I2C master configure transfer setting
590 *
591 * @param i2c_ptr [in] ptr I2C base address
592 * @param device_address [in] I2C slave address
593 * @param size [in] size of data to be transferred in bytes
594 * @param read [in] true for receive, false for transmit
595 * @retval hpm_stat_t status_success if configuring transmission without any error
596 */
597 hpm_stat_t i2c_master_configure_transfer(I2C_Type *i2c_ptr, const uint16_t device_address, uint32_t size, bool read);
598
599 /**
600 * @brief sequential transmit in master I2C mode an amount of data in blocking
601 *
602 * @param i2c_ptr [in] ptr I2C base address
603 * @param device_address [in] I2C slave address
604 * @param [in] buf pointer of the buffer to store data sent from device
605 * @param [in] size size of data to be sent in bytes
606 * @param [in] opt I2c sequential transfer options
607 * @retval hpm_stat_t status_success if transmit is completed without any error
608 */
609 hpm_stat_t i2c_master_seq_transmit(I2C_Type *ptr, const uint16_t device_address,
610 uint8_t *buf, const uint32_t size, i2c_seq_transfer_opt_t opt);
611
612 /**
613 * @brief sequential receive in master I2C mode an amount of data in blocking
614 *
615 * @param i2c_ptr [in] ptr I2C base address
616 * @param device_address [in] I2C slave address
617 * @param [in] buf pointer of the buffer to store data sent from device
618 * @param [in] size size of data to be sent in bytes
619 * @param [in] opt I2c sequential transfer options
620 * @retval hpm_stat_t status_success if receive is completed without any error
621 */
622 hpm_stat_t i2c_master_seq_receive(I2C_Type *ptr, const uint16_t device_address,
623 uint8_t *buf, const uint32_t size, i2c_seq_transfer_opt_t opt);
624
625 #if defined(I2C_SOC_SUPPORT_RESET) && (I2C_SOC_SUPPORT_RESET == 1)
626 /**
627 * @brief generate SCL clock as reset signal
628 *
629 * @param i2c_ptr [in] ptr I2C base address
630 * @param [in] clk_len SCL clock length
631 */
i2s_gen_reset_signal(I2C_Type * ptr,uint8_t clk_len)632 static inline void i2s_gen_reset_signal(I2C_Type *ptr, uint8_t clk_len)
633 {
634 ptr->CTRL = (ptr->CTRL & ~I2C_CTRL_RESET_LEN_MASK) | I2C_CTRL_RESET_LEN_SET(clk_len) \
635 | I2C_CTRL_RESET_HOLD_SCKIN_MASK | I2C_CTRL_RESET_ON_MASK;
636 }
637 #endif
638
639 /**
640 * @}
641 */
642
643 #ifdef __cplusplus
644 }
645 #endif
646
647 #endif /* HPM_I2C_DRV_H */
648
649