1 /*
2 * Copyright (c) 2022 HPMicro
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 *
6 */
7
8 #ifndef HPM_PLA_DRV_H
9 #define HPM_PLA_DRV_H
10
11 #include "hpm_common.h"
12 #include "hpm_pla_regs.h"
13
14 /**
15 * @brief PLA driver APIs
16 * @defgroup pla_interface PLA driver APIs
17 * @ingroup io_interfaces
18 * @{
19 */
20
21 #define PLA_AOI_16TO8_SIGNAL_NUM (16U)
22 #define PLA_AOI_8TO7_SIGNAL_NUM (8U)
23 #define PLA_CHN_CFG_ACTIVE_WORD (0xF00DU)
24
25 #define PLA_AOI_16TO8_CONNECT_(input, value) \
26 PLA_CHN_AOI_16TO8_AOI_16TO8_##input##_SET(value)
27 /**
28 * @brief Input signal configuration for synthetic aoi_16to8
29 *
30 */
31 #define PLA_AOI_16TO8_CONNECT(input_signal, operation) \
32 PLA_AOI_16TO8_CONNECT_(input_signal, operation)
33
34 /**
35 * @brief aoi_16to8 operation on input signals
36 *
37 */
38 typedef enum pla_aoi_signal_operation_type {
39 pla_aoi_operation_and_0 = 0, /**< signal & 0 */
40 pla_aoi_operation_and_1 = 1, /**< signal & 1 */
41 pla_aoi_operation_xor_1 = 2, /**< signal xor 1 */
42 pla_aoi_operation_or_1 = 3, /**< signal | 1 */
43 } pla_aoi_signal_operation_type_t;
44
45 typedef enum pla_filter_sw_inject_type {
46 pla_filter_sw_inject_low = 0,
47 pla_filter_sw_inject_height = 1,
48 pla_filter_sw_inject_disable = 2,
49 } pla_filter_sw_inject_type_t;
50
51 /**
52 * @brief aoi channel index
53 *
54 */
55 typedef enum pla_channel_type {
56 pla_chn_0 = PLA_CHN_0, /**< channel 0 */
57 pla_chn_1 = PLA_CHN_1, /**< channel 1 */
58 pla_chn_2 = PLA_CHN_2, /**< channel 2 */
59 pla_chn_3 = PLA_CHN_3, /**< channel 3 */
60 pla_chn_4 = PLA_CHN_4, /**< channel 4 */
61 pla_chn_5 = PLA_CHN_5, /**< channel 5 */
62 pla_chn_6 = PLA_CHN_6, /**< channel 6 */
63 pla_chn_7 = PLA_CHN_7, /**< channel 7 */
64 } pla_channel_type_t;
65
66 /**
67 * @brief Raw input signal for aoi16to8 module
68 *
69 */
70 typedef enum pla_aoi_16to8_input_signal_type {
71 pla_level1_filter_out_0 = 0,
72 pla_level1_filter_out_1 = 1,
73 pla_level1_filter_out_2 = 2,
74 pla_level1_filter_out_3 = 3,
75 pla_level1_filter_out_4 = 4,
76 pla_level1_filter_out_5 = 5,
77 pla_level1_filter_out_6 = 6,
78 pla_level1_filter_out_7 = 7,
79 pla_level1_filter_out_8 = 8,
80 pla_level1_filter_out_9 = 9,
81 pla_level1_filter_out_10 = 10,
82 pla_level1_filter_out_11 = 11,
83 pla_level1_filter_out_12 = 12,
84 pla_level1_filter_out_13 = 13,
85 pla_level1_filter_out_14 = 14,
86 pla_level1_filter_out_15 = 15,
87 } pla_aoi_16to8_input_signal_type_t;
88
89 /**
90 * @brief aoi_16to8 channel index
91 *
92 */
93 typedef enum pla_aoi_16to8_channel_type {
94 pla_aoi_16to8_chn_0 = PLA_CHN_AOI_16TO8_AOI_16TO8_00, /**< channel 0 */
95 pla_aoi_16to8_chn_1 = PLA_CHN_AOI_16TO8_AOI_16TO8_01, /**< channel 1 */
96 pla_aoi_16to8_chn_2 = PLA_CHN_AOI_16TO8_AOI_16TO8_02, /**< channel 2 */
97 pla_aoi_16to8_chn_3 = PLA_CHN_AOI_16TO8_AOI_16TO8_03, /**< channel 3 */
98 pla_aoi_16to8_chn_4 = PLA_CHN_AOI_16TO8_AOI_16TO8_04, /**< channel 4 */
99 pla_aoi_16to8_chn_5 = PLA_CHN_AOI_16TO8_AOI_16TO8_05, /**< channel 5 */
100 pla_aoi_16to8_chn_6 = PLA_CHN_AOI_16TO8_AOI_16TO8_06, /**< channel 6 */
101 pla_aoi_16to8_chn_7 = PLA_CHN_AOI_16TO8_AOI_16TO8_07, /**< channel 7 */
102 } pla_aoi_16to8_channel_type_t;
103
104 /**
105 * @brief aoi_16to8 config unit
106 *
107 */
108 typedef struct pla_aoi_16to8_cfg_unit {
109 pla_aoi_16to8_input_signal_type_t signal;
110 pla_aoi_signal_operation_type_t op;
111 } pla_aoi_16to8_cfg_unit_t;
112
113 /**
114 * @brief aoi_16to8 channel config
115 *
116 */
117 typedef struct pla_aoi_16to8_chn_cfg {
118 pla_channel_type_t chn; /**< pla channel */
119 pla_aoi_16to8_channel_type_t aoi_16to8_chn; /**< aoi_16to8 channel */
120 pla_aoi_16to8_cfg_unit_t input[PLA_AOI_16TO8_SIGNAL_NUM]; /**< Configuration of each aoi_16to8 input signal */
121 } pla_aoi_16to8_chn_cfg_t;
122
123 /**
124 * @brief aoi_8_to_7 input signal
125 *
126 */
127 typedef enum pla_aoi_8to7_input_signal_type {
128 pla_level2_filter_out_0 = 0,
129 pla_level2_filter_out_1 = 1,
130 pla_level2_filter_out_2 = 2,
131 pla_level2_filter_out_3 = 3,
132 pla_level2_filter_out_4 = 4,
133 pla_level2_filter_out_5 = 5,
134 pla_level2_filter_out_6 = 6,
135 pla_level2_filter_out_7 = 7,
136 } pla_aoi_8to7_input_signal_type_t;
137
138 /**
139 * @brief aoi_8to7 channel number
140 *
141 */
142 typedef enum pla_aoi_8to7_channel_type {
143 pla_aoi_8to7_chn_0 = 0, /**< channel 0 */
144 pla_aoi_8to7_chn_1 = 1, /**< channel 1 */
145 pla_aoi_8to7_chn_2 = 2, /**< channel 2 */
146 pla_aoi_8to7_chn_3 = 3, /**< channel 3 */
147 pla_aoi_8to7_chn_4 = 4, /**< channel 4 */
148 pla_aoi_8to7_chn_5 = 5, /**< channel 5 */
149 pla_aoi_8to7_chn_6 = 6, /**< channel 6 */
150 } pla_aoi_8to7_channel_type_t;
151
152
153 /**
154 * @brief aoi_8to7 config unit
155 *
156 */
157 typedef struct pla_aoi_8to7_cfg_unit {
158 pla_aoi_8to7_input_signal_type_t signal;
159 pla_aoi_signal_operation_type_t op;
160 } pla_aoi_8to7_cfg_unit_t;
161
162 /**
163 * @brief aoi_8_to_7 channel config
164 *
165 */
166 typedef struct pla_aoi_8to7_chn_cfg {
167 pla_channel_type_t chn; /**< pla channel */
168 pla_aoi_8to7_channel_type_t aoi_8to7_chn; /**< aoi_16to8 channel */
169 pla_aoi_8to7_cfg_unit_t input[PLA_AOI_8TO7_SIGNAL_NUM]; /**< Configuration of each aoi_16to8 input signal */
170 } pla_aoi_8to7_chn_cfg_t;
171
172 /**
173 * @brief pla filter config
174 *
175 */
176 typedef union pla_filter_cfg {
177 struct {
178 uint32_t sync_edge_filter_disable:1;
179 uint32_t software_inject:2;
180 uint32_t filter_reverse:1;
181 uint32_t edge_dect_en:1;
182 uint32_t nege_edge_dect_en:1;
183 uint32_t pose_edge_dect_en:1;
184 uint32_t filter_sync_level:1;
185 uint32_t filter_ext_en:1;
186 uint32_t reserved0:3;
187 uint32_t filter_ext_type:3;
188 uint32_t reserved1:1;
189 uint32_t filter_ext_counter:16;
190 };
191 uint32_t val;
192 } pla_filter_cfg_t;
193
194 /**
195 * @brief pla function selection config
196 *
197 */
198 typedef union pla_ff_cfg {
199 struct {
200 uint32_t sel_cfg_ff_type:3;
201 uint32_t sel_clk_source:1;
202 uint32_t sel_adder_minus:1;
203 uint32_t reserved0:11;
204 uint32_t dis_osc_loop_clamp:1;
205 uint32_t osc_loop_clamp_value:1;
206 uint32_t reserved1:14;
207 };
208 uint32_t val;
209 } pla_ff_cfg_t;
210
211 /**
212 * @brief pla configurable functions
213 *
214 */
215 typedef enum pla_ff_type {
216 pla_ff_type_dff = 0,
217 pla_ff_type_level3_filter0 = 1,
218 pla_ff_type_dual_edge_DFF = 2,
219 pla_ff_type_trigger_ff = 3,
220 pla_ff_type_jk_ff = 4,
221 pla_ff_type_latch = 5,
222 pla_ff_type_adder_minus = 6
223 } pla_ff_type_t;
224
225
226 typedef enum pla_filter1_inchannel_type {
227 pla_filter1_inchn0 = PLA_FILTER_1ST_PLA_IN_FRIST_FILTER_PLA_IN_0,
228 pla_filter1_inchn1 = PLA_FILTER_1ST_PLA_IN_FRIST_FILTER_PLA_IN_1,
229 pla_filter1_inchn2 = PLA_FILTER_1ST_PLA_IN_FRIST_FILTER_PLA_IN_2,
230 pla_filter1_inchn3 = PLA_FILTER_1ST_PLA_IN_FRIST_FILTER_PLA_IN_3,
231 pla_filter1_inchn4 = PLA_FILTER_1ST_PLA_IN_FRIST_FILTER_PLA_IN_4,
232 pla_filter1_inchn5 = PLA_FILTER_1ST_PLA_IN_FRIST_FILTER_PLA_IN_5,
233 pla_filter1_inchn6 = PLA_FILTER_1ST_PLA_IN_FRIST_FILTER_PLA_IN_6,
234 pla_filter1_inchn7 = PLA_FILTER_1ST_PLA_IN_FRIST_FILTER_PLA_IN_7,
235 } pla_filter1_inchannel_type_t;
236
237 typedef enum pla_filter1_outchannel_type {
238 pla_filter1_outchn0 = PLA_FILTER_1ST_PLA_OUT_FRIST_FILTER_PLA_OUT_0,
239 pla_filter1_outchn1 = PLA_FILTER_1ST_PLA_OUT_FRIST_FILTER_PLA_OUT_1,
240 pla_filter1_outchn2 = PLA_FILTER_1ST_PLA_OUT_FRIST_FILTER_PLA_OUT_2,
241 pla_filter1_outchn3 = PLA_FILTER_1ST_PLA_OUT_FRIST_FILTER_PLA_OUT_3,
242 pla_filter1_outchn4 = PLA_FILTER_1ST_PLA_OUT_FRIST_FILTER_PLA_OUT_4,
243 pla_filter1_outchn5 = PLA_FILTER_1ST_PLA_OUT_FRIST_FILTER_PLA_OUT_5,
244 pla_filter1_outchn6 = PLA_FILTER_1ST_PLA_OUT_FRIST_FILTER_PLA_OUT_6,
245 pla_filter1_outchn7 = PLA_FILTER_1ST_PLA_OUT_FRIST_FILTER_PLA_OUT_7,
246 } pla_filter1_outchannel_type_t;
247
248
249 typedef enum pla_filter2_channel_type {
250 pla_filter2_chn0 = PLA_CHN_FILTER_2ND_SECOND_FILTER_0,
251 pla_filter2_chn1 = PLA_CHN_FILTER_2ND_SECOND_FILTER_1,
252 pla_filter2_chn2 = PLA_CHN_FILTER_2ND_SECOND_FILTER_2,
253 pla_filter2_chn3 = PLA_CHN_FILTER_2ND_SECOND_FILTER_3,
254 pla_filter2_chn4 = PLA_CHN_FILTER_2ND_SECOND_FILTER_4,
255 pla_filter2_chn5 = PLA_CHN_FILTER_2ND_SECOND_FILTER_5,
256 pla_filter2_chn6 = PLA_CHN_FILTER_2ND_SECOND_FILTER_6,
257 pla_filter2_chn7 = PLA_CHN_FILTER_2ND_SECOND_FILTER_7,
258 } pla_filter2_channel_type_t;
259
260 typedef enum pla_filter3_channel_type {
261 pla_filter3_chn0 = PLA_CHN_FILTER_3RD_THIRD_FILTER_0,
262 pla_filter3_chn1 = PLA_CHN_FILTER_3RD_THIRD_FILTER_1,
263 pla_filter3_chn2 = PLA_CHN_FILTER_3RD_THIRD_FILTER_2,
264 pla_filter3_chn3 = PLA_CHN_FILTER_3RD_THIRD_FILTER_3,
265 pla_filter3_chn4 = PLA_CHN_FILTER_3RD_THIRD_FILTER_4,
266 pla_filter3_chn5 = PLA_CHN_FILTER_3RD_THIRD_FILTER_5,
267 pla_filter3_chn6 = PLA_CHN_FILTER_3RD_THIRD_FILTER_6,
268 } pla_filter3_channel_type_t;
269
270 #ifdef __cplusplus
271 extern "C" {
272 #endif
273
274 /**
275 * @brief Configure one channel of aoi_16to8
276 *
277 * @param pla @ref PLA_Type
278 * @param cfg @ref pla_aoi_16to8_cfg_t
279 */
280 void pla_set_aoi_16to8_one_channel(PLA_Type * pla,
281 pla_aoi_16to8_chn_cfg_t *cfg);
282
283 /**
284 * @brief Get one channel of aoi_16to8
285 *
286 * @param pla @ref PLA_Type
287 * @param chn @ref pla_channel_type_t
288 * @param aoi_16to8_chn @ref pla_aoi_16to8_channel_type_t
289 * @param cfg @ref pla_aoi_16to8_chn_cfg_t
290 */
291 void pla_get_aoi_16to8_one_channel(PLA_Type *pla,
292 pla_channel_type_t chn,
293 pla_aoi_16to8_channel_type_t aoi_16to8_chn,
294 pla_aoi_16to8_chn_cfg_t *cfg);
295
296 /**
297 * @brief Set one signal of aoi_16to8
298 *
299 * @param pla @ref PLA_Type
300 * @param chn @ref pla_channel_type_t
301 * @param aoi_16to8_chn @ref pla_aoi_16to8_channel_type_t
302 * @param cfg @ref pla_aoi_16to8_cfg_unit_t
303 */
pla_set_aoi_16to8_input_signal(PLA_Type * pla,pla_channel_type_t chn,pla_aoi_16to8_channel_type_t aoi_16to8_chn,pla_aoi_16to8_cfg_unit_t * cfg)304 static inline void pla_set_aoi_16to8_input_signal(PLA_Type *pla,
305 pla_channel_type_t chn,
306 pla_aoi_16to8_channel_type_t aoi_16to8_chn,
307 pla_aoi_16to8_cfg_unit_t *cfg)
308 {
309 pla->CHN[chn].AOI_16TO8[aoi_16to8_chn] = pla->CHN[chn].AOI_16TO8[aoi_16to8_chn] &
310 ~(((uint32_t)cfg->op) << (cfg->signal << 1));
311 }
312
313 /**
314 * @brief Get one signal of aoi_16to8
315 *
316 * @param pla @ref PLA_Type
317 * @param chn @ref pla_channel_type_t
318 * @param aoi_16to8_chn @ref pla_aoi_16to8_channel_type_t
319 * @param signal @ref pla_aoi_16to8_input_signal_type_t
320 * @param cfg @ref pla_aoi_16to8_cfg_unit_t
321 */
pla_get_aoi_16to8_input_signal(PLA_Type * pla,pla_channel_type_t chn,pla_aoi_16to8_channel_type_t aoi_16to8_chn,pla_aoi_16to8_input_signal_type_t signal,pla_aoi_16to8_cfg_unit_t * cfg)322 static inline void pla_get_aoi_16to8_input_signal(PLA_Type *pla,
323 pla_channel_type_t chn,
324 pla_aoi_16to8_channel_type_t aoi_16to8_chn,
325 pla_aoi_16to8_input_signal_type_t signal,
326 pla_aoi_16to8_cfg_unit_t *cfg)
327 {
328 cfg->op = (pla->CHN[chn].AOI_16TO8[aoi_16to8_chn] >> (signal << 1)) & 0x03;
329 cfg->signal = signal;
330 }
331
332
333 /**
334 * @brief Configure one channel of aoi_8to7
335 *
336 * @param pla @ref PLA_Type
337 * @param cfg @ref pla_aoi_8to7_chn_cfg_t
338 */
339 void pla_set_aoi_8to7_one_channel(PLA_Type *pla,
340 pla_aoi_8to7_chn_cfg_t *cfg);
341
342 /**
343 * @brief Get one channel of aoi_8to7
344 *
345 * @param pla @ref PLA_Type
346 * @param cfg @ref pla_aoi_8to7_chn_cfg_t
347 */
348 void pla_get_aoi_8to7_one_channel(PLA_Type *pla,
349 pla_aoi_8to7_chn_cfg_t *cfg);
350
351 /**
352 * @brief Configure one signal of aoi_8to7
353 *
354 * @param pla @ref PLA_Type
355 * @param chn @ref pla_channel_type_t
356 * @param aoi_16to8_chn @ref pla_aoi_8to7_channel_type_t
357 * @param cfg @ref pla_aoi_8to7_cfg_unit_t
358 */
359 void pla_set_aoi_8to7_input_signal(PLA_Type *pla,
360 pla_channel_type_t chn,
361 pla_aoi_8to7_channel_type_t aoi_8to7_chn,
362 pla_aoi_8to7_cfg_unit_t *cfg);
363
364 /**
365 * @brief Get one signal of aoi_8to7
366 *
367 * @param pla @ref PLA_Type
368 * @param chn @ref pla_channel_type_t
369 * @param aoi_8to7_chn @ref pla_aoi_8to7_channel_type_t
370 * @param signal @ref pla_aoi_8to7_input_signal_type_t
371 * @param cfg @ref pla_aoi_8to7_cfg_unit_t
372 */
373 void pla_get_aoi_8to7_input_signal(PLA_Type *pla,
374 pla_channel_type_t chn,
375 pla_aoi_8to7_channel_type_t aoi_8to7_chn,
376 pla_aoi_8to7_input_signal_type_t signal,
377 pla_aoi_8to7_cfg_unit_t *cfg);
378
379 /**
380 * @brief Configure filter1 out
381 *
382 * @param pla @ref PLA_Type
383 * @param filter1_out_chn @ref pla_filter1_outchannel_type_t
384 * @param cfg @ref pla_filter_cfg_t
385 */
pla_set_filter1_out(PLA_Type * pla,pla_filter1_outchannel_type_t filter1_out_chn,pla_filter_cfg_t * cfg)386 static inline void pla_set_filter1_out(PLA_Type *pla,
387 pla_filter1_outchannel_type_t filter1_out_chn,
388 pla_filter_cfg_t *cfg)
389 {
390 pla->FILTER_1ST_PLA_OUT[filter1_out_chn] = cfg->val;
391 }
392
393 /**
394 * @brief Get filter1 out
395 *
396 * @param pla @ref PLA_Type
397 * @param filter1_out_chn @ref pla_filter1_outchannel_type_t
398 * @param cfg @ref pla_filter_cfg_t
399 */
pla_get_filter1_out(PLA_Type * pla,pla_filter1_outchannel_type_t filter1_out_chn,pla_filter_cfg_t * cfg)400 static inline void pla_get_filter1_out(PLA_Type *pla,
401 pla_filter1_outchannel_type_t filter1_out_chn,
402 pla_filter_cfg_t *cfg)
403 {
404 cfg->val = pla->FILTER_1ST_PLA_OUT[filter1_out_chn];
405 }
406
407 /**
408 * @brief Configure filter1 in
409 *
410 * @param pla @ref PLA_Type
411 * @param filter1_in_chn @ref pla_filter1_inchannel_type_t
412 * @param cfg @ref pla_filter_cfg_t
413 */
pla_set_filter1_in(PLA_Type * pla,pla_filter1_inchannel_type_t filter1_in_chn,pla_filter_cfg_t * cfg)414 static inline void pla_set_filter1_in(PLA_Type *pla,
415 pla_filter1_inchannel_type_t filter1_in_chn,
416 pla_filter_cfg_t *cfg)
417 {
418 pla->FILTER_1ST_PLA_IN[filter1_in_chn] = cfg->val;
419 }
420
421 /**
422 * @brief Get filter 1
423 *
424 * @param pla @ref PLA_Type
425 * @param filter1_in_chn @ref pla_filter1_inchannel_type_t
426 * @param cfg @ref pla_filter_cfg_t
427 */
pla_get_filter1_in(PLA_Type * pla,pla_filter1_inchannel_type_t filter1_in_chn,pla_filter_cfg_t * cfg)428 static inline void pla_get_filter1_in(PLA_Type *pla,
429 pla_filter1_inchannel_type_t filter1_in_chn,
430 pla_filter_cfg_t *cfg)
431 {
432 cfg->val = pla->FILTER_1ST_PLA_IN[filter1_in_chn];
433 }
434
435 /**
436 * @brief Configure filter 2
437 *
438 * @param pla @ref PLA_Type
439 * @param chn @ref pla_channel_type_t
440 * @param filter2_chn @ref pla_filter2_channel_type_t
441 * @param cfg @ref pla_filter_cfg_t
442 */
pla_set_filter2(PLA_Type * pla,pla_channel_type_t chn,pla_filter2_channel_type_t filter2_chn,pla_filter_cfg_t * cfg)443 static inline void pla_set_filter2(PLA_Type *pla,
444 pla_channel_type_t chn,
445 pla_filter2_channel_type_t filter2_chn,
446 pla_filter_cfg_t *cfg)
447 {
448 pla->CHN[chn].FILTER_2ND[filter2_chn] = cfg->val;
449 }
450
451 /**
452 * @brief Get filter2
453 *
454 * @param pla @ref PLA_Type
455 * @param chn @ref pla_channel_type_t
456 * @param filter2_chn @ref pla_filter2_channel_type_t
457 * @param cfg @ref pla_filter_cfg_t
458 */
pla_get_filter2(PLA_Type * pla,pla_channel_type_t chn,pla_filter2_channel_type_t filter2_chn,pla_filter_cfg_t * cfg)459 static inline void pla_get_filter2(PLA_Type *pla,
460 pla_channel_type_t chn,
461 pla_filter2_channel_type_t filter2_chn,
462 pla_filter_cfg_t *cfg)
463 {
464 cfg->val = pla->CHN[chn].FILTER_2ND[filter2_chn];
465 }
466
467 /**
468 * @brief Configure filter3
469 *
470 * @param pla @ref PLA_Type
471 * @param chn @ref pla_channel_type_t
472 * @param filter3_chn @ref pla_filter3_channel_type_t
473 * @param cfg @ref pla_filter_cfg_t
474 */
pla_set_filter3(PLA_Type * pla,pla_channel_type_t chn,pla_filter3_channel_type_t filter3_chn,pla_filter_cfg_t * cfg)475 static inline void pla_set_filter3(PLA_Type *pla,
476 pla_channel_type_t chn,
477 pla_filter3_channel_type_t filter3_chn,
478 pla_filter_cfg_t *cfg)
479 {
480 pla->CHN[chn].FILTER_3RD[filter3_chn] = cfg->val;
481 }
482
483 /**
484 * @brief Get filter3
485 *
486 * @param pla @ref PLA_Type
487 * @param chn @ref pla_channel_type_t
488 * @param filter3_chn @ref pla_filter3_channel_type_t
489 * @param cfg @ref pla_filter_cfg_t
490 */
pla_get_filter3(PLA_Type * pla,pla_channel_type_t chn,pla_filter3_channel_type_t filter3_chn,pla_filter_cfg_t * cfg)491 static inline void pla_get_filter3(PLA_Type *pla,
492 pla_channel_type_t chn,
493 pla_filter3_channel_type_t filter3_chn,
494 pla_filter_cfg_t *cfg)
495 {
496 cfg->val = pla->CHN[chn].FILTER_3RD[filter3_chn];
497 }
498
499 /**
500 * @brief Set ff function
501 *
502 * @param pla @ref PLA_Type
503 * @param chn @ref pla_channel_type_t
504 * @param cfg @ref pla_ff_cfg_t
505 */
pla_set_ff(PLA_Type * pla,pla_channel_type_t chn,pla_ff_cfg_t * cfg)506 static inline void pla_set_ff(PLA_Type *pla,
507 pla_channel_type_t chn,
508 pla_ff_cfg_t *cfg)
509 {
510 pla->CHN[chn].CFG_FF = cfg->val;
511 }
512
513 /**
514 * @brief Get ff function
515 *
516 * @param pla @ref PLA_Type
517 * @param chn @ref pla_channel_type_t
518 * @param cfg @ref pla_ff_cfg_t
519 */
pla_get_ff(PLA_Type * pla,pla_channel_type_t chn,pla_ff_cfg_t * cfg)520 static inline void pla_get_ff(PLA_Type *pla,
521 pla_channel_type_t chn,
522 pla_ff_cfg_t *cfg)
523 {
524 cfg->val = pla->CHN[chn].CFG_FF;
525 }
526
527 /**
528 * @brief enable pla channel
529 *
530 * @param pla @ref PLA_Type
531 * @param chn @ref pla_channel_type_t
532 */
pla_channel_enable(PLA_Type * pla,pla_channel_type_t chn)533 static inline void pla_channel_enable(PLA_Type *pla,
534 pla_channel_type_t chn)
535 {
536 pla->CHN_CFG_ACTIVE[chn] = PLA_CHN_CFG_ACTIVE_WORD;
537 }
538
539 /**
540 * @brief disable pla channel
541 *
542 * @param pla @ref PLA_Type
543 * @param chn @ref pla_channel_type_t
544 */
pla_channel_disable(PLA_Type * pla,pla_channel_type_t chn)545 static inline void pla_channel_disable(PLA_Type *pla,
546 pla_channel_type_t chn)
547 {
548 pla->CHN_CFG_ACTIVE[chn] = false;
549 }
550
551 /**
552 * @}
553 */
554
555 #ifdef __cplusplus
556 }
557 #endif
558
559 #endif /* HPM_PLA_DRV_H */
560
561