1 /*
2 * Copyright (c) 2022 HPMicro
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 *
6 */
7
8 #ifndef HPM_PLLCTLV2_DRV_H
9 #define HPM_PLLCTLV2_DRV_H
10
11
12 #include "hpm_common.h"
13 #include "hpm_soc_feature.h"
14 #include "hpm_pllctlv2_regs.h"
15
16 #define PLLCTLV2_CLK_SRC_XTAL24M (0U)
17 #define PLLCTLV2_CLK_SRC_IRC24M (1U)
18
19 /**
20 * @brief PLLCTLV2 driver APIs
21 * @defgroup pllctlv2_interface PLLCTLV2 driver APIs
22 * @{
23 */
24
25 /**
26 * @brief Check if external crystal is stable
27 * @param [in] ptr PLLCTLV2 base address
28 * @return true if external crystal is stable
29 */
pllctlv2_xtal_is_stable(PLLCTLV2_Type * ptr)30 static inline bool pllctlv2_xtal_is_stable(PLLCTLV2_Type *ptr)
31 {
32 return IS_HPM_BITMASK_SET(ptr->XTAL, PLLCTLV2_XTAL_RESPONSE_MASK);
33 }
34
35 /**
36 * @brief Check if external crystal is enabled
37 * @param [in] ptr PLLCTLV2 base address
38 * @return true if external crystal is enabled
39 */
pllctlv2_xtal_is_enabled(PLLCTLV2_Type * ptr)40 static inline bool pllctlv2_xtal_is_enabled(PLLCTLV2_Type *ptr)
41 {
42 return IS_HPM_BITMASK_SET(ptr->XTAL, PLLCTLV2_XTAL_ENABLE_MASK);
43 }
44
45 /**
46 * @brief Set external crystal ramp-up time
47 * @param [in] ptr PLLCTLV2 base address
48 * @param [in] rc24m_cycles Cycles of RC24M clock
49 */
pllctlv2_xtal_set_rampup_time(PLLCTLV2_Type * ptr,uint32_t rc24m_cycles)50 static inline void pllctlv2_xtal_set_rampup_time(PLLCTLV2_Type *ptr, uint32_t rc24m_cycles)
51 {
52 ptr->XTAL = (ptr->XTAL & ~PLLCTLV2_XTAL_RAMP_TIME_MASK) | PLLCTLV2_XTAL_RAMP_TIME_SET(rc24m_cycles);
53 }
54
55 /**
56 * @brief Check is PLL is stable
57 * @param [in] ptr PLLCTLv2 base address
58 * @param [in] pll PLL index
59 * @return true if PLL is stable
60 */
pllctlv2_pll_is_stable(PLLCTLV2_Type * ptr,uint8_t pll)61 static inline bool pllctlv2_pll_is_stable(PLLCTLV2_Type *ptr, uint8_t pll)
62 {
63 return IS_HPM_BITMASK_SET(ptr->PLL[pll].MFI, PLLCTLV2_PLL_MFI_RESPONSE_MASK);
64 }
65
66 /**
67 * @brief Check if PLL is enabled
68 * @param [in] ptr PLLCTLV2 base address
69 * @param [in] pll PLL index
70 * @return true if PLL is enabled
71 */
pllctlv2_pll_is_enabled(PLLCTLV2_Type * ptr,uint8_t pll)72 static inline bool pllctlv2_pll_is_enabled(PLLCTLV2_Type *ptr, uint8_t pll)
73 {
74 return IS_HPM_BITMASK_SET(ptr->PLL[pll].MFI, PLLCTLV2_PLL_MFI_ENABLE_MASK);
75 }
76
77 /**
78 * @brief Select the PLL reference clock
79 * @param [in] ptr PLLCTLV2 base address
80 * @param [in] pll PLL index
81 * @param [in] src PLL reference lcock source
82 * @arg 0 - XTAL24M
83 * @arg 1 - IRC24M
84 */
pllctlv2_select_reference_clock(PLLCTLV2_Type * ptr,uint8_t pll,uint8_t src)85 static inline void pllctlv2_select_reference_clock(PLLCTLV2_Type *ptr, uint8_t pll, uint8_t src)
86 {
87 ptr->PLL[pll].CONFIG = (ptr->PLL[pll].CONFIG & PLLCTLV2_PLL_CONFIG_REFSEL_MASK) | PLLCTLV2_PLL_CONFIG_REFSEL_SET(src);
88 }
89
90 /**
91 * @brief Enable PLL Spread Spectrum feature
92 * @param [in] ptr PLLCTLV2 base address
93 * @param [in] pll PLL index
94 * @param [in] step Step of spread spectrum modulator
95 * @param [in] stop Stop point of spread spectrum modulator
96 */
97 void pllctlv2_enable_spread_spectrum(PLLCTLV2_Type *ptr, uint8_t pll, uint32_t step, uint32_t stop);
98
99 /**
100 * @brief Disable PLL Spread spectrum
101 * @param [in] ptr PLLCTLV2 base address
102 * @param [in] pll PLL index
103 */
pllctlv2_disable_spread_spectrum(PLLCTLV2_Type * ptr,uint8_t pll)104 static inline void pllctlv2_disable_spread_spectrum(PLLCTLV2_Type *ptr, uint8_t pll)
105 {
106 ptr->PLL[pll].CONFIG &= ~PLLCTLV2_PLL_CONFIG_SPREAD_MASK;
107 }
108
109 /**
110 * @brief Set PLL lock time
111 * @param [in] ptr PLLCTLV2 base address
112 * @param [in] pll PLL index
113 * @param [in] xtal_cycles external Crystal cycles
114 */
pllctlv2_set_pll_lock_time(PLLCTLV2_Type * ptr,uint8_t pll,uint32_t xtal_cycles)115 static inline void pllctlv2_set_pll_lock_time(PLLCTLV2_Type *ptr, uint8_t pll, uint32_t xtal_cycles)
116 {
117 ptr->PLL[pll].LOCKTIME = PLLCTLV2_PLL_LOCKTIME_LOCKTIME_SET(xtal_cycles);
118 }
119
120 /**
121 * @brief Set PLL step time
122 * @param [in] ptr PLLCTLV2 base address
123 * @param [in] pll PLL index
124 * @param [in] xtal_cycles external Crystal cycles
125 */
pllctlv2_set_pll_step_time(PLLCTLV2_Type * ptr,uint8_t pll,uint32_t xtal_cycles)126 static inline void pllctlv2_set_pll_step_time(PLLCTLV2_Type *ptr, uint8_t pll, uint32_t xtal_cycles)
127 {
128 ptr->PLL[pll].STEPTIME = PLLCTLV2_PLL_STEPTIME_STEPTIME_SET(xtal_cycles);
129 }
130
131 /**
132 * @brief Set PLL Post divider
133 * @param [in] ptr PLLCTLV2 base
134 * @param [in] pll PLL index
135 * @param [in] div_index Divider index
136 * @param [in] div_value divider value, divider factor is 1 + div_value / 5
137 */
138 void pllctlv2_set_postdiv(PLLCTLV2_Type *ptr, uint8_t pll, uint8_t div_index, uint8_t div_value);
139
140 /**
141 * @brief Initialize PLL to specified frequency
142 * Note: the specified PLL clock needs to be enabled before being configured
143 * @param [in] ptr PLLCTLV2 base
144 * @param [in] pll PLL index
145 * @param [in] freq_in_hz expected PLL frequency
146 * @retval status_invalid_argument some parameters are invalid
147 * @retval status_success operation is successful
148 */
149 hpm_stat_t pllctlv2_init_pll_with_freq(PLLCTLV2_Type *ptr, uint8_t pll, uint32_t freq_in_hz);
150
151 /**
152 * @brief Get the specified PLl clock frequency
153 * @param [in] ptr PLLCTLV2 base
154 * @param [in] pll PLL index
155 * @return PLL frequency in Hz
156 */
157 uint32_t pllctlv2_get_pll_freq_in_hz(PLLCTLV2_Type *ptr, uint8_t pll);
158
159 /**
160 * @brief Get the selected PLL post divider frequency
161 * @param [in] ptr PLLCTLV2 base
162 * @param [in] pll PLL index
163 * @param [in] div_index Post divider index
164 * @return PLL frequency in Hz
165 */
166 uint32_t pllctlv2_get_pll_postdiv_freq_in_hz(PLLCTLV2_Type *ptr, uint8_t pll, uint8_t div_index);
167
168
169 /**
170 * @}
171 */
172 #endif /* HPM_PLLCTLV2_DRV_H */
173