1 /*
2 * Copyright (c) 2023 HPMicro
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 *
6 */
7
8 #ifndef HPM_QEIV2_DRV_H
9 #define HPM_QEIV2_DRV_H
10
11 #include "hpm_common.h"
12 #include "hpm_qeiv2_regs.h"
13 /**
14 * @brief QEIV2 driver APIs
15 * @defgroup qeiv2_interface QEIV2 driver APIs
16 * @ingroup io_interfaces
17 * @{
18 */
19 #define QEIV2_EVENT_WDOG_FLAG_MASK (1U << 31U) /**< watchdog flag */
20 #define QEIV2_EVENT_HOME_FLAG_MASK (1U << 30U) /**< home flag */
21 #define QEIV2_EVENT_POSITION_COMPARE_FLAG_MASK (1U << 29U) /**< postion compare match flag */
22 #define QEIV2_EVENT_Z_PHASE_FLAG_MASK (1U << 28U) /**< z input flag */
23 #define QEIV2_EVENT_Z_MISS_FLAG_MASK (1U << 27U) /**< z miss flag */
24 #define QEIV2_EVENT_WIDTH_TIME_FLAG_MASK (1U << 26U) /**< width time flag */
25 #define QEIV2_EVENT_POSITION2_COMPARE_FLAG_MASK (1U << 25U) /**< postion2 compare match flag */
26 #define QEIV2_EVENT_DIR_CHG_FLAG_MASK (1U << 24U) /**< direction change flag */
27 #define QEIV2_EVENT_CYCLE0_FLAG_MASK (1U << 23U) /**< cycle0 flag */
28 #define QEIV2_EVENT_CYCLE1_FLAG_MASK (1U << 22U) /**< cycle1 flag */
29 #define QEIV2_EVENT_PULSE0_FLAG_MASK (1U << 21U) /**< pulse0 flag */
30 #define QEIV2_EVENT_PULSE1_FLAG_MASK (1U << 20U) /**< pulse1 flag */
31 #define QEIV2_EVENT_HOME2_FLAG_MASK (1U << 19U) /**< home2 flag */
32 #define QEIV2_EVENT_FAULT_FLAG_MASK (1U << 18U) /**< fault flag */
33
34 /**
35 * @brief qeiv2 work mode
36 *
37 */
38 typedef enum qeiv2_work_mode {
39 qeiv2_work_mode_abz = 0, /**< Orthogonal decoder mode */
40 qeiv2_work_mode_pd = 1, /**< Directional (PD) mode */
41 qeiv2_work_mode_ud = 2, /**< Up and Down (UD) mode */
42 qeiv2_work_mode_uvw = 3, /**< UVW mode */
43 qeiv2_work_mode_single = 4, /**< Single-phase mode */
44 qeiv2_work_mode_sin = 5, /**< Single sinewave mode */
45 qeiv2_work_mode_sincos = 6, /**< Orthogonal sinewave mode */
46 } qeiv2_work_mode_t;
47
48 /**
49 * @brief spd and tmr read selection
50 *
51 */
52 typedef enum qeiv2_spd_tmr_content {
53 qeiv2_spd_tmr_as_spd_tm = 0, /**< spd and timer register as spd and time */
54 qeiv2_spd_tmr_as_pos_angle = 1, /**< spd and timer register as position and angle */
55 } qeiv2_spd_tmr_content_t;
56
57 /**
58 * @brief compare match rotate direction
59 *
60 */
61 typedef enum qeiv2_rotate_dir {
62 qeiv2_rotate_dir_forward = 0,
63 qeiv2_rotate_dir_reverse = 1,
64 } qeiv2_rotate_dir_t; /**< compare match rotate direction */
65
66 /**
67 * @brief compare match position direction
68 *
69 */
70 typedef enum qeiv2_position_dir {
71 qeiv2_pos_dir_decrease = 0,
72 qeiv2_pos_dir_increase = 1,
73 } qeiv2_position_dir_t; /**< compare match position direction */
74
75 /**
76 * @brief counting mode of Z-phase counter
77 *
78 */
79 typedef enum qeiv2_z_count_work_mode {
80 qeiv2_z_count_inc_on_z_input_assert = 0, /**< zcnt will increment or decrement when Z input assert */
81 qeiv2_z_count_inc_on_phase_count_max = 1, /**< zcnt will increment when phcnt upcount to phmax, decrement when phcnt downcount to 0 */
82 } qeiv2_z_count_work_mode_t;
83
84 /**
85 * @brief counter type
86 *
87 */
88 typedef enum qeiv2_counter_type {
89 qeiv2_counter_type_z = 0, /**< Z counter */
90 qeiv2_counter_type_phase = 1, /**< Phase counter */
91 qeiv2_counter_type_speed = 2, /**< Speed counter */
92 qeiv2_counter_type_timer = 3, /**< Timer counter */
93 } qeiv2_counter_type_t;
94
95 /**
96 * @brief filter mode
97 *
98 */
99 typedef enum qeiv2_filter_mode {
100 qeiv2_filter_mode_bypass = 0, /**< bypass */
101 qeiv2_filter_mode_burr = 4, /**< rapid change mode */
102 qeiv2_filter_mode_delay, /**< delay filter mode */
103 qeiv2_filter_mode_peak, /**< stable low mode */
104 qeiv2_filter_mode_valley, /**< stable high mode */
105 } qeiv2_filter_mode_t;
106
107 /**
108 * @brief filter type
109 *
110 */
111 typedef enum qeiv2_filter_phase {
112 qeiv2_filter_phase_a = 0, /**< filter phase a */
113 qeiv2_filter_phase_b, /**< filter phase b */
114 qeiv2_filter_phase_z, /**< filter phase z */
115 qeiv2_filter_phase_h, /**< filter phase h */
116 qeiv2_filter_phase_h2, /**< filter phase h2 */
117 qeiv2_filter_phase_f, /**< filter phase f */
118 } qeiv2_filter_phase_t; /**< qeiv2_filter_phase_t */
119
120 /**
121 * @brief uvw position option
122 *
123 */
124 typedef enum qeiv2_uvw_pos_opt {
125 qeiv2_uvw_pos_opt_current = 0, /**< output exact point position, MMC use this */
126 qeiv2_uvw_pos_opt_next, /**< output next area position, QEO use this */
127 } qeiv2_uvw_pos_opt_t;
128
129 typedef enum qeiv2_uvw_pos_sel {
130 qeiv2_uvw_pos_sel_low = 0,
131 qeiv2_uvw_pos_sel_high,
132 qeiv2_uvw_pos_sel_edge
133 } qeiv2_uvw_pos_sel_t; /**< qeiv2_uvw_pos_sel_t */
134
135 /**
136 * @brief qeiv2 uvw position selection
137 *
138 */
139 #define QEIV2_UVW_POS_OPT_CUR_SEL_LOW 0u
140 #define QEIV2_UVW_POS_OPT_CUR_SEL_HIGH 1u
141 #define QEIV2_UVW_POS_OPT_CUR_SEL_EDGE 2u
142 #define QEIV2_UVW_POS_OPT_NEX_SEL_LOW 0u
143 #define QEIV2_UVW_POS_OPT_NEX_SEL_HIGH 3u
144
145 typedef enum qeiv2_uvw_pos_idx {
146 qeiv2_uvw_pos0 = 0,
147 qeiv2_uvw_pos1,
148 qeiv2_uvw_pos2,
149 qeiv2_uvw_pos3,
150 qeiv2_uvw_pos4,
151 qeiv2_uvw_pos5,
152 } qeiv2_uvw_pos_idx_t; /**< qeiv2_uvw_pos_idx_t */
153
154 /**
155 * @brief phase counter compare match config structure
156 *
157 */
158 typedef struct {
159 uint32_t phcnt_cmp_value;
160 bool ignore_rotate_dir;
161 qeiv2_rotate_dir_t rotate_dir;
162 bool ignore_zcmp;
163 uint32_t zcmp_value;
164 } qeiv2_phcnt_cmp_match_config_t;
165
166 /**
167 * @brief position compare match config structure
168 *
169 */
170 typedef struct {
171 uint32_t pos_cmp_value;
172 bool ignore_pos_dir;
173 qeiv2_position_dir_t pos_dir;
174 } qeiv2_pos_cmp_match_config_t;
175
176 /**
177 * @brief uvw config structure
178 */
179 typedef struct {
180 qeiv2_uvw_pos_opt_t pos_opt;
181 qeiv2_uvw_pos_sel_t u_pos_sel[6];
182 qeiv2_uvw_pos_sel_t v_pos_sel[6];
183 qeiv2_uvw_pos_sel_t w_pos_sel[6];
184 uint32_t pos_cfg[6];
185 } qeiv2_uvw_config_t;
186
187 /**
188 * @brief adc config structure
189 */
190 typedef struct {
191 uint8_t adc_select;
192 uint8_t adc_channel;
193 int16_t param0;
194 int16_t param1;
195 uint32_t offset;
196 } qeiv2_adc_config_t;
197
198 #ifdef __cplusplus
199 extern "C" {
200 #endif
201
202 /**
203 * @brief load phcnt, zcnt, spdcnt and tmrcnt into their read registers
204 *
205 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
206 */
qeiv2_load_counter_to_read_registers(QEIV2_Type * qeiv2_x)207 static inline void qeiv2_load_counter_to_read_registers(QEIV2_Type *qeiv2_x)
208 {
209 qeiv2_x->CR |= QEIV2_CR_READ_MASK;
210 }
211
212 /**
213 * @brief config z phase counter increment and decrement mode
214 *
215 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
216 * @param[in] mode
217 * @arg 1 zcnt will increment when phcnt upcount to phmax, decrement when phcnt downcount to 0
218 * @arg 0 zcnt will increment or decrement when Z input assert
219 */
qeiv2_config_z_phase_counter_mode(QEIV2_Type * qeiv2_x,qeiv2_z_count_work_mode_t mode)220 static inline void qeiv2_config_z_phase_counter_mode(QEIV2_Type *qeiv2_x, qeiv2_z_count_work_mode_t mode)
221 {
222 qeiv2_x->CR = (qeiv2_x->CR & ~QEIV2_CR_ZCNTCFG_MASK) | QEIV2_CR_ZCNTCFG_SET(mode);
223 }
224
225 /**
226 * @brief config phase max value and phase param
227 *
228 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
229 * @param[in] phmax maximum phcnt number, phcnt will rollover to 0 when it upcount to phmax
230 */
qeiv2_config_phmax_phparam(QEIV2_Type * qeiv2_x,uint32_t phmax)231 static inline void qeiv2_config_phmax_phparam(QEIV2_Type *qeiv2_x, uint32_t phmax)
232 {
233 uint32_t tmp;
234
235 if (phmax > 0u) {
236 phmax--;
237 }
238 qeiv2_x->PHCFG = QEIV2_PHCFG_PHMAX_SET(phmax);
239 if (phmax == 0u) {
240 qeiv2_x->PHASE_PARAM = 0xFFFFFFFFu;
241 } else {
242 tmp = (0x80000000u / (phmax + 1u));
243 tmp <<= 1u;
244 qeiv2_x->PHASE_PARAM = QEIV2_PHASE_PARAM_PHASE_PARAM_SET(tmp);
245 }
246 }
247
248 /**
249 * @brief config phase calibration value trigged by z phase
250 *
251 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
252 * @param[in] enable phcnt will set to phidx when Z input assert
253 * @param[in] phidx phcnt reset value
254 * @param[in] mode qeiv2_work_mode_t
255 */
qeiv2_config_z_phase_calibration(QEIV2_Type * qeiv2_x,uint32_t phidx,bool enable,qeiv2_work_mode_t mode)256 static inline void qeiv2_config_z_phase_calibration(QEIV2_Type *qeiv2_x, uint32_t phidx, bool enable, qeiv2_work_mode_t mode)
257 {
258 uint32_t tmp = qeiv2_x->CR;
259 qeiv2_x->PHIDX = QEIV2_PHIDX_PHIDX_SET(phidx);
260 if (enable) {
261 tmp |= QEIV2_CR_PHCALIZ_MASK;
262 } else {
263 tmp &= ~QEIV2_CR_PHCALIZ_MASK;
264 }
265 if (enable && ((mode == qeiv2_work_mode_sin) || (mode == qeiv2_work_mode_sincos))) {
266 tmp |= QEIV2_CR_Z_ONLY_EN_MASK;
267 } else {
268 tmp &= ~QEIV2_CR_Z_ONLY_EN_MASK;
269 }
270 qeiv2_x->CR = tmp;
271 }
272
273 /**
274 * @brief pause counter when pause assert
275 *
276 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
277 * @param[in] counter_mask
278 * @arg QEIV2_CR_PAUSEPOS_MASK
279 * @arg QEIV2_CR_PAUSESPD_MASK
280 * @arg QEIV2_CR_PAUSEPH_MASK
281 * @arg QEIV2_CR_PAUSEZ_MASK
282 * @param[in] enable enable or disable pause
283 */
qeiv2_pause_counter(QEIV2_Type * qeiv2_x,uint32_t counter_mask,bool enable)284 static inline void qeiv2_pause_counter(QEIV2_Type *qeiv2_x, uint32_t counter_mask, bool enable)
285 {
286 if (enable) {
287 qeiv2_x->CR |= counter_mask;
288 } else {
289 qeiv2_x->CR &= ~counter_mask;
290 }
291 }
292
293 /**
294 * @brief pause pos counter when fault assert
295 *
296 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
297 * @param[in] enable enable or disable pause
298 */
qeiv2_pause_pos_counter_on_fault(QEIV2_Type * qeiv2_x,bool enable)299 static inline void qeiv2_pause_pos_counter_on_fault(QEIV2_Type *qeiv2_x, bool enable)
300 {
301 if (enable) {
302 qeiv2_x->CR |= QEIV2_CR_FAULTPOS_MASK;
303 } else {
304 qeiv2_x->CR &= ~QEIV2_CR_FAULTPOS_MASK;
305 }
306 }
307
308 /**
309 * @brief enable load phcnt, zcnt, spdcnt and tmrcnt into their snap registers
310 *
311 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
312 */
qeiv2_enable_snap(QEIV2_Type * qeiv2_x)313 static inline void qeiv2_enable_snap(QEIV2_Type *qeiv2_x)
314 {
315 qeiv2_x->CR |= QEIV2_CR_SNAPEN_MASK;
316 }
317
318 /**
319 * @brief disable snap
320 *
321 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
322 */
qeiv2_disable_snap(QEIV2_Type * qeiv2_x)323 static inline void qeiv2_disable_snap(QEIV2_Type *qeiv2_x)
324 {
325 qeiv2_x->CR &= ~QEIV2_CR_SNAPEN_MASK;
326 }
327
328 /**
329 * @brief reset zcnt, spdcnt and tmrcnt to 0, reset phcnt to phidx.
330 *
331 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
332 */
qeiv2_reset_counter(QEIV2_Type * qeiv2_x)333 static inline void qeiv2_reset_counter(QEIV2_Type *qeiv2_x)
334 {
335 qeiv2_x->CR |= QEIV2_CR_RSTCNT_MASK;
336 }
337
338 /**
339 * @brief release counter.
340 *
341 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
342 */
qeiv2_release_counter(QEIV2_Type * qeiv2_x)343 static inline void qeiv2_release_counter(QEIV2_Type *qeiv2_x)
344 {
345 qeiv2_x->CR &= ~QEIV2_CR_RSTCNT_MASK;
346 }
347
348 /**
349 * @brief select spd and tmr register content
350 *
351 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
352 * @param[in] mode @ref qeiv2_spd_tmr_content_select_t
353 */
qeiv2_select_spd_tmr_register_content(QEIV2_Type * qeiv2_x,qeiv2_spd_tmr_content_t content)354 static inline void qeiv2_select_spd_tmr_register_content(QEIV2_Type *qeiv2_x, qeiv2_spd_tmr_content_t content)
355 {
356 qeiv2_x->CR = (qeiv2_x->CR & ~QEIV2_CR_RD_SEL_MASK) | QEIV2_CR_RD_SEL_SET(content);
357 }
358
359 /**
360 * @brief check spd and tmr register content as pos and angle
361 *
362 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
363 * @return true if spd and timer register as pos and angle register
364 */
qeiv2_check_spd_tmr_as_pos_angle(QEIV2_Type * qeiv2_x)365 static inline bool qeiv2_check_spd_tmr_as_pos_angle(QEIV2_Type *qeiv2_x)
366 {
367 return ((qeiv2_x->CR & QEIV2_CR_RD_SEL_MASK) != 0) ? true : false;
368 }
369
370 /**
371 * @brief set qeiv2 work mode
372 *
373 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
374 * @param[in] mode @ref qeiv2_work_mode_t
375 */
qeiv2_set_work_mode(QEIV2_Type * qeiv2_x,qeiv2_work_mode_t mode)376 static inline void qeiv2_set_work_mode(QEIV2_Type *qeiv2_x, qeiv2_work_mode_t mode)
377 {
378 qeiv2_x->CR = (qeiv2_x->CR & ~QEIV2_CR_ENCTYP_MASK) | QEIV2_CR_ENCTYP_SET(mode);
379 }
380
381 /**
382 * @brief config watchdog
383 *
384 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
385 * @param[in] timeout watchdog timeout time
386 * @param[in] clr_phcnt the phase_cnt time passed, then clear wdog counter
387 * @param[in] enable
388 * @arg 1 - enable watchdog
389 * @arg 0 - disable watchdog
390 */
qeiv2_config_wdog(QEIV2_Type * qeiv2_x,uint32_t timeout,uint8_t clr_phcnt,bool enable)391 static inline void qeiv2_config_wdog(QEIV2_Type *qeiv2_x, uint32_t timeout, uint8_t clr_phcnt, bool enable)
392 {
393 uint32_t tmp;
394 tmp = QEIV2_WDGCFG_WDGTO_SET(timeout) | QEIV2_WDGCFG_WDOG_CFG_SET(clr_phcnt);
395 if (enable) {
396 tmp |= QEIV2_WDGCFG_WDGEN_MASK;
397 } else {
398 tmp &= ~QEIV2_WDGCFG_WDGEN_MASK;
399 }
400 qeiv2_x->WDGCFG = tmp;
401 }
402
403 /**
404 * @brief enable trig out trigger event
405 *
406 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
407 * @param[in] event_mask
408 * @arg @ref QEIV2_EVENT_WDOG_FLAG_MASK
409 * @arg @ref QEIV2_EVENT_HOME_FLAG_MASK
410 * @arg @ref QEIV2_EVENT_POSITION_COMPARE_FLAG_MASK
411 * @arg @ref QEIV2_EVENT_Z_PHASE_FLAG_MASK
412 * @arg @ref QEIV2_EVENT_Z_MISS_FLAG_MASK
413 * @arg @ref QEIV2_EVENT_WIDTH_TIME_FLAG_MASK
414 * @arg @ref QEIV2_EVENT_POSITION2_COMPARE_FLAG_MASK
415 * @arg @ref QEIV2_EVENT_DIR_CHG_FLAG_MASK
416 * @arg @ref QEIV2_EVENT_CYCLE0_FLAG_MASK
417 * @arg @ref QEIV2_EVENT_CYCLE1_FLAG_MASK
418 * @arg @ref QEIV2_EVENT_PULSE0_FLAG_MASK
419 * @arg @ref QEIV2_EVENT_PULSE1_FLAG_MASK
420 * @arg @ref QEIV2_EVENT_HOME2_FLAG_MASK
421 * @arg @ref QEIV2_EVENT_FAULT_FLAG_MASK
422 */
qeiv2_enable_trig_out_trigger_event(QEIV2_Type * qeiv2_x,uint32_t event_mask)423 static inline void qeiv2_enable_trig_out_trigger_event(QEIV2_Type *qeiv2_x, uint32_t event_mask)
424 {
425 qeiv2_x->TRGOEN |= event_mask;
426 }
427
428 /**
429 * @brief disable trig out trigger event
430 *
431 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
432 * @param[in] event_mask
433 * @arg @ref QEIV2_EVENT_WDOG_FLAG_MASK
434 * @arg @ref QEIV2_EVENT_HOME_FLAG_MASK
435 * @arg @ref QEIV2_EVENT_POSITION_COMPARE_FLAG_MASK
436 * @arg @ref QEIV2_EVENT_Z_PHASE_FLAG_MASK
437 * @arg @ref QEIV2_EVENT_Z_MISS_FLAG_MASK
438 * @arg @ref QEIV2_EVENT_WIDTH_TIME_FLAG_MASK
439 * @arg @ref QEIV2_EVENT_POSITION2_COMPARE_FLAG_MASK
440 * @arg @ref QEIV2_EVENT_DIR_CHG_FLAG_MASK
441 * @arg @ref QEIV2_EVENT_CYCLE0_FLAG_MASK
442 * @arg @ref QEIV2_EVENT_CYCLE1_FLAG_MASK
443 * @arg @ref QEIV2_EVENT_PULSE0_FLAG_MASK
444 * @arg @ref QEIV2_EVENT_PULSE1_FLAG_MASK
445 * @arg @ref QEIV2_EVENT_HOME2_FLAG_MASK
446 * @arg @ref QEIV2_EVENT_FAULT_FLAG_MASK
447 */
qeiv2_disable_trig_out_trigger_event(QEIV2_Type * qeiv2_x,uint32_t event_mask)448 static inline void qeiv2_disable_trig_out_trigger_event(QEIV2_Type *qeiv2_x, uint32_t event_mask)
449 {
450 qeiv2_x->TRGOEN &= ~event_mask;
451 }
452
453 /**
454 * @brief enable load read trigger event
455 *
456 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
457 * @param[in] event_mask
458 * @arg @ref QEIV2_EVENT_WDOG_FLAG_MASK
459 * @arg @ref QEIV2_EVENT_HOME_FLAG_MASK
460 * @arg @ref QEIV2_EVENT_POSITION_COMPARE_FLAG_MASK
461 * @arg @ref QEIV2_EVENT_Z_PHASE_FLAG_MASK
462 * @arg @ref QEIV2_EVENT_Z_MISS_FLAG_MASK
463 * @arg @ref QEIV2_EVENT_WIDTH_TIME_FLAG_MASK
464 * @arg @ref QEIV2_EVENT_POSITION2_COMPARE_FLAG_MASK
465 * @arg @ref QEIV2_EVENT_DIR_CHG_FLAG_MASK
466 * @arg @ref QEIV2_EVENT_CYCLE0_FLAG_MASK
467 * @arg @ref QEIV2_EVENT_CYCLE1_FLAG_MASK
468 * @arg @ref QEIV2_EVENT_PULSE0_FLAG_MASK
469 * @arg @ref QEIV2_EVENT_PULSE1_FLAG_MASK
470 * @arg @ref QEIV2_EVENT_HOME2_FLAG_MASK
471 * @arg @ref QEIV2_EVENT_FAULT_FLAG_MASK
472 */
qeiv2_enable_load_read_trigger_event(QEIV2_Type * qeiv2_x,uint32_t event_mask)473 static inline void qeiv2_enable_load_read_trigger_event(QEIV2_Type *qeiv2_x, uint32_t event_mask)
474 {
475 qeiv2_x->READEN |= event_mask;
476 }
477
478 /**
479 * @brief disable load read trigger event
480 *
481 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
482 * @param[in] event_mask
483 * @arg @ref QEIV2_EVENT_WDOG_FLAG_MASK
484 * @arg @ref QEIV2_EVENT_HOME_FLAG_MASK
485 * @arg @ref QEIV2_EVENT_POSITION_COMPARE_FLAG_MASK
486 * @arg @ref QEIV2_EVENT_Z_PHASE_FLAG_MASK
487 * @arg @ref QEIV2_EVENT_Z_MISS_FLAG_MASK
488 * @arg @ref QEIV2_EVENT_WIDTH_TIME_FLAG_MASK
489 * @arg @ref QEIV2_EVENT_POSITION2_COMPARE_FLAG_MASK
490 * @arg @ref QEIV2_EVENT_DIR_CHG_FLAG_MASK
491 * @arg @ref QEIV2_EVENT_CYCLE0_FLAG_MASK
492 * @arg @ref QEIV2_EVENT_CYCLE1_FLAG_MASK
493 * @arg @ref QEIV2_EVENT_PULSE0_FLAG_MASK
494 * @arg @ref QEIV2_EVENT_PULSE1_FLAG_MASK
495 * @arg @ref QEIV2_EVENT_HOME2_FLAG_MASK
496 * @arg @ref QEIV2_EVENT_FAULT_FLAG_MASK
497 */
qeiv2_disable_load_read_trigger_event(QEIV2_Type * qeiv2_x,uint32_t event_mask)498 static inline void qeiv2_disable_load_read_trigger_event(QEIV2_Type *qeiv2_x, uint32_t event_mask)
499 {
500 qeiv2_x->READEN &= ~event_mask;
501 }
502
503 /**
504 * @brief enable dma request
505 *
506 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
507 * @param[in] mask
508 * @arg @ref QEIV2_EVENT_WDOG_FLAG_MASK
509 * @arg @ref QEIV2_EVENT_HOME_FLAG_MASK
510 * @arg @ref QEIV2_EVENT_POSITION_COMPARE_FLAG_MASK
511 * @arg @ref QEIV2_EVENT_Z_PHASE_FLAG_MASK
512 * @arg @ref QEIV2_EVENT_Z_MISS_FLAG_MASK
513 * @arg @ref QEIV2_EVENT_WIDTH_TIME_FLAG_MASK
514 * @arg @ref QEIV2_EVENT_POSITION2_COMPARE_FLAG_MASK
515 * @arg @ref QEIV2_EVENT_DIR_CHG_FLAG_MASK
516 * @arg @ref QEIV2_EVENT_CYCLE0_FLAG_MASK
517 * @arg @ref QEIV2_EVENT_CYCLE1_FLAG_MASK
518 * @arg @ref QEIV2_EVENT_PULSE0_FLAG_MASK
519 * @arg @ref QEIV2_EVENT_PULSE1_FLAG_MASK
520 * @arg @ref QEIV2_EVENT_HOME2_FLAG_MASK
521 * @arg @ref QEIV2_EVENT_FAULT_FLAG_MASK
522 */
qeiv2_enable_dma_request(QEIV2_Type * qeiv2_x,uint32_t mask)523 static inline void qeiv2_enable_dma_request(QEIV2_Type *qeiv2_x, uint32_t mask)
524 {
525 qeiv2_x->DMAEN |= mask;
526 }
527
528 /**
529 * @brief disable qeiv2 dma
530 *
531 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
532 * @param[in] mask
533 * @arg @ref QEIV2_EVENT_WDOG_FLAG_MASK
534 * @arg @ref QEIV2_EVENT_HOME_FLAG_MASK
535 * @arg @ref QEIV2_EVENT_POSITION_COMPARE_FLAG_MASK
536 * @arg @ref QEIV2_EVENT_Z_PHASE_FLAG_MASK
537 * @arg @ref QEIV2_EVENT_Z_MISS_FLAG_MASK
538 * @arg @ref QEIV2_EVENT_WIDTH_TIME_FLAG_MASK
539 * @arg @ref QEIV2_EVENT_POSITION2_COMPARE_FLAG_MASK
540 * @arg @ref QEIV2_EVENT_DIR_CHG_FLAG_MASK
541 * @arg @ref QEIV2_EVENT_CYCLE0_FLAG_MASK
542 * @arg @ref QEIV2_EVENT_CYCLE1_FLAG_MASK
543 * @arg @ref QEIV2_EVENT_PULSE0_FLAG_MASK
544 * @arg @ref QEIV2_EVENT_PULSE1_FLAG_MASK
545 * @arg @ref QEIV2_EVENT_HOME2_FLAG_MASK
546 * @arg @ref QEIV2_EVENT_FAULT_FLAG_MASK
547 */
qeiv2_disable_dma_request(QEIV2_Type * qeiv2_x,uint32_t mask)548 static inline void qeiv2_disable_dma_request(QEIV2_Type *qeiv2_x, uint32_t mask)
549 {
550 qeiv2_x->DMAEN &= ~mask;
551 }
552
553 /**
554 * @brief clear qeiv2 status register
555 *
556 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
557 * @param[in] mask
558 * @arg @ref QEIV2_EVENT_WDOG_FLAG_MASK
559 * @arg @ref QEIV2_EVENT_HOME_FLAG_MASK
560 * @arg @ref QEIV2_EVENT_POSITION_COMPARE_FLAG_MASK
561 * @arg @ref QEIV2_EVENT_Z_PHASE_FLAG_MASK
562 * @arg @ref QEIV2_EVENT_Z_MISS_FLAG_MASK
563 * @arg @ref QEIV2_EVENT_WIDTH_TIME_FLAG_MASK
564 * @arg @ref QEIV2_EVENT_POSITION2_COMPARE_FLAG_MASK
565 * @arg @ref QEIV2_EVENT_DIR_CHG_FLAG_MASK
566 * @arg @ref QEIV2_EVENT_CYCLE0_FLAG_MASK
567 * @arg @ref QEIV2_EVENT_CYCLE1_FLAG_MASK
568 * @arg @ref QEIV2_EVENT_PULSE0_FLAG_MASK
569 * @arg @ref QEIV2_EVENT_PULSE1_FLAG_MASK
570 * @arg @ref QEIV2_EVENT_HOME2_FLAG_MASK
571 * @arg @ref QEIV2_EVENT_FAULT_FLAG_MASK
572 */
qeiv2_clear_status(QEIV2_Type * qeiv2_x,uint32_t mask)573 static inline void qeiv2_clear_status(QEIV2_Type *qeiv2_x, uint32_t mask)
574 {
575 qeiv2_x->SR = mask;
576 }
577
578 /**
579 * @brief get qeiv2 status
580 *
581 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
582 * @retval qeiv2 status:
583 * @arg @ref QEIV2_EVENT_WDOG_FLAG_MASK
584 * @arg @ref QEIV2_EVENT_HOME_FLAG_MASK
585 * @arg @ref QEIV2_EVENT_POSITION_COMPARE_FLAG_MASK
586 * @arg @ref QEIV2_EVENT_Z_PHASE_FLAG_MASK
587 * @arg @ref QEIV2_EVENT_Z_MISS_FLAG_MASK
588 * @arg @ref QEIV2_EVENT_WIDTH_TIME_FLAG_MASK
589 * @arg @ref QEIV2_EVENT_POSITION2_COMPARE_FLAG_MASK
590 * @arg @ref QEIV2_EVENT_DIR_CHG_FLAG_MASK
591 * @arg @ref QEIV2_EVENT_CYCLE0_FLAG_MASK
592 * @arg @ref QEIV2_EVENT_CYCLE1_FLAG_MASK
593 * @arg @ref QEIV2_EVENT_PULSE0_FLAG_MASK
594 * @arg @ref QEIV2_EVENT_PULSE1_FLAG_MASK
595 * @arg @ref QEIV2_EVENT_HOME2_FLAG_MASK
596 * @arg @ref QEIV2_EVENT_FAULT_FLAG_MASK
597 */
qeiv2_get_status(QEIV2_Type * qeiv2_x)598 static inline uint32_t qeiv2_get_status(QEIV2_Type *qeiv2_x)
599 {
600 return qeiv2_x->SR;
601 }
602
603 /**
604 * @brief get qeiv2 bit status
605 *
606 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
607 * @param[in] mask
608 * @arg @ref QEIV2_EVENT_WDOG_FLAG_MASK
609 * @arg @ref QEIV2_EVENT_HOME_FLAG_MASK
610 * @arg @ref QEIV2_EVENT_POSITION_COMPARE_FLAG_MASK
611 * @arg @ref QEIV2_EVENT_Z_PHASE_FLAG_MASK
612 * @arg @ref QEIV2_EVENT_Z_MISS_FLAG_MASK
613 * @arg @ref QEIV2_EVENT_WIDTH_TIME_FLAG_MASK
614 * @arg @ref QEIV2_EVENT_POSITION2_COMPARE_FLAG_MASK
615 * @arg @ref QEIV2_EVENT_DIR_CHG_FLAG_MASK
616 * @arg @ref QEIV2_EVENT_CYCLE0_FLAG_MASK
617 * @arg @ref QEIV2_EVENT_CYCLE1_FLAG_MASK
618 * @arg @ref QEIV2_EVENT_PULSE0_FLAG_MASK
619 * @arg @ref QEIV2_EVENT_PULSE1_FLAG_MASK
620 * @arg @ref QEIV2_EVENT_HOME2_FLAG_MASK
621 * @arg @ref QEIV2_EVENT_FAULT_FLAG_MASK
622 * @retval true or false
623 */
qeiv2_get_bit_status(QEIV2_Type * qeiv2_x,uint32_t mask)624 static inline bool qeiv2_get_bit_status(QEIV2_Type *qeiv2_x, uint32_t mask)
625 {
626 return ((qeiv2_x->SR & mask) == mask) ? true : false;
627 }
628
629 /**
630 * @brief enable qeiv2 irq
631 *
632 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
633 * @param[in] mask
634 * @arg @ref QEIV2_EVENT_WDOG_FLAG_MASK
635 * @arg @ref QEIV2_EVENT_HOME_FLAG_MASK
636 * @arg @ref QEIV2_EVENT_POSITION_COMPARE_FLAG_MASK
637 * @arg @ref QEIV2_EVENT_Z_PHASE_FLAG_MASK
638 * @arg @ref QEIV2_EVENT_Z_MISS_FLAG_MASK
639 * @arg @ref QEIV2_EVENT_WIDTH_TIME_FLAG_MASK
640 * @arg @ref QEIV2_EVENT_POSITION2_COMPARE_FLAG_MASK
641 * @arg @ref QEIV2_EVENT_DIR_CHG_FLAG_MASK
642 * @arg @ref QEIV2_EVENT_CYCLE0_FLAG_MASK
643 * @arg @ref QEIV2_EVENT_CYCLE1_FLAG_MASK
644 * @arg @ref QEIV2_EVENT_PULSE0_FLAG_MASK
645 * @arg @ref QEIV2_EVENT_PULSE1_FLAG_MASK
646 * @arg @ref QEIV2_EVENT_HOME2_FLAG_MASK
647 * @arg @ref QEIV2_EVENT_FAULT_FLAG_MASK
648 */
qeiv2_enable_irq(QEIV2_Type * qeiv2_x,uint32_t mask)649 static inline void qeiv2_enable_irq(QEIV2_Type *qeiv2_x, uint32_t mask)
650 {
651 qeiv2_x->IRQEN |= mask;
652 }
653
654 /**
655 * @brief disable qeiv2 irq
656 *
657 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
658 * @param[in] mask
659 * @arg @ref QEIV2_EVENT_WDOG_FLAG_MASK
660 * @arg @ref QEIV2_EVENT_HOME_FLAG_MASK
661 * @arg @ref QEIV2_EVENT_POSITION_COMPARE_FLAG_MASK
662 * @arg @ref QEIV2_EVENT_Z_PHASE_FLAG_MASK
663 * @arg @ref QEIV2_EVENT_Z_MISS_FLAG_MASK
664 * @arg @ref QEIV2_EVENT_WIDTH_TIME_FLAG_MASK
665 * @arg @ref QEIV2_EVENT_POSITION2_COMPARE_FLAG_MASK
666 * @arg @ref QEIV2_EVENT_DIR_CHG_FLAG_MASK
667 * @arg @ref QEIV2_EVENT_CYCLE0_FLAG_MASK
668 * @arg @ref QEIV2_EVENT_CYCLE1_FLAG_MASK
669 * @arg @ref QEIV2_EVENT_PULSE0_FLAG_MASK
670 * @arg @ref QEIV2_EVENT_PULSE1_FLAG_MASK
671 * @arg @ref QEIV2_EVENT_HOME2_FLAG_MASK
672 * @arg @ref QEIV2_EVENT_FAULT_FLAG_MASK
673 */
qeiv2_disable_irq(QEIV2_Type * qeiv2_x,uint32_t mask)674 static inline void qeiv2_disable_irq(QEIV2_Type *qeiv2_x, uint32_t mask)
675 {
676 qeiv2_x->IRQEN &= ~mask;
677 }
678
679 /**
680 * @brief get current counter value
681 *
682 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
683 * @param[in] type @ref qeiv2_counter_type_t
684 * @retval counter value
685 */
qeiv2_get_current_count(QEIV2_Type * qeiv2_x,qeiv2_counter_type_t type)686 static inline uint32_t qeiv2_get_current_count(QEIV2_Type *qeiv2_x, qeiv2_counter_type_t type)
687 {
688 return *(&qeiv2_x->COUNT[QEIV2_COUNT_CURRENT].Z + type);
689 }
690
691 /**
692 * @brief get current phcnt value
693 *
694 * @param qeiv2_x QEI base address, HPM_QEIx(x=0...n)
695 * @return phcnt value
696 */
qeiv2_get_current_phase_phcnt(QEIV2_Type * qeiv2_x)697 static inline uint32_t qeiv2_get_current_phase_phcnt(QEIV2_Type *qeiv2_x)
698 {
699 return QEIV2_COUNT_PH_PHCNT_GET(qeiv2_get_current_count(qeiv2_x, qeiv2_counter_type_phase));
700 }
701
702 /**
703 * @brief get current a phase level
704 *
705 * @param qeiv2_x QEI base address, HPM_QEIx(x=0...n)
706 * @return a phase level
707 */
qeiv2_get_current_phase_a_level(QEIV2_Type * qeiv2_x)708 static inline bool qeiv2_get_current_phase_a_level(QEIV2_Type *qeiv2_x)
709 {
710 return QEIV2_COUNT_PH_ASTAT_GET(qeiv2_get_current_count(qeiv2_x, qeiv2_counter_type_phase));
711 }
712
713 /**
714 * @brief get current b phase level
715 *
716 * @param qeiv2_x QEI base address, HPM_QEIx(x=0...n)
717 * @return b phase level
718 */
qeiv2_get_current_phase_b_level(QEIV2_Type * qeiv2_x)719 static inline bool qeiv2_get_current_phase_b_level(QEIV2_Type *qeiv2_x)
720 {
721 return QEIV2_COUNT_PH_BSTAT_GET(qeiv2_get_current_count(qeiv2_x, qeiv2_counter_type_phase));
722 }
723
724 /**
725 * @brief get current phase dir
726 *
727 * @param qeiv2_x QEI base address, HPM_QEIx(x=0...n)
728 * @return dir
729 */
qeiv2_get_current_phase_dir(QEIV2_Type * qeiv2_x)730 static inline bool qeiv2_get_current_phase_dir(QEIV2_Type *qeiv2_x)
731 {
732 return QEIV2_COUNT_PH_DIR_GET(qeiv2_get_current_count(qeiv2_x, qeiv2_counter_type_phase));
733 }
734
735
736 /**
737 * @brief get read event count value
738 *
739 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
740 * @param[in] type @ref qeiv2_counter_type_t
741 * @retval counter value
742 */
qeiv2_get_count_on_read_event(QEIV2_Type * qeiv2_x,qeiv2_counter_type_t type)743 static inline uint32_t qeiv2_get_count_on_read_event(QEIV2_Type *qeiv2_x, qeiv2_counter_type_t type)
744 {
745 return *(&(qeiv2_x->COUNT[QEIV2_COUNT_READ].Z) + type);
746 }
747
748 /**
749 * @brief read the value of each phase snapshot 0 counter
750 *
751 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
752 * @param[in] type @ref qeiv2_counter_type_t
753 * @retval counter value
754 */
qeiv2_get_count_on_snap0_event(QEIV2_Type * qeiv2_x,qeiv2_counter_type_t type)755 static inline uint32_t qeiv2_get_count_on_snap0_event(QEIV2_Type *qeiv2_x, qeiv2_counter_type_t type)
756 {
757 return *(&qeiv2_x->COUNT[QEIV2_COUNT_SNAP0].Z + type);
758 }
759
760 /**
761 * @brief read the value of each phase snapshot 1 counter
762 *
763 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
764 * @param[in] type @ref qeiv2_counter_type_t
765 * @retval counter value
766 */
qeiv2_get_count_on_snap1_event(QEIV2_Type * qeiv2_x,qeiv2_counter_type_t type)767 static inline uint32_t qeiv2_get_count_on_snap1_event(QEIV2_Type *qeiv2_x, qeiv2_counter_type_t type)
768 {
769 return *(&qeiv2_x->COUNT[QEIV2_COUNT_SNAP1].Z + type);
770 }
771
772 /**
773 * @brief set zcnt compare value
774 *
775 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
776 * @param[in] cmp zcnt compare value
777 */
qeiv2_set_z_cmp_value(QEIV2_Type * qeiv2_x,uint32_t cmp)778 static inline void qeiv2_set_z_cmp_value(QEIV2_Type *qeiv2_x, uint32_t cmp)
779 {
780 qeiv2_x->ZCMP = QEIV2_ZCMP_ZCMP_SET(cmp);
781 }
782
783 /**
784 * @brief set phcnt compare value
785 *
786 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
787 * @param[in] cmp phcnt compare value
788 */
qeiv2_set_phcnt_cmp_value(QEIV2_Type * qeiv2_x,uint32_t cmp)789 static inline void qeiv2_set_phcnt_cmp_value(QEIV2_Type *qeiv2_x, uint32_t cmp)
790 {
791 qeiv2_x->PHCMP = QEIV2_PHCMP_PHCMP_SET(cmp);
792 }
793
794 /**
795 * @brief set spdcnt or position compare value. It's selected by CR register rd_sel bit.
796 *
797 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
798 * @param[in] cmp spdcnt or position compare value
799 * when set @ref qeiv2_spd_tmr_as_spd_tm, this is spdcmp value. (ABZ encoder)
800 * when set @ref qeiv2_spd_tmr_as_pos_angle, this is poscmp value. (sin or sincos encoder)
801 */
qeiv2_set_spd_pos_cmp_value(QEIV2_Type * qeiv2_x,uint32_t cmp)802 static inline void qeiv2_set_spd_pos_cmp_value(QEIV2_Type *qeiv2_x, uint32_t cmp)
803 {
804 qeiv2_x->SPDCMP = QEIV2_SPDCMP_SPDCMP_SET(cmp);
805 }
806
807 /**
808 * @brief set compare match options
809 *
810 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
811 * @param[in] ignore_zcmp ignore zcmp
812 * @param[in] ignore_phcmp ignore phcmp
813 * @param[in] ignore_spdposcmp ignore spdposcmp
814 * when set @ref qeiv2_spd_tmr_as_spd_tm, this is spdcmp value. (ABZ encoder)
815 * when set @ref qeiv2_spd_tmr_as_pos_angle, this is poscmp value. (sin or sincos encoder)
816 * @param[in] ignore_rotate_dir ignore encoder rotation direction. (ABZ encoder)
817 * @param[in] rotate_dir when don't ignore rotation direction, match rotation direction. @ref qeiv2_rotate_dir_t. (ABZ encoder)
818 * @param[in] ignore_pos_dir ignore position increase or decrease direction. (sin or sincos encoder)
819 * @param[in] pos_dir when don't ignore position direction, match position direction. @ref qeiv2_position_dir_t. (sin or sincos encoder)
820 */
qeiv2_set_cmp_match_option(QEIV2_Type * qeiv2_x,bool ignore_zcmp,bool ignore_phcmp,bool ignore_spdposcmp,bool ignore_rotate_dir,qeiv2_rotate_dir_t rotate_dir,bool ignore_pos_dir,qeiv2_position_dir_t pos_dir)821 static inline void qeiv2_set_cmp_match_option(QEIV2_Type *qeiv2_x, bool ignore_zcmp, bool ignore_phcmp, bool ignore_spdposcmp,
822 bool ignore_rotate_dir, qeiv2_rotate_dir_t rotate_dir, bool ignore_pos_dir, qeiv2_position_dir_t pos_dir)
823 {
824 qeiv2_x->MATCH_CFG = (qeiv2_x->MATCH_CFG & (~(QEIV2_MATCH_CFG_ZCMPDIS_MASK | QEIV2_MATCH_CFG_PHASE_MATCH_DIS_MASK | QEIV2_MATCH_CFG_SPDCMPDIS_MASK
825 | QEIV2_MATCH_CFG_DIRCMPDIS_MASK | QEIV2_MATCH_CFG_DIRCMP_MASK
826 | QEIV2_MATCH_CFG_POS_MATCH_OPT_MASK | QEIV2_MATCH_CFG_POS_MATCH_DIR_MASK)))
827 | QEIV2_MATCH_CFG_ZCMPDIS_SET(ignore_zcmp) | QEIV2_MATCH_CFG_PHASE_MATCH_DIS_SET(ignore_phcmp)
828 | QEIV2_MATCH_CFG_SPDCMPDIS_SET(ignore_spdposcmp)
829 | QEIV2_MATCH_CFG_DIRCMPDIS_SET(ignore_rotate_dir) | QEIV2_MATCH_CFG_DIRCMP_SET(rotate_dir)
830 | QEIV2_MATCH_CFG_POS_MATCH_OPT_SET(!ignore_pos_dir) | QEIV2_MATCH_CFG_POS_MATCH_DIR_SET(pos_dir);
831 }
832
833 /**
834 * @brief set zcnt compare2 value
835 *
836 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
837 * @param[in] cmp zcnt compare2 value
838 */
qeiv2_set_z_cmp2_value(QEIV2_Type * qeiv2_x,uint32_t cmp)839 static inline void qeiv2_set_z_cmp2_value(QEIV2_Type *qeiv2_x, uint32_t cmp)
840 {
841 qeiv2_x->ZCMP2 = QEIV2_ZCMP2_ZCMP2_SET(cmp);
842 }
843
844 /**
845 * @brief set phcnt compare2 value
846 *
847 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
848 * @param[in] cmp phcnt compare2 value
849 */
qeiv2_set_phcnt_cmp2_value(QEIV2_Type * qeiv2_x,uint32_t cmp)850 static inline void qeiv2_set_phcnt_cmp2_value(QEIV2_Type *qeiv2_x, uint32_t cmp)
851 {
852 qeiv2_x->PHCMP2 = QEIV2_PHCMP2_PHCMP2_SET(cmp);
853 }
854
855 /**
856 * @brief set spdcnt or position compare2 value. It's selected by CR register rd_sel bit.
857 *
858 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
859 * @param[in] cmp spdcnt or position compare2 value
860 */
qeiv2_set_spd_pos_cmp2_value(QEIV2_Type * qeiv2_x,uint32_t cmp)861 static inline void qeiv2_set_spd_pos_cmp2_value(QEIV2_Type *qeiv2_x, uint32_t cmp)
862 {
863 qeiv2_x->SPDCMP2 = QEIV2_SPDCMP2_SPDCMP2_SET(cmp);
864 }
865
866 /**
867 * @brief set compare2 match options
868 *
869 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
870 * @param[in] ignore_zcmp ignore zcmp
871 * @param[in] ignore_phcmp ignore phcmp
872 * @param[in] ignore_spdposcmp ignore spdposcmp.
873 * when set @ref qeiv2_spd_tmr_as_spd_tm, this is spdcmp value. (ABZ encoder)
874 * when set @ref qeiv2_spd_tmr_as_pos_angle, this is poscmp value. (sin or sincos encoder)
875 * @param[in] ignore_rotate_dir ignore encoder rotation direction. (ABZ encoder)
876 * @param[in] rotate_dir when don't ignore rotation direction, match rotation direction. @ref qeiv2_rotate_dir_t. (ABZ encoder)
877 * @param[in] ignore_pos_dir ignore position increase or decrease direction. (sin or sincos encoder)
878 * @param[in] pos_dir when don't ignore position direction, match position direction. @ref qeiv2_position_dir_t. (sin or sincos encoder)
879 */
qeiv2_set_cmp2_match_option(QEIV2_Type * qeiv2_x,bool ignore_zcmp,bool ignore_phcmp,bool ignore_spdposcmp,bool ignore_rotate_dir,qeiv2_rotate_dir_t rotate_dir,bool ignore_pos_dir,qeiv2_position_dir_t pos_dir)880 static inline void qeiv2_set_cmp2_match_option(QEIV2_Type *qeiv2_x, bool ignore_zcmp, bool ignore_phcmp, bool ignore_spdposcmp,
881 bool ignore_rotate_dir, qeiv2_rotate_dir_t rotate_dir, bool ignore_pos_dir, qeiv2_position_dir_t pos_dir)
882 {
883 qeiv2_x->MATCH_CFG = (qeiv2_x->MATCH_CFG & ~(QEIV2_MATCH_CFG_ZCMP2DIS_MASK | QEIV2_MATCH_CFG_PHASE_MATCH_DIS2_MASK | QEIV2_MATCH_CFG_SPDCMP2DIS_MASK
884 | QEIV2_MATCH_CFG_DIRCMP2DIS_MASK | QEIV2_MATCH_CFG_DIRCMP2_MASK
885 | QEIV2_MATCH_CFG_POS_MATCH2_OPT_MASK | QEIV2_MATCH_CFG_POS_MATCH2_DIR_MASK))
886 | QEIV2_MATCH_CFG_ZCMP2DIS_SET(ignore_zcmp) | QEIV2_MATCH_CFG_PHASE_MATCH_DIS2_SET(ignore_phcmp)
887 | QEIV2_MATCH_CFG_SPDCMP2DIS_SET(ignore_spdposcmp)
888 | QEIV2_MATCH_CFG_DIRCMP2DIS_SET(ignore_rotate_dir) | QEIV2_MATCH_CFG_DIRCMP2_SET(rotate_dir)
889 | QEIV2_MATCH_CFG_POS_MATCH2_OPT_SET(!ignore_pos_dir) | QEIV2_MATCH_CFG_POS_MATCH2_DIR_SET(pos_dir);
890 }
891
892 /**
893 * @brief config signal filter
894 *
895 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
896 * @param[in] idx filter index
897 * @arg @ref qeiv2_filter_phase_t
898 * @param[in] outinv Filter will invert the output
899 * @param[in] mode qeiv2_filter_mode_t
900 * @param[in] sync set to enable sychronization input signal with TRGM clock
901 * @param[in] filtlen defines the filter counter length.
902 */
qeiv2_config_filter(QEIV2_Type * qeiv2_x,qeiv2_filter_phase_t phase,bool outinv,qeiv2_filter_mode_t mode,bool sync,uint16_t filtlen)903 static inline void qeiv2_config_filter(QEIV2_Type *qeiv2_x, qeiv2_filter_phase_t phase, bool outinv, qeiv2_filter_mode_t mode, bool sync, uint16_t filtlen)
904 {
905 qeiv2_x->FILT_CFG[phase] =
906 QEIV2_FILT_CFG_OUTINV_SET(outinv) | QEIV2_FILT_CFG_MODE_SET(mode) | QEIV2_FILT_CFG_SYNCEN_SET(sync) | QEIV2_FILT_CFG_FILTLEN_SET(filtlen);
907 }
908
909 /**
910 * @brief config signal enablement and edge
911 *
912 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
913 * @param[in] siga_en enable signal A/U
914 * @param[in] sigb_en enable signal B/V
915 * @param[in] sigz_en enable signal Z/W
916 * @param[in] posedge_en enable rise edge
917 * @param[in] negedge_en enable fall edge
918 */
qeiv2_config_abz_uvw_signal_edge(QEIV2_Type * qeiv2_x,bool siga_en,bool sigb_en,bool sigz_en,bool posedge_en,bool negedge_en)919 static inline void qeiv2_config_abz_uvw_signal_edge(QEIV2_Type *qeiv2_x, bool siga_en, bool sigb_en, bool sigz_en, bool posedge_en, bool negedge_en)
920 {
921 qeiv2_x->QEI_CFG = (qeiv2_x->QEI_CFG & ~(QEIV2_QEI_CFG_SIGA_EN_MASK | QEIV2_QEI_CFG_SIGB_EN_MASK | QEIV2_QEI_CFG_SIGZ_EN_MASK
922 | QEIV2_QEI_CFG_POSIDGE_EN_MASK | QEIV2_QEI_CFG_NEGEDGE_EN_MASK))
923 | (QEIV2_QEI_CFG_SIGA_EN_SET(siga_en) | QEIV2_QEI_CFG_SIGB_EN_SET(sigb_en) | QEIV2_QEI_CFG_SIGZ_EN_SET(sigz_en)
924 | QEIV2_QEI_CFG_POSIDGE_EN_SET(posedge_en) | QEIV2_QEI_CFG_NEGEDGE_EN_SET(negedge_en));
925 }
926
927 /**
928 * @brief set pulse0 value
929 *
930 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
931 * @param[in] pulse_num for speed detection, will count the cycle number for configed pulse_num
932 */
qeiv2_set_pulse0_num(QEIV2_Type * qeiv2_x,uint32_t pulse_num)933 static inline void qeiv2_set_pulse0_num(QEIV2_Type *qeiv2_x, uint32_t pulse_num)
934 {
935 qeiv2_x->PULSE0_NUM = QEIV2_PULSE0_NUM_PULSE0_NUM_SET(pulse_num);
936 }
937
938 /**
939 * @brief get cycle0 snap0 value
940 *
941 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
942 * @retval cycle0 snap0 value
943 */
qeiv2_get_pulse0_cycle_snap0(QEIV2_Type * qeiv2_x)944 static inline uint32_t qeiv2_get_pulse0_cycle_snap0(QEIV2_Type *qeiv2_x)
945 {
946 return qeiv2_x->CYCLE0_SNAP0;
947 }
948
949 /**
950 * @brief get cycle0 snap1 value
951 *
952 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
953 * @retval cycle0 snap1 value
954 */
qeiv2_get_pulse0_cycle_snap1(QEIV2_Type * qeiv2_x)955 static inline uint32_t qeiv2_get_pulse0_cycle_snap1(QEIV2_Type *qeiv2_x)
956 {
957 return qeiv2_x->CYCLE0_SNAP1;
958 }
959
960 /**
961 * @brief set pulse1 value
962 *
963 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
964 * @param[in] pulse_num for speed detection, will count the cycle number for configed pulse_num
965 */
qeiv2_set_pulse1_num(QEIV2_Type * qeiv2_x,uint32_t pulse_num)966 static inline void qeiv2_set_pulse1_num(QEIV2_Type *qeiv2_x, uint32_t pulse_num)
967 {
968 qeiv2_x->PULSE1_NUM = QEIV2_PULSE1_NUM_PULSE1_NUM_SET(pulse_num);
969 }
970
971 /**
972 * @brief get cycle1 snap0 value
973 *
974 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
975 * @retval cycle1 snap0 value
976 */
qeiv2_get_pulse1_cycle_snap0(QEIV2_Type * qeiv2_x)977 static inline uint32_t qeiv2_get_pulse1_cycle_snap0(QEIV2_Type *qeiv2_x)
978 {
979 return qeiv2_x->CYCLE1_SNAP0;
980 }
981
982 /**
983 * @brief get cycle1 snap1 value
984 *
985 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
986 * @retval cycle1 snap1 value
987 */
qeiv2_get_pulse1_cycle_snap1(QEIV2_Type * qeiv2_x)988 static inline uint32_t qeiv2_get_pulse1_cycle_snap1(QEIV2_Type *qeiv2_x)
989 {
990 return qeiv2_x->CYCLE1_SNAP1;
991 }
992
993 /**
994 * @brief set cycle0 value
995 *
996 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
997 * @param[in] cycle_num for speed detection, will count the pulse number for configed cycle_num
998 */
qeiv2_set_cycle0_num(QEIV2_Type * qeiv2_x,uint32_t cycle_num)999 static inline void qeiv2_set_cycle0_num(QEIV2_Type *qeiv2_x, uint32_t cycle_num)
1000 {
1001 qeiv2_x->CYCLE0_NUM = QEIV2_CYCLE0_NUM_CYCLE0_NUM_SET(cycle_num);
1002 }
1003
1004 /**
1005 * @brief get pulse0 snap0 value
1006 *
1007 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
1008 * @retval pulse0 snap0 value
1009 */
qeiv2_get_cycle0_pulse_snap0(QEIV2_Type * qeiv2_x)1010 static inline uint32_t qeiv2_get_cycle0_pulse_snap0(QEIV2_Type *qeiv2_x)
1011 {
1012 return qeiv2_x->PULSE0_SNAP0;
1013 }
1014
1015 /**
1016 * @brief get pulse0 snap1 value
1017 *
1018 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
1019 * @retval pulse0 snap1 value
1020 */
qeiv2_get_cycle0_pulse_snap1(QEIV2_Type * qeiv2_x)1021 static inline uint32_t qeiv2_get_cycle0_pulse_snap1(QEIV2_Type *qeiv2_x)
1022 {
1023 return qeiv2_x->PULSE0_SNAP1;
1024 }
1025
1026 /**
1027 * @brief get pulse0cycle snap0 value
1028 *
1029 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
1030 * @retval pulse0cycle snap0 value
1031 */
qeiv2_get_cycle0_pulse0cycle_snap0(QEIV2_Type * qeiv2_x)1032 static inline uint32_t qeiv2_get_cycle0_pulse0cycle_snap0(QEIV2_Type *qeiv2_x)
1033 {
1034 return qeiv2_x->PULSE0CYCLE_SNAP0;
1035 }
1036
1037 /**
1038 * @brief get pulse0cycle snap1 value
1039 *
1040 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
1041 * @retval pulse0cycle snap1 value
1042 */
qeiv2_get_cycle0_pulse0cycle_snap1(QEIV2_Type * qeiv2_x)1043 static inline uint32_t qeiv2_get_cycle0_pulse0cycle_snap1(QEIV2_Type *qeiv2_x)
1044 {
1045 return qeiv2_x->PULSE0CYCLE_SNAP1;
1046 }
1047
1048 /**
1049 * @brief set cycle1 value
1050 *
1051 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
1052 * @param[in] cycle_num for speed detection, will count the pulse number for configed cycle_num
1053 */
qeiv2_set_cycle1_num(QEIV2_Type * qeiv2_x,uint32_t cycle_num)1054 static inline void qeiv2_set_cycle1_num(QEIV2_Type *qeiv2_x, uint32_t cycle_num)
1055 {
1056 qeiv2_x->CYCLE1_NUM = QEIV2_CYCLE1_NUM_CYCLE1_NUM_SET(cycle_num);
1057 }
1058
1059 /**
1060 * @brief get pulse1 snap0 value
1061 *
1062 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
1063 * @retval pulse1 snap0 value
1064 */
qeiv2_get_cycle1_pulse_snap0(QEIV2_Type * qeiv2_x)1065 static inline uint32_t qeiv2_get_cycle1_pulse_snap0(QEIV2_Type *qeiv2_x)
1066 {
1067 return qeiv2_x->PULSE1_SNAP0;
1068 }
1069
1070 /**
1071 * @brief get pulse1 snap1 value
1072 *
1073 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
1074 * @retval pulse1 snap1 value
1075 */
qeiv2_get_cycle1_pulse_snap1(QEIV2_Type * qeiv2_x)1076 static inline uint32_t qeiv2_get_cycle1_pulse_snap1(QEIV2_Type *qeiv2_x)
1077 {
1078 return qeiv2_x->PULSE1_SNAP1;
1079 }
1080
1081 /**
1082 * @brief get pulse1cycle snap0 value
1083 *
1084 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
1085 * @retval pulse1cycle snap0 value
1086 */
qeiv2_get_cycle1_pulse1cycle_snap0(QEIV2_Type * qeiv2_x)1087 static inline uint32_t qeiv2_get_cycle1_pulse1cycle_snap0(QEIV2_Type *qeiv2_x)
1088 {
1089 return qeiv2_x->PULSE1CYCLE_SNAP0;
1090 }
1091
1092 /**
1093 * @brief get pulse1cycle snap1 value
1094 *
1095 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
1096 * @retval pulse01cycle snap1 value
1097 */
qeiv2_get_cycle1_pulse1cycle_snap1(QEIV2_Type * qeiv2_x)1098 static inline uint32_t qeiv2_get_cycle1_pulse1cycle_snap1(QEIV2_Type *qeiv2_x)
1099 {
1100 return qeiv2_x->PULSE1CYCLE_SNAP1;
1101 }
1102
1103 /**
1104 * @brief enable or disable clear counter if detect direction change
1105 *
1106 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
1107 * @param[in] enable enable or disable clear counter if detect direction change
1108 */
qeiv2_clear_counter_when_dir_chg(QEIV2_Type * qeiv2_x,bool enable)1109 static inline void qeiv2_clear_counter_when_dir_chg(QEIV2_Type *qeiv2_x, bool enable)
1110 {
1111 if (enable) {
1112 qeiv2_x->QEI_CFG |= QEIV2_QEI_CFG_SPEED_DIR_CHG_EN_MASK;
1113 } else {
1114 qeiv2_x->QEI_CFG &= ~QEIV2_QEI_CFG_SPEED_DIR_CHG_EN_MASK;
1115 }
1116 }
1117
1118 /**
1119 * @brief adcx config
1120 *
1121 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
1122 * @param[in] config qeiv2_adc_config_t
1123 */
qeiv2_config_adcx(QEIV2_Type * qeiv2_x,qeiv2_adc_config_t * config,bool enable)1124 static inline void qeiv2_config_adcx(QEIV2_Type *qeiv2_x, qeiv2_adc_config_t *config, bool enable)
1125 {
1126 uint32_t tmp;
1127 tmp = QEIV2_ADCX_CFG0_X_ADCSEL_SET(config->adc_select) | QEIV2_ADCX_CFG0_X_CHAN_SET(config->adc_channel);
1128 qeiv2_x->ADCX_CFG1 = QEIV2_ADCX_CFG1_X_PARAM1_SET(config->param1) | QEIV2_ADCX_CFG1_X_PARAM0_SET(config->param0);
1129 qeiv2_x->ADCX_CFG2 = QEIV2_ADCX_CFG2_X_OFFSET_SET(config->offset);
1130 if (enable) {
1131 tmp |= QEIV2_ADCX_CFG0_X_ADC_ENABLE_MASK;
1132 } else {
1133 tmp &= ~QEIV2_ADCX_CFG0_X_ADC_ENABLE_MASK;
1134 }
1135 qeiv2_x->ADCX_CFG0 = tmp;
1136 }
1137
1138 /**
1139 * @brief adcy config
1140 *
1141 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
1142 * @param[in] config qeiv2_adc_config_t
1143 */
qeiv2_config_adcy(QEIV2_Type * qeiv2_x,qeiv2_adc_config_t * config,bool enable)1144 static inline void qeiv2_config_adcy(QEIV2_Type *qeiv2_x, qeiv2_adc_config_t *config, bool enable)
1145 {
1146 uint32_t tmp;
1147 tmp = QEIV2_ADCY_CFG0_Y_ADCSEL_SET(config->adc_select) | QEIV2_ADCY_CFG0_Y_CHAN_SET(config->adc_channel);
1148 qeiv2_x->ADCY_CFG1 = QEIV2_ADCY_CFG1_Y_PARAM1_SET(config->param1) | QEIV2_ADCY_CFG1_Y_PARAM0_SET(config->param0);
1149 qeiv2_x->ADCY_CFG2 = QEIV2_ADCY_CFG2_Y_OFFSET_SET(config->offset);
1150 if (enable) {
1151 tmp |= QEIV2_ADCY_CFG0_Y_ADC_ENABLE_MASK;
1152 } else {
1153 tmp &= ~QEIV2_ADCY_CFG0_Y_ADC_ENABLE_MASK;
1154 }
1155 qeiv2_x->ADCY_CFG0 = tmp;
1156 }
1157
1158 /**
1159 * @brief set adcx and adcy delay
1160 *
1161 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
1162 * @param[in] delay x/y delay, default 1.25us@200MHz, max 80ms
1163 */
qeiv2_set_adc_xy_delay(QEIV2_Type * qeiv2_x,uint32_t delay)1164 static inline void qeiv2_set_adc_xy_delay(QEIV2_Type *qeiv2_x, uint32_t delay)
1165 {
1166 qeiv2_x->CAL_CFG = QEIV2_CAL_CFG_XY_DELAY_SET(delay);
1167 }
1168
1169 /**
1170 * @brief set position threshold
1171 *
1172 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
1173 * @param[in] threshold Position change threshold. When two position changes exceed this value,
1174 * it will be considered as an invalid position and no valid signal will be output.
1175 */
qeiv2_set_position_threshold(QEIV2_Type * qeiv2_x,uint32_t threshold)1176 static inline void qeiv2_set_position_threshold(QEIV2_Type *qeiv2_x, uint32_t threshold)
1177 {
1178 qeiv2_x->POS_THRESHOLD = QEIV2_POS_THRESHOLD_POS_THRESHOLD_SET(threshold);
1179 }
1180
1181 /**
1182 * @brief set uvw position option
1183 *
1184 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
1185 * @param[in] opt qeiv2_uvw_pos_opt_t
1186 */
qeiv2_set_uvw_position_opt(QEIV2_Type * qeiv2_x,qeiv2_uvw_pos_opt_t opt)1187 static inline void qeiv2_set_uvw_position_opt(QEIV2_Type *qeiv2_x, qeiv2_uvw_pos_opt_t opt)
1188 {
1189 qeiv2_x->QEI_CFG = (qeiv2_x->QEI_CFG & ~QEIV2_QEI_CFG_UVW_POS_OPT0_MASK) | QEIV2_QEI_CFG_UVW_POS_OPT0_SET(opt);
1190 }
1191
1192 /**
1193 * @brief set config uvw position
1194 *
1195 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
1196 * @param[in] idx uvw position config index
1197 * @arg @ref qeiv2_uvw_pos_idx_t
1198 * @param[in] u_pos_sel U position selection based by uvw position option
1199 * @arg @ref QEIV2_UVW_POS_OPT_CUR_SEL_LOW
1200 * @arg @ref QEIV2_UVW_POS_OPT_CUR_SEL_HIGH
1201 * @arg @ref QEIV2_UVW_POS_OPT_CUR_SEL_EDGE
1202 * @arg @ref QEIV2_UVW_POS_OPT_NEX_SEL_LOW
1203 * @arg @ref QEIV2_UVW_POS_OPT_NEX_SEL_HIGH
1204 * @param[in] v_pos_sel V position selection based by uvw position option
1205 * @arg @ref QEIV2_UVW_POS_OPT_CUR_SEL_LOW
1206 * @arg @ref QEIV2_UVW_POS_OPT_CUR_SEL_HIGH
1207 * @arg @ref QEIV2_UVW_POS_OPT_CUR_SEL_EDGE
1208 * @arg @ref QEIV2_UVW_POS_OPT_NEX_SEL_LOW
1209 * @arg @ref QEIV2_UVW_POS_OPT_NEX_SEL_HIGH
1210 * @param[in] w_pos_sel W position selection based by uvw position option
1211 * @arg @ref QEIV2_UVW_POS_OPT_CUR_SEL_LOW
1212 * @arg @ref QEIV2_UVW_POS_OPT_CUR_SEL_HIGH
1213 * @arg @ref QEIV2_UVW_POS_OPT_CUR_SEL_EDGE
1214 * @arg @ref QEIV2_UVW_POS_OPT_NEX_SEL_LOW
1215 * @arg @ref QEIV2_UVW_POS_OPT_NEX_SEL_HIGH
1216 * @param[in] enable enable this uvw config
1217 */
qeiv2_set_uvw_position_sel(QEIV2_Type * qeiv2_x,qeiv2_uvw_pos_idx_t idx,uint8_t u_pos_sel,uint8_t v_pos_sel,uint8_t w_pos_sel,bool enable)1218 static inline void qeiv2_set_uvw_position_sel(QEIV2_Type *qeiv2_x, qeiv2_uvw_pos_idx_t idx, uint8_t u_pos_sel, uint8_t v_pos_sel,
1219 uint8_t w_pos_sel, bool enable)
1220 {
1221 uint32_t tmp;
1222 tmp = QEIV2_UVW_POS_CFG_U_POS_SEL_SET(u_pos_sel)
1223 | QEIV2_UVW_POS_CFG_V_POS_SEL_SET(v_pos_sel)
1224 | QEIV2_UVW_POS_CFG_W_POS_SEL_SET(w_pos_sel);
1225 if (enable) {
1226 tmp |= QEIV2_UVW_POS_CFG_POS_EN_MASK;
1227 } else {
1228 tmp &= ~QEIV2_UVW_POS_CFG_POS_EN_MASK;
1229 }
1230 qeiv2_x->UVW_POS_CFG[idx] = tmp;
1231 }
1232
1233 /**
1234 * @brief set uvw position
1235 *
1236 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
1237 * @param[in] idx uvw position config index
1238 * @arg @ref qeiv2_uvw_pos_idx_t
1239 * @param[in] pos angle corresponding to UVW signal position
1240 */
qeiv2_set_uvw_position(QEIV2_Type * qeiv2_x,qeiv2_uvw_pos_idx_t idx,uint32_t pos)1241 static inline void qeiv2_set_uvw_position(QEIV2_Type *qeiv2_x, qeiv2_uvw_pos_idx_t idx, uint32_t pos)
1242 {
1243 qeiv2_x->UVW_POS[idx] = pos;
1244 }
1245
1246 /**
1247 * @brief set z phase counter value
1248 *
1249 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
1250 * @param[in] cnt z phase counter value
1251 */
qeiv2_set_z_phase(QEIV2_Type * qeiv2_x,uint32_t cnt)1252 static inline void qeiv2_set_z_phase(QEIV2_Type *qeiv2_x, uint32_t cnt)
1253 {
1254 qeiv2_x->COUNT[QEIV2_COUNT_CURRENT].Z = cnt;
1255 }
1256
1257 /**
1258 * @brief set phase counter value
1259 *
1260 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
1261 * @param[in] cnt phase counter value
1262 */
qeiv2_set_phase_cnt(QEIV2_Type * qeiv2_x,uint32_t cnt)1263 static inline void qeiv2_set_phase_cnt(QEIV2_Type *qeiv2_x, uint32_t cnt)
1264 {
1265 qeiv2_x->PHASE_CNT = cnt;
1266 }
1267
1268 /**
1269 * @brief get phase counter value
1270 *
1271 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
1272 * @retval phase counter value
1273 */
qeiv2_get_phase_cnt(QEIV2_Type * qeiv2_x)1274 static inline uint32_t qeiv2_get_phase_cnt(QEIV2_Type *qeiv2_x)
1275 {
1276 return qeiv2_x->PHASE_CNT;
1277 }
1278
1279 /**
1280 * @brief update phase counter value
1281 *
1282 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
1283 * @param[in] inc set to add value to phase_cnt
1284 * @param[in] inc set to minus value to phase_cnt (set inc and dec same time willl act inc)
1285 * @param[in] value value to be added or minus from phase_cnt. only valid when inc or dec is set in one 32bit write operation.
1286 */
qeiv2_update_phase_cnt(QEIV2_Type * qeiv2_x,bool inc,bool dec,uint32_t value)1287 static inline void qeiv2_update_phase_cnt(QEIV2_Type *qeiv2_x, bool inc, bool dec, uint32_t value)
1288 {
1289 qeiv2_x->PHASE_UPDATE = QEIV2_PHASE_UPDATE_INC_SET(inc) | QEIV2_PHASE_UPDATE_DEC_SET(dec) | QEIV2_PHASE_UPDATE_VALUE_SET(value);
1290 }
1291
1292 /**
1293 * @brief set position value
1294 *
1295 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
1296 * @param[in] pos position
1297 */
qeiv2_set_position(QEIV2_Type * qeiv2_x,uint32_t pos)1298 static inline void qeiv2_set_position(QEIV2_Type *qeiv2_x, uint32_t pos)
1299 {
1300 qeiv2_x->POSITION = pos;
1301 }
1302
1303 /**
1304 * @brief get position value
1305 *
1306 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
1307 * @retval position value
1308 */
qeiv2_get_postion(QEIV2_Type * qeiv2_x)1309 static inline uint32_t qeiv2_get_postion(QEIV2_Type *qeiv2_x)
1310 {
1311 return qeiv2_x->POSITION;
1312 }
1313
1314 /**
1315 * @brief update position value
1316 *
1317 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
1318 * @param[in] inc set to add value to position
1319 * @param[in] inc set to minus cnt value to position (set inc and dec same time willl act inc)
1320 * @param[in] value value to be added or minus from position. only valid when inc or dec is set in one 32bit write operation.
1321 */
qeiv2_update_position(QEIV2_Type * qeiv2_x,bool inc,bool dec,uint32_t value)1322 static inline void qeiv2_update_position(QEIV2_Type *qeiv2_x, bool inc, bool dec, uint32_t value)
1323 {
1324 qeiv2_x->POSITION_UPDATE = QEIV2_POSITION_UPDATE_INC_SET(inc) | QEIV2_POSITION_UPDATE_DEC_SET(dec) | QEIV2_POSITION_UPDATE_VALUE_SET(value);
1325 }
1326
1327 /**
1328 * @brief get angle value
1329 *
1330 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
1331 * @retval angle value
1332 */
qeiv2_get_angle(QEIV2_Type * qeiv2_x)1333 static inline uint32_t qeiv2_get_angle(QEIV2_Type *qeiv2_x)
1334 {
1335 return qeiv2_x->ANGLE;
1336 }
1337
1338 /**
1339 * @brief set angle adjust value
1340 *
1341 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
1342 * @param[in] angle_adj angle adjust value
1343 */
qeiv2_set_angle_adjust_value(QEIV2_Type * qeiv2_x,int32_t angle_adj)1344 static inline void qeiv2_set_angle_adjust_value(QEIV2_Type *qeiv2_x, int32_t angle_adj)
1345 {
1346 qeiv2_x->ANGLE_ADJ = QEIV2_ANGLE_ADJ_ANGLE_ADJ_SET(angle_adj);
1347 }
1348
1349 /**
1350 * @brief config position timeout for mmc module
1351 *
1352 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
1353 * @param[in] tm postion timeout value
1354 * @param[in] enable enable position timeout feature. If timeout, send valid again.
1355 */
qeiv2_config_position_timeout(QEIV2_Type * qeiv2_x,uint32_t tm,bool enable)1356 static inline void qeiv2_config_position_timeout(QEIV2_Type *qeiv2_x, uint32_t tm, bool enable)
1357 {
1358 uint32_t tmp;
1359 tmp = QEIV2_POS_TIMEOUT_TIMEOUT_SET(tm);
1360 if (enable) {
1361 tmp |= QEIV2_POS_TIMEOUT_ENABLE_MASK;
1362 } else {
1363 tmp &= ~QEIV2_POS_TIMEOUT_ENABLE_MASK;
1364 }
1365 qeiv2_x->POS_TIMEOUT = tmp;
1366 }
1367
1368 /**
1369 * @brief config phcnt compare match condition
1370 *
1371 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
1372 * @param[in] config @ref qeiv2_phcnt_cmp_match_config_t
1373 * @return status_invalid_argument or status_success
1374 */
1375 hpm_stat_t qeiv2_config_phcnt_cmp_match_condition(QEIV2_Type *qeiv2_x, qeiv2_phcnt_cmp_match_config_t *config);
1376
1377 /**
1378 * @brief config position compare match condition
1379 *
1380 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
1381 * @param[in] config @ref qeiv2_pos_cmp_match_config_t
1382 * @return status_invalid_argument or status_success
1383 */
1384 hpm_stat_t qeiv2_config_position_cmp_match_condition(QEIV2_Type *qeiv2_x, qeiv2_pos_cmp_match_config_t *config);
1385
1386 /**
1387 * @brief config phcnt compare2 match condition
1388 *
1389 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
1390 * @param[in] config @ref qeiv2_phcnt_cmp_match_config_t
1391 * @return status_invalid_argument or status_success
1392 */
1393 hpm_stat_t qeiv2_config_phcnt_cmp2_match_condition(QEIV2_Type *qeiv2_x, qeiv2_phcnt_cmp_match_config_t *config);
1394
1395 /**
1396 * @brief config position compare2 match condition
1397 *
1398 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
1399 * @param[in] config @ref qeiv2_pos_cmp_match_config_t
1400 * @return status_invalid_argument or status_success
1401 */
1402 hpm_stat_t qeiv2_config_position_cmp2_match_condition(QEIV2_Type *qeiv2_x, qeiv2_pos_cmp_match_config_t *config);
1403
1404 /**
1405 * @brief get uvw position default config
1406 *
1407 * @param[out] config uvw position default config structure pointer
1408 */
1409 void qeiv2_get_uvw_position_defconfig(qeiv2_uvw_config_t *config);
1410
1411 /**
1412 * @brief config uvw position
1413 *
1414 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
1415 * @param[in] config uvw position config structure pointer
1416 * @return status_invalid_argument or status_success
1417 */
1418 hpm_stat_t qeiv2_config_uvw_position(QEIV2_Type *qeiv2_x, qeiv2_uvw_config_t *config);
1419
1420 #ifdef __cplusplus
1421 }
1422 #endif
1423 /**
1424 * @}
1425 */
1426 #endif /* HPM_QEIV2_DRV_H */
1427