1 /*
2 * Copyright (c) 2023 HPMicro
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 *
6 */
7
8 #ifndef HPM_RDC_DRV_H
9 #define HPM_RDC_DRV_H
10
11 #include "hpm_common.h"
12 #include "hpm_rdc_regs.h"
13 #include "hpm_soc_feature.h"
14
15 /**
16 * @brief RDC driver APIs
17 * @defgroup rdc_interface RDC driver APIs
18 * @ingroup rdc_interfaces
19 * @{
20 */
21
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26 /**
27 * @name Initialization and Deinitialization
28 * @{
29 */
30
31
32 /**
33 * @brief Rdc output precision, use n points to form an excitation signal period.
34 *
35 */
36 typedef enum rdc_output_precision {
37 rdc_output_precision_4_point = 0,
38 rdc_output_precision_8_point = 1,
39 rdc_output_precision_16_point = 2,
40 rdc_output_precision_32_point = 3,
41 rdc_output_precision_64_point = 4,
42 rdc_output_precision_128_point = 5,
43 rdc_output_precision_256_point = 6,
44 rdc_output_precision_512_point = 7,
45 rdc_output_precision_1024_point = 8,
46 } rdc_output_precision_t;
47
48 /**
49 * @brief Pwm output period in samples
50 *
51 */
52 typedef enum rdc_output_pwm_period {
53 rdc_output_pwm_period_1_sample = 0,
54 rdc_output_pwm_period_2_sample,
55 rdc_output_pwm_period_3_sample,
56 rdc_output_pwm_period_4_sample,
57 rdc_output_pwm_period_5_sample,
58 rdc_output_pwm_period_6_sample,
59 rdc_output_pwm_period_7_sample,
60 rdc_output_pwm_period_8_sample,
61 rdc_output_pwm_period_9_sample,
62 rdc_output_pwm_period_10_sample,
63 rdc_output_pwm_period_11_sample,
64 rdc_output_pwm_period_12_sample,
65 rdc_output_pwm_period_13_sample,
66 rdc_output_pwm_period_14_sample,
67 rdc_output_pwm_period_15_sample,
68 rdc_output_pwm_period_16_sample,
69 } rdc_output_pwm_period_t;
70
71
72
73 /**
74 * @brief Rdc output mode
75 *
76 */
77 typedef enum rdc_output_mode {
78 rdc_output_dac,
79 rdc_output_pwm
80 } rdc_output_mode_t;
81
82 /**
83 * @brief Synchronize output trig adc position
84 *
85 */
86 typedef enum rdc_sync_out_src {
87 rdc_sync_out_exc_0_ph = RDC_SYNC_OUT_CTRL_SYNC_OUT_SEL_SET(0),
88 rdc_sync_out_exc_90_ph = RDC_SYNC_OUT_CTRL_SYNC_OUT_SEL_SET(1),
89 rdc_sync_out_exc_180_ph = RDC_SYNC_OUT_CTRL_SYNC_OUT_SEL_SET(2),
90 rdc_sync_out_exc_270_ph = RDC_SYNC_OUT_CTRL_SYNC_OUT_SEL_SET(3),
91 rdc_sync_out_max = RDC_SYNC_OUT_CTRL_MAX2TRIG_EN_MASK,
92 rdc_sync_out_min = RDC_SYNC_OUT_CTRL_MIN2TRIG_EN_MASK,
93 } rdc_sync_out_src_t;
94
95 /**
96 * @brief Select reference point of rectify signal
97 *
98 */
99 typedef enum rdc_rectify_signal {
100 rdc_rectify_signal_exc_0_ph = 0,
101 rdc_rectify_signal_exc_90_ph = 1,
102 rdc_rectify_signal_exc_180_ph = 2,
103 rdc_rectify_signal_exc_270_ph = 3,
104 rdc_rectify_signal_external = 4,
105 rdc_rectify_signal_external_invert = 5,
106 } rdc_rectify_signal_t;
107
108 /**
109 * @brief Time stamp selection for accumulation
110 *
111 */
112 typedef enum rdc_acc_stamp_time {
113 rdc_acc_stamp_end_of_acc = 0, /**< End of accumulation */
114 rdc_acc_stamp_start_of_acc = 1, /**< Start of accumulation */
115 rdc_acc_stamp_center_of_acc = 2, /**< Center of accumulation */
116 } rdc_acc_stamp_time_t;
117
118 /**
119 * @brief Rdc trigger out channel 0 or channel 1
120 *
121 */
122 typedef enum rdc_output_trig_chn {
123 trigger_out_0 = 0,
124 trigger_out_1 = 1
125 } rdc_output_trig_chn_t;
126
127
128 /**
129 * @brief Rdc input channel
130 *
131 */
132 typedef enum rdc_input_acc_chn {
133 rdc_acc_chn_i = 0,
134 rdc_acc_chn_q = 1
135 } rdc_input_acc_chn_t;
136
137 /**
138 * @brief Rdc status flags
139 *
140 */
141 typedef enum rdc_interrupt_stat {
142 acc_vld_i_stat = RDC_INT_EN_ACC_VLD_I_EN_MASK,
143 acc_vld_q_stat = RDC_INT_EN_ACC_VLD_Q_EN_MASK,
144 rising_delay_i_stat = RDC_INT_EN_RISING_DELAY_I_EN_MASK,
145 falling_delay_i_stat = RDC_INT_EN_FALLING_DELAY_I_EN_MASK,
146 rising_delay_q_stat = RDC_INT_EN_RISING_DELAY_Q_EN_MASK,
147 falling_delay_q_stat = RDC_INT_EN_FALLING_DELAY_Q_EN_MASK,
148 sample_rising_i_stat = RDC_INT_EN_SAMPLE_RISING_I_EN_MASK,
149 sample_falling_i_stat = RDC_INT_EN_SAMPLE_FALLING_I_EN_MASK,
150 sample_rising_q_stat = RDC_INT_EN_SAMPLE_RISING_Q_EN_MASK,
151 sample_falling_q_stat = RDC_INT_EN_SAMPLE_FALLING_Q_EN_MASK,
152 acc_vld_i_ovh_stat = RDC_INT_EN_ACC_VLD_I_OVH_EN_MASK,
153 acc_vld_q_ovh_stat = RDC_INT_EN_ACC_VLD_Q_OVH_EN_MASK,
154 acc_vld_i_ovl_stat = RDC_INT_EN_ACC_VLD_I_OVL_EN_MASK,
155 acc_vld_q_ovl_stat = RDC_INT_EN_ACC_VLD_Q_OVL_EN_MASK,
156 acc_amp_ovh_stat = RDC_INT_EN_ACC_AMP_OVH_EN_MASK,
157 acc_amp_ovl_stat = RDC_INT_EN_ACC_AMP_OVL_EN_MASK,
158 } rdc_interrupt_stat_t;
159
160 /**
161 * @brief Rdc output configuration
162 *
163 */
164 typedef struct rdc_output_cfg {
165 rdc_output_mode_t mode; /**< pwm or dac */
166 uint32_t excitation_period_cycle; /**< The period of the excitation signal, in cycles */
167 rdc_output_precision_t excitation_precision; /**< Excitation signal precision */
168 rdc_output_pwm_period_t pwm_period; /**< Pwm period in samples */
169 bool output_swap; /**< Swap output of PWM and DAC */
170 int32_t amp_offset; /**< Offset for excitation, signed value*/
171 uint16_t amp_man; /**< Amplitude scaling for excitation, amplitude = [table value] x man / 2^exp */
172 uint16_t amp_exp; /**< Amplitude scaling for excitation, amplitude = [table value] x man / 2^exp */
173 bool pwm_dither_enable; /**< Enable dither of pwm */
174 bool pwm_exc_p_low_active; /**< Polarity of exc_p signal */
175 bool pwm_exc_n_low_active; /**< Polarity of exc_n signal */
176 bool trig_by_hw; /**< Hardware triggered excitation signal generation. Software triggering is required after shutdown */
177 uint32_t hw_trig_delay; /**< Trigger in delay timming in bus cycle from rising edge of trigger signal */
178 uint8_t dac_chn_i_sel; /**< Output channel selection for i_channel */
179 uint8_t dac_chn_q_sel; /**< Output channel selection for q_channel */
180 uint8_t pwm_deadzone_p; /**< Exc_p dead zone in clock cycle before swap */
181 uint8_t pwm_deadzone_n; /**< Exc_n dead zone in clock cycle before swap */
182 } rdc_output_cfg_t;
183
184
185 /**
186 * @brief Rdc input configuration
187 *
188 */
189 typedef struct rdc_input_cfg {
190 rdc_rectify_signal_t rectify_signal_sel; /**< Select reference point of rectify signal */
191 uint8_t acc_cycle_len; /**< Accumulate time, support on the fly change */
192 rdc_acc_stamp_time_t acc_stamp; /**< Time stamp selection for accumulation */
193 uint32_t acc_input_chn_i; /**< Input channel selection for i_channel */
194 uint32_t acc_input_port_i; /**< Input port selection for i_channel */
195 uint32_t acc_input_chn_q; /**< Input channel selection for q_channel */
196 uint32_t acc_input_port_q; /**< Input port selection for q_channel */
197 } rdc_input_cfg_t;
198
199 /**
200 * @brief Accumulated configuration information
201 *
202 */
203 typedef struct rdc_acc_cfg {
204 struct {
205 uint16_t continue_edge_num: 3; /**< Filtering val: 1 - 8 */
206 uint16_t edge_distance: 6; /**< Minimum distance between two edges 0-63 */
207 };
208 uint8_t right_shift_without_sign; /**< Right shift without sign bit */
209 bool error_data_remove; /**< Toxic accumulation data be removed */
210 uint32_t exc_carrier_period; /**< The num in clock cycle for period of excitation 0-NULL others-cycles */
211 uint32_t sync_delay_i; /**< Delay in clock cycle for synchronous signal, the value should less than half of exc_period.exc_period. */
212 uint32_t sync_delay_q; /**< Delay in clock cycle for synchronous signal, the value should less than half of exc_period.exc_period. */
213 uint32_t amp_max; /**< The maximum of acc amplitude */
214 uint32_t amp_min; /**< The minimum of acc amplitude */
215 } rdc_acc_cfg_t;
216
217 /** @} */
218
219 /**
220 * @name RDC Control
221 * @{
222 */
223
224 /**
225 * @brief Rdc output configuration, can be configured pwm output or dac output
226 *
227 * @param ptr @ref RDC_Type base
228 * @param cfg @ref rdc_output_cfg_t
229 */
230 void rdc_output_config(RDC_Type *ptr, rdc_output_cfg_t *cfg);
231
232 /**
233 * @brief Rdc input configuration, configuration of adc signal source and calculation parameters
234 *
235 * @param ptr @ref RDC_Type base
236 * @param cfg @ref rdc_input_cfg_t
237 */
238 void rdc_input_config(RDC_Type *ptr, rdc_input_cfg_t *cfg);
239
240 /**
241 * @brief Configuration accumulate time, support on the fly change
242 *
243 * @param ptr @ref RDC_Type base
244 * @param len accumulate time 0-255
245 */
rdc_set_acc_len(RDC_Type * ptr,uint8_t len)246 static inline void rdc_set_acc_len(RDC_Type *ptr, uint8_t len)
247 {
248 ptr->RDC_CTL = (ptr->RDC_CTL & (~RDC_RDC_CTL_ACC_LEN_MASK))
249 | RDC_RDC_CTL_ACC_LEN_SET(len);
250 }
251
252 /**
253 * @brief Enable accumulate calculation function
254 *
255 * @param ptr @ref RDC_Type base
256 */
rdc_acc_enable(RDC_Type * ptr)257 static inline void rdc_acc_enable(RDC_Type *ptr)
258 {
259 ptr->RDC_CTL |= RDC_RDC_CTL_ACC_EN_MASK;
260 }
261
262 /**
263 * @brief Disable accumulate calculation function
264 *
265 * @param ptr @ref RDC_Type base
266 */
rdc_acc_disable(RDC_Type * ptr)267 static inline void rdc_acc_disable(RDC_Type *ptr)
268 {
269 ptr->RDC_CTL &= ~RDC_RDC_CTL_ACC_EN_MASK;
270 }
271
272 /**
273 * @brief Get the accumulate value
274 *
275 * @param ptr @ref RDC_Type base
276 * @param chn @ref rdc_input_acc_chn_t
277 * @return uint32_t accumulate value
278 */
279 uint32_t rdc_get_acc_avl(RDC_Type *ptr, rdc_input_acc_chn_t chn);
280
281 /**
282 * @brief Output trigger configuration
283 * Lead time for trigger out0 or out1 from center of low level , this is a signed value
284 * @param ptr @ref RDC_Type base
285 * @param chn @ref rdc_output_trig_chn_t
286 * @param offset lead_time
287 */
288 void rdc_output_trig_offset_config(RDC_Type *ptr, rdc_output_trig_chn_t chn, int32_t offset);
289
290 /**
291 * @brief Enable output trigger configuration
292 *
293 * @param ptr @ref RDC_Type base
294 * @param chn @ref rdc_output_trig_chn_t
295 */
296 void rdc_output_trig_enable(RDC_Type *ptr, rdc_output_trig_chn_t chn);
297
298 /**
299 * @brief Disable rdc output trigger configuration
300 *
301 * @param ptr @ref RDC_Type base
302 * @param chn @ref rdc_output_trig_chn_t
303 */
304 void rdc_output_trig_disable(RDC_Type *ptr, rdc_output_trig_chn_t chn);
305
306 /**
307 * @brief Select output synchornize signal
308 *
309 * @param ptr @ref RDC_Type base
310 * @param sel @ref rdc_sync_out_src_t
311 */
rdc_sync_output_trig_adc_cfg(RDC_Type * ptr,rdc_sync_out_src_t sel)312 static inline void rdc_sync_output_trig_adc_cfg(RDC_Type *ptr, rdc_sync_out_src_t sel)
313 {
314 ptr->SYNC_OUT_CTRL = sel;
315 }
316
317 /**
318 * @brief Enable rdc excite signal
319 *
320 * @param ptr @ref RDC_Type base
321 */
rdc_exc_enable(RDC_Type * ptr)322 static inline void rdc_exc_enable(RDC_Type *ptr)
323 {
324 ptr->RDC_CTL |= RDC_RDC_CTL_EXC_EN_MASK;
325 }
326
327 /**
328 * @brief Disable rdc excite signal
329 *
330 * @param ptr @ref RDC_Type base
331 */
rdc_exc_disable(RDC_Type * ptr)332 static inline void rdc_exc_disable(RDC_Type *ptr)
333 {
334 ptr->RDC_CTL &= ~RDC_RDC_CTL_EXC_EN_MASK;
335 }
336
337 /**
338 * @brief Software triggered excitation signal output
339 *
340 * @param ptr @ref RDC_Type base
341 */
rdc_output_trig_sw(RDC_Type * ptr)342 static inline void rdc_output_trig_sw(RDC_Type *ptr)
343 {
344 ptr->RDC_CTL |= RDC_RDC_CTL_EXC_START_MASK;
345 }
346
347 /**
348 * @brief Get I-phase maximum
349 *
350 * @param ptr @ref RDC_Type base
351 * @retval - other max value
352 * - -1 illegal data
353 */
354 int32_t rdc_get_i_maxval(RDC_Type *ptr);
355
356 /**
357 * @brief Clear Maximum
358 *
359 * @param ptr @ref RDC_Type base
360 */
rdc_clear_i_maxval(RDC_Type * ptr)361 static inline void rdc_clear_i_maxval(RDC_Type *ptr)
362 {
363 ptr->MAX_I = 0;
364 }
365
366 /**
367 * @brief Get I-phase minimum
368 *
369 * @param ptr @ref RDC_Type base
370 * @retval - other max value
371 * - -1 illegal data
372 */
373 int32_t rdc_get_i_minval(RDC_Type *ptr);
374
375 /**
376 * @brief Clear I-phase minimum
377 *
378 * @param ptr @ref RDC_Type base
379 */
rdc_clear_i_minval(RDC_Type * ptr)380 static inline void rdc_clear_i_minval(RDC_Type *ptr)
381 {
382 ptr->MIN_I = 0;
383 }
384
385 /**
386 * @brief Set Acc sync delay
387 *
388 * @param ptr @ref RDC_Type base
389 * @param chn @ref rdc_input_acc_chn_t
390 * @param delay delay tick
391 */
392 void rdc_set_acc_sync_delay(RDC_Type *ptr, rdc_input_acc_chn_t chn, uint32_t delay);
393
394 /**
395 * @brief Delay bettween the delyed trigger and
396 * the first pwm pulse in clock cycle
397 *
398 * @param ptr @ref RDC_Type base
399 * @retval delay tick
400 */
rdc_get_sync_output_delay(RDC_Type * ptr)401 static inline uint32_t rdc_get_sync_output_delay(RDC_Type *ptr)
402 {
403 return RDC_SYNC_OUT_CTRL_PWM_OUT_DLY_GET(ptr->SYNC_OUT_CTRL);
404 }
405
406 /**
407 * @brief Get Q-phase maximum
408 *
409 * @param ptr @ref RDC_Type base
410 * @retval - other max value
411 * - -1 illegal data
412 */
413 int32_t rdc_get_q_maxval(RDC_Type *ptr);
414
415 /**
416 * @brief Clear Q-phase maxval
417 *
418 * @param ptr @ref RDC_Type base
419 */
rdc_clear_q_maxval(RDC_Type * ptr)420 static inline void rdc_clear_q_maxval(RDC_Type *ptr)
421 {
422 ptr->MAX_Q = 0;
423 }
424
425 /**
426 * @brief Get Q-phase Minval
427 *
428 * @param ptr @ref RDC_Type base
429 * @retval - other max value
430 * - -1 illegal data
431 */
432 int32_t rdc_get_q_minval(RDC_Type *ptr);
433
434 /**
435 * @brief Clear Q-phase Minval
436 *
437 * @param ptr @ref RDC_Type base
438 */
rdc_clear_q_minval(RDC_Type * ptr)439 static inline void rdc_clear_q_minval(RDC_Type *ptr)
440 {
441 ptr->MIN_Q = 0;
442 }
443
444 /**
445 * @brief The offset setting for edge detection of the i_channel or q_channel
446 *
447 * @param ptr @ref RDC_Type base
448 * @param chn @ref rdc_input_acc_chn_t
449 * @param offset offset value
450 */
451 void rdc_set_edge_detection_offset(RDC_Type *ptr, rdc_input_acc_chn_t chn, int32_t offset);
452
453 /**
454 * @brief RDC set accumulate configuration
455 *
456 * @param ptr @ref RDC_Type base
457 * @param cfg @ref rdc_acc_cfg_t
458 */
459 void rdc_set_acc_config(RDC_Type *ptr, rdc_acc_cfg_t *cfg);
460
461 /**
462 * @brief Get delay in clock cycle between excitation synchrnous signal and rising edge of i_channel data
463 *
464 * @param ptr @ref RDC_Type base
465 * @retval clock cycle
466 */
rdc_get_rise_delay_i(RDC_Type * ptr)467 static inline uint32_t rdc_get_rise_delay_i(RDC_Type *ptr)
468 {
469 return RDC_RISE_DELAY_I_RISE_DELAY_GET(ptr->RISE_DELAY_I);
470 }
471
472 /**
473 * @brief Get delay in clock cycle between excitation synchrnous signal and fall edge of i_channel data
474 *
475 * @param ptr @ref RDC_Type base
476 * @retval clock cycle
477 */
rdc_get_fall_delay_i(RDC_Type * ptr)478 static inline uint32_t rdc_get_fall_delay_i(RDC_Type *ptr)
479 {
480 return RDC_FALL_DELAY_I_FALL_DELAY_GET(ptr->FALL_DELAY_I);
481 }
482
483 /**
484 * @brief Get sample value on rising edge of rectify signal
485 *
486 * @param ptr @ref RDC_Type base
487 * @retval clock cycle
488 */
rdc_get_sample_rise_i(RDC_Type * ptr)489 static inline uint32_t rdc_get_sample_rise_i(RDC_Type *ptr)
490 {
491 return RDC_SAMPLE_RISE_I_VALUE_GET(ptr->SAMPLE_RISE_I);
492 }
493
494 /**
495 * @brief Get sample value on falling edge of rectify signal
496 *
497 * @param ptr @ref RDC_Type base
498 * @retval clock cycle
499 */
rdc_get_sample_fall_i(RDC_Type * ptr)500 static inline uint32_t rdc_get_sample_fall_i(RDC_Type *ptr)
501 {
502 return RDC_SAMPLE_FALL_I_VALUE_GET(ptr->SAMPLE_FALL_I);
503 }
504
505 /**
506 * @brief Get sample number during the positive of rectify signal
507 *
508 * @param ptr @ref RDC_Type base
509 * @retval counter
510 */
rdc_get_acc_cnt_positive_i(RDC_Type * ptr)511 static inline uint32_t rdc_get_acc_cnt_positive_i(RDC_Type *ptr)
512 {
513 return RDC_ACC_CNT_I_CNT_POS_GET(ptr->ACC_CNT_I);
514 }
515
516 /**
517 * @brief Get sample number during the negtive of rectify signal
518 *
519 * @param ptr @ref RDC_Type base
520 * @retval counter
521 */
rdc_get_acc_cnt_negative_i(RDC_Type * ptr)522 static inline uint32_t rdc_get_acc_cnt_negative_i(RDC_Type *ptr)
523 {
524 return RDC_ACC_CNT_I_CNT_POS_GET(ptr->ACC_CNT_I);
525 }
526
527 /**
528 * @brief Get Negative sample counter during positive rectify signal
529 *
530 * @param ptr @ref RDC_Type base
531 * @retval counter
532 */
rdc_get_sign_cnt_poitive_i(RDC_Type * ptr)533 static inline uint32_t rdc_get_sign_cnt_poitive_i(RDC_Type *ptr)
534 {
535 return RDC_SIGN_CNT_I_CNT_POS_GET(ptr->SIGN_CNT_I);
536 }
537
538 /**
539 * @brief Get Positive sample counter during negative rectify signal
540 *
541 * @param ptr @ref RDC_Type base
542 * @retval counter
543 */
rdc_get_sign_cnt_negative_i(RDC_Type * ptr)544 static inline uint32_t rdc_get_sign_cnt_negative_i(RDC_Type *ptr)
545 {
546 return RDC_SIGN_CNT_I_CNT_NEG_GET(ptr->SIGN_CNT_I);
547 }
548
549 /**
550 * @brief Get delay in clock cycle between excitation synchrnous signal and rising edge of q_channel data
551 *
552 * @param ptr @ref RDC_Type base
553 * @retval cycles
554 */
rdc_get_rise_delay_q(RDC_Type * ptr)555 static inline uint32_t rdc_get_rise_delay_q(RDC_Type *ptr)
556 {
557 return RDC_RISE_DELAY_Q_RISE_DELAY_GET(ptr->RISE_DELAY_Q);
558 }
559
560 /**
561 * @brief Get delay in clock cycle between excitation synchrnous signal and falling edge of q_channel data
562 *
563 * @param ptr @ref RDC_Type base
564 * @retval cycles
565 */
rdc_get_fall_delay_q(RDC_Type * ptr)566 static inline uint32_t rdc_get_fall_delay_q(RDC_Type *ptr)
567 {
568 return RDC_FALL_DELAY_Q_FALL_DELAY_GET(ptr->FALL_DELAY_Q);
569 }
570
571 /**
572 * @brief Get q channel sample value on rising edge of rectify signal
573 *
574 * @param ptr @ref RDC_Type base
575 * @retval cycles
576 */
rdc_get_sample_rise_q(RDC_Type * ptr)577 static inline uint32_t rdc_get_sample_rise_q(RDC_Type *ptr)
578 {
579 return RDC_SAMPLE_RISE_Q_VALUE_GET(ptr->SAMPLE_RISE_Q);
580 }
581
582 /**
583 * @brief Get q channel sample value on falling edge of rectify signal
584 *
585 * @param ptr @ref RDC_Type base
586 * @retval cycles
587 */
rdc_get_sample_fall_q(RDC_Type * ptr)588 static inline uint32_t rdc_get_sample_fall_q(RDC_Type *ptr)
589 {
590 return RDC_SAMPLE_FALL_Q_VALUE_GET(ptr->SAMPLE_FALL_Q);
591 }
592
593 /**
594 * @brief Get q channel sample number during the positive of rectify signal
595 *
596 * @param ptr @ref RDC_Type base
597 * @retval number
598 */
rdc_get_acc_cnt_positive_q(RDC_Type * ptr)599 static inline uint32_t rdc_get_acc_cnt_positive_q(RDC_Type *ptr)
600 {
601 return RDC_ACC_CNT_Q_CNT_POS_GET(ptr->ACC_CNT_Q);
602 }
603
604 /**
605 * @brief Get q channel sample number during the negtive of rectify signal
606 *
607 * @param ptr @ref RDC_Type base
608 * @retval number
609 */
rdc_get_acc_cnt_negative_q(RDC_Type * ptr)610 static inline uint32_t rdc_get_acc_cnt_negative_q(RDC_Type *ptr)
611 {
612 return RDC_ACC_CNT_Q_CNT_POS_GET(ptr->ACC_CNT_Q);
613 }
614
615 /**
616 * @brief Get q channel negative sample counter during positive rectify signal
617 *
618 * @param ptr @ref RDC_Type base
619 * @retval counter
620 */
rdc_get_sign_cnt_poitive_q(RDC_Type * ptr)621 static inline uint32_t rdc_get_sign_cnt_poitive_q(RDC_Type *ptr)
622 {
623 return RDC_SIGN_CNT_Q_CNT_POS_GET(ptr->SIGN_CNT_Q);
624 }
625
626 /**
627 * @brief Get q channel sample number during the negtive of rectify signal
628 *
629 * @param ptr @ref RDC_Type base
630 * @retval counter
631 */
rdc_get_sign_cnt_negative_q(RDC_Type * ptr)632 static inline uint32_t rdc_get_sign_cnt_negative_q(RDC_Type *ptr)
633 {
634 return RDC_SIGN_CNT_Q_CNT_NEG_GET(ptr->SIGN_CNT_Q);
635 }
636
637 /**
638 * @brief Enables configured interrupts
639 *
640 * @param ptr @ref RDC_Type base
641 * @param status @ref rdc_interrupt_stat_t
642 */
rdc_interrupt_config(RDC_Type * ptr,uint32_t status)643 static inline void rdc_interrupt_config(RDC_Type *ptr, uint32_t status)
644 {
645 ptr->INT_EN |= status;
646 }
647
648 /**
649 * @brief Clear interrupts configured
650 *
651 * @param ptr @ref RDC_Type base
652 * @param status @ref rdc_interrupt_stat_t
653 */
rdc_interrupt_reset_config(RDC_Type * ptr,uint32_t status)654 static inline void rdc_interrupt_reset_config(RDC_Type *ptr, uint32_t status)
655 {
656 ptr->INT_EN &= ~status;
657 }
658
659 /**
660 * @brief Enable rdc interrupt
661 *
662 * @param ptr @ref RDC_Type base
663 */
rdc_interrupt_enable(RDC_Type * ptr)664 static inline void rdc_interrupt_enable(RDC_Type *ptr)
665 {
666 ptr->INT_EN |= RDC_INT_EN_INT_EN_MASK;
667 }
668
669 /**
670 * @brief Disable rdc interrupt
671 *
672 * @param ptr @ref RDC_Type base
673 */
rdc_interrupt_disable(RDC_Type * ptr)674 static inline void rdc_interrupt_disable(RDC_Type *ptr)
675 {
676 ptr->INT_EN &= ~RDC_INT_EN_INT_EN_MASK;
677 }
678
679 /**
680 * @brief Clear interrupt flag bits
681 *
682 * @param ptr @ref RDC_Type base
683 * @param mask @ref rdc_interrupt_stat_t
684 */
rdc_interrupt_clear_flag_bits(RDC_Type * ptr,uint32_t mask)685 static inline void rdc_interrupt_clear_flag_bits(RDC_Type *ptr, uint32_t mask)
686 {
687 ptr->ADC_INT_STATE &= mask;
688 }
689
690 /**
691 * @brief Get the interrupt status object
692 *
693 * @param ptr @ref RDC_Type base
694 * @retval @ref rdc_interrupt_stat_t
695 */
get_interrupt_status(RDC_Type * ptr)696 static inline uint32_t get_interrupt_status(RDC_Type *ptr)
697 {
698 return ptr->ADC_INT_STATE;
699 }
700
701 /** @} */
702
703 #ifdef __cplusplus
704 }
705 #endif
706
707 /** @} */
708 #endif /* HPM_ADC12_DRV_H */
709