1 /*
2 * Copyright (c) 2021 HPMicro
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 *
6 */
7
8 #include "hpm_soc_feature.h"
9 #include "hpm_pla_drv.h"
10
pla_set_aoi_16to8_one_channel(PLA_Type * pla,pla_aoi_16to8_chn_cfg_t * cfg)11 void pla_set_aoi_16to8_one_channel(PLA_Type *pla,
12 pla_aoi_16to8_chn_cfg_t *cfg)
13 {
14 uint8_t i;
15 uint32_t value;
16
17 value = 0;
18 for (i = 0; i < PLA_AOI_16TO8_SIGNAL_NUM; i++) {
19 value |= ((uint32_t)cfg->input[i].op) << (cfg->input[i].signal << 1);
20 }
21 pla->CHN[cfg->chn].AOI_16TO8[cfg->aoi_16to8_chn] = value;
22 }
23
pla_get_aoi_16to8_one_channel(PLA_Type * pla,pla_channel_type_t chn,pla_aoi_16to8_channel_type_t aoi_16to8_chn,pla_aoi_16to8_chn_cfg_t * cfg)24 void pla_get_aoi_16to8_one_channel(PLA_Type *pla,
25 pla_channel_type_t chn,
26 pla_aoi_16to8_channel_type_t aoi_16to8_chn,
27 pla_aoi_16to8_chn_cfg_t *cfg)
28 {
29 uint8_t i;
30
31 for (i = 0; i < PLA_AOI_16TO8_SIGNAL_NUM; i++) {
32 cfg->input[i].signal = i;
33 cfg->input[i].op = (pla->CHN[chn].AOI_16TO8[aoi_16to8_chn] >> (i << 1)) & 0x03;
34 }
35 }
36
pla_set_aoi_8to7_one_channel(PLA_Type * pla,pla_aoi_8to7_chn_cfg_t * cfg)37 void pla_set_aoi_8to7_one_channel(PLA_Type *pla,
38 pla_aoi_8to7_chn_cfg_t *cfg)
39 {
40 uint8_t i;
41 uint32_t value;
42
43 value = 0;
44 for (i = 0; i < PLA_AOI_8TO7_SIGNAL_NUM; i++) {
45 value |= ((uint32_t)cfg->input[i].op) << (cfg->input[i].signal << 1);
46 }
47 switch (cfg->aoi_8to7_chn) {
48 case pla_aoi_8to7_chn_0:
49 pla->CHN[cfg->chn].AOI_8TO7_00_01 = (pla->CHN[cfg->chn].AOI_8TO7_00_01 & 0xffff0000) | value;
50 break;
51 case pla_aoi_8to7_chn_1:
52 pla->CHN[cfg->chn].AOI_8TO7_00_01 = (pla->CHN[cfg->chn].AOI_8TO7_00_01 & 0x0000ffff) | (value << 16);
53 break;
54 case pla_aoi_8to7_chn_2:
55 pla->CHN[cfg->chn].AOI_8TO7_02_03 = (pla->CHN[cfg->chn].AOI_8TO7_02_03 & 0xffff0000) | value;
56 break;
57 case pla_aoi_8to7_chn_3:
58 pla->CHN[cfg->chn].AOI_8TO7_02_03 = (pla->CHN[cfg->chn].AOI_8TO7_02_03 & 0x0000ffff) | (value << 16);
59 break;
60 case pla_aoi_8to7_chn_4:
61 pla->CHN[cfg->chn].AOI_8TO7_04_05 = (pla->CHN[cfg->chn].AOI_8TO7_04_05 & 0xffff0000) | value;
62 break;
63 case pla_aoi_8to7_chn_5:
64 pla->CHN[cfg->chn].AOI_8TO7_04_05 = (pla->CHN[cfg->chn].AOI_8TO7_04_05 & 0x0000ffff) | (value << 16);
65 break;
66 case pla_aoi_8to7_chn_6:
67 pla->CHN[cfg->chn].AOI_8TO7_06 = value;
68 break;
69 default:
70 break;
71 }
72 }
73
pla_get_aoi_8to7_one_channel(PLA_Type * pla,pla_aoi_8to7_chn_cfg_t * cfg)74 void pla_get_aoi_8to7_one_channel(PLA_Type *pla,
75 pla_aoi_8to7_chn_cfg_t *cfg)
76 {
77 uint8_t i;
78
79 switch (cfg->aoi_8to7_chn) {
80 case pla_aoi_8to7_chn_0:
81 for (i = 0; i < PLA_AOI_8TO7_SIGNAL_NUM; i++) {
82 cfg->input[i].signal = i;
83 cfg->input[i].op = (pla->CHN[cfg->chn].AOI_8TO7_00_01 >> (i << 1)) & 0x03;
84 }
85 break;
86 case pla_aoi_8to7_chn_1:
87 for (i = 0; i < PLA_AOI_8TO7_SIGNAL_NUM; i++) {
88 cfg->input[i].signal = i;
89 cfg->input[i].op = (pla->CHN[cfg->chn].AOI_8TO7_00_01 >> (i << 17)) & 0x03;
90 }
91 break;
92 case pla_aoi_8to7_chn_2:
93 for (i = 0; i < PLA_AOI_8TO7_SIGNAL_NUM; i++) {
94 cfg->input[i].signal = i;
95 cfg->input[i].op = (pla->CHN[cfg->chn].AOI_8TO7_02_03 >> (i << 1)) & 0x03;
96 }
97 break;
98 case pla_aoi_8to7_chn_3:
99 for (i = 0; i < PLA_AOI_8TO7_SIGNAL_NUM; i++) {
100 cfg->input[i].signal = i;
101 cfg->input[i].op = (pla->CHN[cfg->chn].AOI_8TO7_02_03 >> (i << 17)) & 0x03;
102 }
103 break;
104 case pla_aoi_8to7_chn_4:
105 for (i = 0; i < PLA_AOI_8TO7_SIGNAL_NUM; i++) {
106 cfg->input[i].signal = i;
107 cfg->input[i].op = (pla->CHN[cfg->chn].AOI_8TO7_04_05 >> (i << 1)) & 0x03;
108 }
109 break;
110 case pla_aoi_8to7_chn_5:
111 for (i = 0; i < PLA_AOI_8TO7_SIGNAL_NUM; i++) {
112 cfg->input[i].signal = i;
113 cfg->input[i].op = (pla->CHN[cfg->chn].AOI_8TO7_04_05 >> (i << 17)) & 0x03;
114 }
115 break;
116 case pla_aoi_8to7_chn_6:
117 for (i = 0; i < PLA_AOI_8TO7_SIGNAL_NUM; i++) {
118 cfg->input[i].signal = i;
119 cfg->input[i].op = (pla->CHN[cfg->chn].AOI_8TO7_06 >> (i << 1)) & 0x03;
120 }
121 break;
122 default:
123 break;
124 }
125 }
126
pla_set_aoi_8to7_input_signal(PLA_Type * pla,pla_channel_type_t chn,pla_aoi_8to7_channel_type_t aoi_8to7_chn,pla_aoi_8to7_cfg_unit_t * cfg)127 void pla_set_aoi_8to7_input_signal(PLA_Type *pla,
128 pla_channel_type_t chn,
129 pla_aoi_8to7_channel_type_t aoi_8to7_chn,
130 pla_aoi_8to7_cfg_unit_t *cfg)
131 {
132 uint32_t value;
133
134 value = ((uint32_t)cfg->op) << (cfg->signal << 1);
135 switch (aoi_8to7_chn) {
136 case pla_aoi_8to7_chn_0:
137 pla->CHN[chn].AOI_8TO7_00_01 = (pla->CHN[chn].AOI_8TO7_00_01 & 0xffff0000) | value;
138 break;
139 case pla_aoi_8to7_chn_1:
140 pla->CHN[chn].AOI_8TO7_00_01 = (pla->CHN[chn].AOI_8TO7_00_01 & 0x0000ffff) | (value << 16);
141 break;
142 case pla_aoi_8to7_chn_2:
143 pla->CHN[chn].AOI_8TO7_02_03 = (pla->CHN[chn].AOI_8TO7_02_03 & 0xffff0000) | value;
144 break;
145 case pla_aoi_8to7_chn_3:
146 pla->CHN[chn].AOI_8TO7_02_03 = (pla->CHN[chn].AOI_8TO7_02_03 & 0x0000ffff) | (value << 16);
147 break;
148 case pla_aoi_8to7_chn_4:
149 pla->CHN[chn].AOI_8TO7_04_05 = (pla->CHN[chn].AOI_8TO7_04_05 & 0xffff0000) | value;
150 break;
151 case pla_aoi_8to7_chn_5:
152 pla->CHN[chn].AOI_8TO7_04_05 = (pla->CHN[chn].AOI_8TO7_04_05 & 0x0000ffff) | (value << 16);
153 break;
154 case pla_aoi_8to7_chn_6:
155 pla->CHN[chn].AOI_8TO7_06 = value;
156 break;
157 default:
158 break;
159 }
160 }
161
pla_get_aoi_8to7_input_signal(PLA_Type * pla,pla_channel_type_t chn,pla_aoi_8to7_channel_type_t aoi_8to7_chn,pla_aoi_8to7_input_signal_type_t signal,pla_aoi_8to7_cfg_unit_t * cfg)162 void pla_get_aoi_8to7_input_signal(PLA_Type *pla,
163 pla_channel_type_t chn,
164 pla_aoi_8to7_channel_type_t aoi_8to7_chn,
165 pla_aoi_8to7_input_signal_type_t signal,
166 pla_aoi_8to7_cfg_unit_t *cfg)
167 {
168
169 switch (aoi_8to7_chn) {
170 case pla_aoi_8to7_chn_0:
171 cfg->signal = signal;
172 cfg->op = (pla->CHN[chn].AOI_8TO7_00_01 >> (signal << 1)) & 0x03;
173 break;
174 case pla_aoi_8to7_chn_1:
175 cfg->signal = signal;
176 cfg->op = (pla->CHN[chn].AOI_8TO7_00_01 >> (signal << 17)) & 0x03;
177 break;
178 case pla_aoi_8to7_chn_2:
179 cfg->signal = signal;
180 cfg->op = (pla->CHN[chn].AOI_8TO7_02_03 >> (signal << 1)) & 0x03;
181 break;
182 case pla_aoi_8to7_chn_3:
183 cfg->signal = signal;
184 cfg->op = (pla->CHN[chn].AOI_8TO7_02_03 >> (signal << 17)) & 0x03;
185 break;
186 case pla_aoi_8to7_chn_4:
187 cfg->signal = signal;
188 cfg->op = (pla->CHN[chn].AOI_8TO7_04_05 >> (signal << 1)) & 0x03;
189 break;
190 case pla_aoi_8to7_chn_5:
191 cfg->signal = signal;
192 cfg->op = (pla->CHN[chn].AOI_8TO7_04_05 >> (signal << 17)) & 0x03;
193 break;
194 case pla_aoi_8to7_chn_6:
195 cfg->signal = signal;
196 cfg->op = (pla->CHN[chn].AOI_8TO7_06 >> (signal << 1)) & 0x03;
197 break;
198 default:
199 break;
200 }
201 }
202