1 /*
2 * Copyright (c) 2023 HPMicro
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 *
6 */
7
8 #ifndef HPM_INTERRUPT_H
9 #define HPM_INTERRUPT_H
10 #include "hpm_common.h"
11 #include "hpm_csr_drv.h"
12 #include "hpm_plic_drv.h"
13
14 /**
15 * @brief INTERRUPT driver APIs
16 * @defgroup irq_interface INTERRUPT driver APIs
17 * @{
18 */
19
20 #define M_MODE 0 /*!< Machine mode */
21 #define S_MODE 1 /*!< Supervisor mode */
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Machine mode API: these APIs are supposed to be called at machine mode */
28
29 /**
30 * @brief Enable global IRQ with mask
31 *
32 * @param[in] mask interrupt mask to be enabaled
33 */
enable_global_irq(uint32_t mask)34 ATTR_ALWAYS_INLINE static inline void enable_global_irq(uint32_t mask)
35 {
36 set_csr(CSR_MSTATUS, mask);
37 }
38
39 /**
40 * @brief Disable global IRQ with mask and return mstatus
41 *
42 * @param[in] mask interrupt mask to be disabled
43 * @retval current mstatus value before irq mask is disabled
44 */
disable_global_irq(uint32_t mask)45 ATTR_ALWAYS_INLINE static inline uint32_t disable_global_irq(uint32_t mask)
46 {
47 return read_clear_csr(CSR_MSTATUS, mask);
48 }
49
50 /**
51 * @brief Restore global IRQ with mask
52 *
53 * @param[in] mask interrupt mask to be restored
54 */
restore_global_irq(uint32_t mask)55 ATTR_ALWAYS_INLINE static inline void restore_global_irq(uint32_t mask)
56 {
57 set_csr(CSR_MSTATUS, mask);
58 }
59
60 /**
61 * @brief Enable IRQ from interrupt controller
62 *
63 */
enable_irq_from_intc(void)64 ATTR_ALWAYS_INLINE static inline void enable_irq_from_intc(void)
65 {
66 set_csr(CSR_MIE, CSR_MIE_MEIE_MASK);
67 }
68
69 /**
70 * @brief Disable IRQ from interrupt controller
71 *
72 */
disable_irq_from_intc(void)73 ATTR_ALWAYS_INLINE static inline void disable_irq_from_intc(void)
74 {
75 clear_csr(CSR_MIE, CSR_MIE_MEIE_MASK);
76 }
77
78 /**
79 * @brief Enable machine timer IRQ
80 */
enable_mchtmr_irq(void)81 ATTR_ALWAYS_INLINE static inline void enable_mchtmr_irq(void)
82 {
83 set_csr(CSR_MIE, CSR_MIE_MTIE_MASK);
84 }
85
86 /**
87 * @brief Disable machine timer IRQ
88 *
89 */
disable_mchtmr_irq(void)90 ATTR_ALWAYS_INLINE static inline void disable_mchtmr_irq(void)
91 {
92 clear_csr(CSR_MIE, CSR_MIE_MTIE_MASK);
93 }
94
95 /*
96 * CPU Machine SWI control
97 *
98 * Machine SWI (MSIP) is connected to PLICSW irq 1.
99 */
100 #define PLICSWI 1
101
102 /**
103 * @brief Initialize software interrupt
104 *
105 */
intc_m_init_swi(void)106 ATTR_ALWAYS_INLINE static inline void intc_m_init_swi(void)
107 {
108 __plic_enable_irq(HPM_PLICSW_BASE, HPM_PLIC_TARGET_M_MODE, PLICSWI);
109 }
110
111
112 /**
113 * @brief Enable software interrupt
114 *
115 */
intc_m_enable_swi(void)116 ATTR_ALWAYS_INLINE static inline void intc_m_enable_swi(void)
117 {
118 set_csr(CSR_MIE, CSR_MIE_MSIE_MASK);
119 }
120
121
122 /**
123 * @brief Disable software interrupt
124 *
125 */
intc_m_disable_swi(void)126 ATTR_ALWAYS_INLINE static inline void intc_m_disable_swi(void)
127 {
128 clear_csr(CSR_MIE, CSR_MIE_MSIE_MASK);
129 }
130
131
132 /**
133 * @brief Trigger software interrupt
134 *
135 */
intc_m_trigger_swi(void)136 ATTR_ALWAYS_INLINE static inline void intc_m_trigger_swi(void)
137 {
138 __plic_set_irq_pending(HPM_PLICSW_BASE, PLICSWI);
139 }
140
141 /**
142 * @brief Claim software interrupt
143 *
144 */
intc_m_claim_swi(void)145 ATTR_ALWAYS_INLINE static inline void intc_m_claim_swi(void)
146 {
147 __plic_claim_irq(HPM_PLICSW_BASE, 0);
148 }
149
150 /**
151 * @brief Complete software interrupt
152 *
153 */
intc_m_complete_swi(void)154 ATTR_ALWAYS_INLINE static inline void intc_m_complete_swi(void)
155 {
156 __plic_complete_irq(HPM_PLICSW_BASE, HPM_PLIC_TARGET_M_MODE, PLICSWI);
157 }
158
159 /*
160 * @brief Enable IRQ for machine mode
161 *
162 * @param[in] irq Interrupt number
163 */
164 #define intc_m_enable_irq(irq) \
165 intc_enable_irq(HPM_PLIC_TARGET_M_MODE, irq)
166
167 /*
168 * @brief Disable IRQ for machine mode
169 *
170 * @param[in] irq Interrupt number
171 */
172 #define intc_m_disable_irq(irq) \
173 intc_disable_irq(HPM_PLIC_TARGET_M_MODE, irq)
174
175 #define intc_m_set_threshold(threshold) \
176 intc_set_threshold(HPM_PLIC_TARGET_M_MODE, threshold)
177
178 /*
179 * @brief Complete IRQ for machine mode
180 *
181 * @param[in] irq Interrupt number
182 */
183 #define intc_m_complete_irq(irq) \
184 intc_complete_irq(HPM_PLIC_TARGET_M_MODE, irq)
185
186 /*
187 * @brief Claim IRQ for machine mode
188 *
189 */
190 #define intc_m_claim_irq() intc_claim_irq(HPM_PLIC_TARGET_M_MODE)
191
192 /*
193 * @brief Enable IRQ for machine mode with priority
194 *
195 * @param[in] irq Interrupt number
196 * @param[in] priority Priority of interrupt
197 */
198 #define intc_m_enable_irq_with_priority(irq, priority) \
199 do { \
200 intc_set_irq_priority(irq, priority); \
201 intc_m_enable_irq(irq); \
202 } while (0)
203
204 /*
205 * @brief Enable specific interrupt
206 *
207 * @param[in] target Target to handle specific interrupt
208 * @param[in] irq Interrupt number
209 */
intc_enable_irq(uint32_t target,uint32_t irq)210 ATTR_ALWAYS_INLINE static inline void intc_enable_irq(uint32_t target, uint32_t irq)
211 {
212 __plic_enable_irq(HPM_PLIC_BASE, target, irq);
213 }
214
215 /**
216 * @brief Set interrupt priority
217 *
218 * @param[in] irq Interrupt number
219 * @param[in] priority Priority of interrupt
220 */
intc_set_irq_priority(uint32_t irq,uint32_t priority)221 ATTR_ALWAYS_INLINE static inline void intc_set_irq_priority(uint32_t irq, uint32_t priority)
222 {
223 __plic_set_irq_priority(HPM_PLIC_BASE, irq, priority);
224 }
225
226 /**
227 * @brief Disable specific interrupt
228 *
229 * @param[in] target Target to handle specific interrupt
230 * @param[in] irq Interrupt number
231 */
intc_disable_irq(uint32_t target,uint32_t irq)232 ATTR_ALWAYS_INLINE static inline void intc_disable_irq(uint32_t target, uint32_t irq)
233 {
234 __plic_disable_irq(HPM_PLIC_BASE, target, irq);
235 }
236
237 /**
238 * @brief Set interrupt threshold
239 *
240 * @param[in] target Target to handle specific interrupt
241 * @param[in] threshold Threshold of IRQ can be serviced
242 */
intc_set_threshold(uint32_t target,uint32_t threshold)243 ATTR_ALWAYS_INLINE static inline void intc_set_threshold(uint32_t target, uint32_t threshold)
244 {
245 __plic_set_threshold(HPM_PLIC_BASE, target, threshold);
246 }
247
248 /**
249 * @brief Claim IRQ
250 *
251 * @param[in] target Target to handle specific interrupt
252 *
253 */
intc_claim_irq(uint32_t target)254 ATTR_ALWAYS_INLINE static inline uint32_t intc_claim_irq(uint32_t target)
255 {
256 return __plic_claim_irq(HPM_PLIC_BASE, target);
257 }
258
259 /**
260 * @brief Complete IRQ
261 *
262 * @param[in] target Target to handle specific interrupt
263 * @param[in] irq Specific IRQ to be completed
264 *
265 */
intc_complete_irq(uint32_t target,uint32_t irq)266 ATTR_ALWAYS_INLINE static inline void intc_complete_irq(uint32_t target, uint32_t irq)
267 {
268 __plic_complete_irq(HPM_PLIC_BASE, target, irq);
269 }
270
271 /*
272 * Vectored based irq install and uninstall
273 */
274 /* Machine mode */
275 extern int __vector_table[];
276
277 extern void default_irq_entry(void);
278
279 /**
280 * @brief Install ISR for certain IRQ for ram based vector table
281 *
282 * @param[in] irq Target interrupt number
283 * @param[in] isr Interrupt service routine
284 *
285 */
install_isr(uint32_t irq,uint32_t isr)286 ATTR_ALWAYS_INLINE static inline void install_isr(uint32_t irq, uint32_t isr)
287 {
288 __vector_table[irq] = isr;
289 }
290
291 /**
292 * @brief Uninstall ISR for certain IRQ for ram based vector table
293 *
294 * @param[in] irq Target interrupt number
295 *
296 */
uninstall_isr(uint32_t irq)297 ATTR_ALWAYS_INLINE static inline void uninstall_isr(uint32_t irq)
298 {
299 __vector_table[irq] = (int) default_irq_entry;
300 }
301
302 /*
303 * Inline nested irq entry/exit macros
304 */
305 /*
306 * @brief Save CSR
307 * @param[in] r Target CSR to be saved
308 */
309 #define SAVE_CSR(r) register long __##r = read_csr(r);
310
311 /*
312 * @brief Restore macro
313 *
314 * @param[in] r Target CSR to be restored
315 */
316 #define RESTORE_CSR(r) write_csr(r, __##r);
317
318 #if defined(SUPPORT_PFT_ARCH) && SUPPORT_PFT_ARCH
319 #define SAVE_MXSTATUS() SAVE_CSR(CSR_MXSTATUS)
320 #define RESTORE_MXSTATUS() RESTORE_CSR(CSR_MXSTATUS)
321 #else
322 #define SAVE_MXSTATUS()
323 #define RESTORE_MXSTATUS()
324 #endif
325
326 #ifdef __riscv_flen
327 #define SAVE_FCSR() register int __fcsr = read_fcsr();
328 #define RESTORE_FCSR() write_fcsr(__fcsr);
329 #else
330 #define SAVE_FCSR()
331 #define RESTORE_FCSR()
332 #endif
333
334 #ifdef __riscv_dsp
335 #define SAVE_UCODE() SAVE_CSR(CSR_UCODE)
336 #define RESTORE_UCODE() RESTORE_CSR(CSR_UCODE)
337 #else
338 #define SAVE_UCODE()
339 #define RESTORE_UCODE()
340 #endif
341
342 #ifdef __riscv_flen
343 #if __riscv_flen == 32
344 /* RV32I caller registers + MCAUSE + MEPC + MSTATUS +MXSTATUS + 20 FPU caller registers +FCSR + UCODE (DSP) */
345 #define CONTEXT_REG_NUM (4 * (16 + 4 + 20))
346 #else /* __riscv_flen = 64 */
347 /* RV32I caller registers + MCAUSE + MEPC + MSTATUS +MXSTATUS + 20 DFPU caller + FCSR registers + UCODE (DSP) */
348 #define CONTEXT_REG_NUM (4 * (16 + 4 + 20 * 2))
349 #endif
350
351 #else
352 /* RV32I caller registers + MCAUSE + MEPC + MSTATUS +MXSTATUS + UCODE (DSP)*/
353 #define CONTEXT_REG_NUM (4 * (16 + 4))
354 #endif
355
356 #ifdef __riscv_flen
357 /*
358 * Save FPU caller registers:
359 * NOTE: To simplify the logic, the FPU caller registers are always stored at word offset 20 in the stack
360 */
361 #if __riscv_flen == 32
362 #define SAVE_FPU_CONTEXT() { \
363 __asm volatile("\n\
364 c.fswsp ft0, 20*4(sp)\n\
365 c.fswsp ft1, 21*4(sp) \n\
366 c.fswsp ft2, 22*4(sp) \n\
367 c.fswsp ft3, 23*4(sp) \n\
368 c.fswsp ft4, 24*4(sp) \n\
369 c.fswsp ft5, 25*4(sp) \n\
370 c.fswsp ft6, 26*4(sp) \n\
371 c.fswsp ft7, 27*4(sp) \n\
372 c.fswsp fa0, 28*4(sp) \n\
373 c.fswsp fa1, 29*4(sp) \n\
374 c.fswsp fa2, 30*4(sp) \n\
375 c.fswsp fa3, 31*4(sp) \n\
376 c.fswsp fa4, 32*4(sp) \n\
377 c.fswsp fa5, 33*4(sp) \n\
378 c.fswsp fa6, 34*4(sp) \n\
379 c.fswsp fa7, 35*4(sp) \n\
380 c.fswsp ft8, 36*4(sp) \n\
381 c.fswsp ft9, 37*4(sp) \n\
382 c.fswsp ft10, 38*4(sp) \n\
383 c.fswsp ft11, 39*4(sp) \n");\
384 }
385
386 /*
387 * Restore FPU caller registers:
388 * NOTE: To simplify the logic, the FPU caller registers are always stored at word offset 20 in the stack
389 */
390 #define RESTORE_FPU_CONTEXT() { \
391 __asm volatile("\n\
392 c.flwsp ft0, 20*4(sp)\n\
393 c.flwsp ft1, 21*4(sp) \n\
394 c.flwsp ft2, 22*4(sp) \n\
395 c.flwsp ft3, 23*4(sp) \n\
396 c.flwsp ft4, 24*4(sp) \n\
397 c.flwsp ft5, 25*4(sp) \n\
398 c.flwsp ft6, 26*4(sp) \n\
399 c.flwsp ft7, 27*4(sp) \n\
400 c.flwsp fa0, 28*4(sp) \n\
401 c.flwsp fa1, 29*4(sp) \n\
402 c.flwsp fa2, 30*4(sp) \n\
403 c.flwsp fa3, 31*4(sp) \n\
404 c.flwsp fa4, 32*4(sp) \n\
405 c.flwsp fa5, 33*4(sp) \n\
406 c.flwsp fa6, 34*4(sp) \n\
407 c.flwsp fa7, 35*4(sp) \n\
408 c.flwsp ft8, 36*4(sp) \n\
409 c.flwsp ft9, 37*4(sp) \n\
410 c.flwsp ft10, 38*4(sp) \n\
411 c.flwsp ft11, 39*4(sp) \n");\
412 }
413 #else /*__riscv_flen == 64*/
414 #define SAVE_FPU_CONTEXT() { \
415 __asm volatile("\n\
416 c.fsdsp ft0, 20*4(sp)\n\
417 c.fsdsp ft1, 22*4(sp) \n\
418 c.fsdsp ft2, 24*4(sp) \n\
419 c.fsdsp ft3, 26*4(sp) \n\
420 c.fsdsp ft4, 28*4(sp) \n\
421 c.fsdsp ft5, 30*4(sp) \n\
422 c.fsdsp ft6, 32*4(sp) \n\
423 c.fsdsp ft7, 34*4(sp) \n\
424 c.fsdsp fa0, 36*4(sp) \n\
425 c.fsdsp fa1, 38*4(sp) \n\
426 c.fsdsp fa2, 40*4(sp) \n\
427 c.fsdsp fa3, 42*4(sp) \n\
428 c.fsdsp fa4, 44*4(sp) \n\
429 c.fsdsp fa5, 46*4(sp) \n\
430 c.fsdsp fa6, 48*4(sp) \n\
431 c.fsdsp fa7, 50*4(sp) \n\
432 c.fsdsp ft8, 52*4(sp) \n\
433 c.fsdsp ft9, 54*4(sp) \n\
434 c.fsdsp ft10, 56*4(sp) \n\
435 c.fsdsp ft11, 58*4(sp) \n");\
436 }
437
438 /*
439 * Restore FPU caller registers:
440 * NOTE: To simplify the logic, the FPU caller registers are always stored at word offset 20 in the stack
441 */
442 #define RESTORE_FPU_CONTEXT() { \
443 __asm volatile("\n\
444 c.fldsp ft0, 20*4(sp)\n\
445 c.fldsp ft1, 22*4(sp) \n\
446 c.fldsp ft2, 24*4(sp) \n\
447 c.fldsp ft3, 26*4(sp) \n\
448 c.fldsp ft4, 28*4(sp) \n\
449 c.fldsp ft5, 30*4(sp) \n\
450 c.fldsp ft6, 32*4(sp) \n\
451 c.fldsp ft7, 34*4(sp) \n\
452 c.fldsp fa0, 36*4(sp) \n\
453 c.fldsp fa1, 38*4(sp) \n\
454 c.fldsp fa2, 40*4(sp) \n\
455 c.fldsp fa3, 42*4(sp) \n\
456 c.fldsp fa4, 44*4(sp) \n\
457 c.fldsp fa5, 46*4(sp) \n\
458 c.fldsp fa6, 48*4(sp) \n\
459 c.fldsp fa7, 50*4(sp) \n\
460 c.fldsp ft8, 52*4(sp) \n\
461 c.fldsp ft9, 54*4(sp) \n\
462 c.fldsp ft10, 56*4(sp) \n\
463 c.fldsp ft11, 58*4(sp) \n");\
464 }
465 #endif
466 #else
467 #define SAVE_FPU_CONTEXT()
468 #define RESTORE_FPU_CONTEXT()
469 #endif
470
471 /**
472 * @brief Save the caller registers based on the RISC-V ABI specification
473 */
474 #define SAVE_CALLER_CONTEXT() { \
475 __asm volatile("addi sp, sp, %0" : : "i"(-CONTEXT_REG_NUM) :);\
476 __asm volatile("\n\
477 c.swsp ra, 0*4(sp) \n\
478 c.swsp t0, 1*4(sp) \n\
479 c.swsp t1, 2*4(sp) \n\
480 c.swsp t2, 3*4(sp) \n\
481 c.swsp s0, 4*4(sp) \n\
482 c.swsp s1, 5*4(sp) \n\
483 c.swsp a0, 6*4(sp) \n\
484 c.swsp a1, 7*4(sp) \n\
485 c.swsp a2, 8*4(sp) \n\
486 c.swsp a3, 9*4(sp) \n\
487 c.swsp a4, 10*4(sp) \n\
488 c.swsp a5, 11*4(sp) \n\
489 c.swsp a6, 12*4(sp) \n\
490 c.swsp a7, 13*4(sp) \n\
491 c.swsp s2, 14*4(sp) \n\
492 c.swsp s3, 15*4(sp) \n\
493 c.swsp t3, 16*4(sp) \n\
494 c.swsp t4, 17*4(sp) \n\
495 c.swsp t5, 18*4(sp) \n\
496 c.swsp t6, 19*4(sp)"); \
497 SAVE_FPU_CONTEXT(); \
498 }
499
500 /**
501 * @brief Restore the caller registers based on the RISC-V ABI specification
502 */
503 #define RESTORE_CALLER_CONTEXT() { \
504 __asm volatile("\n\
505 c.lwsp ra, 0*4(sp) \n\
506 c.lwsp t0, 1*4(sp) \n\
507 c.lwsp t1, 2*4(sp) \n\
508 c.lwsp t2, 3*4(sp) \n\
509 c.lwsp s0, 4*4(sp) \n\
510 c.lwsp s1, 5*4(sp) \n\
511 c.lwsp a0, 6*4(sp) \n\
512 c.lwsp a1, 7*4(sp) \n\
513 c.lwsp a2, 8*4(sp) \n\
514 c.lwsp a3, 9*4(sp) \n\
515 c.lwsp a4, 10*4(sp) \n\
516 c.lwsp a5, 11*4(sp) \n\
517 c.lwsp a6, 12*4(sp) \n\
518 c.lwsp a7, 13*4(sp) \n\
519 c.lwsp s2, 14*4(sp) \n\
520 c.lwsp s3, 15*4(sp) \n\
521 c.lwsp t3, 16*4(sp) \n\
522 c.lwsp t4, 17*4(sp) \n\
523 c.lwsp t5, 18*4(sp) \n\
524 c.lwsp t6, 19*4(sp) \n");\
525 RESTORE_FPU_CONTEXT(); \
526 __asm volatile("addi sp, sp, %0" : : "i"(CONTEXT_REG_NUM) :);\
527 }
528
529 #ifdef __riscv_flen
530 #define SAVE_FPU_STATE() { \
531 __asm volatile("frsr s1\n"); \
532 }
533
534 #define RESTORE_FPU_STATE() { \
535 __asm volatile("fssr s1\n"); \
536 }
537 #else
538 #define SAVE_FPU_STATE()
539 #define RESTORE_FPU_STATE()
540 #endif
541
542 #ifdef __riscv_dsp
543 /*
544 * Save DSP context
545 * NOTE: DSP context registers are stored at word offset 41 in the stack
546 */
547 #define SAVE_DSP_CONTEXT() { \
548 __asm volatile("rdov s0\n"); \
549 }
550 /*
551 * @brief Restore DSP context
552 * @note DSP context registers are stored at word offset 41 in the stack
553 */
554 #define RESTORE_DSP_CONTEXT() {\
555 __asm volatile("csrw ucode, s0\n"); \
556 }
557
558 #else
559 #define SAVE_DSP_CONTEXT()
560 #define RESTORE_DSP_CONTEXT()
561 #endif
562
563 /*
564 * @brief Enter Nested IRQ Handling
565 * @note To simplify the logic, Nested IRQ related registers are stored in the stack as below:
566 * MCAUSE - word offset 16 (not used in the vectored mode)
567 * EPC - word offset 17
568 * MSTATUS = word offset 18
569 * MXSTATUS = word offset 19
570 */
571 #define ENTER_NESTED_IRQ_HANDLING_M() { \
572 __asm volatile("\n\
573 csrr s2, mepc \n\
574 csrr s3, mstatus \n");\
575 SAVE_FPU_STATE(); \
576 SAVE_DSP_CONTEXT(); \
577 __asm volatile("csrsi mstatus, 8"); \
578 }
579
580 /*
581 * @brief Complete IRQ Handling
582 */
583 #define COMPLETE_IRQ_HANDLING_M(irq_num) { \
584 __asm volatile("csrci mstatus, 8"); \
585 __asm volatile("lui a4, 0xe4200"); \
586 __asm volatile("li a3, %0" : : "i" (irq_num) :); \
587 __asm volatile("sw a3, 4(a4)"); \
588 }
589
590 /*
591 * @brief Exit Nested IRQ Handling
592 * @note To simplify the logic, Nested IRQ related registers are stored in the stack as below:
593 * MCAUSE - word offset 16 (not used in the vectored mode)
594 * EPC - word offset 17
595 * MSTATUS = word offset 18
596 * MXSTATUS = word offset 19
597 */
598 #define EXIT_NESTED_IRQ_HANDLING_M() { \
599 __asm volatile("\n\
600 csrw mstatus, s3 \n\
601 csrw mepc, s2 \n");\
602 RESTORE_FPU_STATE(); \
603 RESTORE_DSP_CONTEXT(); \
604 }
605
606 /* @brief Nested IRQ entry macro : Save CSRs and enable global irq. */
607 #define NESTED_IRQ_ENTER() \
608 SAVE_CSR(CSR_MEPC) \
609 SAVE_CSR(CSR_MSTATUS) \
610 SAVE_MXSTATUS() \
611 SAVE_FCSR() \
612 SAVE_UCODE() \
613 set_csr(CSR_MSTATUS, CSR_MSTATUS_MIE_MASK);
614
615 /* @brief Nested IRQ exit macro : Restore CSRs */
616 #define NESTED_IRQ_EXIT() \
617 RESTORE_CSR(CSR_MSTATUS) \
618 RESTORE_CSR(CSR_MEPC) \
619 RESTORE_MXSTATUS() \
620 RESTORE_FCSR() \
621 RESTORE_UCODE()
622
623 #ifdef __cplusplus
624 #define EXTERN_C extern "C"
625 #else
626 #define EXTERN_C
627 #endif
628
629 #define ISR_NAME_M(irq_num) default_isr_##irq_num
630 /**
631 * @brief Declare an external interrupt handler for machine mode
632 *
633 * @param[in] irq_num - IRQ number index
634 * @param[in] isr - Application IRQ handler function pointer
635 */
636 #ifndef USE_NONVECTOR_MODE
637
638 #define SDK_DECLARE_EXT_ISR_M(irq_num, isr) \
639 void isr(void) __attribute__((section(".isr_vector")));\
640 EXTERN_C void ISR_NAME_M(irq_num)(void) __attribute__((section(".isr_vector")));\
641 void ISR_NAME_M(irq_num)(void) \
642 { \
643 SAVE_CALLER_CONTEXT(); \
644 ENTER_NESTED_IRQ_HANDLING_M();\
645 __asm volatile("la t1, %0\n\t" : : "i" (isr) : );\
646 __asm volatile("jalr t1\n");\
647 COMPLETE_IRQ_HANDLING_M(irq_num);\
648 EXIT_NESTED_IRQ_HANDLING_M();\
649 RESTORE_CALLER_CONTEXT();\
650 __asm volatile("fence io, io");\
651 __asm volatile("mret\n");\
652 }
653 #else
654
655 #define SDK_DECLARE_EXT_ISR_M(irq_num, isr) \
656 void isr(void) __attribute__((section(".isr_vector")));\
657 EXTERN_C void ISR_NAME_M(irq_num)(void) __attribute__((section(".isr_vector")));\
658 void ISR_NAME_M(irq_num)(void) { \
659 isr(); \
660 }
661 #endif
662
663
664 /**
665 * @brief Declare machine timer interrupt handler
666 *
667 * @param[in] isr - MCHTMR IRQ handler function pointer
668 */
669 #define SDK_DECLARE_MCHTMR_ISR(isr) \
670 void isr(void) __attribute__((section(".isr_vector")));\
671 EXTERN_C void mchtmr_isr(void) __attribute__((section(".isr_vector"))); \
672 void mchtmr_isr(void) \
673 {\
674 isr();\
675 }
676
677 /**
678 * @brief Declare machine software interrupt handler
679 *
680 * @param[in] isr - SWI IRQ handler function pointer
681 */
682 #define SDK_DECLARE_SWI_ISR(isr)\
683 void isr(void) __attribute__((section(".isr_vector")));\
684 EXTERN_C void swi_isr(void) __attribute__((section(".isr_vector"))); \
685 void swi_isr(void) \
686 {\
687 isr();\
688 }
689
690 #ifdef __cplusplus
691 }
692 #endif
693
694 /**
695 * @}
696 */
697 #endif /* HPM_INTERRUPT_H */
698