1 /* 2 * Copyright (c) 2021-2023 HPMicro 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 */ 7 8 9 #ifndef HPM_SYSCTL_H 10 #define HPM_SYSCTL_H 11 12 typedef struct { 13 __RW uint32_t RESOURCE[311]; /* 0x0 - 0x4D8: Resource control register for cpu0_core */ 14 __R uint8_t RESERVED0[804]; /* 0x4DC - 0x7FF: Reserved */ 15 struct { 16 __RW uint32_t VALUE; /* 0x800: Group setting */ 17 __RW uint32_t SET; /* 0x804: Group setting */ 18 __RW uint32_t CLEAR; /* 0x808: Group setting */ 19 __RW uint32_t TOGGLE; /* 0x80C: Group setting */ 20 } GROUP0[2]; 21 __R uint8_t RESERVED1[224]; /* 0x820 - 0x8FF: Reserved */ 22 struct { 23 __RW uint32_t VALUE; /* 0x900: Affiliate of Group */ 24 __RW uint32_t SET; /* 0x904: Affiliate of Group */ 25 __RW uint32_t CLEAR; /* 0x908: Affiliate of Group */ 26 __RW uint32_t TOGGLE; /* 0x90C: Affiliate of Group */ 27 } AFFILIATE[1]; 28 __R uint8_t RESERVED2[16]; /* 0x910 - 0x91F: Reserved */ 29 struct { 30 __RW uint32_t VALUE; /* 0x920: Retention Contol */ 31 __RW uint32_t SET; /* 0x924: Retention Contol */ 32 __RW uint32_t CLEAR; /* 0x928: Retention Contol */ 33 __RW uint32_t TOGGLE; /* 0x92C: Retention Contol */ 34 } RETENTION[1]; 35 __R uint8_t RESERVED3[1744]; /* 0x930 - 0xFFF: Reserved */ 36 struct { 37 __RW uint32_t STATUS; /* 0x1000: Power Setting */ 38 __RW uint32_t LF_WAIT; /* 0x1004: Power Setting */ 39 __R uint8_t RESERVED0[4]; /* 0x1008 - 0x100B: Reserved */ 40 __RW uint32_t OFF_WAIT; /* 0x100C: Power Setting */ 41 __RW uint32_t RET_WAIT; /* 0x1010: Power Setting */ 42 } POWER[1]; 43 __R uint8_t RESERVED4[1004]; /* 0x1014 - 0x13FF: Reserved */ 44 struct { 45 __RW uint32_t CONTROL; /* 0x1400: Reset Setting */ 46 __RW uint32_t CONFIG; /* 0x1404: Reset Setting */ 47 __R uint8_t RESERVED0[4]; /* 0x1408 - 0x140B: Reserved */ 48 __RW uint32_t COUNTER; /* 0x140C: Reset Setting */ 49 } RESET[2]; 50 __R uint8_t RESERVED5[992]; /* 0x1420 - 0x17FF: Reserved */ 51 __RW uint32_t CLOCK_CPU[1]; /* 0x1800: Clock setting */ 52 __RW uint32_t CLOCK[36]; /* 0x1804 - 0x1890: Clock setting */ 53 __R uint8_t RESERVED6[876]; /* 0x1894 - 0x1BFF: Reserved */ 54 __RW uint32_t ADCCLK[2]; /* 0x1C00 - 0x1C04: Clock setting */ 55 __RW uint32_t DACCLK[2]; /* 0x1C08 - 0x1C0C: Clock setting */ 56 __R uint8_t RESERVED7[1008]; /* 0x1C10 - 0x1FFF: Reserved */ 57 __RW uint32_t GLOBAL00; /* 0x2000: Clock senario */ 58 __R uint8_t RESERVED8[1020]; /* 0x2004 - 0x23FF: Reserved */ 59 struct { 60 __RW uint32_t CONTROL; /* 0x2400: Clock measure and monitor control */ 61 __R uint32_t CURRENT; /* 0x2404: Clock measure result */ 62 __RW uint32_t LOW_LIMIT; /* 0x2408: Clock lower limit */ 63 __RW uint32_t HIGH_LIMIT; /* 0x240C: Clock upper limit */ 64 __R uint8_t RESERVED0[16]; /* 0x2410 - 0x241F: Reserved */ 65 } MONITOR[4]; 66 __R uint8_t RESERVED9[896]; /* 0x2480 - 0x27FF: Reserved */ 67 struct { 68 __RW uint32_t LP; /* 0x2800: CPU0 LP control */ 69 __RW uint32_t LOCK; /* 0x2804: CPU0 Lock GPR */ 70 __RW uint32_t GPR[14]; /* 0x2808 - 0x283C: CPU0 GPR0 */ 71 __R uint32_t WAKEUP_STATUS[4]; /* 0x2840 - 0x284C: CPU0 wakeup IRQ status */ 72 __R uint8_t RESERVED0[48]; /* 0x2850 - 0x287F: Reserved */ 73 __RW uint32_t WAKEUP_ENABLE[4]; /* 0x2880 - 0x288C: CPU0 wakeup IRQ enable */ 74 __R uint8_t RESERVED1[880]; /* 0x2890 - 0x2BFF: Reserved */ 75 } CPU[1]; 76 } SYSCTL_Type; 77 78 79 /* Bitfield definition for register array: RESOURCE */ 80 /* 81 * GLB_BUSY (RO) 82 * 83 * global busy 84 * 0: no changes pending to any nodes 85 * 1: any of nodes is changing status 86 */ 87 #define SYSCTL_RESOURCE_GLB_BUSY_MASK (0x80000000UL) 88 #define SYSCTL_RESOURCE_GLB_BUSY_SHIFT (31U) 89 #define SYSCTL_RESOURCE_GLB_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_RESOURCE_GLB_BUSY_MASK) >> SYSCTL_RESOURCE_GLB_BUSY_SHIFT) 90 91 /* 92 * LOC_BUSY (RO) 93 * 94 * local busy 95 * 0: no change is pending for current node 96 * 1: current node is changing status 97 */ 98 #define SYSCTL_RESOURCE_LOC_BUSY_MASK (0x40000000UL) 99 #define SYSCTL_RESOURCE_LOC_BUSY_SHIFT (30U) 100 #define SYSCTL_RESOURCE_LOC_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_RESOURCE_LOC_BUSY_MASK) >> SYSCTL_RESOURCE_LOC_BUSY_SHIFT) 101 102 /* 103 * MODE (RW) 104 * 105 * resource work mode 106 * 0:auto turn on and off as system required(recommended) 107 * 1:always on 108 * 2:always off 109 * 3:reserved 110 */ 111 #define SYSCTL_RESOURCE_MODE_MASK (0x3U) 112 #define SYSCTL_RESOURCE_MODE_SHIFT (0U) 113 #define SYSCTL_RESOURCE_MODE_SET(x) (((uint32_t)(x) << SYSCTL_RESOURCE_MODE_SHIFT) & SYSCTL_RESOURCE_MODE_MASK) 114 #define SYSCTL_RESOURCE_MODE_GET(x) (((uint32_t)(x) & SYSCTL_RESOURCE_MODE_MASK) >> SYSCTL_RESOURCE_MODE_SHIFT) 115 116 /* Bitfield definition for register of struct array GROUP0: VALUE */ 117 /* 118 * LINK (RW) 119 * 120 * denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral 121 * 0: peripheral is not needed 122 * 1: periphera is needed 123 */ 124 #define SYSCTL_GROUP0_VALUE_LINK_MASK (0xFFFFFFFFUL) 125 #define SYSCTL_GROUP0_VALUE_LINK_SHIFT (0U) 126 #define SYSCTL_GROUP0_VALUE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_GROUP0_VALUE_LINK_SHIFT) & SYSCTL_GROUP0_VALUE_LINK_MASK) 127 #define SYSCTL_GROUP0_VALUE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_GROUP0_VALUE_LINK_MASK) >> SYSCTL_GROUP0_VALUE_LINK_SHIFT) 128 129 /* Bitfield definition for register of struct array GROUP0: SET */ 130 /* 131 * LINK (RW) 132 * 133 * denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral 134 * 0: no effect 135 * 1: add periphera into this group，periphera is needed 136 */ 137 #define SYSCTL_GROUP0_SET_LINK_MASK (0xFFFFFFFFUL) 138 #define SYSCTL_GROUP0_SET_LINK_SHIFT (0U) 139 #define SYSCTL_GROUP0_SET_LINK_SET(x) (((uint32_t)(x) << SYSCTL_GROUP0_SET_LINK_SHIFT) & SYSCTL_GROUP0_SET_LINK_MASK) 140 #define SYSCTL_GROUP0_SET_LINK_GET(x) (((uint32_t)(x) & SYSCTL_GROUP0_SET_LINK_MASK) >> SYSCTL_GROUP0_SET_LINK_SHIFT) 141 142 /* Bitfield definition for register of struct array GROUP0: CLEAR */ 143 /* 144 * LINK (RW) 145 * 146 * denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral 147 * 0: no effect 148 * 1: delete periphera in this group，periphera is not needed 149 */ 150 #define SYSCTL_GROUP0_CLEAR_LINK_MASK (0xFFFFFFFFUL) 151 #define SYSCTL_GROUP0_CLEAR_LINK_SHIFT (0U) 152 #define SYSCTL_GROUP0_CLEAR_LINK_SET(x) (((uint32_t)(x) << SYSCTL_GROUP0_CLEAR_LINK_SHIFT) & SYSCTL_GROUP0_CLEAR_LINK_MASK) 153 #define SYSCTL_GROUP0_CLEAR_LINK_GET(x) (((uint32_t)(x) & SYSCTL_GROUP0_CLEAR_LINK_MASK) >> SYSCTL_GROUP0_CLEAR_LINK_SHIFT) 154 155 /* Bitfield definition for register of struct array GROUP0: TOGGLE */ 156 /* 157 * LINK (RW) 158 * 159 * denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral 160 * 0: no effect 161 * 1: toggle the result that whether periphera is needed before 162 */ 163 #define SYSCTL_GROUP0_TOGGLE_LINK_MASK (0xFFFFFFFFUL) 164 #define SYSCTL_GROUP0_TOGGLE_LINK_SHIFT (0U) 165 #define SYSCTL_GROUP0_TOGGLE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_GROUP0_TOGGLE_LINK_SHIFT) & SYSCTL_GROUP0_TOGGLE_LINK_MASK) 166 #define SYSCTL_GROUP0_TOGGLE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_GROUP0_TOGGLE_LINK_MASK) >> SYSCTL_GROUP0_TOGGLE_LINK_SHIFT) 167 168 /* Bitfield definition for register of struct array AFFILIATE: VALUE */ 169 /* 170 * LINK (RW) 171 * 172 * Affiliate groups of cpu0, each bit represents a group 173 * bit0: cpu0 depends on group0 174 * bit1: cpu0 depends on group1 175 * bit2: cpu0 depends on group2 176 * bit3: cpu0 depends on group3 177 */ 178 #define SYSCTL_AFFILIATE_VALUE_LINK_MASK (0xFU) 179 #define SYSCTL_AFFILIATE_VALUE_LINK_SHIFT (0U) 180 #define SYSCTL_AFFILIATE_VALUE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_AFFILIATE_VALUE_LINK_SHIFT) & SYSCTL_AFFILIATE_VALUE_LINK_MASK) 181 #define SYSCTL_AFFILIATE_VALUE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_AFFILIATE_VALUE_LINK_MASK) >> SYSCTL_AFFILIATE_VALUE_LINK_SHIFT) 182 183 /* Bitfield definition for register of struct array AFFILIATE: SET */ 184 /* 185 * LINK (RW) 186 * 187 * Affiliate groups of cpu0，each bit represents a group 188 * 0: no effect 189 * 1: the group is assigned to CPU0 190 */ 191 #define SYSCTL_AFFILIATE_SET_LINK_MASK (0xFU) 192 #define SYSCTL_AFFILIATE_SET_LINK_SHIFT (0U) 193 #define SYSCTL_AFFILIATE_SET_LINK_SET(x) (((uint32_t)(x) << SYSCTL_AFFILIATE_SET_LINK_SHIFT) & SYSCTL_AFFILIATE_SET_LINK_MASK) 194 #define SYSCTL_AFFILIATE_SET_LINK_GET(x) (((uint32_t)(x) & SYSCTL_AFFILIATE_SET_LINK_MASK) >> SYSCTL_AFFILIATE_SET_LINK_SHIFT) 195 196 /* Bitfield definition for register of struct array AFFILIATE: CLEAR */ 197 /* 198 * LINK (RW) 199 * 200 * Affiliate groups of cpu0, each bit represents a group 201 * 0: no effect 202 * 1: the group is not assigned to CPU0 203 */ 204 #define SYSCTL_AFFILIATE_CLEAR_LINK_MASK (0xFU) 205 #define SYSCTL_AFFILIATE_CLEAR_LINK_SHIFT (0U) 206 #define SYSCTL_AFFILIATE_CLEAR_LINK_SET(x) (((uint32_t)(x) << SYSCTL_AFFILIATE_CLEAR_LINK_SHIFT) & SYSCTL_AFFILIATE_CLEAR_LINK_MASK) 207 #define SYSCTL_AFFILIATE_CLEAR_LINK_GET(x) (((uint32_t)(x) & SYSCTL_AFFILIATE_CLEAR_LINK_MASK) >> SYSCTL_AFFILIATE_CLEAR_LINK_SHIFT) 208 209 /* Bitfield definition for register of struct array AFFILIATE: TOGGLE */ 210 /* 211 * LINK (RW) 212 * 213 * Affiliate groups of cpu0, each bit represents a group 214 * 0: no effect 215 * 1: toggle the result that whether the group is assigned to CPU0 before 216 */ 217 #define SYSCTL_AFFILIATE_TOGGLE_LINK_MASK (0xFU) 218 #define SYSCTL_AFFILIATE_TOGGLE_LINK_SHIFT (0U) 219 #define SYSCTL_AFFILIATE_TOGGLE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_AFFILIATE_TOGGLE_LINK_SHIFT) & SYSCTL_AFFILIATE_TOGGLE_LINK_MASK) 220 #define SYSCTL_AFFILIATE_TOGGLE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_AFFILIATE_TOGGLE_LINK_MASK) >> SYSCTL_AFFILIATE_TOGGLE_LINK_SHIFT) 221 222 /* Bitfield definition for register of struct array RETENTION: VALUE */ 223 /* 224 * LINK (RW) 225 * 226 * retention setting while CPU0 enter stop mode, each bit represents a resource 227 * bit00: soc_mem is kept on while cpu0 stop 228 * bit01: soc_ctx is kept on while cpu0 stop 229 * bit02: cpu0_mem is kept on while cpu0 stop 230 * bit03: cpu0_ctx is kept on while cpu0 stop 231 * bit04: xtal_hold is kept on while cpu0 stop 232 * bit05: pll0_hold is kept on while cpu0 stop 233 * bit06: pll1_hold is kept on while cpu0 stop 234 */ 235 #define SYSCTL_RETENTION_VALUE_LINK_MASK (0x7FFFU) 236 #define SYSCTL_RETENTION_VALUE_LINK_SHIFT (0U) 237 #define SYSCTL_RETENTION_VALUE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_RETENTION_VALUE_LINK_SHIFT) & SYSCTL_RETENTION_VALUE_LINK_MASK) 238 #define SYSCTL_RETENTION_VALUE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_RETENTION_VALUE_LINK_MASK) >> SYSCTL_RETENTION_VALUE_LINK_SHIFT) 239 240 /* Bitfield definition for register of struct array RETENTION: SET */ 241 /* 242 * LINK (RW) 243 * 244 * retention setting while CPU0 enter stop mode, each bit represents a resource 245 * 0: no effect 246 * 1: keep 247 */ 248 #define SYSCTL_RETENTION_SET_LINK_MASK (0x7FFFU) 249 #define SYSCTL_RETENTION_SET_LINK_SHIFT (0U) 250 #define SYSCTL_RETENTION_SET_LINK_SET(x) (((uint32_t)(x) << SYSCTL_RETENTION_SET_LINK_SHIFT) & SYSCTL_RETENTION_SET_LINK_MASK) 251 #define SYSCTL_RETENTION_SET_LINK_GET(x) (((uint32_t)(x) & SYSCTL_RETENTION_SET_LINK_MASK) >> SYSCTL_RETENTION_SET_LINK_SHIFT) 252 253 /* Bitfield definition for register of struct array RETENTION: CLEAR */ 254 /* 255 * LINK (RW) 256 * 257 * retention setting while CPU0 enter stop mode, each bit represents a resource 258 * 0: no effect 259 * 1: no keep 260 */ 261 #define SYSCTL_RETENTION_CLEAR_LINK_MASK (0x7FFFU) 262 #define SYSCTL_RETENTION_CLEAR_LINK_SHIFT (0U) 263 #define SYSCTL_RETENTION_CLEAR_LINK_SET(x) (((uint32_t)(x) << SYSCTL_RETENTION_CLEAR_LINK_SHIFT) & SYSCTL_RETENTION_CLEAR_LINK_MASK) 264 #define SYSCTL_RETENTION_CLEAR_LINK_GET(x) (((uint32_t)(x) & SYSCTL_RETENTION_CLEAR_LINK_MASK) >> SYSCTL_RETENTION_CLEAR_LINK_SHIFT) 265 266 /* Bitfield definition for register of struct array RETENTION: TOGGLE */ 267 /* 268 * LINK (RW) 269 * 270 * retention setting while CPU0 enter stop mode, each bit represents a resource 271 * 0: no effect 272 * 1: toggle the result that whether the resource is kept on while CPU0 stop before 273 */ 274 #define SYSCTL_RETENTION_TOGGLE_LINK_MASK (0x7FFFU) 275 #define SYSCTL_RETENTION_TOGGLE_LINK_SHIFT (0U) 276 #define SYSCTL_RETENTION_TOGGLE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_RETENTION_TOGGLE_LINK_SHIFT) & SYSCTL_RETENTION_TOGGLE_LINK_MASK) 277 #define SYSCTL_RETENTION_TOGGLE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_RETENTION_TOGGLE_LINK_MASK) >> SYSCTL_RETENTION_TOGGLE_LINK_SHIFT) 278 279 /* Bitfield definition for register of struct array POWER: STATUS */ 280 /* 281 * FLAG (RW) 282 * 283 * flag represents power cycle happened from last clear of this bit 284 * 0: power domain did not edurance power cycle since last clear of this bit 285 * 1: power domain enduranced power cycle since last clear of this bit 286 */ 287 #define SYSCTL_POWER_STATUS_FLAG_MASK (0x80000000UL) 288 #define SYSCTL_POWER_STATUS_FLAG_SHIFT (31U) 289 #define SYSCTL_POWER_STATUS_FLAG_SET(x) (((uint32_t)(x) << SYSCTL_POWER_STATUS_FLAG_SHIFT) & SYSCTL_POWER_STATUS_FLAG_MASK) 290 #define SYSCTL_POWER_STATUS_FLAG_GET(x) (((uint32_t)(x) & SYSCTL_POWER_STATUS_FLAG_MASK) >> SYSCTL_POWER_STATUS_FLAG_SHIFT) 291 292 /* 293 * FLAG_WAKE (RW) 294 * 295 * flag represents wakeup power cycle happened from last clear of this bit 296 * 0: power domain did not edurance wakeup power cycle since last clear of this bit 297 * 1: power domain enduranced wakeup power cycle since last clear of this bit 298 */ 299 #define SYSCTL_POWER_STATUS_FLAG_WAKE_MASK (0x40000000UL) 300 #define SYSCTL_POWER_STATUS_FLAG_WAKE_SHIFT (30U) 301 #define SYSCTL_POWER_STATUS_FLAG_WAKE_SET(x) (((uint32_t)(x) << SYSCTL_POWER_STATUS_FLAG_WAKE_SHIFT) & SYSCTL_POWER_STATUS_FLAG_WAKE_MASK) 302 #define SYSCTL_POWER_STATUS_FLAG_WAKE_GET(x) (((uint32_t)(x) & SYSCTL_POWER_STATUS_FLAG_WAKE_MASK) >> SYSCTL_POWER_STATUS_FLAG_WAKE_SHIFT) 303 304 /* 305 * MEM_RET_N (RO) 306 * 307 * memory info retention control signal 308 * 0: memory enter retention mode 309 * 1: memory exit retention mode 310 */ 311 #define SYSCTL_POWER_STATUS_MEM_RET_N_MASK (0x20000UL) 312 #define SYSCTL_POWER_STATUS_MEM_RET_N_SHIFT (17U) 313 #define SYSCTL_POWER_STATUS_MEM_RET_N_GET(x) (((uint32_t)(x) & SYSCTL_POWER_STATUS_MEM_RET_N_MASK) >> SYSCTL_POWER_STATUS_MEM_RET_N_SHIFT) 314 315 /* 316 * MEM_RET_P (RO) 317 * 318 * memory info retention control signal 319 * 0: memory not enterexitretention mode 320 * 1: memory enter retention mode 321 */ 322 #define SYSCTL_POWER_STATUS_MEM_RET_P_MASK (0x10000UL) 323 #define SYSCTL_POWER_STATUS_MEM_RET_P_SHIFT (16U) 324 #define SYSCTL_POWER_STATUS_MEM_RET_P_GET(x) (((uint32_t)(x) & SYSCTL_POWER_STATUS_MEM_RET_P_MASK) >> SYSCTL_POWER_STATUS_MEM_RET_P_SHIFT) 325 326 /* 327 * LF_DISABLE (RO) 328 * 329 * low fanout power switch disable 330 * 0: low fanout power switches are turned on 331 * 1: low fanout power switches are truned off 332 */ 333 #define SYSCTL_POWER_STATUS_LF_DISABLE_MASK (0x1000U) 334 #define SYSCTL_POWER_STATUS_LF_DISABLE_SHIFT (12U) 335 #define SYSCTL_POWER_STATUS_LF_DISABLE_GET(x) (((uint32_t)(x) & SYSCTL_POWER_STATUS_LF_DISABLE_MASK) >> SYSCTL_POWER_STATUS_LF_DISABLE_SHIFT) 336 337 /* 338 * LF_ACK (RO) 339 * 340 * low fanout power switch feedback 341 * 0: low fanout power switches are turned on 342 * 1: low fanout power switches are truned off 343 */ 344 #define SYSCTL_POWER_STATUS_LF_ACK_MASK (0x100U) 345 #define SYSCTL_POWER_STATUS_LF_ACK_SHIFT (8U) 346 #define SYSCTL_POWER_STATUS_LF_ACK_GET(x) (((uint32_t)(x) & SYSCTL_POWER_STATUS_LF_ACK_MASK) >> SYSCTL_POWER_STATUS_LF_ACK_SHIFT) 347 348 /* Bitfield definition for register of struct array POWER: LF_WAIT */ 349 /* 350 * WAIT (RW) 351 * 352 * wait time for low fan out power switch turn on, default value is 255 353 * 0: 0 clock cycle 354 * 1: 1 clock cycles 355 * . . . 356 * clock cycles count on 24MHz 357 */ 358 #define SYSCTL_POWER_LF_WAIT_WAIT_MASK (0xFFFFFUL) 359 #define SYSCTL_POWER_LF_WAIT_WAIT_SHIFT (0U) 360 #define SYSCTL_POWER_LF_WAIT_WAIT_SET(x) (((uint32_t)(x) << SYSCTL_POWER_LF_WAIT_WAIT_SHIFT) & SYSCTL_POWER_LF_WAIT_WAIT_MASK) 361 #define SYSCTL_POWER_LF_WAIT_WAIT_GET(x) (((uint32_t)(x) & SYSCTL_POWER_LF_WAIT_WAIT_MASK) >> SYSCTL_POWER_LF_WAIT_WAIT_SHIFT) 362 363 /* Bitfield definition for register of struct array POWER: OFF_WAIT */ 364 /* 365 * WAIT (RW) 366 * 367 * wait time for power switch turn off, default value is 15 368 * 0: 0 clock cycle 369 * 1: 1 clock cycles 370 * . . . 371 * clock cycles count on 24MHz 372 */ 373 #define SYSCTL_POWER_OFF_WAIT_WAIT_MASK (0xFFFFFUL) 374 #define SYSCTL_POWER_OFF_WAIT_WAIT_SHIFT (0U) 375 #define SYSCTL_POWER_OFF_WAIT_WAIT_SET(x) (((uint32_t)(x) << SYSCTL_POWER_OFF_WAIT_WAIT_SHIFT) & SYSCTL_POWER_OFF_WAIT_WAIT_MASK) 376 #define SYSCTL_POWER_OFF_WAIT_WAIT_GET(x) (((uint32_t)(x) & SYSCTL_POWER_OFF_WAIT_WAIT_MASK) >> SYSCTL_POWER_OFF_WAIT_WAIT_SHIFT) 377 378 /* Bitfield definition for register of struct array POWER: RET_WAIT */ 379 /* 380 * WAIT (RW) 381 * 382 * wait time for memory retention mode transition, default value is 15 383 * 0: 0 clock cycle 384 * 1: 1 clock cycles 385 * . . . 386 * clock cycles count on 24MHz 387 */ 388 #define SYSCTL_POWER_RET_WAIT_WAIT_MASK (0xFFFFFUL) 389 #define SYSCTL_POWER_RET_WAIT_WAIT_SHIFT (0U) 390 #define SYSCTL_POWER_RET_WAIT_WAIT_SET(x) (((uint32_t)(x) << SYSCTL_POWER_RET_WAIT_WAIT_SHIFT) & SYSCTL_POWER_RET_WAIT_WAIT_MASK) 391 #define SYSCTL_POWER_RET_WAIT_WAIT_GET(x) (((uint32_t)(x) & SYSCTL_POWER_RET_WAIT_WAIT_MASK) >> SYSCTL_POWER_RET_WAIT_WAIT_SHIFT) 392 393 /* Bitfield definition for register of struct array RESET: CONTROL */ 394 /* 395 * FLAG (RW) 396 * 397 * flag represents reset happened from last clear of this bit 398 * 0: domain did not edurance reset cycle since last clear of this bit 399 * 1: domain enduranced reset cycle since last clear of this bit 400 */ 401 #define SYSCTL_RESET_CONTROL_FLAG_MASK (0x80000000UL) 402 #define SYSCTL_RESET_CONTROL_FLAG_SHIFT (31U) 403 #define SYSCTL_RESET_CONTROL_FLAG_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONTROL_FLAG_SHIFT) & SYSCTL_RESET_CONTROL_FLAG_MASK) 404 #define SYSCTL_RESET_CONTROL_FLAG_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONTROL_FLAG_MASK) >> SYSCTL_RESET_CONTROL_FLAG_SHIFT) 405 406 /* 407 * FLAG_WAKE (RW) 408 * 409 * flag represents wakeup reset happened from last clear of this bit 410 * 0: domain did not edurance wakeup reset cycle since last clear of this bit 411 * 1: domain enduranced wakeup reset cycle since last clear of this bit 412 */ 413 #define SYSCTL_RESET_CONTROL_FLAG_WAKE_MASK (0x40000000UL) 414 #define SYSCTL_RESET_CONTROL_FLAG_WAKE_SHIFT (30U) 415 #define SYSCTL_RESET_CONTROL_FLAG_WAKE_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONTROL_FLAG_WAKE_SHIFT) & SYSCTL_RESET_CONTROL_FLAG_WAKE_MASK) 416 #define SYSCTL_RESET_CONTROL_FLAG_WAKE_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONTROL_FLAG_WAKE_MASK) >> SYSCTL_RESET_CONTROL_FLAG_WAKE_SHIFT) 417 418 /* 419 * HOLD (RW) 420 * 421 * perform reset and hold in reset, until ths bit cleared by software 422 * 0: reset is released for function 423 * 1: reset is assert and hold 424 */ 425 #define SYSCTL_RESET_CONTROL_HOLD_MASK (0x10U) 426 #define SYSCTL_RESET_CONTROL_HOLD_SHIFT (4U) 427 #define SYSCTL_RESET_CONTROL_HOLD_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONTROL_HOLD_SHIFT) & SYSCTL_RESET_CONTROL_HOLD_MASK) 428 #define SYSCTL_RESET_CONTROL_HOLD_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONTROL_HOLD_MASK) >> SYSCTL_RESET_CONTROL_HOLD_SHIFT) 429 430 /* 431 * RESET (RW) 432 * 433 * perform reset and release imediately 434 * 0: reset is released 435 * 1 reset is asserted and will release automaticly 436 */ 437 #define SYSCTL_RESET_CONTROL_RESET_MASK (0x1U) 438 #define SYSCTL_RESET_CONTROL_RESET_SHIFT (0U) 439 #define SYSCTL_RESET_CONTROL_RESET_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONTROL_RESET_SHIFT) & SYSCTL_RESET_CONTROL_RESET_MASK) 440 #define SYSCTL_RESET_CONTROL_RESET_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONTROL_RESET_MASK) >> SYSCTL_RESET_CONTROL_RESET_SHIFT) 441 442 /* Bitfield definition for register of struct array RESET: CONFIG */ 443 /* 444 * PRE_WAIT (RW) 445 * 446 * wait cycle numbers before assert reset 447 * 0: wait 0 cycle 448 * 1: wait 1 cycles 449 * . . . 450 * Note, clock cycle is base on 24M 451 */ 452 #define SYSCTL_RESET_CONFIG_PRE_WAIT_MASK (0xFF0000UL) 453 #define SYSCTL_RESET_CONFIG_PRE_WAIT_SHIFT (16U) 454 #define SYSCTL_RESET_CONFIG_PRE_WAIT_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONFIG_PRE_WAIT_SHIFT) & SYSCTL_RESET_CONFIG_PRE_WAIT_MASK) 455 #define SYSCTL_RESET_CONFIG_PRE_WAIT_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONFIG_PRE_WAIT_MASK) >> SYSCTL_RESET_CONFIG_PRE_WAIT_SHIFT) 456 457 /* 458 * RSTCLK_NUM (RW) 459 * 460 * reset clock number(must be even number) 461 * 0: 0 cycle 462 * 1: 0 cycles 463 * 2: 2 cycles 464 * 3: 2 cycles 465 * . . . 466 * Note, clock cycle is base on 24M 467 */ 468 #define SYSCTL_RESET_CONFIG_RSTCLK_NUM_MASK (0xFF00U) 469 #define SYSCTL_RESET_CONFIG_RSTCLK_NUM_SHIFT (8U) 470 #define SYSCTL_RESET_CONFIG_RSTCLK_NUM_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONFIG_RSTCLK_NUM_SHIFT) & SYSCTL_RESET_CONFIG_RSTCLK_NUM_MASK) 471 #define SYSCTL_RESET_CONFIG_RSTCLK_NUM_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONFIG_RSTCLK_NUM_MASK) >> SYSCTL_RESET_CONFIG_RSTCLK_NUM_SHIFT) 472 473 /* 474 * POST_WAIT (RW) 475 * 476 * time guard band for reset release 477 * 0: wait 0 cycle 478 * 1: wait 1 cycles 479 * . . . 480 * Note, clock cycle is base on 24M 481 */ 482 #define SYSCTL_RESET_CONFIG_POST_WAIT_MASK (0xFFU) 483 #define SYSCTL_RESET_CONFIG_POST_WAIT_SHIFT (0U) 484 #define SYSCTL_RESET_CONFIG_POST_WAIT_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONFIG_POST_WAIT_SHIFT) & SYSCTL_RESET_CONFIG_POST_WAIT_MASK) 485 #define SYSCTL_RESET_CONFIG_POST_WAIT_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONFIG_POST_WAIT_MASK) >> SYSCTL_RESET_CONFIG_POST_WAIT_SHIFT) 486 487 /* Bitfield definition for register of struct array RESET: COUNTER */ 488 /* 489 * COUNTER (RW) 490 * 491 * self clear trigger counter, reset triggered when counter value is 1, write 0 will cancel reset 492 * 0: wait 0 cycle 493 * 1: wait 1 cycles 494 * . . . 495 * Note, clock cycle is base on 24M 496 */ 497 #define SYSCTL_RESET_COUNTER_COUNTER_MASK (0xFFFFFUL) 498 #define SYSCTL_RESET_COUNTER_COUNTER_SHIFT (0U) 499 #define SYSCTL_RESET_COUNTER_COUNTER_SET(x) (((uint32_t)(x) << SYSCTL_RESET_COUNTER_COUNTER_SHIFT) & SYSCTL_RESET_COUNTER_COUNTER_MASK) 500 #define SYSCTL_RESET_COUNTER_COUNTER_GET(x) (((uint32_t)(x) & SYSCTL_RESET_COUNTER_COUNTER_MASK) >> SYSCTL_RESET_COUNTER_COUNTER_SHIFT) 501 502 /* Bitfield definition for register array: CLOCK_CPU */ 503 /* 504 * GLB_BUSY (RO) 505 * 506 * global busy 507 * 0: no changes pending to any clock 508 * 1: any of nodes is changing status 509 */ 510 #define SYSCTL_CLOCK_CPU_GLB_BUSY_MASK (0x80000000UL) 511 #define SYSCTL_CLOCK_CPU_GLB_BUSY_SHIFT (31U) 512 #define SYSCTL_CLOCK_CPU_GLB_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_CPU_GLB_BUSY_MASK) >> SYSCTL_CLOCK_CPU_GLB_BUSY_SHIFT) 513 514 /* 515 * LOC_BUSY (RO) 516 * 517 * local busy 518 * 0: a change is pending for current node 519 * 1: current node is changing status 520 */ 521 #define SYSCTL_CLOCK_CPU_LOC_BUSY_MASK (0x40000000UL) 522 #define SYSCTL_CLOCK_CPU_LOC_BUSY_SHIFT (30U) 523 #define SYSCTL_CLOCK_CPU_LOC_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_CPU_LOC_BUSY_MASK) >> SYSCTL_CLOCK_CPU_LOC_BUSY_SHIFT) 524 525 /* 526 * PRESERVE (RW) 527 * 528 * preserve function against global select 529 * 0: select global clock setting 530 * 1: not select global clock setting 531 */ 532 #define SYSCTL_CLOCK_CPU_PRESERVE_MASK (0x10000000UL) 533 #define SYSCTL_CLOCK_CPU_PRESERVE_SHIFT (28U) 534 #define SYSCTL_CLOCK_CPU_PRESERVE_SET(x) (((uint32_t)(x) << SYSCTL_CLOCK_CPU_PRESERVE_SHIFT) & SYSCTL_CLOCK_CPU_PRESERVE_MASK) 535 #define SYSCTL_CLOCK_CPU_PRESERVE_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_CPU_PRESERVE_MASK) >> SYSCTL_CLOCK_CPU_PRESERVE_SHIFT) 536 537 /* 538 * SUB0_DIV (RW) 539 * 540 * ahb bus divider, the bus clock is generated by cpu_clock/div 541 * 0: divider by 1 542 * 1: divider by 2 543 * … 544 */ 545 #define SYSCTL_CLOCK_CPU_SUB0_DIV_MASK (0xF0000UL) 546 #define SYSCTL_CLOCK_CPU_SUB0_DIV_SHIFT (16U) 547 #define SYSCTL_CLOCK_CPU_SUB0_DIV_SET(x) (((uint32_t)(x) << SYSCTL_CLOCK_CPU_SUB0_DIV_SHIFT) & SYSCTL_CLOCK_CPU_SUB0_DIV_MASK) 548 #define SYSCTL_CLOCK_CPU_SUB0_DIV_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_CPU_SUB0_DIV_MASK) >> SYSCTL_CLOCK_CPU_SUB0_DIV_SHIFT) 549 550 /* 551 * MUX (RW) 552 * 553 * current mux in clock component 554 * 0:osc0_clk0 555 * 1:pll0_clk0 556 * 2:pll0_clk1 557 * 3:pll0_clk2 558 * 4:pll1_clk0 559 * 5:pll1_clk1 560 * 6:pll1_clk2 561 * 7:pll1_clk3 562 */ 563 #define SYSCTL_CLOCK_CPU_MUX_MASK (0x700U) 564 #define SYSCTL_CLOCK_CPU_MUX_SHIFT (8U) 565 #define SYSCTL_CLOCK_CPU_MUX_SET(x) (((uint32_t)(x) << SYSCTL_CLOCK_CPU_MUX_SHIFT) & SYSCTL_CLOCK_CPU_MUX_MASK) 566 #define SYSCTL_CLOCK_CPU_MUX_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_CPU_MUX_MASK) >> SYSCTL_CLOCK_CPU_MUX_SHIFT) 567 568 /* 569 * DIV (RW) 570 * 571 * clock divider 572 * 0: divider by 1 573 * 1: divider by 2 574 * 2: divider by 3 575 * . . . 576 * 255: divider by 256 577 */ 578 #define SYSCTL_CLOCK_CPU_DIV_MASK (0xFFU) 579 #define SYSCTL_CLOCK_CPU_DIV_SHIFT (0U) 580 #define SYSCTL_CLOCK_CPU_DIV_SET(x) (((uint32_t)(x) << SYSCTL_CLOCK_CPU_DIV_SHIFT) & SYSCTL_CLOCK_CPU_DIV_MASK) 581 #define SYSCTL_CLOCK_CPU_DIV_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_CPU_DIV_MASK) >> SYSCTL_CLOCK_CPU_DIV_SHIFT) 582 583 /* Bitfield definition for register array: CLOCK */ 584 /* 585 * GLB_BUSY (RO) 586 * 587 * global busy 588 * 0: no changes pending to any clock 589 * 1: any of nodes is changing status 590 */ 591 #define SYSCTL_CLOCK_GLB_BUSY_MASK (0x80000000UL) 592 #define SYSCTL_CLOCK_GLB_BUSY_SHIFT (31U) 593 #define SYSCTL_CLOCK_GLB_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_GLB_BUSY_MASK) >> SYSCTL_CLOCK_GLB_BUSY_SHIFT) 594 595 /* 596 * LOC_BUSY (RO) 597 * 598 * local busy 599 * 0: a change is pending for current node 600 * 1: current node is changing status 601 */ 602 #define SYSCTL_CLOCK_LOC_BUSY_MASK (0x40000000UL) 603 #define SYSCTL_CLOCK_LOC_BUSY_SHIFT (30U) 604 #define SYSCTL_CLOCK_LOC_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_LOC_BUSY_MASK) >> SYSCTL_CLOCK_LOC_BUSY_SHIFT) 605 606 /* 607 * PRESERVE (RW) 608 * 609 * preserve function against global select 610 * 0: select global clock setting 611 * 1: not select global clock setting 612 */ 613 #define SYSCTL_CLOCK_PRESERVE_MASK (0x10000000UL) 614 #define SYSCTL_CLOCK_PRESERVE_SHIFT (28U) 615 #define SYSCTL_CLOCK_PRESERVE_SET(x) (((uint32_t)(x) << SYSCTL_CLOCK_PRESERVE_SHIFT) & SYSCTL_CLOCK_PRESERVE_MASK) 616 #define SYSCTL_CLOCK_PRESERVE_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_PRESERVE_MASK) >> SYSCTL_CLOCK_PRESERVE_SHIFT) 617 618 /* 619 * MUX (RW) 620 * 621 * current mux in clock component 622 * 0:osc0_clk0 623 * 1:pll0_clk0 624 * 2:pll0_clk1 625 * 3:pll0_clk2 626 * 4:pll1_clk0 627 * 5:pll1_clk1 628 * 6:pll1_clk2 629 * 7:pll1_clk3 630 */ 631 #define SYSCTL_CLOCK_MUX_MASK (0x700U) 632 #define SYSCTL_CLOCK_MUX_SHIFT (8U) 633 #define SYSCTL_CLOCK_MUX_SET(x) (((uint32_t)(x) << SYSCTL_CLOCK_MUX_SHIFT) & SYSCTL_CLOCK_MUX_MASK) 634 #define SYSCTL_CLOCK_MUX_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_MUX_MASK) >> SYSCTL_CLOCK_MUX_SHIFT) 635 636 /* 637 * DIV (RW) 638 * 639 * clock divider 640 * 0: divider by 1 641 * 1: divider by 2 642 * 2: divider by 3 643 * . . . 644 * 255: divider by 256 645 */ 646 #define SYSCTL_CLOCK_DIV_MASK (0xFFU) 647 #define SYSCTL_CLOCK_DIV_SHIFT (0U) 648 #define SYSCTL_CLOCK_DIV_SET(x) (((uint32_t)(x) << SYSCTL_CLOCK_DIV_SHIFT) & SYSCTL_CLOCK_DIV_MASK) 649 #define SYSCTL_CLOCK_DIV_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_DIV_MASK) >> SYSCTL_CLOCK_DIV_SHIFT) 650 651 /* Bitfield definition for register array: ADCCLK */ 652 /* 653 * GLB_BUSY (RO) 654 * 655 * global busy 656 * 0: no changes pending to any clock 657 * 1: any of nodes is changing status 658 */ 659 #define SYSCTL_ADCCLK_GLB_BUSY_MASK (0x80000000UL) 660 #define SYSCTL_ADCCLK_GLB_BUSY_SHIFT (31U) 661 #define SYSCTL_ADCCLK_GLB_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_ADCCLK_GLB_BUSY_MASK) >> SYSCTL_ADCCLK_GLB_BUSY_SHIFT) 662 663 /* 664 * LOC_BUSY (RO) 665 * 666 * local busy 667 * 0: a change is pending for current node 668 * 1: current node is changing status 669 */ 670 #define SYSCTL_ADCCLK_LOC_BUSY_MASK (0x40000000UL) 671 #define SYSCTL_ADCCLK_LOC_BUSY_SHIFT (30U) 672 #define SYSCTL_ADCCLK_LOC_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_ADCCLK_LOC_BUSY_MASK) >> SYSCTL_ADCCLK_LOC_BUSY_SHIFT) 673 674 /* 675 * PRESERVE (RW) 676 * 677 * preserve function against global select 678 * 0: select global clock setting 679 * 1: not select global clock setting 680 */ 681 #define SYSCTL_ADCCLK_PRESERVE_MASK (0x10000000UL) 682 #define SYSCTL_ADCCLK_PRESERVE_SHIFT (28U) 683 #define SYSCTL_ADCCLK_PRESERVE_SET(x) (((uint32_t)(x) << SYSCTL_ADCCLK_PRESERVE_SHIFT) & SYSCTL_ADCCLK_PRESERVE_MASK) 684 #define SYSCTL_ADCCLK_PRESERVE_GET(x) (((uint32_t)(x) & SYSCTL_ADCCLK_PRESERVE_MASK) >> SYSCTL_ADCCLK_PRESERVE_SHIFT) 685 686 /* 687 * MUX (RW) 688 * 689 * current mux 690 * 0: ahb0 clock N 691 * 1: ana clock 692 */ 693 #define SYSCTL_ADCCLK_MUX_MASK (0x100U) 694 #define SYSCTL_ADCCLK_MUX_SHIFT (8U) 695 #define SYSCTL_ADCCLK_MUX_SET(x) (((uint32_t)(x) << SYSCTL_ADCCLK_MUX_SHIFT) & SYSCTL_ADCCLK_MUX_MASK) 696 #define SYSCTL_ADCCLK_MUX_GET(x) (((uint32_t)(x) & SYSCTL_ADCCLK_MUX_MASK) >> SYSCTL_ADCCLK_MUX_SHIFT) 697 698 /* Bitfield definition for register array: DACCLK */ 699 /* 700 * GLB_BUSY (RO) 701 * 702 * global busy 703 * 0: no changes pending to any clock 704 * 1: any of nodes is changing status 705 */ 706 #define SYSCTL_DACCLK_GLB_BUSY_MASK (0x80000000UL) 707 #define SYSCTL_DACCLK_GLB_BUSY_SHIFT (31U) 708 #define SYSCTL_DACCLK_GLB_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_DACCLK_GLB_BUSY_MASK) >> SYSCTL_DACCLK_GLB_BUSY_SHIFT) 709 710 /* 711 * LOC_BUSY (RO) 712 * 713 * local busy 714 * 0: a change is pending for current node 715 * 1: current node is changing status 716 */ 717 #define SYSCTL_DACCLK_LOC_BUSY_MASK (0x40000000UL) 718 #define SYSCTL_DACCLK_LOC_BUSY_SHIFT (30U) 719 #define SYSCTL_DACCLK_LOC_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_DACCLK_LOC_BUSY_MASK) >> SYSCTL_DACCLK_LOC_BUSY_SHIFT) 720 721 /* 722 * PRESERVE (RW) 723 * 724 * preserve function against global select 725 * 0: select global clock setting 726 * 1: not select global clock setting 727 */ 728 #define SYSCTL_DACCLK_PRESERVE_MASK (0x10000000UL) 729 #define SYSCTL_DACCLK_PRESERVE_SHIFT (28U) 730 #define SYSCTL_DACCLK_PRESERVE_SET(x) (((uint32_t)(x) << SYSCTL_DACCLK_PRESERVE_SHIFT) & SYSCTL_DACCLK_PRESERVE_MASK) 731 #define SYSCTL_DACCLK_PRESERVE_GET(x) (((uint32_t)(x) & SYSCTL_DACCLK_PRESERVE_MASK) >> SYSCTL_DACCLK_PRESERVE_SHIFT) 732 733 /* 734 * MUX (RW) 735 * 736 * current mux 737 * 0: ahb0 clock N 738 * 1: ana clock 739 */ 740 #define SYSCTL_DACCLK_MUX_MASK (0x100U) 741 #define SYSCTL_DACCLK_MUX_SHIFT (8U) 742 #define SYSCTL_DACCLK_MUX_SET(x) (((uint32_t)(x) << SYSCTL_DACCLK_MUX_SHIFT) & SYSCTL_DACCLK_MUX_MASK) 743 #define SYSCTL_DACCLK_MUX_GET(x) (((uint32_t)(x) & SYSCTL_DACCLK_MUX_MASK) >> SYSCTL_DACCLK_MUX_SHIFT) 744 745 /* Bitfield definition for register: GLOBAL00 */ 746 /* 747 * MUX (RW) 748 * 749 * global clock override request 750 * bit0: override to preset0 751 * bit1: override to preset1 752 * bit2: override to preset2 753 * bit3: override to preset3 754 * bit4: override to preset4 755 * bit5: override to preset5 756 * bit6: override to preset6 757 * bit7: override to preset7 758 */ 759 #define SYSCTL_GLOBAL00_MUX_MASK (0xFFU) 760 #define SYSCTL_GLOBAL00_MUX_SHIFT (0U) 761 #define SYSCTL_GLOBAL00_MUX_SET(x) (((uint32_t)(x) << SYSCTL_GLOBAL00_MUX_SHIFT) & SYSCTL_GLOBAL00_MUX_MASK) 762 #define SYSCTL_GLOBAL00_MUX_GET(x) (((uint32_t)(x) & SYSCTL_GLOBAL00_MUX_MASK) >> SYSCTL_GLOBAL00_MUX_SHIFT) 763 764 /* Bitfield definition for register of struct array MONITOR: CONTROL */ 765 /* 766 * VALID (RW) 767 * 768 * result is ready for read 769 * 0: not ready 770 * 1: result is ready 771 */ 772 #define SYSCTL_MONITOR_CONTROL_VALID_MASK (0x80000000UL) 773 #define SYSCTL_MONITOR_CONTROL_VALID_SHIFT (31U) 774 #define SYSCTL_MONITOR_CONTROL_VALID_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_VALID_SHIFT) & SYSCTL_MONITOR_CONTROL_VALID_MASK) 775 #define SYSCTL_MONITOR_CONTROL_VALID_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_VALID_MASK) >> SYSCTL_MONITOR_CONTROL_VALID_SHIFT) 776 777 /* 778 * DIV_BUSY (RO) 779 * 780 * divider is applying new setting 781 */ 782 #define SYSCTL_MONITOR_CONTROL_DIV_BUSY_MASK (0x8000000UL) 783 #define SYSCTL_MONITOR_CONTROL_DIV_BUSY_SHIFT (27U) 784 #define SYSCTL_MONITOR_CONTROL_DIV_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_DIV_BUSY_MASK) >> SYSCTL_MONITOR_CONTROL_DIV_BUSY_SHIFT) 785 786 /* 787 * OUTEN (RW) 788 * 789 * enable clock output 790 */ 791 #define SYSCTL_MONITOR_CONTROL_OUTEN_MASK (0x1000000UL) 792 #define SYSCTL_MONITOR_CONTROL_OUTEN_SHIFT (24U) 793 #define SYSCTL_MONITOR_CONTROL_OUTEN_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_OUTEN_SHIFT) & SYSCTL_MONITOR_CONTROL_OUTEN_MASK) 794 #define SYSCTL_MONITOR_CONTROL_OUTEN_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_OUTEN_MASK) >> SYSCTL_MONITOR_CONTROL_OUTEN_SHIFT) 795 796 /* 797 * DIV (RW) 798 * 799 * output divider 800 */ 801 #define SYSCTL_MONITOR_CONTROL_DIV_MASK (0xFF0000UL) 802 #define SYSCTL_MONITOR_CONTROL_DIV_SHIFT (16U) 803 #define SYSCTL_MONITOR_CONTROL_DIV_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_DIV_SHIFT) & SYSCTL_MONITOR_CONTROL_DIV_MASK) 804 #define SYSCTL_MONITOR_CONTROL_DIV_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_DIV_MASK) >> SYSCTL_MONITOR_CONTROL_DIV_SHIFT) 805 806 /* 807 * HIGH (RW) 808 * 809 * clock frequency higher than upper limit 810 */ 811 #define SYSCTL_MONITOR_CONTROL_HIGH_MASK (0x8000U) 812 #define SYSCTL_MONITOR_CONTROL_HIGH_SHIFT (15U) 813 #define SYSCTL_MONITOR_CONTROL_HIGH_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_HIGH_SHIFT) & SYSCTL_MONITOR_CONTROL_HIGH_MASK) 814 #define SYSCTL_MONITOR_CONTROL_HIGH_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_HIGH_MASK) >> SYSCTL_MONITOR_CONTROL_HIGH_SHIFT) 815 816 /* 817 * LOW (RW) 818 * 819 * clock frequency lower than lower limit 820 */ 821 #define SYSCTL_MONITOR_CONTROL_LOW_MASK (0x4000U) 822 #define SYSCTL_MONITOR_CONTROL_LOW_SHIFT (14U) 823 #define SYSCTL_MONITOR_CONTROL_LOW_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_LOW_SHIFT) & SYSCTL_MONITOR_CONTROL_LOW_MASK) 824 #define SYSCTL_MONITOR_CONTROL_LOW_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_LOW_MASK) >> SYSCTL_MONITOR_CONTROL_LOW_SHIFT) 825 826 /* 827 * START (RW) 828 * 829 * start measurement 830 */ 831 #define SYSCTL_MONITOR_CONTROL_START_MASK (0x1000U) 832 #define SYSCTL_MONITOR_CONTROL_START_SHIFT (12U) 833 #define SYSCTL_MONITOR_CONTROL_START_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_START_SHIFT) & SYSCTL_MONITOR_CONTROL_START_MASK) 834 #define SYSCTL_MONITOR_CONTROL_START_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_START_MASK) >> SYSCTL_MONITOR_CONTROL_START_SHIFT) 835 836 /* 837 * MODE (RW) 838 * 839 * work mode, 840 * 0: register value will be compared to measurement 841 * 1: upper and lower value will be recordered in register 842 */ 843 #define SYSCTL_MONITOR_CONTROL_MODE_MASK (0x400U) 844 #define SYSCTL_MONITOR_CONTROL_MODE_SHIFT (10U) 845 #define SYSCTL_MONITOR_CONTROL_MODE_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_MODE_SHIFT) & SYSCTL_MONITOR_CONTROL_MODE_MASK) 846 #define SYSCTL_MONITOR_CONTROL_MODE_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_MODE_MASK) >> SYSCTL_MONITOR_CONTROL_MODE_SHIFT) 847 848 /* 849 * ACCURACY (RW) 850 * 851 * measurement accuracy, 852 * 0: resolution is 1kHz 853 * 1: resolution is 1Hz 854 */ 855 #define SYSCTL_MONITOR_CONTROL_ACCURACY_MASK (0x200U) 856 #define SYSCTL_MONITOR_CONTROL_ACCURACY_SHIFT (9U) 857 #define SYSCTL_MONITOR_CONTROL_ACCURACY_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_ACCURACY_SHIFT) & SYSCTL_MONITOR_CONTROL_ACCURACY_MASK) 858 #define SYSCTL_MONITOR_CONTROL_ACCURACY_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_ACCURACY_MASK) >> SYSCTL_MONITOR_CONTROL_ACCURACY_SHIFT) 859 860 /* 861 * REFERENCE (RW) 862 * 863 * refrence clock selection, 864 * 0: 32k 865 * 1: 24M 866 */ 867 #define SYSCTL_MONITOR_CONTROL_REFERENCE_MASK (0x100U) 868 #define SYSCTL_MONITOR_CONTROL_REFERENCE_SHIFT (8U) 869 #define SYSCTL_MONITOR_CONTROL_REFERENCE_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_REFERENCE_SHIFT) & SYSCTL_MONITOR_CONTROL_REFERENCE_MASK) 870 #define SYSCTL_MONITOR_CONTROL_REFERENCE_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_REFERENCE_MASK) >> SYSCTL_MONITOR_CONTROL_REFERENCE_SHIFT) 871 872 /* 873 * SELECTION (RW) 874 * 875 * clock measurement selection 876 */ 877 #define SYSCTL_MONITOR_CONTROL_SELECTION_MASK (0xFFU) 878 #define SYSCTL_MONITOR_CONTROL_SELECTION_SHIFT (0U) 879 #define SYSCTL_MONITOR_CONTROL_SELECTION_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_SELECTION_SHIFT) & SYSCTL_MONITOR_CONTROL_SELECTION_MASK) 880 #define SYSCTL_MONITOR_CONTROL_SELECTION_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_SELECTION_MASK) >> SYSCTL_MONITOR_CONTROL_SELECTION_SHIFT) 881 882 /* Bitfield definition for register of struct array MONITOR: CURRENT */ 883 /* 884 * FREQUENCY (RO) 885 * 886 * self updating measure result 887 */ 888 #define SYSCTL_MONITOR_CURRENT_FREQUENCY_MASK (0xFFFFFFFFUL) 889 #define SYSCTL_MONITOR_CURRENT_FREQUENCY_SHIFT (0U) 890 #define SYSCTL_MONITOR_CURRENT_FREQUENCY_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CURRENT_FREQUENCY_MASK) >> SYSCTL_MONITOR_CURRENT_FREQUENCY_SHIFT) 891 892 /* Bitfield definition for register of struct array MONITOR: LOW_LIMIT */ 893 /* 894 * FREQUENCY (RW) 895 * 896 * lower frequency 897 */ 898 #define SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_MASK (0xFFFFFFFFUL) 899 #define SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SHIFT (0U) 900 #define SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SHIFT) & SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_MASK) 901 #define SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_MASK) >> SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SHIFT) 902 903 /* Bitfield definition for register of struct array MONITOR: HIGH_LIMIT */ 904 /* 905 * FREQUENCY (RW) 906 * 907 * upper frequency 908 */ 909 #define SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_MASK (0xFFFFFFFFUL) 910 #define SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SHIFT (0U) 911 #define SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SHIFT) & SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_MASK) 912 #define SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_MASK) >> SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SHIFT) 913 914 /* Bitfield definition for register of struct array CPU: LP */ 915 /* 916 * WAKE_CNT (RW) 917 * 918 * CPU0 wake up counter, counter satuated at 255, write 0x00 to clear 919 */ 920 #define SYSCTL_CPU_LP_WAKE_CNT_MASK (0xFF000000UL) 921 #define SYSCTL_CPU_LP_WAKE_CNT_SHIFT (24U) 922 #define SYSCTL_CPU_LP_WAKE_CNT_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LP_WAKE_CNT_SHIFT) & SYSCTL_CPU_LP_WAKE_CNT_MASK) 923 #define SYSCTL_CPU_LP_WAKE_CNT_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_WAKE_CNT_MASK) >> SYSCTL_CPU_LP_WAKE_CNT_SHIFT) 924 925 /* 926 * HALT (RW) 927 * 928 * halt request for CPU0, 929 * 0: CPU0 will start to execute after reset or receive wakeup request 930 * 1: CPU0 will not start after reset, or wakeup after WFI 931 */ 932 #define SYSCTL_CPU_LP_HALT_MASK (0x10000UL) 933 #define SYSCTL_CPU_LP_HALT_SHIFT (16U) 934 #define SYSCTL_CPU_LP_HALT_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LP_HALT_SHIFT) & SYSCTL_CPU_LP_HALT_MASK) 935 #define SYSCTL_CPU_LP_HALT_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_HALT_MASK) >> SYSCTL_CPU_LP_HALT_SHIFT) 936 937 /* 938 * WAKE (RO) 939 * 940 * CPU0 is waking up 941 * 0: CPU0 wake up not asserted 942 * 1: CPU0 wake up asserted 943 */ 944 #define SYSCTL_CPU_LP_WAKE_MASK (0x2000U) 945 #define SYSCTL_CPU_LP_WAKE_SHIFT (13U) 946 #define SYSCTL_CPU_LP_WAKE_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_WAKE_MASK) >> SYSCTL_CPU_LP_WAKE_SHIFT) 947 948 /* 949 * EXEC (RO) 950 * 951 * CPU0 is executing 952 * 0: CPU0 is not executing 953 * 1: CPU0 is executing 954 */ 955 #define SYSCTL_CPU_LP_EXEC_MASK (0x1000U) 956 #define SYSCTL_CPU_LP_EXEC_SHIFT (12U) 957 #define SYSCTL_CPU_LP_EXEC_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_EXEC_MASK) >> SYSCTL_CPU_LP_EXEC_SHIFT) 958 959 /* 960 * WAKE_FLAG (RW) 961 * 962 * CPU0 wakeup flag, indicate a wakeup event got active, write 1 to clear this bit 963 * 0: CPU0 wakeup not happened 964 * 1: CPU0 wake up happened 965 */ 966 #define SYSCTL_CPU_LP_WAKE_FLAG_MASK (0x400U) 967 #define SYSCTL_CPU_LP_WAKE_FLAG_SHIFT (10U) 968 #define SYSCTL_CPU_LP_WAKE_FLAG_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LP_WAKE_FLAG_SHIFT) & SYSCTL_CPU_LP_WAKE_FLAG_MASK) 969 #define SYSCTL_CPU_LP_WAKE_FLAG_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_WAKE_FLAG_MASK) >> SYSCTL_CPU_LP_WAKE_FLAG_SHIFT) 970 971 /* 972 * SLEEP_FLAG (RW) 973 * 974 * CPU0 sleep flag, indicate a sleep event got active, write 1 to clear this bit 975 * 0: CPU0 sleep not happened 976 * 1: CPU0 sleep happened 977 */ 978 #define SYSCTL_CPU_LP_SLEEP_FLAG_MASK (0x200U) 979 #define SYSCTL_CPU_LP_SLEEP_FLAG_SHIFT (9U) 980 #define SYSCTL_CPU_LP_SLEEP_FLAG_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LP_SLEEP_FLAG_SHIFT) & SYSCTL_CPU_LP_SLEEP_FLAG_MASK) 981 #define SYSCTL_CPU_LP_SLEEP_FLAG_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_SLEEP_FLAG_MASK) >> SYSCTL_CPU_LP_SLEEP_FLAG_SHIFT) 982 983 /* 984 * RESET_FLAG (RW) 985 * 986 * CPU0 reset flag, indicate a reset event got active, write 1 to clear this bit 987 * 0: CPU0 reset not happened 988 * 1: CPU0 reset happened 989 */ 990 #define SYSCTL_CPU_LP_RESET_FLAG_MASK (0x100U) 991 #define SYSCTL_CPU_LP_RESET_FLAG_SHIFT (8U) 992 #define SYSCTL_CPU_LP_RESET_FLAG_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LP_RESET_FLAG_SHIFT) & SYSCTL_CPU_LP_RESET_FLAG_MASK) 993 #define SYSCTL_CPU_LP_RESET_FLAG_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_RESET_FLAG_MASK) >> SYSCTL_CPU_LP_RESET_FLAG_SHIFT) 994 995 /* 996 * MODE (RW) 997 * 998 * Low power mode, system behavior after WFI 999 * 00: CPU clock stop after WFI 1000 * 01: System enter low power mode after WFI 1001 * 10: Keep running after WFI 1002 * 11: reserved 1003 */ 1004 #define SYSCTL_CPU_LP_MODE_MASK (0x3U) 1005 #define SYSCTL_CPU_LP_MODE_SHIFT (0U) 1006 #define SYSCTL_CPU_LP_MODE_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LP_MODE_SHIFT) & SYSCTL_CPU_LP_MODE_MASK) 1007 #define SYSCTL_CPU_LP_MODE_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_MODE_MASK) >> SYSCTL_CPU_LP_MODE_SHIFT) 1008 1009 /* Bitfield definition for register of struct array CPU: LOCK */ 1010 /* 1011 * GPR (RW) 1012 * 1013 * Lock bit for CPU_DATA0 to CPU_DATA13, once set, this bit will not clear untile next reset 1014 */ 1015 #define SYSCTL_CPU_LOCK_GPR_MASK (0xFFFCU) 1016 #define SYSCTL_CPU_LOCK_GPR_SHIFT (2U) 1017 #define SYSCTL_CPU_LOCK_GPR_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LOCK_GPR_SHIFT) & SYSCTL_CPU_LOCK_GPR_MASK) 1018 #define SYSCTL_CPU_LOCK_GPR_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LOCK_GPR_MASK) >> SYSCTL_CPU_LOCK_GPR_SHIFT) 1019 1020 /* 1021 * LOCK (RW) 1022 * 1023 * Lock bit for CPU_LOCK 1024 */ 1025 #define SYSCTL_CPU_LOCK_LOCK_MASK (0x2U) 1026 #define SYSCTL_CPU_LOCK_LOCK_SHIFT (1U) 1027 #define SYSCTL_CPU_LOCK_LOCK_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LOCK_LOCK_SHIFT) & SYSCTL_CPU_LOCK_LOCK_MASK) 1028 #define SYSCTL_CPU_LOCK_LOCK_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LOCK_LOCK_MASK) >> SYSCTL_CPU_LOCK_LOCK_SHIFT) 1029 1030 /* Bitfield definition for register of struct array CPU: GPR0 */ 1031 /* 1032 * GPR (RW) 1033 * 1034 * register for software to handle resume, can save resume address or status 1035 */ 1036 #define SYSCTL_CPU_GPR_GPR_MASK (0xFFFFFFFFUL) 1037 #define SYSCTL_CPU_GPR_GPR_SHIFT (0U) 1038 #define SYSCTL_CPU_GPR_GPR_SET(x) (((uint32_t)(x) << SYSCTL_CPU_GPR_GPR_SHIFT) & SYSCTL_CPU_GPR_GPR_MASK) 1039 #define SYSCTL_CPU_GPR_GPR_GET(x) (((uint32_t)(x) & SYSCTL_CPU_GPR_GPR_MASK) >> SYSCTL_CPU_GPR_GPR_SHIFT) 1040 1041 /* Bitfield definition for register of struct array CPU: STATUS0 */ 1042 /* 1043 * STATUS (RO) 1044 * 1045 * IRQ values 1046 */ 1047 #define SYSCTL_CPU_WAKEUP_STATUS_STATUS_MASK (0xFFFFFFFFUL) 1048 #define SYSCTL_CPU_WAKEUP_STATUS_STATUS_SHIFT (0U) 1049 #define SYSCTL_CPU_WAKEUP_STATUS_STATUS_GET(x) (((uint32_t)(x) & SYSCTL_CPU_WAKEUP_STATUS_STATUS_MASK) >> SYSCTL_CPU_WAKEUP_STATUS_STATUS_SHIFT) 1050 1051 /* Bitfield definition for register of struct array CPU: ENABLE0 */ 1052 /* 1053 * ENABLE (RW) 1054 * 1055 * IRQ wakeup enable 1056 */ 1057 #define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_MASK (0xFFFFFFFFUL) 1058 #define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_SHIFT (0U) 1059 #define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_SET(x) (((uint32_t)(x) << SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_SHIFT) & SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_MASK) 1060 #define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_GET(x) (((uint32_t)(x) & SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_MASK) >> SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_SHIFT) 1061 1062 1063 1064 /* RESOURCE register group index macro definition */ 1065 #define SYSCTL_RESOURCE_CPU0 (0UL) 1066 #define SYSCTL_RESOURCE_CPX0 (1UL) 1067 #define SYSCTL_RESOURCE_POW_CPU0 (21UL) 1068 #define SYSCTL_RESOURCE_RST_SOC (22UL) 1069 #define SYSCTL_RESOURCE_RST_CPU0 (23UL) 1070 #define SYSCTL_RESOURCE_CLK_SRC_XTAL (32UL) 1071 #define SYSCTL_RESOURCE_CLK_SRC_PLL0 (33UL) 1072 #define SYSCTL_RESOURCE_CLK_SRC_CLK0_PLL0 (34UL) 1073 #define SYSCTL_RESOURCE_CLK_SRC_CLK1_PLL0 (35UL) 1074 #define SYSCTL_RESOURCE_CLK_SRC_CLK2_PLL0 (36UL) 1075 #define SYSCTL_RESOURCE_CLK_SRC_PLL1 (37UL) 1076 #define SYSCTL_RESOURCE_CLK_SRC_CLK0_PLL1 (38UL) 1077 #define SYSCTL_RESOURCE_CLK_SRC_CLK1_PLL1 (39UL) 1078 #define SYSCTL_RESOURCE_CLK_SRC_CLK2_PLL1 (40UL) 1079 #define SYSCTL_RESOURCE_CLK_SRC_CLK3_PLL1 (41UL) 1080 #define SYSCTL_RESOURCE_CLK_SRC_PLL0_REF (42UL) 1081 #define SYSCTL_RESOURCE_CLK_SRC_PLL1_REF (43UL) 1082 #define SYSCTL_RESOURCE_CLK_TOP_CPU0 (64UL) 1083 #define SYSCTL_RESOURCE_CLK_TOP_MCT0 (65UL) 1084 #define SYSCTL_RESOURCE_CLK_TOP_CAN0 (66UL) 1085 #define SYSCTL_RESOURCE_CLK_TOP_CAN1 (67UL) 1086 #define SYSCTL_RESOURCE_CLK_TOP_CAN2 (68UL) 1087 #define SYSCTL_RESOURCE_CLK_TOP_CAN3 (69UL) 1088 #define SYSCTL_RESOURCE_CLK_TOP_LIN0 (70UL) 1089 #define SYSCTL_RESOURCE_CLK_TOP_LIN1 (71UL) 1090 #define SYSCTL_RESOURCE_CLK_TOP_LIN2 (72UL) 1091 #define SYSCTL_RESOURCE_CLK_TOP_LIN3 (73UL) 1092 #define SYSCTL_RESOURCE_CLK_TOP_TMR0 (74UL) 1093 #define SYSCTL_RESOURCE_CLK_TOP_TMR1 (75UL) 1094 #define SYSCTL_RESOURCE_CLK_TOP_TMR2 (76UL) 1095 #define SYSCTL_RESOURCE_CLK_TOP_TMR3 (77UL) 1096 #define SYSCTL_RESOURCE_CLK_TOP_I2C0 (78UL) 1097 #define SYSCTL_RESOURCE_CLK_TOP_I2C1 (79UL) 1098 #define SYSCTL_RESOURCE_CLK_TOP_I2C2 (80UL) 1099 #define SYSCTL_RESOURCE_CLK_TOP_I2C3 (81UL) 1100 #define SYSCTL_RESOURCE_CLK_TOP_SPI0 (82UL) 1101 #define SYSCTL_RESOURCE_CLK_TOP_SPI1 (83UL) 1102 #define SYSCTL_RESOURCE_CLK_TOP_SPI2 (84UL) 1103 #define SYSCTL_RESOURCE_CLK_TOP_SPI3 (85UL) 1104 #define SYSCTL_RESOURCE_CLK_TOP_URT0 (86UL) 1105 #define SYSCTL_RESOURCE_CLK_TOP_URT1 (87UL) 1106 #define SYSCTL_RESOURCE_CLK_TOP_URT2 (88UL) 1107 #define SYSCTL_RESOURCE_CLK_TOP_URT3 (89UL) 1108 #define SYSCTL_RESOURCE_CLK_TOP_URT4 (90UL) 1109 #define SYSCTL_RESOURCE_CLK_TOP_URT5 (91UL) 1110 #define SYSCTL_RESOURCE_CLK_TOP_URT6 (92UL) 1111 #define SYSCTL_RESOURCE_CLK_TOP_URT7 (93UL) 1112 #define SYSCTL_RESOURCE_CLK_TOP_XPI0 (94UL) 1113 #define SYSCTL_RESOURCE_CLK_TOP_ANA0 (95UL) 1114 #define SYSCTL_RESOURCE_CLK_TOP_ANA1 (96UL) 1115 #define SYSCTL_RESOURCE_CLK_TOP_ANA2 (97UL) 1116 #define SYSCTL_RESOURCE_CLK_TOP_ANA3 (98UL) 1117 #define SYSCTL_RESOURCE_CLK_TOP_REF0 (99UL) 1118 #define SYSCTL_RESOURCE_CLK_TOP_REF1 (100UL) 1119 #define SYSCTL_RESOURCE_CLK_TOP_ADC0 (101UL) 1120 #define SYSCTL_RESOURCE_CLK_TOP_ADC1 (102UL) 1121 #define SYSCTL_RESOURCE_CLK_TOP_DAC0 (103UL) 1122 #define SYSCTL_RESOURCE_CLK_TOP_DAC1 (104UL) 1123 #define SYSCTL_RESOURCE_AHB0 (256UL) 1124 #define SYSCTL_RESOURCE_LMM0 (257UL) 1125 #define SYSCTL_RESOURCE_MCT0 (258UL) 1126 #define SYSCTL_RESOURCE_ROM0 (259UL) 1127 #define SYSCTL_RESOURCE_CAN0 (260UL) 1128 #define SYSCTL_RESOURCE_CAN1 (261UL) 1129 #define SYSCTL_RESOURCE_CAN2 (262UL) 1130 #define SYSCTL_RESOURCE_CAN3 (263UL) 1131 #define SYSCTL_RESOURCE_PTPC (264UL) 1132 #define SYSCTL_RESOURCE_LIN0 (265UL) 1133 #define SYSCTL_RESOURCE_LIN1 (266UL) 1134 #define SYSCTL_RESOURCE_LIN2 (267UL) 1135 #define SYSCTL_RESOURCE_LIN3 (268UL) 1136 #define SYSCTL_RESOURCE_TMR0 (269UL) 1137 #define SYSCTL_RESOURCE_TMR1 (270UL) 1138 #define SYSCTL_RESOURCE_TMR2 (271UL) 1139 #define SYSCTL_RESOURCE_TMR3 (272UL) 1140 #define SYSCTL_RESOURCE_I2C0 (273UL) 1141 #define SYSCTL_RESOURCE_I2C1 (274UL) 1142 #define SYSCTL_RESOURCE_I2C2 (275UL) 1143 #define SYSCTL_RESOURCE_I2C3 (276UL) 1144 #define SYSCTL_RESOURCE_SPI0 (277UL) 1145 #define SYSCTL_RESOURCE_SPI1 (278UL) 1146 #define SYSCTL_RESOURCE_SPI2 (279UL) 1147 #define SYSCTL_RESOURCE_SPI3 (280UL) 1148 #define SYSCTL_RESOURCE_URT0 (281UL) 1149 #define SYSCTL_RESOURCE_URT1 (282UL) 1150 #define SYSCTL_RESOURCE_URT2 (283UL) 1151 #define SYSCTL_RESOURCE_URT3 (284UL) 1152 #define SYSCTL_RESOURCE_URT4 (285UL) 1153 #define SYSCTL_RESOURCE_URT5 (286UL) 1154 #define SYSCTL_RESOURCE_URT6 (287UL) 1155 #define SYSCTL_RESOURCE_URT7 (288UL) 1156 #define SYSCTL_RESOURCE_WDG0 (289UL) 1157 #define SYSCTL_RESOURCE_WDG1 (290UL) 1158 #define SYSCTL_RESOURCE_MBX0 (291UL) 1159 #define SYSCTL_RESOURCE_TSNS (292UL) 1160 #define SYSCTL_RESOURCE_CRC0 (293UL) 1161 #define SYSCTL_RESOURCE_ADC0 (294UL) 1162 #define SYSCTL_RESOURCE_ADC1 (295UL) 1163 #define SYSCTL_RESOURCE_DAC0 (296UL) 1164 #define SYSCTL_RESOURCE_DAC1 (297UL) 1165 #define SYSCTL_RESOURCE_ACMP (298UL) 1166 #define SYSCTL_RESOURCE_OPA0 (299UL) 1167 #define SYSCTL_RESOURCE_OPA1 (300UL) 1168 #define SYSCTL_RESOURCE_MOT0 (301UL) 1169 #define SYSCTL_RESOURCE_RNG0 (302UL) 1170 #define SYSCTL_RESOURCE_SDP0 (303UL) 1171 #define SYSCTL_RESOURCE_KMAN (304UL) 1172 #define SYSCTL_RESOURCE_GPIO (305UL) 1173 #define SYSCTL_RESOURCE_HDMA (306UL) 1174 #define SYSCTL_RESOURCE_XPI0 (307UL) 1175 #define SYSCTL_RESOURCE_USB0 (308UL) 1176 #define SYSCTL_RESOURCE_REF0 (309UL) 1177 #define SYSCTL_RESOURCE_REF1 (310UL) 1178 1179 /* GROUP0 register group index macro definition */ 1180 #define SYSCTL_GROUP0_LINK0 (0UL) 1181 #define SYSCTL_GROUP0_LINK1 (1UL) 1182 1183 /* AFFILIATE register group index macro definition */ 1184 #define SYSCTL_AFFILIATE_CPU0 (0UL) 1185 1186 /* RETENTION register group index macro definition */ 1187 #define SYSCTL_RETENTION_CPU0 (0UL) 1188 1189 /* POWER register group index macro definition */ 1190 #define SYSCTL_POWER_CPU0 (0UL) 1191 1192 /* RESET register group index macro definition */ 1193 #define SYSCTL_RESET_SOC (0UL) 1194 #define SYSCTL_RESET_CPU0 (1UL) 1195 1196 /* CLOCK_CPU register group index macro definition */ 1197 #define SYSCTL_CLOCK_CPU_CLK_TOP_CPU0 (0UL) 1198 1199 /* CLOCK register group index macro definition */ 1200 #define SYSCTL_CLOCK_CLK_TOP_MCT0 (0UL) 1201 #define SYSCTL_CLOCK_CLK_TOP_CAN0 (1UL) 1202 #define SYSCTL_CLOCK_CLK_TOP_CAN1 (2UL) 1203 #define SYSCTL_CLOCK_CLK_TOP_CAN2 (3UL) 1204 #define SYSCTL_CLOCK_CLK_TOP_CAN3 (4UL) 1205 #define SYSCTL_CLOCK_CLK_TOP_LIN0 (5UL) 1206 #define SYSCTL_CLOCK_CLK_TOP_LIN1 (6UL) 1207 #define SYSCTL_CLOCK_CLK_TOP_LIN2 (7UL) 1208 #define SYSCTL_CLOCK_CLK_TOP_LIN3 (8UL) 1209 #define SYSCTL_CLOCK_CLK_TOP_TMR0 (9UL) 1210 #define SYSCTL_CLOCK_CLK_TOP_TMR1 (10UL) 1211 #define SYSCTL_CLOCK_CLK_TOP_TMR2 (11UL) 1212 #define SYSCTL_CLOCK_CLK_TOP_TMR3 (12UL) 1213 #define SYSCTL_CLOCK_CLK_TOP_I2C0 (13UL) 1214 #define SYSCTL_CLOCK_CLK_TOP_I2C1 (14UL) 1215 #define SYSCTL_CLOCK_CLK_TOP_I2C2 (15UL) 1216 #define SYSCTL_CLOCK_CLK_TOP_I2C3 (16UL) 1217 #define SYSCTL_CLOCK_CLK_TOP_SPI0 (17UL) 1218 #define SYSCTL_CLOCK_CLK_TOP_SPI1 (18UL) 1219 #define SYSCTL_CLOCK_CLK_TOP_SPI2 (19UL) 1220 #define SYSCTL_CLOCK_CLK_TOP_SPI3 (20UL) 1221 #define SYSCTL_CLOCK_CLK_TOP_URT0 (21UL) 1222 #define SYSCTL_CLOCK_CLK_TOP_URT1 (22UL) 1223 #define SYSCTL_CLOCK_CLK_TOP_URT2 (23UL) 1224 #define SYSCTL_CLOCK_CLK_TOP_URT3 (24UL) 1225 #define SYSCTL_CLOCK_CLK_TOP_URT4 (25UL) 1226 #define SYSCTL_CLOCK_CLK_TOP_URT5 (26UL) 1227 #define SYSCTL_CLOCK_CLK_TOP_URT6 (27UL) 1228 #define SYSCTL_CLOCK_CLK_TOP_URT7 (28UL) 1229 #define SYSCTL_CLOCK_CLK_TOP_XPI0 (29UL) 1230 #define SYSCTL_CLOCK_CLK_TOP_ANA0 (30UL) 1231 #define SYSCTL_CLOCK_CLK_TOP_ANA1 (31UL) 1232 #define SYSCTL_CLOCK_CLK_TOP_ANA2 (32UL) 1233 #define SYSCTL_CLOCK_CLK_TOP_ANA3 (33UL) 1234 #define SYSCTL_CLOCK_CLK_TOP_REF0 (34UL) 1235 #define SYSCTL_CLOCK_CLK_TOP_REF1 (35UL) 1236 1237 /* ADCCLK register group index macro definition */ 1238 #define SYSCTL_ADCCLK_CLK_TOP_ADC0 (0UL) 1239 #define SYSCTL_ADCCLK_CLK_TOP_ADC1 (1UL) 1240 1241 /* DACCLK register group index macro definition */ 1242 #define SYSCTL_DACCLK_CLK_TOP_DAC0 (0UL) 1243 #define SYSCTL_DACCLK_CLK_TOP_DAC1 (1UL) 1244 1245 /* MONITOR register group index macro definition */ 1246 #define SYSCTL_MONITOR_SLICE0 (0UL) 1247 #define SYSCTL_MONITOR_SLICE1 (1UL) 1248 #define SYSCTL_MONITOR_SLICE2 (2UL) 1249 #define SYSCTL_MONITOR_SLICE3 (3UL) 1250 1251 /* GPR register group index macro definition */ 1252 #define SYSCTL_CPU_GPR_GPR0 (0UL) 1253 #define SYSCTL_CPU_GPR_GPR1 (1UL) 1254 #define SYSCTL_CPU_GPR_GPR2 (2UL) 1255 #define SYSCTL_CPU_GPR_GPR3 (3UL) 1256 #define SYSCTL_CPU_GPR_GPR4 (4UL) 1257 #define SYSCTL_CPU_GPR_GPR5 (5UL) 1258 #define SYSCTL_CPU_GPR_GPR6 (6UL) 1259 #define SYSCTL_CPU_GPR_GPR7 (7UL) 1260 #define SYSCTL_CPU_GPR_GPR8 (8UL) 1261 #define SYSCTL_CPU_GPR_GPR9 (9UL) 1262 #define SYSCTL_CPU_GPR_GPR10 (10UL) 1263 #define SYSCTL_CPU_GPR_GPR11 (11UL) 1264 #define SYSCTL_CPU_GPR_GPR12 (12UL) 1265 #define SYSCTL_CPU_GPR_GPR13 (13UL) 1266 1267 /* WAKEUP_STATUS register group index macro definition */ 1268 #define SYSCTL_CPU_WAKEUP_STATUS_STATUS0 (0UL) 1269 #define SYSCTL_CPU_WAKEUP_STATUS_STATUS1 (1UL) 1270 #define SYSCTL_CPU_WAKEUP_STATUS_STATUS2 (2UL) 1271 #define SYSCTL_CPU_WAKEUP_STATUS_STATUS3 (3UL) 1272 1273 /* WAKEUP_ENABLE register group index macro definition */ 1274 #define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE0 (0UL) 1275 #define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE1 (1UL) 1276 #define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE2 (2UL) 1277 #define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE3 (3UL) 1278 1279 /* CPU register group index macro definition */ 1280 #define SYSCTL_CPU_CPU0 (0UL) 1281 1282 1283 #endif /* HPM_SYSCTL_H */ 1284