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1 /*
2  * Copyright (c) 2021-2023 HPMicro
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  *
6  */
7 
8 
9 #ifndef HPM_TRGM_H
10 #define HPM_TRGM_H
11 
12 typedef struct {
13     __RW uint32_t FILTCFG[20];                 /* 0x0 - 0x4C: Filter configure register */
14     __R  uint8_t  RESERVED0[176];              /* 0x50 - 0xFF: Reserved */
15     __RW uint32_t TRGOCFG[64];                 /* 0x100 - 0x1FC: Trigger manager output configure register */
16     __RW uint32_t DMACFG[4];                   /* 0x200 - 0x20C: DMA request configure register */
17     __R  uint8_t  RESERVED1[496];              /* 0x210 - 0x3FF: Reserved */
18     __RW uint32_t GCR;                         /* 0x400: General Control Register */
19 } TRGM_Type;
20 
21 
22 /* Bitfield definition for register array: FILTCFG */
23 /*
24  * OUTINV (RW)
25  *
26  * 1- Filter will invert the output
27  * 0- Filter will not invert the output
28  */
29 #define TRGM_FILTCFG_OUTINV_MASK (0x10000UL)
30 #define TRGM_FILTCFG_OUTINV_SHIFT (16U)
31 #define TRGM_FILTCFG_OUTINV_SET(x) (((uint32_t)(x) << TRGM_FILTCFG_OUTINV_SHIFT) & TRGM_FILTCFG_OUTINV_MASK)
32 #define TRGM_FILTCFG_OUTINV_GET(x) (((uint32_t)(x) & TRGM_FILTCFG_OUTINV_MASK) >> TRGM_FILTCFG_OUTINV_SHIFT)
33 
34 /*
35  * MODE (RW)
36  *
37  * This bitfields defines the filter mode
38  * 000-bypass;
39  * 100-rapid change mode;
40  * 101-delay filter mode;
41  * 110-stalbe low mode;
42  * 111-stable high mode
43  */
44 #define TRGM_FILTCFG_MODE_MASK (0xE000U)
45 #define TRGM_FILTCFG_MODE_SHIFT (13U)
46 #define TRGM_FILTCFG_MODE_SET(x) (((uint32_t)(x) << TRGM_FILTCFG_MODE_SHIFT) & TRGM_FILTCFG_MODE_MASK)
47 #define TRGM_FILTCFG_MODE_GET(x) (((uint32_t)(x) & TRGM_FILTCFG_MODE_MASK) >> TRGM_FILTCFG_MODE_SHIFT)
48 
49 /*
50  * SYNCEN (RW)
51  *
52  * set to enable sychronization input signal with TRGM clock
53  */
54 #define TRGM_FILTCFG_SYNCEN_MASK (0x1000U)
55 #define TRGM_FILTCFG_SYNCEN_SHIFT (12U)
56 #define TRGM_FILTCFG_SYNCEN_SET(x) (((uint32_t)(x) << TRGM_FILTCFG_SYNCEN_SHIFT) & TRGM_FILTCFG_SYNCEN_MASK)
57 #define TRGM_FILTCFG_SYNCEN_GET(x) (((uint32_t)(x) & TRGM_FILTCFG_SYNCEN_MASK) >> TRGM_FILTCFG_SYNCEN_SHIFT)
58 
59 /*
60  * FILTLEN (RW)
61  *
62  * This bitfields defines the filter counter length.
63  */
64 #define TRGM_FILTCFG_FILTLEN_MASK (0xFFFU)
65 #define TRGM_FILTCFG_FILTLEN_SHIFT (0U)
66 #define TRGM_FILTCFG_FILTLEN_SET(x) (((uint32_t)(x) << TRGM_FILTCFG_FILTLEN_SHIFT) & TRGM_FILTCFG_FILTLEN_MASK)
67 #define TRGM_FILTCFG_FILTLEN_GET(x) (((uint32_t)(x) & TRGM_FILTCFG_FILTLEN_MASK) >> TRGM_FILTCFG_FILTLEN_SHIFT)
68 
69 /* Bitfield definition for register array: TRGOCFG */
70 /*
71  * OUTINV (RW)
72  *
73  * 1- Invert the output
74  */
75 #define TRGM_TRGOCFG_OUTINV_MASK (0x100U)
76 #define TRGM_TRGOCFG_OUTINV_SHIFT (8U)
77 #define TRGM_TRGOCFG_OUTINV_SET(x) (((uint32_t)(x) << TRGM_TRGOCFG_OUTINV_SHIFT) & TRGM_TRGOCFG_OUTINV_MASK)
78 #define TRGM_TRGOCFG_OUTINV_GET(x) (((uint32_t)(x) & TRGM_TRGOCFG_OUTINV_MASK) >> TRGM_TRGOCFG_OUTINV_SHIFT)
79 
80 /*
81  * FEDG2PEN (RW)
82  *
83  * 1- The selected input signal falling edge will be convert to an pulse on output.
84  */
85 #define TRGM_TRGOCFG_FEDG2PEN_MASK (0x80U)
86 #define TRGM_TRGOCFG_FEDG2PEN_SHIFT (7U)
87 #define TRGM_TRGOCFG_FEDG2PEN_SET(x) (((uint32_t)(x) << TRGM_TRGOCFG_FEDG2PEN_SHIFT) & TRGM_TRGOCFG_FEDG2PEN_MASK)
88 #define TRGM_TRGOCFG_FEDG2PEN_GET(x) (((uint32_t)(x) & TRGM_TRGOCFG_FEDG2PEN_MASK) >> TRGM_TRGOCFG_FEDG2PEN_SHIFT)
89 
90 /*
91  * REDG2PEN (RW)
92  *
93  * 1- The selected input signal rising edge will be convert to an pulse on output.
94  */
95 #define TRGM_TRGOCFG_REDG2PEN_MASK (0x40U)
96 #define TRGM_TRGOCFG_REDG2PEN_SHIFT (6U)
97 #define TRGM_TRGOCFG_REDG2PEN_SET(x) (((uint32_t)(x) << TRGM_TRGOCFG_REDG2PEN_SHIFT) & TRGM_TRGOCFG_REDG2PEN_MASK)
98 #define TRGM_TRGOCFG_REDG2PEN_GET(x) (((uint32_t)(x) & TRGM_TRGOCFG_REDG2PEN_MASK) >> TRGM_TRGOCFG_REDG2PEN_SHIFT)
99 
100 /*
101  * TRIGOSEL (RW)
102  *
103  * This bitfield selects one of the TRGM inputs as output.
104  */
105 #define TRGM_TRGOCFG_TRIGOSEL_MASK (0x3FU)
106 #define TRGM_TRGOCFG_TRIGOSEL_SHIFT (0U)
107 #define TRGM_TRGOCFG_TRIGOSEL_SET(x) (((uint32_t)(x) << TRGM_TRGOCFG_TRIGOSEL_SHIFT) & TRGM_TRGOCFG_TRIGOSEL_MASK)
108 #define TRGM_TRGOCFG_TRIGOSEL_GET(x) (((uint32_t)(x) & TRGM_TRGOCFG_TRIGOSEL_MASK) >> TRGM_TRGOCFG_TRIGOSEL_SHIFT)
109 
110 /* Bitfield definition for register array: DMACFG */
111 /*
112  * DMASRCSEL (RW)
113  *
114  * This field selects one of the DMA requests as the DMA request output.
115  */
116 #define TRGM_DMACFG_DMASRCSEL_MASK (0x1FU)
117 #define TRGM_DMACFG_DMASRCSEL_SHIFT (0U)
118 #define TRGM_DMACFG_DMASRCSEL_SET(x) (((uint32_t)(x) << TRGM_DMACFG_DMASRCSEL_SHIFT) & TRGM_DMACFG_DMASRCSEL_MASK)
119 #define TRGM_DMACFG_DMASRCSEL_GET(x) (((uint32_t)(x) & TRGM_DMACFG_DMASRCSEL_MASK) >> TRGM_DMACFG_DMASRCSEL_SHIFT)
120 
121 /* Bitfield definition for register: GCR */
122 /*
123  * TRGOPEN (RW)
124  *
125  * The bitfield enable the TRGM outputs.
126  */
127 #define TRGM_GCR_TRGOPEN_MASK (0xFFFU)
128 #define TRGM_GCR_TRGOPEN_SHIFT (0U)
129 #define TRGM_GCR_TRGOPEN_SET(x) (((uint32_t)(x) << TRGM_GCR_TRGOPEN_SHIFT) & TRGM_GCR_TRGOPEN_MASK)
130 #define TRGM_GCR_TRGOPEN_GET(x) (((uint32_t)(x) & TRGM_GCR_TRGOPEN_MASK) >> TRGM_GCR_TRGOPEN_SHIFT)
131 
132 
133 
134 /* FILTCFG register group index macro definition */
135 #define TRGM_FILTCFG_PWM_IN0 (0UL)
136 #define TRGM_FILTCFG_PWM_IN1 (1UL)
137 #define TRGM_FILTCFG_PWM_IN2 (2UL)
138 #define TRGM_FILTCFG_PWM_IN3 (3UL)
139 #define TRGM_FILTCFG_PWM_IN4 (4UL)
140 #define TRGM_FILTCFG_PWM_IN5 (5UL)
141 #define TRGM_FILTCFG_PWM_IN6 (6UL)
142 #define TRGM_FILTCFG_PWM_IN7 (7UL)
143 #define TRGM_FILTCFG_TRGM_IN0 (8UL)
144 #define TRGM_FILTCFG_TRGM_IN1 (9UL)
145 #define TRGM_FILTCFG_TRGM_IN2 (10UL)
146 #define TRGM_FILTCFG_TRGM_IN3 (11UL)
147 #define TRGM_FILTCFG_TRGM_IN4 (12UL)
148 #define TRGM_FILTCFG_TRGM_IN5 (13UL)
149 #define TRGM_FILTCFG_TRGM_IN6 (14UL)
150 #define TRGM_FILTCFG_TRGM_IN7 (15UL)
151 #define TRGM_FILTCFG_TRGM_IN8 (16UL)
152 #define TRGM_FILTCFG_TRGM_IN9 (17UL)
153 #define TRGM_FILTCFG_TRGM_IN10 (18UL)
154 #define TRGM_FILTCFG_TRGM_IN11 (19UL)
155 
156 /* TRGOCFG register group index macro definition */
157 #define TRGM_TRGOCFG_TRGM_OUT0 (0UL)
158 #define TRGM_TRGOCFG_TRGM_OUT1 (1UL)
159 #define TRGM_TRGOCFG_TRGM_OUT2 (2UL)
160 #define TRGM_TRGOCFG_TRGM_OUT3 (3UL)
161 #define TRGM_TRGOCFG_TRGM_OUT4 (4UL)
162 #define TRGM_TRGOCFG_TRGM_OUT5 (5UL)
163 #define TRGM_TRGOCFG_TRGM_OUT6 (6UL)
164 #define TRGM_TRGOCFG_TRGM_OUT7 (7UL)
165 #define TRGM_TRGOCFG_TRGM_OUT8 (8UL)
166 #define TRGM_TRGOCFG_TRGM_OUT9 (9UL)
167 #define TRGM_TRGOCFG_TRGM_OUT10 (10UL)
168 #define TRGM_TRGOCFG_TRGM_OUT11 (11UL)
169 #define TRGM_TRGOCFG_TRGM_OUTX0 (12UL)
170 #define TRGM_TRGOCFG_TRGM_OUTX1 (13UL)
171 #define TRGM_TRGOCFG_PWM_SYNCI (14UL)
172 #define TRGM_TRGOCFG_PWM_FRCI (15UL)
173 #define TRGM_TRGOCFG_PWM_FRCSYNCI (16UL)
174 #define TRGM_TRGOCFG_PWM_SHRLDSYNCI (17UL)
175 #define TRGM_TRGOCFG_PWM_FAULTI0 (18UL)
176 #define TRGM_TRGOCFG_PWM_FAULTI1 (19UL)
177 #define TRGM_TRGOCFG_PWM_FAULTI2 (20UL)
178 #define TRGM_TRGOCFG_PWM_FAULTI3 (21UL)
179 #define TRGM_TRGOCFG_PWM_IN8 (22UL)
180 #define TRGM_TRGOCFG_PWM_IN9 (23UL)
181 #define TRGM_TRGOCFG_PWM_IN10 (24UL)
182 #define TRGM_TRGOCFG_PWM_IN11 (25UL)
183 #define TRGM_TRGOCFG_PWM_IN12 (26UL)
184 #define TRGM_TRGOCFG_PWM_IN13 (27UL)
185 #define TRGM_TRGOCFG_PWM_IN14 (28UL)
186 #define TRGM_TRGOCFG_PWM_IN15 (29UL)
187 #define TRGM_TRGOCFG_PWM_IN16 (30UL)
188 #define TRGM_TRGOCFG_PWM_IN17 (31UL)
189 #define TRGM_TRGOCFG_PWM_IN18 (32UL)
190 #define TRGM_TRGOCFG_PWM_IN19 (33UL)
191 #define TRGM_TRGOCFG_PWM_IN20 (34UL)
192 #define TRGM_TRGOCFG_PWM_IN21 (35UL)
193 #define TRGM_TRGOCFG_PWM_IN22 (36UL)
194 #define TRGM_TRGOCFG_PWM_IN23 (37UL)
195 #define TRGM_TRGOCFG_QEI_A (38UL)
196 #define TRGM_TRGOCFG_QEI_B (39UL)
197 #define TRGM_TRGOCFG_QEI_Z (40UL)
198 #define TRGM_TRGOCFG_QEI_H (41UL)
199 #define TRGM_TRGOCFG_QEI_PAUSE (42UL)
200 #define TRGM_TRGOCFG_QEI_SNAPI (43UL)
201 #define TRGM_TRGOCFG_HALL_U (44UL)
202 #define TRGM_TRGOCFG_HALL_V (45UL)
203 #define TRGM_TRGOCFG_HALL_W (46UL)
204 #define TRGM_TRGOCFG_HALL_SNAPI (47UL)
205 #define TRGM_TRGOCFG_ADC0_STRGI (48UL)
206 #define TRGM_TRGOCFG_ADC1_STRGI (49UL)
207 #define TRGM_TRGOCFG_ADC2_STRGI (50UL)
208 #define TRGM_TRGOCFG_ADC3_STRGI (51UL)
209 #define TRGM_TRGOCFG_ADCX_PTRGI0A (52UL)
210 #define TRGM_TRGOCFG_ADCX_PTRGI0B (53UL)
211 #define TRGM_TRGOCFG_ADCX_PTRGI0C (54UL)
212 #define TRGM_TRGOCFG_GPTMRA_SYNCI (55UL)
213 #define TRGM_TRGOCFG_GPTMRA_IN2 (56UL)
214 #define TRGM_TRGOCFG_GPTMRA_IN3 (57UL)
215 #define TRGM_TRGOCFG_GPTMRB_SYNCI (58UL)
216 #define TRGM_TRGOCFG_GPTMRB_IN2 (59UL)
217 #define TRGM_TRGOCFG_GPTMRB_IN3 (60UL)
218 #define TRGM_TRGOCFG_CMPX_WIN (61UL)
219 #define TRGM_TRGOCFG_CAN_PTPC0_CAP (62UL)
220 #define TRGM_TRGOCFG_CAN_PTPC1_CAP (63UL)
221 
222 /* DMACFG register group index macro definition */
223 #define TRGM_DMACFG_0 (0UL)
224 #define TRGM_DMACFG_1 (1UL)
225 #define TRGM_DMACFG_2 (2UL)
226 #define TRGM_DMACFG_3 (3UL)
227 
228 
229 #endif /* HPM_TRGM_H */
230