1 /*
2 * Copyright (c) 2021-2023 HPMicro
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 *
6 */
7
8 #ifndef HPM_ROMAPI_H
9 #define HPM_ROMAPI_H
10
11 /**
12 * @brief ROM APIs
13 * @defgroup romapi_interface ROM APIs
14 * @{
15 */
16
17 #include "hpm_common.h"
18 #include "hpm_otp_drv.h"
19 #include "hpm_romapi_xpi_def.h"
20 #include "hpm_romapi_xpi_soc_def.h"
21 #include "hpm_romapi_xpi_nor_def.h"
22 #include "hpm_romapi_xpi_ram_def.h"
23 #include "hpm_sdp_drv.h"
24
25 /* XPI0 base address */
26 #define HPM_XPI0_BASE (0xF3040000UL) /**< XPI0 Base address */
27 /* XPI0 base pointer */
28 #define HPM_XPI0 ((XPI_Type *) HPM_XPI0_BASE) /**< XPI0 Base pointer */
29 /* XPI1 base address */
30 #define HPM_XPI1_BASE (0xF3044000UL) /**< XPI1 Base address */
31 /* XPI1 base pointer */
32 #define HPM_XPI1 ((XPI_Type *) HPM_XPI1_BASE) /**< XPI1 Base pointer */
33
34
35 /***********************************************************************************************************************
36 *
37 *
38 * Definitions
39 *
40 *
41 **********************************************************************************************************************/
42 /**
43 * @brief Enter Bootloader API argument
44 */
45 typedef union {
46 uint32_t U;
47 struct {
48 uint32_t index: 8; /**< Image index */
49 uint32_t peripheral: 8; /**< Boot peripheral */
50 uint32_t src: 8; /**< Boot source */
51 uint32_t tag: 8; /**< ROM API parameter tag, must be 0xEB */
52 };
53 } api_boot_arg_t;
54
55 /*EXiP Region Parameter */
56 typedef struct {
57 uint32_t start; /**< Start address, must be 4KB aligned */
58 uint32_t len; /**< Must be 4KB aligned */
59 uint8_t key[16]; /**< AES Key */
60 uint8_t ctr[8]; /**< Initial Vector/Counter */
61 } exip_region_param_t;
62
63 #define API_BOOT_TAG (0xEBU) /**< ROM API parameter tag */
64 #define API_BOOT_SRC_OTP (0U) /**< Boot source: OTP */
65 #define API_BOOT_SRC_PRIMARY (1U) /**< Boot source: Primary */
66 #define API_BOOT_SRC_SERIAL_BOOT (2U) /**< Boot source: Serial Boot */
67 #define API_BOOT_SRC_ISP (3U) /**< Boot source: ISP */
68 #define API_BOOT_PERIPH_AUTO (0U) /**< Boot peripheral: Auto detected */
69 #define API_BOOT_PERIPH_UART (1U) /**< Boot peripheral: UART */
70 #define API_BOOT_PERIPH_USBHID (2U) /**< Boot Peripheral: USB-HID */
71
72 typedef struct {
73 uint32_t _internal[138];
74 } sm3_context_t;
75
76 #define SM4_ENCRYPT 1
77 #define SM4_DECRYPT 0
78
79 typedef struct {
80 uint32_t mode;
81 uint32_t _internal[116];
82 } sm4_context_t;
83
84 /**
85 * @brief OTP driver interface
86 */
87 typedef struct {
88 /**< OTP driver interface version */
89 uint32_t version;
90 /**< OTP driver interface: init */
91 void (*init)(void);
92 /**< OTP driver interface: deinit */
93 void (*deinit)(void);
94 /**< OTP driver interface: read from shadow */
95 uint32_t (*read_from_shadow)(uint32_t addr);
96 /**< OTP driver interface: read from ip */
97 uint32_t (*read_from_ip)(uint32_t addr);
98 /**< OTP driver interface: program */
99 hpm_stat_t (*program)(uint32_t addr, const uint32_t *src, uint32_t num_of_words);
100 /**< OTP driver interface: reload */
101 hpm_stat_t (*reload)(otp_region_t region);
102 /**< OTP driver interface: lock */
103 hpm_stat_t (*lock)(uint32_t addr, otp_lock_option_t lock_option);
104 /**< OTP driver interface: lock_shadow */
105 hpm_stat_t (*lock_shadow)(uint32_t addr, otp_lock_option_t lock_option);
106 /**< OTP driver interface: set_configurable_region */
107 hpm_stat_t (*set_configurable_region)(uint32_t start, uint32_t num_of_words);
108 /**< OTP driver interface: write_shadow_register */
109 hpm_stat_t (*write_shadow_register)(uint32_t addr, uint32_t data);
110 } otp_driver_interface_t;
111
112 /**
113 * @brief XPI driver interface
114 */
115 typedef struct {
116 /**< XPI driver interface: version */
117 uint32_t version;
118 /**< XPI driver interface: get default configuration */
119 hpm_stat_t (*get_default_config)(xpi_config_t *xpi_config);
120 /**< XPI driver interface: get default device configuration */
121 hpm_stat_t (*get_default_device_config)(xpi_device_config_t *dev_config);
122 /**< XPI driver interface: initialize the XPI using xpi_config */
123 hpm_stat_t (*init)(XPI_Type *base, xpi_config_t *xpi_config);
124 /**< XPI driver interface: configure the AHB buffer */
125 hpm_stat_t (*config_ahb_buffer)(XPI_Type *base, xpi_ahb_buffer_cfg_t *ahb_buf_cfg);
126 /**< XPI driver interface: configure the device */
127 hpm_stat_t (*config_device)(XPI_Type *base, xpi_device_config_t *dev_cfg, xpi_channel_t channel);
128 /**< XPI driver interface: update instruction talbe */
129 hpm_stat_t (*update_instr_table)(XPI_Type *base, const uint32_t *inst_base, uint32_t seq_idx, uint32_t num);
130 /**< XPI driver interface: transfer command/data using block interface */
131 hpm_stat_t (*transfer_blocking)(XPI_Type *base, xpi_xfer_ctx_t *xfer);
132 /**< Software reset the XPI controller */
133 void (*software_reset)(XPI_Type *base);
134 /**< XPI driver interface: Check whether IP is idle */
135 bool (*is_idle)(XPI_Type *base);
136 /**< XPI driver interface: update delay line setting */
137 void (*update_dllcr)(XPI_Type *base, uint32_t serial_root_clk_freq, uint32_t data_valid_time, xpi_channel_t channel,
138 uint32_t dly_target);
139 /**< XPI driver interface: Get absolute address for APB transfer */
140 hpm_stat_t (*get_abs_apb_xfer_addr)(XPI_Type *base, xpi_xfer_channel_t channel, uint32_t in_addr,
141 uint32_t *out_addr);
142 } xpi_driver_interface_t;
143
144 /**
145 * @brief XPI NOR driver interface
146 */
147 typedef struct {
148 /**< XPI NOR driver interface: API version */
149 uint32_t version;
150 /**< XPI NOR driver interface: Get FLASH configuration */
151 hpm_stat_t (*get_config)(XPI_Type *base, xpi_nor_config_t *nor_cfg, xpi_nor_config_option_t *cfg_option);
152 /**< XPI NOR driver interface: initialize FLASH */
153 hpm_stat_t (*init)(XPI_Type *base, xpi_nor_config_t *nor_config);
154 /**< XPI NOR driver interface: Enable write access to FLASH */
155 hpm_stat_t (*enable_write)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config,
156 uint32_t addr);
157 /**< XPI NOR driver interface: Get FLASH status register */
158 hpm_stat_t (*get_status)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config,
159 uint32_t addr,
160 uint16_t *out_status);
161 /**< XPI NOR driver interface: Wait when FLASH is still busy */
162 hpm_stat_t (*wait_busy)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config,
163 uint32_t addr);
164 /**< XPI NOR driver interface: erase a specified FLASH region */
165 hpm_stat_t (*erase)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config, uint32_t start,
166 uint32_t length);
167 /**< XPI NOR driver interface: Erase the whole FLASH */
168 hpm_stat_t (*erase_chip)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config);
169 /**< XPI NOR driver interface: Erase specified FLASH sector */
170 hpm_stat_t (*erase_sector)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config,
171 uint32_t addr);
172 /**< XPI NOR driver interface: Erase specified FLASH block */
173 hpm_stat_t (*erase_block)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config,
174 uint32_t addr);
175 /**< XPI NOR driver interface: Program data to specified FLASH address */
176 hpm_stat_t (*program)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config,
177 const uint32_t *src,
178 uint32_t dst_addr, uint32_t length);
179 /**< XPI NOR driver interface: read data from specified FLASH address */
180 hpm_stat_t (*read)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config, uint32_t *dst,
181 uint32_t start, uint32_t length);
182 /**< XPI NOR driver interface: program FLASH page using nonblocking interface */
183 hpm_stat_t (*page_program_nonblocking)(XPI_Type *base, xpi_xfer_channel_t channel,
184 const xpi_nor_config_t *nor_config,
185 const uint32_t *src, uint32_t dst_addr, uint32_t length);
186 /**< XPI NOR driver interface: erase FLASH sector using nonblocking interface */
187 hpm_stat_t (*erase_sector_nonblocking)(XPI_Type *base, xpi_xfer_channel_t channel,
188 const xpi_nor_config_t *nor_config,
189 uint32_t addr);
190 /**< XPI NOR driver interface: erase FLASH block using nonblocking interface */
191 hpm_stat_t (*erase_block_nonblocking)(XPI_Type *base, xpi_xfer_channel_t channel,
192 const xpi_nor_config_t *nor_config,
193 uint32_t addr);
194 /**< XPI NOR driver interface: erase the whole FLASh using nonblocking interface */
195 hpm_stat_t (*erase_chip_nonblocking)(XPI_Type *base, xpi_xfer_channel_t channel,
196 const xpi_nor_config_t *nor_config);
197
198 uint32_t reserved0[3];
199
200 /**< XPI NOR driver interface: automatically configuration flash based on the cfg_option setting */
201 hpm_stat_t (*auto_config)(XPI_Type *base, xpi_nor_config_t *nor_cfg, xpi_nor_config_option_t *cfg_option);
202
203 /**< XPI NOR driver interface: Get FLASH properties */
204 hpm_stat_t (*get_property)(XPI_Type *base, xpi_nor_config_t *nor_cfg, uint32_t property_id, uint32_t *value);
205
206 } xpi_nor_driver_interface_t;
207
208 /**
209 * @brief XPI RAM driver interface
210 */
211 typedef struct {
212 /**< XPI RAM driver interface: API version */
213 uint32_t version;
214
215 /**< Get XPI RAM configuration based on cfg_option */
216 hpm_stat_t (*get_config)(XPI_Type *base, xpi_ram_config_t *ram_cfg, xpi_ram_config_option_t *cfg_option);
217
218 /**< XPI RAM driver interface: Initialize XPI RAM */
219 hpm_stat_t (*init)(XPI_Type *base, xpi_ram_config_t *ram_cfg);
220 } xpi_ram_driver_interface_t;
221
222 /**
223 * @brief SDP API interface
224 */
225 typedef struct {
226 /**< SDP API interface: API version */
227 uint32_t version;
228 /**< SDP API interface: Initialize IP */
229 hpm_stat_t (*sdp_ip_init)(void);
230 /**< SDP API interface: Deinitialize IP */
231 hpm_stat_t (*sdp_ip_deinit)(void);
232 /**< SDP API interface: Set AES key */
233 hpm_stat_t (*aes_set_key)(sdp_aes_ctx_t *aes_ctx, const uint8_t *key, sdp_aes_key_bits_t keybits, uint32_t key_idx);
234 /**< SDP API interface: AES ECB crypto operation */
235 hpm_stat_t (*aes_crypt_ecb)(sdp_aes_ctx_t *aes_ctx, sdp_aes_op_t op, uint32_t len, const uint8_t *in, uint8_t *out);
236 /**< SDP API interface: AES CBC crypto operation */
237 hpm_stat_t (*aes_crypt_cbc)(sdp_aes_ctx_t *aes_ctx, sdp_aes_op_t op, uint32_t length, uint8_t iv[16],
238 const uint8_t *input, uint8_t *output);
239 /**< SDP API interface: AES CTR crypto operation */
240 hpm_stat_t (*aes_crypt_ctr)(sdp_aes_ctx_t *aes_ctx, uint8_t *nonce_ctr, uint8_t *input, uint8_t *output,
241 uint32_t length);
242 /**< SDP API interface: AES CCM encryption */
243 hpm_stat_t (*aes_ccm_gen_enc)(sdp_aes_ctx_t *aes_ctx, uint32_t input_len, const uint8_t *nonce, uint32_t nonce_len,
244 const uint8_t *aad, uint32_t aad_len, const uint8_t *input, uint8_t *output,
245 uint8_t *tag, uint32_t tag_len);
246 /**< SDP API interface: AES CCM Decrypt and verify */
247 hpm_stat_t (*aes_ccm_dec_verify)(sdp_aes_ctx_t *aes_ctx, uint32_t input_len, const uint8_t *nonce,
248 uint32_t nonce_len, const uint8_t *aad, uint32_t aad_len, const uint8_t *input,
249 uint8_t *output, const uint8_t *tag, uint32_t tag_len);
250 /**< SDP API interface: memcpy */
251 hpm_stat_t (*memcpy)(sdp_dma_ctx_t *dma_ctx, void *dst, const void *src, uint32_t length);
252 /**< SDP API interface: memset */
253 hpm_stat_t (*memset)(sdp_dma_ctx_t *dma_ctx, void *dst, uint8_t pattern, uint32_t length);
254 /**< SDP API interface: HASH initialization */
255 hpm_stat_t (*hash_init)(sdp_hash_ctx_t *hash_ctx, sdp_hash_alg_t alg);
256 /**< SDP API interface: HASH update */
257 hpm_stat_t (*hash_update)(sdp_hash_ctx_t *hash_ctx, const uint8_t *data, uint32_t length);
258 /**< SDP API interface: HASH finish */
259 hpm_stat_t (*hash_finish)(sdp_hash_ctx_t *hash_ctx, uint8_t *digest);
260 } sdp_driver_interface_t;
261
262 typedef struct {
263 /**< SM3 API version*/
264 uint32_t version;
265 /**< SM3 API itnerface: HASH Initialization */
266 hpm_stat_t (*init)(sm3_context_t *ctx);
267 /**< SM3 API interface: HASH update */
268 hpm_stat_t (*update)(sm3_context_t *ctx, const void *input, uint32_t len);
269 /**< SM3 API interface: HASH finish */
270 hpm_stat_t (*finalize)(sm3_context_t *ctx, uint8_t output[32]);
271 } sm3_api_interface_t;
272
273 typedef struct {
274 /**< SM4 API interface: Version */
275 uint32_t version;
276 /**< SM4 API interface: Set encryption key */
277 void (*setkey_enc)(sm4_context_t *ctx, const uint8_t key[16]);
278 /**< SM4 API interface: Set decryption key */
279 void (*setkey_dec)(sm4_context_t *ctx, const uint8_t key[16]);
280 /**< SM4 API interface: SM4 ECB operation */
281 hpm_stat_t (*crypt_ecb)(sm4_context_t *ctx, uint32_t mode, uint32_t length, const uint8_t *input, uint8_t *output);
282 /**< SM4 API interface: SM4 CBC operation */
283 hpm_stat_t (*crypt_cbc)(sm4_context_t *ctx, uint32_t mode, uint32_t length, const uint8_t iv[16],
284 const uint8_t *input, uint8_t *output);
285 /**< SM4 API interface: SM4 CTR operation */
286 hpm_stat_t (*crypt_ctr)(sm4_context_t *ctx, uint8_t *nonce_counter, const uint8_t *input,
287 uint8_t *output, uint32_t length);
288 /**< SM4 API interface: SM4 CCB encryption */
289 hpm_stat_t (*ccm_gen_enc)(sm4_context_t *ctx, uint32_t input_len, const uint8_t *iv,
290 uint32_t iv_len, const uint8_t *aad, uint32_t aad_len, const uint8_t *input,
291 uint8_t *output, uint8_t *tag, uint32_t tag_len);
292 /**< SM4 API interface: SM4 CCM Decryption and verifying */
293 hpm_stat_t (*ccm_dec_verify)(sm4_context_t *ctx, uint32_t input_len, const uint8_t *iv,
294 uint32_t iv_len, const uint8_t *aad, uint32_t aad_len, const uint8_t *input,
295 uint8_t *output, const uint8_t *tag, uint32_t tag_len);
296 } sm4_api_interface_t;
297
298 /**
299 * @brief Bootloader API table
300 */
301 typedef struct {
302 /**< Bootloader API table: version */
303 const uint32_t version;
304 /**< Bootloader API table: copyright string address */
305 const char *copyright;
306 /**< Bootloader API table: run_bootloader API */
307 hpm_stat_t (*run_bootloader)(void *arg);
308 /**< Bootloader API table: otp driver interface address */
309 const otp_driver_interface_t *otp_driver_if;
310 /**< Bootloader API table: xpi driver interface address */
311 const xpi_driver_interface_t *xpi_driver_if;
312 /**< Bootloader API table: xpi nor driver interface address */
313 const xpi_nor_driver_interface_t *xpi_nor_driver_if;
314 /**< Bootloader API table: xpi ram driver interface address */
315 const xpi_ram_driver_interface_t *xpi_ram_driver_if;
316 /**< Bootloader API table: sdp driver interface address */
317 const sdp_driver_interface_t *sdp_driver_if;
318 const uint32_t reserved0;
319 const sm3_api_interface_t *sm3_api_if; /* SM3 driver interface address */
320 const sm4_api_interface_t *sm4_api_if; /* SM4 driver itnerface address */
321 } bootloader_api_table_t;
322
323 /**< Bootloader API table Root */
324 #define ROM_API_TABLE_ROOT ((const bootloader_api_table_t *)0x2001FF00U)
325
326 #ifdef __cplusplus
327 extern "C" {
328 #endif
329
330 /***********************************************************************************************************************
331 *
332 *
333 * Enter bootloader Wrapper
334 *
335 *
336 **********************************************************************************************************************/
337
338 /**
339 * @brief Eneter specified Boot mode
340 * @param [in] ctx Enter bootloader context
341 * @retval status_invalid Invalid parameters were deteced
342 */
rom_enter_bootloader(void * ctx)343 static inline hpm_stat_t rom_enter_bootloader(void *ctx)
344 {
345 return ROM_API_TABLE_ROOT->run_bootloader(ctx);
346 }
347
348 /***********************************************************************************************************************
349 *
350 *
351 * XPI NOR Driver Wrapper
352 *
353 *
354 **********************************************************************************************************************/
355
356 /**
357 * @brief Get XPI NOR configuration via cfg_option
358 * @param [in] base XPI base address
359 * @param [out] nor_cfg XPI NOR configuration structure
360 * @param [in] cfg_option XPI NOR configuration option
361 * @return API execution status
362 */
rom_xpi_nor_get_config(XPI_Type * base,xpi_nor_config_t * nor_cfg,xpi_nor_config_option_t * cfg_option)363 static inline hpm_stat_t rom_xpi_nor_get_config(XPI_Type *base, xpi_nor_config_t *nor_cfg,
364 xpi_nor_config_option_t *cfg_option)
365 {
366 return ROM_API_TABLE_ROOT->xpi_nor_driver_if->get_config(base, nor_cfg, cfg_option);
367 }
368
369 /**
370 * @brief Initialize XPI NOR based on nor_config
371 * @param [in] base XPI base address
372 * @param[in] nor_config XPI NOR configuration
373 * @return API execution status
374 */
rom_xpi_nor_init(XPI_Type * base,xpi_nor_config_t * nor_config)375 static inline hpm_stat_t rom_xpi_nor_init(XPI_Type *base, xpi_nor_config_t *nor_config)
376 {
377 return ROM_API_TABLE_ROOT->xpi_nor_driver_if->init(base, nor_config);
378 }
379
380 /**
381 * @brief Erase specified FLASH region
382 * @param[in] base XPI base address
383 * @param[in] channel XPI transfer channel
384 * @param[in] nor_config XPI nOR configuration
385 * @param[in] start Erase address start address
386 * @param[in] length Region size to be erased
387 * @return API execution status
388 */
rom_xpi_nor_erase(XPI_Type * base,xpi_xfer_channel_t channel,const xpi_nor_config_t * nor_config,uint32_t start,uint32_t length)389 static inline hpm_stat_t rom_xpi_nor_erase(XPI_Type *base, xpi_xfer_channel_t channel,
390 const xpi_nor_config_t *nor_config,
391 uint32_t start, uint32_t length)
392 {
393 hpm_stat_t status = ROM_API_TABLE_ROOT->xpi_nor_driver_if->erase(base, channel, nor_config, start, length);
394 fencei();
395 return status;
396 }
397
398 /**
399 * @brief Erase specified FLASH sector in blocking way
400 * @param[in] base XPI base address
401 * @param[in] channel XPI transfer channel
402 * @param[in] nor_config XPI NOR configuration
403 * @param[in] start Sector address
404 * @return API execution status
405 */
rom_xpi_nor_erase_sector(XPI_Type * base,xpi_xfer_channel_t channel,const xpi_nor_config_t * nor_config,uint32_t start)406 static inline hpm_stat_t rom_xpi_nor_erase_sector(XPI_Type *base, xpi_xfer_channel_t channel,
407 const xpi_nor_config_t *nor_config,
408 uint32_t start)
409 {
410 hpm_stat_t status = ROM_API_TABLE_ROOT->xpi_nor_driver_if->erase_sector(base, channel, nor_config, start);
411 fencei();
412 return status;
413 }
414
415 /**
416 * @brief Erase specified FLASH sector in non-blocking way
417 * @param[in] base XPI base address
418 * @param[in] channel XPI transfer channel
419 * @param[in] nor_config XPI NOR configuration
420 * @param[in] start Sector address
421 * @return API execution status
422 */
rom_xpi_nor_erase_sector_nonblocking(XPI_Type * base,xpi_xfer_channel_t channel,const xpi_nor_config_t * nor_config,uint32_t start)423 static inline hpm_stat_t rom_xpi_nor_erase_sector_nonblocking(XPI_Type *base, xpi_xfer_channel_t channel,
424 const xpi_nor_config_t *nor_config,
425 uint32_t start)
426 {
427 return ROM_API_TABLE_ROOT->xpi_nor_driver_if->erase_sector_nonblocking(base, channel, nor_config, start);
428 }
429
430 /**
431 * @brief Erase specified FLASH blcok in blocking way
432 * @param[in] base XPI base address
433 * @param[in] channel XPI transfer channel
434 * @param[in] nor_config XPI NOR configuration
435 * @param[in] start Block address
436 * @return API execution status
437 */
rom_xpi_nor_erase_block(XPI_Type * base,xpi_xfer_channel_t channel,const xpi_nor_config_t * nor_config,uint32_t start)438 static inline hpm_stat_t rom_xpi_nor_erase_block(XPI_Type *base, xpi_xfer_channel_t channel,
439 const xpi_nor_config_t *nor_config,
440 uint32_t start)
441 {
442 hpm_stat_t status = ROM_API_TABLE_ROOT->xpi_nor_driver_if->erase_block(base, channel, nor_config, start);
443 fencei();
444 return status;
445 }
446
447 /**
448 * @brief Erase specified FLASH blcok in non-blocking way
449 * @param[in] base XPI base address
450 * @param[in] channel XPI transfer channel
451 * @param[in] nor_config XPI NOR configuration
452 * @param[in] start Block address
453 * @return API execution status
454 */
rom_xpi_nor_erase_block_nonblocking(XPI_Type * base,xpi_xfer_channel_t channel,const xpi_nor_config_t * nor_config,uint32_t start)455 static inline hpm_stat_t rom_xpi_nor_erase_block_nonblocking(XPI_Type *base, xpi_xfer_channel_t channel,
456 const xpi_nor_config_t *nor_config,
457 uint32_t start)
458 {
459 return ROM_API_TABLE_ROOT->xpi_nor_driver_if->erase_block_nonblocking(base, channel, nor_config, start);
460 }
461
462 /**
463 * @brief Erase the whole FLASH in blocking way
464 * @param[in] base XPI base address
465 * @param[in] channel XPI transfer channel
466 * @param[in] nor_config XPI NOR configuration
467 * @return API execution status
468 */
rom_xpi_nor_erase_chip(XPI_Type * base,xpi_xfer_channel_t channel,const xpi_nor_config_t * nor_config)469 static inline hpm_stat_t rom_xpi_nor_erase_chip(XPI_Type *base, xpi_xfer_channel_t channel,
470 const xpi_nor_config_t *nor_config)
471 {
472 return ROM_API_TABLE_ROOT->xpi_nor_driver_if->erase_chip(base, channel, nor_config);
473 }
474
475 /**
476 * @brief Erase the whole FLASH in non-blocking way
477 * @param[in] base XPI base address
478 * @param[in] channel XPI transfer channel
479 * @param[in] nor_config XPI NOR configuration
480 * @return API execution status
481 */
rom_xpi_nor_erase_chip_nonblocking(XPI_Type * base,xpi_xfer_channel_t channel,const xpi_nor_config_t * nor_config)482 static inline hpm_stat_t rom_xpi_nor_erase_chip_nonblocking(XPI_Type *base, xpi_xfer_channel_t channel,
483 const xpi_nor_config_t *nor_config)
484 {
485 hpm_stat_t status = ROM_API_TABLE_ROOT->xpi_nor_driver_if->erase_chip_nonblocking(base, channel, nor_config);
486 fencei();
487 return status;
488 }
489
490 /**
491 * @brief Program data to specified FLASH address in blocking way
492 * @param[in] base XPI base address
493 * @param[in] channel XPI transfer channel
494 * @param[in] nor_config XPI NOR configuration
495 * @param[in] src data source address
496 * @param[in] dst_addr Destination FLASH address
497 * @param[in] length length of data to be programmed
498 * @return API execution status
499 */
rom_xpi_nor_program(XPI_Type * base,xpi_xfer_channel_t channel,const xpi_nor_config_t * nor_config,const uint32_t * src,uint32_t dst_addr,uint32_t length)500 static inline hpm_stat_t rom_xpi_nor_program(XPI_Type *base, xpi_xfer_channel_t channel,
501 const xpi_nor_config_t *nor_config,
502 const uint32_t *src, uint32_t dst_addr, uint32_t length)
503 {
504 hpm_stat_t
505 status = ROM_API_TABLE_ROOT->xpi_nor_driver_if->program(base, channel, nor_config, src, dst_addr, length);
506 fencei();
507 return status;
508 }
509
510 /**
511 * @brief Page-Program data to specified FLASH address in non-blocking way
512 * @param[in] base XPI base address
513 * @param[in] channel XPI transfer channel
514 * @param[in] nor_config XPI NOR configuration
515 * @param[in] src data source address
516 * @param[in] dst_addr Destination FLASH address
517 * @param[in] length length of data to be programmed
518 * @return API execution status
519 */
rom_xpi_nor_page_program_nonblocking(XPI_Type * base,xpi_xfer_channel_t channel,const xpi_nor_config_t * nor_config,const uint32_t * src,uint32_t dst_addr,uint32_t length)520 static inline hpm_stat_t rom_xpi_nor_page_program_nonblocking(XPI_Type *base, xpi_xfer_channel_t channel,
521 const xpi_nor_config_t *nor_config, const uint32_t *src,
522 uint32_t dst_addr, uint32_t length)
523 {
524 return ROM_API_TABLE_ROOT->xpi_nor_driver_if->page_program_nonblocking(base, channel, nor_config, src, dst_addr,
525 length);
526 }
527
528 /**
529 * @brief Read data from specified FLASH address
530 * @param [in] base XPI base address
531 * @param [in] channel XPI transfer channel
532 * @param [in] nor_config XPI NOR configuration
533 * @param [in] dst Memory start address to store the data read out from FLASH
534 * @param [in] start FLASH address for data read
535 * @param [in] length length of data to be read out
536 * @return API exection address
537 */
rom_xpi_nor_read(XPI_Type * base,xpi_xfer_channel_t channel,const xpi_nor_config_t * nor_config,uint32_t * dst,uint32_t start,uint32_t length)538 static inline hpm_stat_t rom_xpi_nor_read(XPI_Type *base, xpi_xfer_channel_t channel,
539 const xpi_nor_config_t *nor_config,
540 uint32_t *dst, uint32_t start, uint32_t length)
541 {
542 return ROM_API_TABLE_ROOT->xpi_nor_driver_if->read(base, channel, nor_config, dst, start, length);
543 }
544
545 /**
546 * @brief Automatically configure XPI NOR based on cfg_option
547 * @param [in] base XPI base address
548 * @param [out] config XPI NOR configuration structure
549 * @param [in] cfg_option XPI NOR configuration option
550 * @return API execution status
551 */
rom_xpi_nor_auto_config(XPI_Type * base,xpi_nor_config_t * config,xpi_nor_config_option_t * cfg_option)552 static inline hpm_stat_t rom_xpi_nor_auto_config(XPI_Type *base, xpi_nor_config_t *config,
553 xpi_nor_config_option_t *cfg_option)
554 {
555 return ROM_API_TABLE_ROOT->xpi_nor_driver_if->auto_config(base, config, cfg_option);
556 }
557
558 /**
559 * @brief Get XPI NOR properties
560 * @param [in] base XPI base address
561 * @param [in] nor_cfg XPI NOR configuration structure
562 * @param [in] property_id
563 * @param [out] value property value retrieved by this API
564 * @return API execution status
565 */
rom_xpi_nor_get_property(XPI_Type * base,xpi_nor_config_t * nor_cfg,uint32_t property_id,uint32_t * value)566 static inline hpm_stat_t rom_xpi_nor_get_property(XPI_Type *base, xpi_nor_config_t *nor_cfg, uint32_t property_id,
567 uint32_t *value)
568 {
569 return ROM_API_TABLE_ROOT->xpi_nor_driver_if->get_property(base, nor_cfg, property_id, value);
570 }
571
572 /**
573 * @brief Return the status register value on XPI NOR FLASH
574 *
575 * @param [in] base XPI base address
576 * @param [in] channel XPI transfer channel
577 * @param [in] nor_config XPI NOR configuration
578 * @param [in] addr FLASH address offset
579 * @param [out] out_status FLASH status register value
580 * @return API execution status
581 */
rom_xpi_nor_get_status(XPI_Type * base,xpi_xfer_channel_t channel,const xpi_nor_config_t * nor_config,uint32_t addr,uint16_t * out_status)582 static inline hpm_stat_t rom_xpi_nor_get_status(XPI_Type *base, xpi_xfer_channel_t channel,
583 const xpi_nor_config_t *nor_config, uint32_t addr,
584 uint16_t *out_status)
585 {
586 return ROM_API_TABLE_ROOT->xpi_nor_driver_if->get_status(base, channel, nor_config, addr, out_status);
587 }
588
589 /**
590 * @brief Configure the XPI Address Remapping Logic
591 * @param [in] base XPI base address
592 * @param [in] start Start Address (memory mapped address)
593 * @param [in] len Size for the remapping region
594 * @param [in] offset Relative address based on parameter "start"
595 * @retval true is all parameters are valid
596 * @retval false if any parameter is invalid
597 */
598 ATTR_RAMFUNC
rom_xpi_nor_remap_config(XPI_Type * base,uint32_t start,uint32_t len,uint32_t offset)599 static inline bool rom_xpi_nor_remap_config(XPI_Type *base, uint32_t start, uint32_t len, uint32_t offset)
600 {
601 if (((base != HPM_XPI0) && (base != HPM_XPI1)) || ((start & 0xFFF) != 0) || ((len & 0xFFF) != 0)
602 || ((offset & 0xFFF) != 0)) {
603 return false;
604 }
605 static const uint8_t k_mc_xpi_remap_config[] = {
606 0x2e, 0x96, 0x23, 0x22, 0xc5, 0x42, 0x23, 0x24,
607 0xd5, 0x42, 0x93, 0xe5, 0x15, 0x00, 0x23, 0x20,
608 0xb5, 0x42, 0x05, 0x45, 0x82, 0x80,
609 };
610 typedef bool (*remap_config_cb_t)(XPI_Type *, uint32_t, uint32_t, uint32_t);
611 remap_config_cb_t cb = (remap_config_cb_t) &k_mc_xpi_remap_config;
612 bool result = cb(base, start, len, offset);
613 ROM_API_TABLE_ROOT->xpi_driver_if->software_reset(base);
614 fencei();
615 return result;
616 }
617
618 /**
619 * @brief Disable XPI Remapping logic
620 * @param [in] base XPI base address
621 */
622 ATTR_RAMFUNC
rom_xpi_nor_remap_disable(XPI_Type * base)623 static inline void rom_xpi_nor_remap_disable(XPI_Type *base)
624 {
625 static const uint8_t k_mc_xpi_remap_disable[] = {
626 0x83, 0x27, 0x05, 0x42, 0xf9, 0x9b, 0x23, 0x20,
627 0xf5, 0x42, 0x82, 0x80,
628 };
629 typedef void (*remap_disable_cb_t)(XPI_Type *);
630 remap_disable_cb_t cb = (remap_disable_cb_t) &k_mc_xpi_remap_disable;
631 cb(base);
632 fencei();
633 }
634
635 /**
636 * @brief Check whether XPI Remapping is enabled
637 * @param [in] base XPI base address
638 *
639 * @retval true Remapping logic is enabled
640 * @retval false Remapping logic is disabled
641 */
642 ATTR_RAMFUNC
rom_xpi_nor_is_remap_enabled(XPI_Type * base)643 static inline bool rom_xpi_nor_is_remap_enabled(XPI_Type *base)
644 {
645 static const uint8_t k_mc_xpi_remap_enabled[] = {
646 0x03, 0x25, 0x05, 0x42, 0x05, 0x89, 0x82, 0x80,
647 };
648 typedef bool (*remap_chk_cb_t)(XPI_Type *);
649 remap_chk_cb_t chk_cb = (remap_chk_cb_t) &k_mc_xpi_remap_enabled;
650 return chk_cb(base);
651 }
652
653 /**
654 * @brief Configure Specified EXiP Region
655 * @param [in] base XPI base address
656 * @param [in] index EXiP Region index
657 * @param [in] param ExiP Region Parameter
658 * @retval true All parameters are valid
659 * @retval false Any parameter is invalid
660 */
661 ATTR_RAMFUNC
rom_xpi_nor_exip_region_config(XPI_Type * base,uint32_t index,exip_region_param_t * param)662 static inline bool rom_xpi_nor_exip_region_config(XPI_Type *base, uint32_t index, exip_region_param_t *param)
663 {
664 if ((base != HPM_XPI0) && (base != HPM_XPI1)) {
665 return false;
666 }
667 static const uint8_t k_mc_exip_region_config[] = {
668 0x18, 0x4a, 0x9a, 0x05, 0x2e, 0x95, 0x85, 0x67,
669 0xaa, 0x97, 0x23, 0xa4, 0xe7, 0xd0, 0x4c, 0x4a,
670 0x14, 0x42, 0x58, 0x42, 0x23, 0xa6, 0xb7, 0xd0,
671 0x4c, 0x46, 0x36, 0x97, 0x13, 0x77, 0x07, 0xc0,
672 0x23, 0xa2, 0xb7, 0xd0, 0x0c, 0x46, 0x13, 0x67,
673 0x37, 0x00, 0x05, 0x45, 0x23, 0xa0, 0xb7, 0xd0,
674 0x0c, 0x4e, 0x23, 0xaa, 0xb7, 0xd0, 0x50, 0x4e,
675 0x23, 0xa8, 0xc7, 0xd0, 0x23, 0xac, 0xd7, 0xd0,
676 0x23, 0xae, 0xe7, 0xd0, 0x82, 0x80,
677 };
678 typedef void (*exip_region_config_cb_t)(XPI_Type *, uint32_t, exip_region_param_t *);
679 exip_region_config_cb_t cb = (exip_region_config_cb_t) &k_mc_exip_region_config;
680 cb(base, index, param);
681 ROM_API_TABLE_ROOT->xpi_driver_if->software_reset(base);
682 fencei();
683 return true;
684 }
685
686 /**
687 * @brief Disable EXiP Feature on specified EXiP Region
688 * @@param [in] base XPI base address
689 * @param [in] index EXiP Region index
690 */
691 ATTR_RAMFUNC
rom_xpi_nor_exip_region_disable(XPI_Type * base,uint32_t index)692 static inline void rom_xpi_nor_exip_region_disable(XPI_Type *base, uint32_t index)
693 {
694 static const uint8_t k_mc_exip_region_disable[] = {
695 0x9a, 0x05, 0x2e, 0x95, 0x85, 0x67, 0xaa, 0x97,
696 0x03, 0xa7, 0xc7, 0xd1, 0x75, 0x9b, 0x23, 0xae,
697 0xe7, 0xd0, 0x82, 0x80
698 };
699 typedef void (*exip_region_disable_cb_t)(XPI_Type *, uint32_t);
700 exip_region_disable_cb_t cb = (exip_region_disable_cb_t) &k_mc_exip_region_disable;
701 cb(base, index);
702 ROM_API_TABLE_ROOT->xpi_driver_if->software_reset(base);
703 fencei();
704 }
705
706 /**
707 * @brief Enable global EXiP logic
708 * @@param [in] base XPI base address
709 */
710 ATTR_RAMFUNC
rom_xpi_nor_exip_enable(XPI_Type * base)711 static inline void rom_xpi_nor_exip_enable(XPI_Type *base)
712 {
713 static const uint8_t k_mc_exip_enable[] = {
714 0x85, 0x67, 0x3e, 0x95, 0x83, 0x27, 0x05, 0xc0,
715 0x37, 0x07, 0x00, 0x80, 0xd9, 0x8f, 0x23, 0x20,
716 0xf5, 0xc0, 0x82, 0x80
717 };
718 typedef void (*exip_enable_cb_t)(XPI_Type *);
719 exip_enable_cb_t cb = (exip_enable_cb_t) &k_mc_exip_enable;
720 cb(base);
721 }
722
723 /**
724 * @brief Disable global EXiP logic
725 * @@param [in] base XPI base address
726 */
727 ATTR_RAMFUNC
rom_xpi_nor_exip_disable(XPI_Type * base)728 static inline void rom_xpi_nor_exip_disable(XPI_Type *base)
729 {
730 static const uint8_t k_mc_exip_disable[] = {
731 0x85, 0x67, 0x3e, 0x95, 0x83, 0x27, 0x05, 0xc0,
732 0x86, 0x07, 0x85, 0x83, 0x23, 0x20, 0xf5, 0xc0,
733 0x82, 0x80
734 };
735 typedef void (*exip_disable_cb_t)(XPI_Type *);
736 exip_disable_cb_t cb = (exip_disable_cb_t) &k_mc_exip_disable;
737 cb(base);
738 ROM_API_TABLE_ROOT->xpi_driver_if->software_reset(base);
739 fencei();
740 }
741
742 /***********************************************************************************************************************
743 *
744 *
745 * XPI RAM Driver Wrapper
746 *
747 *
748 **********************************************************************************************************************/
749 /**
750 * @brief Get XPI RAM configuration based on cfg_option
751 * @param [in] base XPI base address
752 * @param [out] ram_cfg XPI RAM configuration structure
753 * @param [in] cfg_option XPI RAM configuration option
754 * @return API execution status
755 */
rom_xpi_ram_get_config(XPI_Type * base,xpi_ram_config_t * ram_cfg,xpi_ram_config_option_t * cfg_option)756 static inline hpm_stat_t rom_xpi_ram_get_config(XPI_Type *base, xpi_ram_config_t *ram_cfg,
757 xpi_ram_config_option_t *cfg_option)
758 {
759 return ROM_API_TABLE_ROOT->xpi_ram_driver_if->get_config(base, ram_cfg, cfg_option);
760 }
761
762 /**
763 * @brief Initialize XPI RAM
764 * @param [in] base XPI base address
765 * @param [in] ram_cfg XPI ram configuration
766 * @return API execution status
767 */
rom_xpi_ram_init(XPI_Type * base,xpi_ram_config_t * ram_cfg)768 static inline hpm_stat_t rom_xpi_ram_init(XPI_Type *base, xpi_ram_config_t *ram_cfg)
769 {
770 return ROM_API_TABLE_ROOT->xpi_ram_driver_if->init(base, ram_cfg);
771 }
772
773 /***********************************************************************************************************************
774 *
775 *
776 * SDP Driver Wrapper
777 *
778 *
779 **********************************************************************************************************************/
780 /**
781 * @brief Initialize SDP IP
782 */
rom_sdp_init(void)783 static inline void rom_sdp_init(void)
784 {
785 ROM_API_TABLE_ROOT->sdp_driver_if->sdp_ip_init();
786 }
787
788 /**
789 * @brief De-initialize SDP IP
790 */
rom_sdp_deinit(void)791 static inline void rom_sdp_deinit(void)
792 {
793 ROM_API_TABLE_ROOT->sdp_driver_if->sdp_ip_deinit();
794 }
795
796 /**
797 * @brief Set AES key to SDP
798 * @param [in] aes_ctx AES context
799 * @param [in] key AES key buffer
800 * @param [in] key_bits AES key-bit option
801 * @param[in] key_idx AES key index
802 * @return API execution status
803 */
rom_sdp_aes_set_key(sdp_aes_ctx_t * aes_ctx,const uint8_t * key,sdp_aes_key_bits_t key_bits,uint32_t key_idx)804 static inline hpm_stat_t rom_sdp_aes_set_key(sdp_aes_ctx_t *aes_ctx, const uint8_t *key,
805 sdp_aes_key_bits_t key_bits, uint32_t key_idx)
806 {
807 return ROM_API_TABLE_ROOT->sdp_driver_if->aes_set_key(aes_ctx, key, key_bits, key_idx);
808 }
809
810 /**
811 * @brief SDP AES ECB crypto operation(Encrypt or Decrypt)
812 * @param [in] aes_ctx AES context
813 * @param [in] op AES operation: encrypt or decrypt
814 * @param [in] len Data length for AES encryption/decryption
815 * @param [in] in Input data
816 * @param [out] out Output data
817 * @return API execution status
818 */
rom_sdp_aes_crypt_ecb(sdp_aes_ctx_t * aes_ctx,sdp_aes_op_t op,uint32_t len,const uint8_t * in,uint8_t * out)819 static inline hpm_stat_t rom_sdp_aes_crypt_ecb(sdp_aes_ctx_t *aes_ctx, sdp_aes_op_t op,
820 uint32_t len, const uint8_t *in, uint8_t *out)
821 {
822 return ROM_API_TABLE_ROOT->sdp_driver_if->aes_crypt_ecb(aes_ctx, op, len, in, out);
823 }
824
825 /**
826 * @brief SDP AES ECB crypto operation(Encrypt or Decrypt)
827 * @param [in] aes_ctx AES context
828 * @param [in] op AES operation: encrypt or decrypt
829 * @param [in] length Data length for AES encryption/decryption
830 * @param [in] iv Initial vector/nonce
831 * @param [in] in Input data
832 * @param [out] out Output data
833 * @return API execution status
834 */
rom_sdp_aes_crypt_cbc(sdp_aes_ctx_t * aes_ctx,sdp_aes_op_t op,uint32_t length,uint8_t iv[16],const uint8_t * in,uint8_t * out)835 static inline hpm_stat_t rom_sdp_aes_crypt_cbc(sdp_aes_ctx_t *aes_ctx, sdp_aes_op_t op, uint32_t length, uint8_t iv[16],
836 const uint8_t *in, uint8_t *out)
837 {
838 return ROM_API_TABLE_ROOT->sdp_driver_if->aes_crypt_cbc(aes_ctx, op, length, iv, in, out);
839 }
840
841 /**
842 * @brief HASH initialization
843 * @param [in] hash_ctx HASH context
844 * @param [in] alg HASH algorithm
845 * @return API execution status
846 */
rom_sdp_hash_init(sdp_hash_ctx_t * hash_ctx,sdp_hash_alg_t alg)847 static inline hpm_stat_t rom_sdp_hash_init(sdp_hash_ctx_t *hash_ctx, sdp_hash_alg_t alg)
848 {
849 return ROM_API_TABLE_ROOT->sdp_driver_if->hash_init(hash_ctx, alg);
850 }
851
852 /**
853 * @brief HASH Update
854 * @param [in] hash_ctx HASH context
855 * @param [in] data Data for HASH operation
856 * @param [in] length of the data for HASH operation
857 * @return API execution status
858 */
rom_sdp_hash_update(sdp_hash_ctx_t * hash_ctx,const uint8_t * data,uint32_t length)859 static inline hpm_stat_t rom_sdp_hash_update(sdp_hash_ctx_t *hash_ctx, const uint8_t *data, uint32_t length)
860 {
861 return ROM_API_TABLE_ROOT->sdp_driver_if->hash_update(hash_ctx, data, length);
862 }
863
864 /**
865 * @brief HASH finialize
866 * @param [in] hash_ctx HASH context
867 * @param [out] digest the output digest
868 * @return API execution status
869 */
rom_sdp_hash_finish(sdp_hash_ctx_t * hash_ctx,uint8_t * digest)870 static inline hpm_stat_t rom_sdp_hash_finish(sdp_hash_ctx_t *hash_ctx, uint8_t *digest)
871 {
872 return ROM_API_TABLE_ROOT->sdp_driver_if->hash_finish(hash_ctx, digest);
873 }
874
875 /**
876 * @brief SDP memcpy operation
877 * @param [in] dma_ctx DMA context
878 * @param [out] dst Destination address for memcpy
879 * @param [in] src Source address for memcpy
880 * @param [in] length Size of data for memcpy operation
881 * @return API execution status
882 */
rom_sdp_memcpy(sdp_dma_ctx_t * dma_ctx,void * dst,const void * src,uint32_t length)883 static inline hpm_stat_t rom_sdp_memcpy(sdp_dma_ctx_t *dma_ctx, void *dst, const void *src, uint32_t length)
884 {
885 return ROM_API_TABLE_ROOT->sdp_driver_if->memcpy(dma_ctx, dst, src, length);
886 }
887
888 /**
889 * @brief SDP memset operation
890 * @param [in] dma_ctx DMA context
891 * @param [out] dst Destination address for memset
892 * @param [in] pattern pattern for memset
893 * @param [in] length Size of data for memset operation
894 * @return API execution status
895 */
rom_sdp_memset(sdp_dma_ctx_t * dma_ctx,void * dst,uint8_t pattern,uint32_t length)896 static inline hpm_stat_t rom_sdp_memset(sdp_dma_ctx_t *dma_ctx, void *dst, uint8_t pattern, uint32_t length)
897 {
898 return ROM_API_TABLE_ROOT->sdp_driver_if->memset(dma_ctx, dst, pattern, length);
899 }
900
901
902 /***********************************************************************************************************************
903 *
904 *
905 * SM3 Driver Wrapper
906 *
907 *
908 **********************************************************************************************************************/
909
910 /**
911 * @brief SM4 initialization
912 *
913 * @param [in] ctx SM3 context
914 * @return API execution status
915 */
rom_sm3_init(sm3_context_t * ctx)916 static inline hpm_stat_t rom_sm3_init(sm3_context_t *ctx)
917 {
918 return ROM_API_TABLE_ROOT->sm3_api_if->init(ctx);
919 }
920
921 /**
922 * @brief SM3 update operation
923 *
924 * @param [in,out] ctx SM3 context
925 * @param [in] input Data for SM3 calculation
926 * @param [in] len length of the data for SM3 calculation
927 * @return API execution status
928 */
rom_sm3_update(sm3_context_t * ctx,const void * input,uint32_t len)929 static inline hpm_stat_t rom_sm3_update(sm3_context_t *ctx, const void *input, uint32_t len)
930 {
931 return ROM_API_TABLE_ROOT->sm3_api_if->update(ctx, input, len);
932 }
933
934 /**
935 * @brief SM3 finalize
936 * Return the computing SM3 digest
937 *
938 * @param [in] ctx SM3 context
939 * @param [out] output SM3 digest calculated by the above API
940 * @return API execution status
941 */
rom_sm3_finalize(sm3_context_t * ctx,uint8_t output[32])942 static inline hpm_stat_t rom_sm3_finalize(sm3_context_t *ctx, uint8_t output[32])
943 {
944 return ROM_API_TABLE_ROOT->sm3_api_if->finalize(ctx, output);
945 }
946
947 /***********************************************************************************************************************
948 *
949 *
950 * SM4 Driver Wrapper
951 *
952 *
953 **********************************************************************************************************************/
954 /**
955 * @brief Set SM4 encryption key
956 *
957 * @param [in] ctx SM4 context
958 * @param [in] key SM4 encryption key
959 */
rom_sm4_setkey_enc(sm4_context_t * ctx,const uint8_t key[16])960 static inline void rom_sm4_setkey_enc(sm4_context_t *ctx, const uint8_t key[16])
961 {
962 ROM_API_TABLE_ROOT->sm4_api_if->setkey_enc(ctx, key);
963 }
964
965 /**
966 * @brief Set SM4 decryption key
967 *
968 * @param [in] ctx SM4 context
969 * @param [in] key SM4 decryption key
970 */
rom_sm4_setkey_dec(sm4_context_t * ctx,const uint8_t key[16])971 static inline void rom_sm4_setkey_dec(sm4_context_t *ctx, const uint8_t key[16])
972 {
973 ROM_API_TABLE_ROOT->sm4_api_if->setkey_dec(ctx, key);
974 }
975
976 /**
977 * @brief SM4 ECB crypto operation(Encrypt or Decrypt)
978 * @param [in] ctx SM4 context
979 * @param [in] mode SM4 operation: 1 - ENCRYPT, 0 - DECRYPT
980 * @param [in] length Data length for SM4 encryption/decryption
981 * @param [in] input Input data
982 * @param [out] output Output data
983 * @return API execution status
984 */
rom_sm4_crypt_ecb(sm4_context_t * ctx,uint32_t mode,uint32_t length,const uint8_t * input,uint8_t * output)985 static inline hpm_stat_t rom_sm4_crypt_ecb(sm4_context_t *ctx, uint32_t mode, uint32_t length, const uint8_t *input,
986 uint8_t *output)
987 {
988 return ROM_API_TABLE_ROOT->sm4_api_if->crypt_ecb(ctx, mode, length, input, output);
989 }
990
991 /**
992 * @brief SM4 CBC crypto operation(Encrypt or Decrypt)
993 * @param [in] ctx SM4 context
994 * @param [in] mode SM4 operation: 1 - ENCRYPT, 0 - DECRYPT
995 * @param [in] length Data length for SM4 encryption/decryption
996 * @param [in] input Input data
997 * @param [out] output Output data
998 * @return API execution status
999 */
rom_sm4_crypt_cbc(sm4_context_t * ctx,uint32_t mode,uint32_t length,const uint8_t iv[16],const uint8_t * input,uint8_t * output)1000 static inline hpm_stat_t rom_sm4_crypt_cbc(sm4_context_t *ctx, uint32_t mode, uint32_t length, const uint8_t iv[16],
1001 const uint8_t *input, uint8_t *output)
1002 {
1003 return ROM_API_TABLE_ROOT->sm4_api_if->crypt_cbc(ctx, mode, length, iv, input, output);
1004 }
1005
1006 #ifdef __cplusplus
1007 }
1008 #endif
1009
1010 /**
1011 * @}
1012 */
1013
1014
1015 #endif /* HPM_ROMAPI_H */
1016