1 /* 2 * Copyright (c) 2021-2023 HPMicro 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 */ 7 8 9 #ifndef HPM_SYSCTL_H 10 #define HPM_SYSCTL_H 11 12 typedef struct { 13 __RW uint32_t RESOURCE[353]; /* 0x0 - 0x580: Resource control register for cpu0_core */ 14 __R uint8_t RESERVED0[636]; /* 0x584 - 0x7FF: Reserved */ 15 struct { 16 __RW uint32_t VALUE; /* 0x800: Group setting */ 17 __RW uint32_t SET; /* 0x804: Group setting */ 18 __RW uint32_t CLEAR; /* 0x808: Group setting */ 19 __RW uint32_t TOGGLE; /* 0x80C: Group setting */ 20 } GROUP0[4]; 21 __R uint8_t RESERVED1[192]; /* 0x840 - 0x8FF: Reserved */ 22 struct { 23 __RW uint32_t VALUE; /* 0x900: Affiliate of Group */ 24 __RW uint32_t SET; /* 0x904: Affiliate of Group */ 25 __RW uint32_t CLEAR; /* 0x908: Affiliate of Group */ 26 __RW uint32_t TOGGLE; /* 0x90C: Affiliate of Group */ 27 } AFFILIATE[1]; 28 __R uint8_t RESERVED2[16]; /* 0x910 - 0x91F: Reserved */ 29 struct { 30 __RW uint32_t VALUE; /* 0x920: Retention Contol */ 31 __RW uint32_t SET; /* 0x924: Retention Contol */ 32 __RW uint32_t CLEAR; /* 0x928: Retention Contol */ 33 __RW uint32_t TOGGLE; /* 0x92C: Retention Contol */ 34 } RETENTION[1]; 35 __R uint8_t RESERVED3[1744]; /* 0x930 - 0xFFF: Reserved */ 36 struct { 37 __RW uint32_t STATUS; /* 0x1000: Power Setting */ 38 __RW uint32_t LF_WAIT; /* 0x1004: Power Setting */ 39 __R uint8_t RESERVED0[4]; /* 0x1008 - 0x100B: Reserved */ 40 __RW uint32_t OFF_WAIT; /* 0x100C: Power Setting */ 41 } POWER[3]; 42 __R uint8_t RESERVED4[976]; /* 0x1030 - 0x13FF: Reserved */ 43 struct { 44 __RW uint32_t CONTROL; /* 0x1400: Reset Setting */ 45 __RW uint32_t CONFIG; /* 0x1404: Reset Setting */ 46 __R uint8_t RESERVED0[4]; /* 0x1408 - 0x140B: Reserved */ 47 __RW uint32_t COUNTER; /* 0x140C: Reset Setting */ 48 } RESET[5]; 49 __R uint8_t RESERVED5[944]; /* 0x1450 - 0x17FF: Reserved */ 50 __RW uint32_t CLOCK[69]; /* 0x1800 - 0x1910: Clock setting */ 51 __R uint8_t RESERVED6[748]; /* 0x1914 - 0x1BFF: Reserved */ 52 __RW uint32_t ADCCLK[2]; /* 0x1C00 - 0x1C04: Clock setting */ 53 __RW uint32_t I2SCLK[4]; /* 0x1C08 - 0x1C14: Clock setting */ 54 __R uint8_t RESERVED7[1000]; /* 0x1C18 - 0x1FFF: Reserved */ 55 __RW uint32_t GLOBAL00; /* 0x2000: Clock senario */ 56 __R uint8_t RESERVED8[1020]; /* 0x2004 - 0x23FF: Reserved */ 57 struct { 58 __RW uint32_t CONTROL; /* 0x2400: Clock measure and monitor control */ 59 __R uint32_t CURRENT; /* 0x2404: Clock measure result */ 60 __RW uint32_t LOW_LIMIT; /* 0x2408: Clock lower limit */ 61 __RW uint32_t HIGH_LIMIT; /* 0x240C: Clock upper limit */ 62 __R uint8_t RESERVED0[16]; /* 0x2410 - 0x241F: Reserved */ 63 } MONITOR[4]; 64 __R uint8_t RESERVED9[896]; /* 0x2480 - 0x27FF: Reserved */ 65 struct { 66 __RW uint32_t LP; /* 0x2800: CPU0 LP control */ 67 __RW uint32_t LOCK; /* 0x2804: CPU0 Lock GPR */ 68 __RW uint32_t GPR[14]; /* 0x2808 - 0x283C: CPU0 GPR0 */ 69 __R uint32_t WAKEUP_STATUS[4]; /* 0x2840 - 0x284C: CPU0 wakeup IRQ status */ 70 __R uint8_t RESERVED0[48]; /* 0x2850 - 0x287F: Reserved */ 71 __RW uint32_t WAKEUP_ENABLE[4]; /* 0x2880 - 0x288C: CPU0 wakeup IRQ enable */ 72 __R uint8_t RESERVED1[880]; /* 0x2890 - 0x2BFF: Reserved */ 73 } CPU[1]; 74 } SYSCTL_Type; 75 76 77 /* Bitfield definition for register array: RESOURCE */ 78 /* 79 * GLB_BUSY (RO) 80 * 81 * global busy 82 * 0: no changes pending to any nodes 83 * 1: any of nodes is changing status 84 */ 85 #define SYSCTL_RESOURCE_GLB_BUSY_MASK (0x80000000UL) 86 #define SYSCTL_RESOURCE_GLB_BUSY_SHIFT (31U) 87 #define SYSCTL_RESOURCE_GLB_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_RESOURCE_GLB_BUSY_MASK) >> SYSCTL_RESOURCE_GLB_BUSY_SHIFT) 88 89 /* 90 * LOC_BUSY (RO) 91 * 92 * local busy 93 * 0: no change is pending for current node 94 * 1: current node is changing status 95 */ 96 #define SYSCTL_RESOURCE_LOC_BUSY_MASK (0x40000000UL) 97 #define SYSCTL_RESOURCE_LOC_BUSY_SHIFT (30U) 98 #define SYSCTL_RESOURCE_LOC_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_RESOURCE_LOC_BUSY_MASK) >> SYSCTL_RESOURCE_LOC_BUSY_SHIFT) 99 100 /* 101 * MODE (RW) 102 * 103 * resource work mode 104 * 0:auto turn on and off as system required(recommended) 105 * 1:always on 106 * 2:always off 107 * 3:reserved 108 */ 109 #define SYSCTL_RESOURCE_MODE_MASK (0x3U) 110 #define SYSCTL_RESOURCE_MODE_SHIFT (0U) 111 #define SYSCTL_RESOURCE_MODE_SET(x) (((uint32_t)(x) << SYSCTL_RESOURCE_MODE_SHIFT) & SYSCTL_RESOURCE_MODE_MASK) 112 #define SYSCTL_RESOURCE_MODE_GET(x) (((uint32_t)(x) & SYSCTL_RESOURCE_MODE_MASK) >> SYSCTL_RESOURCE_MODE_SHIFT) 113 114 /* Bitfield definition for register of struct array GROUP0: VALUE */ 115 /* 116 * LINK (RW) 117 * 118 * denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral 119 * 0: peripheral is not needed 120 * 1: periphera is needed 121 */ 122 #define SYSCTL_GROUP0_VALUE_LINK_MASK (0xFFFFFFFFUL) 123 #define SYSCTL_GROUP0_VALUE_LINK_SHIFT (0U) 124 #define SYSCTL_GROUP0_VALUE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_GROUP0_VALUE_LINK_SHIFT) & SYSCTL_GROUP0_VALUE_LINK_MASK) 125 #define SYSCTL_GROUP0_VALUE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_GROUP0_VALUE_LINK_MASK) >> SYSCTL_GROUP0_VALUE_LINK_SHIFT) 126 127 /* Bitfield definition for register of struct array GROUP0: SET */ 128 /* 129 * LINK (RW) 130 * 131 * denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral 132 * 0: no effect 133 * 1: add periphera into this group，periphera is needed 134 */ 135 #define SYSCTL_GROUP0_SET_LINK_MASK (0xFFFFFFFFUL) 136 #define SYSCTL_GROUP0_SET_LINK_SHIFT (0U) 137 #define SYSCTL_GROUP0_SET_LINK_SET(x) (((uint32_t)(x) << SYSCTL_GROUP0_SET_LINK_SHIFT) & SYSCTL_GROUP0_SET_LINK_MASK) 138 #define SYSCTL_GROUP0_SET_LINK_GET(x) (((uint32_t)(x) & SYSCTL_GROUP0_SET_LINK_MASK) >> SYSCTL_GROUP0_SET_LINK_SHIFT) 139 140 /* Bitfield definition for register of struct array GROUP0: CLEAR */ 141 /* 142 * LINK (RW) 143 * 144 * denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral 145 * 0: no effect 146 * 1: delete periphera in this group，periphera is not needed 147 */ 148 #define SYSCTL_GROUP0_CLEAR_LINK_MASK (0xFFFFFFFFUL) 149 #define SYSCTL_GROUP0_CLEAR_LINK_SHIFT (0U) 150 #define SYSCTL_GROUP0_CLEAR_LINK_SET(x) (((uint32_t)(x) << SYSCTL_GROUP0_CLEAR_LINK_SHIFT) & SYSCTL_GROUP0_CLEAR_LINK_MASK) 151 #define SYSCTL_GROUP0_CLEAR_LINK_GET(x) (((uint32_t)(x) & SYSCTL_GROUP0_CLEAR_LINK_MASK) >> SYSCTL_GROUP0_CLEAR_LINK_SHIFT) 152 153 /* Bitfield definition for register of struct array GROUP0: TOGGLE */ 154 /* 155 * LINK (RW) 156 * 157 * denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral 158 * 0: no effect 159 * 1: toggle the result that whether periphera is needed before 160 */ 161 #define SYSCTL_GROUP0_TOGGLE_LINK_MASK (0xFFFFFFFFUL) 162 #define SYSCTL_GROUP0_TOGGLE_LINK_SHIFT (0U) 163 #define SYSCTL_GROUP0_TOGGLE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_GROUP0_TOGGLE_LINK_SHIFT) & SYSCTL_GROUP0_TOGGLE_LINK_MASK) 164 #define SYSCTL_GROUP0_TOGGLE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_GROUP0_TOGGLE_LINK_MASK) >> SYSCTL_GROUP0_TOGGLE_LINK_SHIFT) 165 166 /* Bitfield definition for register of struct array AFFILIATE: VALUE */ 167 /* 168 * LINK (RW) 169 * 170 * Affiliate groups of cpu0, each bit represents a group 171 * bit0: cpu0 depends on group0 172 * bit1: cpu0 depends on group1 173 * bit2: cpu0 depends on group2 174 * bit3: cpu0 depends on group3 175 */ 176 #define SYSCTL_AFFILIATE_VALUE_LINK_MASK (0xFU) 177 #define SYSCTL_AFFILIATE_VALUE_LINK_SHIFT (0U) 178 #define SYSCTL_AFFILIATE_VALUE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_AFFILIATE_VALUE_LINK_SHIFT) & SYSCTL_AFFILIATE_VALUE_LINK_MASK) 179 #define SYSCTL_AFFILIATE_VALUE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_AFFILIATE_VALUE_LINK_MASK) >> SYSCTL_AFFILIATE_VALUE_LINK_SHIFT) 180 181 /* Bitfield definition for register of struct array AFFILIATE: SET */ 182 /* 183 * LINK (RW) 184 * 185 * Affiliate groups of cpu0，each bit represents a group 186 * 0: no effect 187 * 1: the group is assigned to CPU0 188 */ 189 #define SYSCTL_AFFILIATE_SET_LINK_MASK (0xFU) 190 #define SYSCTL_AFFILIATE_SET_LINK_SHIFT (0U) 191 #define SYSCTL_AFFILIATE_SET_LINK_SET(x) (((uint32_t)(x) << SYSCTL_AFFILIATE_SET_LINK_SHIFT) & SYSCTL_AFFILIATE_SET_LINK_MASK) 192 #define SYSCTL_AFFILIATE_SET_LINK_GET(x) (((uint32_t)(x) & SYSCTL_AFFILIATE_SET_LINK_MASK) >> SYSCTL_AFFILIATE_SET_LINK_SHIFT) 193 194 /* Bitfield definition for register of struct array AFFILIATE: CLEAR */ 195 /* 196 * LINK (RW) 197 * 198 * Affiliate groups of cpu0, each bit represents a group 199 * 0: no effect 200 * 1: the group is not assigned to CPU0 201 */ 202 #define SYSCTL_AFFILIATE_CLEAR_LINK_MASK (0xFU) 203 #define SYSCTL_AFFILIATE_CLEAR_LINK_SHIFT (0U) 204 #define SYSCTL_AFFILIATE_CLEAR_LINK_SET(x) (((uint32_t)(x) << SYSCTL_AFFILIATE_CLEAR_LINK_SHIFT) & SYSCTL_AFFILIATE_CLEAR_LINK_MASK) 205 #define SYSCTL_AFFILIATE_CLEAR_LINK_GET(x) (((uint32_t)(x) & SYSCTL_AFFILIATE_CLEAR_LINK_MASK) >> SYSCTL_AFFILIATE_CLEAR_LINK_SHIFT) 206 207 /* Bitfield definition for register of struct array AFFILIATE: TOGGLE */ 208 /* 209 * LINK (RW) 210 * 211 * Affiliate groups of cpu0, each bit represents a group 212 * 0: no effect 213 * 1: toggle the result that whether the group is assigned to CPU0 before 214 */ 215 #define SYSCTL_AFFILIATE_TOGGLE_LINK_MASK (0xFU) 216 #define SYSCTL_AFFILIATE_TOGGLE_LINK_SHIFT (0U) 217 #define SYSCTL_AFFILIATE_TOGGLE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_AFFILIATE_TOGGLE_LINK_SHIFT) & SYSCTL_AFFILIATE_TOGGLE_LINK_MASK) 218 #define SYSCTL_AFFILIATE_TOGGLE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_AFFILIATE_TOGGLE_LINK_MASK) >> SYSCTL_AFFILIATE_TOGGLE_LINK_SHIFT) 219 220 /* Bitfield definition for register of struct array RETENTION: VALUE */ 221 /* 222 * LINK (RW) 223 * 224 * retention setting while CPU0 enter stop mode, each bit represents a resource 225 * bit00: soc_mem is kept on while cpu0 stop 226 * bit01: soc_ctx is kept on while cpu0 stop 227 * bit02: cpu0_mem is kept on while cpu0 stop 228 * bit03: cpu0_ctx is kept on while cpu0 stop 229 * bit04: con_ctx is kept on while cpu0 stop 230 * bit05: vis_mem is kept on while cpu0 stop 231 * bit06: vis_ctx is kept on while cpu0 stop 232 * bit07: gpu_mem is kept on while cpu0 stop 233 * bit08: gpu_ctx is kept on while cpu0 stop 234 * bit09: xtal_hold is kept on while cpu0 stop 235 * bit10: pll0_hold is kept on while cpu0 stop 236 * bit11: pll1_hold is kept on while cpu0 stop 237 * bit12: pll2_hold is kept on while cpu0 stop 238 * bit13: pll3 is kept on while cpu0 stop 239 * bit14: pll4 is kept on while cpu0 stop 240 */ 241 #define SYSCTL_RETENTION_VALUE_LINK_MASK (0x7FFFU) 242 #define SYSCTL_RETENTION_VALUE_LINK_SHIFT (0U) 243 #define SYSCTL_RETENTION_VALUE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_RETENTION_VALUE_LINK_SHIFT) & SYSCTL_RETENTION_VALUE_LINK_MASK) 244 #define SYSCTL_RETENTION_VALUE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_RETENTION_VALUE_LINK_MASK) >> SYSCTL_RETENTION_VALUE_LINK_SHIFT) 245 246 /* Bitfield definition for register of struct array RETENTION: SET */ 247 /* 248 * LINK (RW) 249 * 250 * retention setting while CPU0 enter stop mode, each bit represents a resource 251 * 0: no effect 252 * 1: keep 253 */ 254 #define SYSCTL_RETENTION_SET_LINK_MASK (0x7FFFU) 255 #define SYSCTL_RETENTION_SET_LINK_SHIFT (0U) 256 #define SYSCTL_RETENTION_SET_LINK_SET(x) (((uint32_t)(x) << SYSCTL_RETENTION_SET_LINK_SHIFT) & SYSCTL_RETENTION_SET_LINK_MASK) 257 #define SYSCTL_RETENTION_SET_LINK_GET(x) (((uint32_t)(x) & SYSCTL_RETENTION_SET_LINK_MASK) >> SYSCTL_RETENTION_SET_LINK_SHIFT) 258 259 /* Bitfield definition for register of struct array RETENTION: CLEAR */ 260 /* 261 * LINK (RW) 262 * 263 * retention setting while CPU0 enter stop mode, each bit represents a resource 264 * 0: no effect 265 * 1: no keep 266 */ 267 #define SYSCTL_RETENTION_CLEAR_LINK_MASK (0x7FFFU) 268 #define SYSCTL_RETENTION_CLEAR_LINK_SHIFT (0U) 269 #define SYSCTL_RETENTION_CLEAR_LINK_SET(x) (((uint32_t)(x) << SYSCTL_RETENTION_CLEAR_LINK_SHIFT) & SYSCTL_RETENTION_CLEAR_LINK_MASK) 270 #define SYSCTL_RETENTION_CLEAR_LINK_GET(x) (((uint32_t)(x) & SYSCTL_RETENTION_CLEAR_LINK_MASK) >> SYSCTL_RETENTION_CLEAR_LINK_SHIFT) 271 272 /* Bitfield definition for register of struct array RETENTION: TOGGLE */ 273 /* 274 * LINK (RW) 275 * 276 * retention setting while CPU0 enter stop mode, each bit represents a resource 277 * 0: no effect 278 * 1: toggle the result that whether the resource is kept on while CPU0 stop before 279 */ 280 #define SYSCTL_RETENTION_TOGGLE_LINK_MASK (0x7FFFU) 281 #define SYSCTL_RETENTION_TOGGLE_LINK_SHIFT (0U) 282 #define SYSCTL_RETENTION_TOGGLE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_RETENTION_TOGGLE_LINK_SHIFT) & SYSCTL_RETENTION_TOGGLE_LINK_MASK) 283 #define SYSCTL_RETENTION_TOGGLE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_RETENTION_TOGGLE_LINK_MASK) >> SYSCTL_RETENTION_TOGGLE_LINK_SHIFT) 284 285 /* Bitfield definition for register of struct array POWER: STATUS */ 286 /* 287 * FLAG (RW) 288 * 289 * flag represents power cycle happened from last clear of this bit 290 * 0: power domain did not edurance power cycle since last clear of this bit 291 * 1: power domain enduranced power cycle since last clear of this bit 292 */ 293 #define SYSCTL_POWER_STATUS_FLAG_MASK (0x80000000UL) 294 #define SYSCTL_POWER_STATUS_FLAG_SHIFT (31U) 295 #define SYSCTL_POWER_STATUS_FLAG_SET(x) (((uint32_t)(x) << SYSCTL_POWER_STATUS_FLAG_SHIFT) & SYSCTL_POWER_STATUS_FLAG_MASK) 296 #define SYSCTL_POWER_STATUS_FLAG_GET(x) (((uint32_t)(x) & SYSCTL_POWER_STATUS_FLAG_MASK) >> SYSCTL_POWER_STATUS_FLAG_SHIFT) 297 298 /* 299 * FLAG_WAKE (RW) 300 * 301 * flag represents wakeup power cycle happened from last clear of this bit 302 * 0: power domain did not edurance wakeup power cycle since last clear of this bit 303 * 1: power domain enduranced wakeup power cycle since last clear of this bit 304 */ 305 #define SYSCTL_POWER_STATUS_FLAG_WAKE_MASK (0x40000000UL) 306 #define SYSCTL_POWER_STATUS_FLAG_WAKE_SHIFT (30U) 307 #define SYSCTL_POWER_STATUS_FLAG_WAKE_SET(x) (((uint32_t)(x) << SYSCTL_POWER_STATUS_FLAG_WAKE_SHIFT) & SYSCTL_POWER_STATUS_FLAG_WAKE_MASK) 308 #define SYSCTL_POWER_STATUS_FLAG_WAKE_GET(x) (((uint32_t)(x) & SYSCTL_POWER_STATUS_FLAG_WAKE_MASK) >> SYSCTL_POWER_STATUS_FLAG_WAKE_SHIFT) 309 310 /* 311 * LF_DISABLE (RO) 312 * 313 * low fanout power switch disable 314 * 0: low fanout power switches are turned on 315 * 1: low fanout power switches are truned off 316 */ 317 #define SYSCTL_POWER_STATUS_LF_DISABLE_MASK (0x1000U) 318 #define SYSCTL_POWER_STATUS_LF_DISABLE_SHIFT (12U) 319 #define SYSCTL_POWER_STATUS_LF_DISABLE_GET(x) (((uint32_t)(x) & SYSCTL_POWER_STATUS_LF_DISABLE_MASK) >> SYSCTL_POWER_STATUS_LF_DISABLE_SHIFT) 320 321 /* 322 * LF_ACK (RO) 323 * 324 * low fanout power switch feedback 325 * 0: low fanout power switches are turned on 326 * 1: low fanout power switches are truned off 327 */ 328 #define SYSCTL_POWER_STATUS_LF_ACK_MASK (0x100U) 329 #define SYSCTL_POWER_STATUS_LF_ACK_SHIFT (8U) 330 #define SYSCTL_POWER_STATUS_LF_ACK_GET(x) (((uint32_t)(x) & SYSCTL_POWER_STATUS_LF_ACK_MASK) >> SYSCTL_POWER_STATUS_LF_ACK_SHIFT) 331 332 /* Bitfield definition for register of struct array POWER: LF_WAIT */ 333 /* 334 * WAIT (RW) 335 * 336 * wait time for low fan out power switch turn on, default value is 255 337 * 0: 0 clock cycle 338 * 1: 1 clock cycles 339 * . . . 340 * clock cycles count on 24MHz 341 */ 342 #define SYSCTL_POWER_LF_WAIT_WAIT_MASK (0xFFFFFUL) 343 #define SYSCTL_POWER_LF_WAIT_WAIT_SHIFT (0U) 344 #define SYSCTL_POWER_LF_WAIT_WAIT_SET(x) (((uint32_t)(x) << SYSCTL_POWER_LF_WAIT_WAIT_SHIFT) & SYSCTL_POWER_LF_WAIT_WAIT_MASK) 345 #define SYSCTL_POWER_LF_WAIT_WAIT_GET(x) (((uint32_t)(x) & SYSCTL_POWER_LF_WAIT_WAIT_MASK) >> SYSCTL_POWER_LF_WAIT_WAIT_SHIFT) 346 347 /* Bitfield definition for register of struct array POWER: OFF_WAIT */ 348 /* 349 * WAIT (RW) 350 * 351 * wait time for power switch turn off, default value is 15 352 * 0: 0 clock cycle 353 * 1: 1 clock cycles 354 * . . . 355 * clock cycles count on 24MHz 356 */ 357 #define SYSCTL_POWER_OFF_WAIT_WAIT_MASK (0xFFFFFUL) 358 #define SYSCTL_POWER_OFF_WAIT_WAIT_SHIFT (0U) 359 #define SYSCTL_POWER_OFF_WAIT_WAIT_SET(x) (((uint32_t)(x) << SYSCTL_POWER_OFF_WAIT_WAIT_SHIFT) & SYSCTL_POWER_OFF_WAIT_WAIT_MASK) 360 #define SYSCTL_POWER_OFF_WAIT_WAIT_GET(x) (((uint32_t)(x) & SYSCTL_POWER_OFF_WAIT_WAIT_MASK) >> SYSCTL_POWER_OFF_WAIT_WAIT_SHIFT) 361 362 /* Bitfield definition for register of struct array RESET: CONTROL */ 363 /* 364 * FLAG (RW) 365 * 366 * flag represents reset happened from last clear of this bit 367 * 0: domain did not edurance reset cycle since last clear of this bit 368 * 1: domain enduranced reset cycle since last clear of this bit 369 */ 370 #define SYSCTL_RESET_CONTROL_FLAG_MASK (0x80000000UL) 371 #define SYSCTL_RESET_CONTROL_FLAG_SHIFT (31U) 372 #define SYSCTL_RESET_CONTROL_FLAG_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONTROL_FLAG_SHIFT) & SYSCTL_RESET_CONTROL_FLAG_MASK) 373 #define SYSCTL_RESET_CONTROL_FLAG_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONTROL_FLAG_MASK) >> SYSCTL_RESET_CONTROL_FLAG_SHIFT) 374 375 /* 376 * FLAG_WAKE (RW) 377 * 378 * flag represents wakeup reset happened from last clear of this bit 379 * 0: domain did not edurance wakeup reset cycle since last clear of this bit 380 * 1: domain enduranced wakeup reset cycle since last clear of this bit 381 */ 382 #define SYSCTL_RESET_CONTROL_FLAG_WAKE_MASK (0x40000000UL) 383 #define SYSCTL_RESET_CONTROL_FLAG_WAKE_SHIFT (30U) 384 #define SYSCTL_RESET_CONTROL_FLAG_WAKE_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONTROL_FLAG_WAKE_SHIFT) & SYSCTL_RESET_CONTROL_FLAG_WAKE_MASK) 385 #define SYSCTL_RESET_CONTROL_FLAG_WAKE_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONTROL_FLAG_WAKE_MASK) >> SYSCTL_RESET_CONTROL_FLAG_WAKE_SHIFT) 386 387 /* 388 * HOLD (RW) 389 * 390 * perform reset and hold in reset, until ths bit cleared by software 391 * 0: reset is released for function 392 * 1: reset is assert and hold 393 */ 394 #define SYSCTL_RESET_CONTROL_HOLD_MASK (0x10U) 395 #define SYSCTL_RESET_CONTROL_HOLD_SHIFT (4U) 396 #define SYSCTL_RESET_CONTROL_HOLD_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONTROL_HOLD_SHIFT) & SYSCTL_RESET_CONTROL_HOLD_MASK) 397 #define SYSCTL_RESET_CONTROL_HOLD_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONTROL_HOLD_MASK) >> SYSCTL_RESET_CONTROL_HOLD_SHIFT) 398 399 /* 400 * RESET (RW) 401 * 402 * perform reset and release imediately 403 * 0: reset is released 404 * 1 reset is asserted and will release automaticly 405 */ 406 #define SYSCTL_RESET_CONTROL_RESET_MASK (0x1U) 407 #define SYSCTL_RESET_CONTROL_RESET_SHIFT (0U) 408 #define SYSCTL_RESET_CONTROL_RESET_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONTROL_RESET_SHIFT) & SYSCTL_RESET_CONTROL_RESET_MASK) 409 #define SYSCTL_RESET_CONTROL_RESET_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONTROL_RESET_MASK) >> SYSCTL_RESET_CONTROL_RESET_SHIFT) 410 411 /* Bitfield definition for register of struct array RESET: CONFIG */ 412 /* 413 * PRE_WAIT (RW) 414 * 415 * wait cycle numbers before assert reset 416 * 0: wait 0 cycle 417 * 1: wait 1 cycles 418 * . . . 419 * Note, clock cycle is base on 24M 420 */ 421 #define SYSCTL_RESET_CONFIG_PRE_WAIT_MASK (0xFF0000UL) 422 #define SYSCTL_RESET_CONFIG_PRE_WAIT_SHIFT (16U) 423 #define SYSCTL_RESET_CONFIG_PRE_WAIT_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONFIG_PRE_WAIT_SHIFT) & SYSCTL_RESET_CONFIG_PRE_WAIT_MASK) 424 #define SYSCTL_RESET_CONFIG_PRE_WAIT_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONFIG_PRE_WAIT_MASK) >> SYSCTL_RESET_CONFIG_PRE_WAIT_SHIFT) 425 426 /* 427 * RSTCLK_NUM (RW) 428 * 429 * reset clock number(must be even number) 430 * 0: 0 cycle 431 * 1: 0 cycles 432 * 2: 2 cycles 433 * 3: 2 cycles 434 * . . . 435 * Note, clock cycle is base on 24M 436 */ 437 #define SYSCTL_RESET_CONFIG_RSTCLK_NUM_MASK (0xFF00U) 438 #define SYSCTL_RESET_CONFIG_RSTCLK_NUM_SHIFT (8U) 439 #define SYSCTL_RESET_CONFIG_RSTCLK_NUM_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONFIG_RSTCLK_NUM_SHIFT) & SYSCTL_RESET_CONFIG_RSTCLK_NUM_MASK) 440 #define SYSCTL_RESET_CONFIG_RSTCLK_NUM_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONFIG_RSTCLK_NUM_MASK) >> SYSCTL_RESET_CONFIG_RSTCLK_NUM_SHIFT) 441 442 /* 443 * POST_WAIT (RW) 444 * 445 * time guard band for reset release 446 * 0: wait 0 cycle 447 * 1: wait 1 cycles 448 * . . . 449 * Note, clock cycle is base on 24M 450 */ 451 #define SYSCTL_RESET_CONFIG_POST_WAIT_MASK (0xFFU) 452 #define SYSCTL_RESET_CONFIG_POST_WAIT_SHIFT (0U) 453 #define SYSCTL_RESET_CONFIG_POST_WAIT_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONFIG_POST_WAIT_SHIFT) & SYSCTL_RESET_CONFIG_POST_WAIT_MASK) 454 #define SYSCTL_RESET_CONFIG_POST_WAIT_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONFIG_POST_WAIT_MASK) >> SYSCTL_RESET_CONFIG_POST_WAIT_SHIFT) 455 456 /* Bitfield definition for register of struct array RESET: COUNTER */ 457 /* 458 * COUNTER (RW) 459 * 460 * self clear trigger counter, reset triggered when counter value is 1, write 0 will cancel reset 461 * 0: wait 0 cycle 462 * 1: wait 1 cycles 463 * . . . 464 * Note, clock cycle is base on 24M 465 */ 466 #define SYSCTL_RESET_COUNTER_COUNTER_MASK (0xFFFFFUL) 467 #define SYSCTL_RESET_COUNTER_COUNTER_SHIFT (0U) 468 #define SYSCTL_RESET_COUNTER_COUNTER_SET(x) (((uint32_t)(x) << SYSCTL_RESET_COUNTER_COUNTER_SHIFT) & SYSCTL_RESET_COUNTER_COUNTER_MASK) 469 #define SYSCTL_RESET_COUNTER_COUNTER_GET(x) (((uint32_t)(x) & SYSCTL_RESET_COUNTER_COUNTER_MASK) >> SYSCTL_RESET_COUNTER_COUNTER_SHIFT) 470 471 /* Bitfield definition for register array: CLOCK */ 472 /* 473 * GLB_BUSY (RO) 474 * 475 * global busy 476 * 0: no changes pending to any clock 477 * 1: any of nodes is changing status 478 */ 479 #define SYSCTL_CLOCK_GLB_BUSY_MASK (0x80000000UL) 480 #define SYSCTL_CLOCK_GLB_BUSY_SHIFT (31U) 481 #define SYSCTL_CLOCK_GLB_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_GLB_BUSY_MASK) >> SYSCTL_CLOCK_GLB_BUSY_SHIFT) 482 483 /* 484 * LOC_BUSY (RO) 485 * 486 * local busy 487 * 0: a change is pending for current node 488 * 1: current node is changing status 489 */ 490 #define SYSCTL_CLOCK_LOC_BUSY_MASK (0x40000000UL) 491 #define SYSCTL_CLOCK_LOC_BUSY_SHIFT (30U) 492 #define SYSCTL_CLOCK_LOC_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_LOC_BUSY_MASK) >> SYSCTL_CLOCK_LOC_BUSY_SHIFT) 493 494 /* 495 * PRESERVE (RW) 496 * 497 * preserve function against global select 498 * 0: select global clock setting 499 * 1: not select global clock setting 500 */ 501 #define SYSCTL_CLOCK_PRESERVE_MASK (0x10000000UL) 502 #define SYSCTL_CLOCK_PRESERVE_SHIFT (28U) 503 #define SYSCTL_CLOCK_PRESERVE_SET(x) (((uint32_t)(x) << SYSCTL_CLOCK_PRESERVE_SHIFT) & SYSCTL_CLOCK_PRESERVE_MASK) 504 #define SYSCTL_CLOCK_PRESERVE_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_PRESERVE_MASK) >> SYSCTL_CLOCK_PRESERVE_SHIFT) 505 506 /* 507 * MUX (RW) 508 * 509 * current mux in clock component 510 * 0:osc0_clk0 511 * 1:pll0_clk0 512 * 2:pll1_clk0 513 * 3:pll1_clk1 514 * 4:pll2_clk0 515 * 5:pll2_clk1 516 * 6:pll3_clk0 517 * 7:pll4_clk0 518 */ 519 #define SYSCTL_CLOCK_MUX_MASK (0x700U) 520 #define SYSCTL_CLOCK_MUX_SHIFT (8U) 521 #define SYSCTL_CLOCK_MUX_SET(x) (((uint32_t)(x) << SYSCTL_CLOCK_MUX_SHIFT) & SYSCTL_CLOCK_MUX_MASK) 522 #define SYSCTL_CLOCK_MUX_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_MUX_MASK) >> SYSCTL_CLOCK_MUX_SHIFT) 523 524 /* 525 * DIV (RW) 526 * 527 * clock divider 528 * 0: divider by 1 529 * 1: divider by 2 530 * 2: divider by 3 531 * . . . 532 * 255: divider by 256 533 */ 534 #define SYSCTL_CLOCK_DIV_MASK (0xFFU) 535 #define SYSCTL_CLOCK_DIV_SHIFT (0U) 536 #define SYSCTL_CLOCK_DIV_SET(x) (((uint32_t)(x) << SYSCTL_CLOCK_DIV_SHIFT) & SYSCTL_CLOCK_DIV_MASK) 537 #define SYSCTL_CLOCK_DIV_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_DIV_MASK) >> SYSCTL_CLOCK_DIV_SHIFT) 538 539 /* Bitfield definition for register array: ADCCLK */ 540 /* 541 * GLB_BUSY (RO) 542 * 543 * global busy 544 * 0: no changes pending to any clock 545 * 1: any of nodes is changing status 546 */ 547 #define SYSCTL_ADCCLK_GLB_BUSY_MASK (0x80000000UL) 548 #define SYSCTL_ADCCLK_GLB_BUSY_SHIFT (31U) 549 #define SYSCTL_ADCCLK_GLB_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_ADCCLK_GLB_BUSY_MASK) >> SYSCTL_ADCCLK_GLB_BUSY_SHIFT) 550 551 /* 552 * LOC_BUSY (RO) 553 * 554 * local busy 555 * 0: a change is pending for current node 556 * 1: current node is changing status 557 */ 558 #define SYSCTL_ADCCLK_LOC_BUSY_MASK (0x40000000UL) 559 #define SYSCTL_ADCCLK_LOC_BUSY_SHIFT (30U) 560 #define SYSCTL_ADCCLK_LOC_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_ADCCLK_LOC_BUSY_MASK) >> SYSCTL_ADCCLK_LOC_BUSY_SHIFT) 561 562 /* 563 * PRESERVE (RW) 564 * 565 * preserve function against global select 566 * 0: select global clock setting 567 * 1: not select global clock setting 568 */ 569 #define SYSCTL_ADCCLK_PRESERVE_MASK (0x10000000UL) 570 #define SYSCTL_ADCCLK_PRESERVE_SHIFT (28U) 571 #define SYSCTL_ADCCLK_PRESERVE_SET(x) (((uint32_t)(x) << SYSCTL_ADCCLK_PRESERVE_SHIFT) & SYSCTL_ADCCLK_PRESERVE_MASK) 572 #define SYSCTL_ADCCLK_PRESERVE_GET(x) (((uint32_t)(x) & SYSCTL_ADCCLK_PRESERVE_MASK) >> SYSCTL_ADCCLK_PRESERVE_SHIFT) 573 574 /* 575 * MUX (RW) 576 * 577 * current mux 578 * 0: ana clock N 579 * 1: axi clock 580 */ 581 #define SYSCTL_ADCCLK_MUX_MASK (0x100U) 582 #define SYSCTL_ADCCLK_MUX_SHIFT (8U) 583 #define SYSCTL_ADCCLK_MUX_SET(x) (((uint32_t)(x) << SYSCTL_ADCCLK_MUX_SHIFT) & SYSCTL_ADCCLK_MUX_MASK) 584 #define SYSCTL_ADCCLK_MUX_GET(x) (((uint32_t)(x) & SYSCTL_ADCCLK_MUX_MASK) >> SYSCTL_ADCCLK_MUX_SHIFT) 585 586 /* Bitfield definition for register array: I2SCLK */ 587 /* 588 * GLB_BUSY (RO) 589 * 590 * global busy 591 * 0: no changes pending to any clock 592 * 1: any of nodes is changing status 593 */ 594 #define SYSCTL_I2SCLK_GLB_BUSY_MASK (0x80000000UL) 595 #define SYSCTL_I2SCLK_GLB_BUSY_SHIFT (31U) 596 #define SYSCTL_I2SCLK_GLB_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_I2SCLK_GLB_BUSY_MASK) >> SYSCTL_I2SCLK_GLB_BUSY_SHIFT) 597 598 /* 599 * LOC_BUSY (RO) 600 * 601 * local busy 602 * 0: a change is pending for current node 603 * 1: current node is changing status 604 */ 605 #define SYSCTL_I2SCLK_LOC_BUSY_MASK (0x40000000UL) 606 #define SYSCTL_I2SCLK_LOC_BUSY_SHIFT (30U) 607 #define SYSCTL_I2SCLK_LOC_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_I2SCLK_LOC_BUSY_MASK) >> SYSCTL_I2SCLK_LOC_BUSY_SHIFT) 608 609 /* 610 * PRESERVE (RW) 611 * 612 * preserve function against global select 613 * 0: select global clock setting 614 * 1: not select global clock setting 615 */ 616 #define SYSCTL_I2SCLK_PRESERVE_MASK (0x10000000UL) 617 #define SYSCTL_I2SCLK_PRESERVE_SHIFT (28U) 618 #define SYSCTL_I2SCLK_PRESERVE_SET(x) (((uint32_t)(x) << SYSCTL_I2SCLK_PRESERVE_SHIFT) & SYSCTL_I2SCLK_PRESERVE_MASK) 619 #define SYSCTL_I2SCLK_PRESERVE_GET(x) (((uint32_t)(x) & SYSCTL_I2SCLK_PRESERVE_MASK) >> SYSCTL_I2SCLK_PRESERVE_SHIFT) 620 621 /* 622 * MUX (RW) 623 * 624 * current mux 625 * 0: aud clock N 626 * 1: aud clock 0 627 */ 628 #define SYSCTL_I2SCLK_MUX_MASK (0x100U) 629 #define SYSCTL_I2SCLK_MUX_SHIFT (8U) 630 #define SYSCTL_I2SCLK_MUX_SET(x) (((uint32_t)(x) << SYSCTL_I2SCLK_MUX_SHIFT) & SYSCTL_I2SCLK_MUX_MASK) 631 #define SYSCTL_I2SCLK_MUX_GET(x) (((uint32_t)(x) & SYSCTL_I2SCLK_MUX_MASK) >> SYSCTL_I2SCLK_MUX_SHIFT) 632 633 /* Bitfield definition for register: GLOBAL00 */ 634 /* 635 * MUX (RW) 636 * 637 * global clock override request 638 * bit0: override to preset0 639 * bit1: override to preset1 640 * bit2: override to preset2 641 * bit3: override to preset3 642 * bit4: override to preset4 643 * bit5: override to preset5 644 * bit6: override to preset6 645 * bit7: override to preset7 646 */ 647 #define SYSCTL_GLOBAL00_MUX_MASK (0xFFU) 648 #define SYSCTL_GLOBAL00_MUX_SHIFT (0U) 649 #define SYSCTL_GLOBAL00_MUX_SET(x) (((uint32_t)(x) << SYSCTL_GLOBAL00_MUX_SHIFT) & SYSCTL_GLOBAL00_MUX_MASK) 650 #define SYSCTL_GLOBAL00_MUX_GET(x) (((uint32_t)(x) & SYSCTL_GLOBAL00_MUX_MASK) >> SYSCTL_GLOBAL00_MUX_SHIFT) 651 652 /* Bitfield definition for register of struct array MONITOR: CONTROL */ 653 /* 654 * VALID (RW) 655 * 656 * result is ready for read 657 * 0: not ready 658 * 1: result is ready 659 */ 660 #define SYSCTL_MONITOR_CONTROL_VALID_MASK (0x80000000UL) 661 #define SYSCTL_MONITOR_CONTROL_VALID_SHIFT (31U) 662 #define SYSCTL_MONITOR_CONTROL_VALID_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_VALID_SHIFT) & SYSCTL_MONITOR_CONTROL_VALID_MASK) 663 #define SYSCTL_MONITOR_CONTROL_VALID_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_VALID_MASK) >> SYSCTL_MONITOR_CONTROL_VALID_SHIFT) 664 665 /* 666 * DIV_BUSY (RO) 667 * 668 * divider is applying new setting 669 */ 670 #define SYSCTL_MONITOR_CONTROL_DIV_BUSY_MASK (0x8000000UL) 671 #define SYSCTL_MONITOR_CONTROL_DIV_BUSY_SHIFT (27U) 672 #define SYSCTL_MONITOR_CONTROL_DIV_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_DIV_BUSY_MASK) >> SYSCTL_MONITOR_CONTROL_DIV_BUSY_SHIFT) 673 674 /* 675 * OUTEN (RW) 676 * 677 * enable clock output 678 */ 679 #define SYSCTL_MONITOR_CONTROL_OUTEN_MASK (0x1000000UL) 680 #define SYSCTL_MONITOR_CONTROL_OUTEN_SHIFT (24U) 681 #define SYSCTL_MONITOR_CONTROL_OUTEN_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_OUTEN_SHIFT) & SYSCTL_MONITOR_CONTROL_OUTEN_MASK) 682 #define SYSCTL_MONITOR_CONTROL_OUTEN_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_OUTEN_MASK) >> SYSCTL_MONITOR_CONTROL_OUTEN_SHIFT) 683 684 /* 685 * DIV (RW) 686 * 687 * output divider 688 */ 689 #define SYSCTL_MONITOR_CONTROL_DIV_MASK (0xFF0000UL) 690 #define SYSCTL_MONITOR_CONTROL_DIV_SHIFT (16U) 691 #define SYSCTL_MONITOR_CONTROL_DIV_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_DIV_SHIFT) & SYSCTL_MONITOR_CONTROL_DIV_MASK) 692 #define SYSCTL_MONITOR_CONTROL_DIV_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_DIV_MASK) >> SYSCTL_MONITOR_CONTROL_DIV_SHIFT) 693 694 /* 695 * HIGH (RW) 696 * 697 * clock frequency higher than upper limit 698 */ 699 #define SYSCTL_MONITOR_CONTROL_HIGH_MASK (0x8000U) 700 #define SYSCTL_MONITOR_CONTROL_HIGH_SHIFT (15U) 701 #define SYSCTL_MONITOR_CONTROL_HIGH_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_HIGH_SHIFT) & SYSCTL_MONITOR_CONTROL_HIGH_MASK) 702 #define SYSCTL_MONITOR_CONTROL_HIGH_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_HIGH_MASK) >> SYSCTL_MONITOR_CONTROL_HIGH_SHIFT) 703 704 /* 705 * LOW (RW) 706 * 707 * clock frequency lower than lower limit 708 */ 709 #define SYSCTL_MONITOR_CONTROL_LOW_MASK (0x4000U) 710 #define SYSCTL_MONITOR_CONTROL_LOW_SHIFT (14U) 711 #define SYSCTL_MONITOR_CONTROL_LOW_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_LOW_SHIFT) & SYSCTL_MONITOR_CONTROL_LOW_MASK) 712 #define SYSCTL_MONITOR_CONTROL_LOW_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_LOW_MASK) >> SYSCTL_MONITOR_CONTROL_LOW_SHIFT) 713 714 /* 715 * START (RW) 716 * 717 * start measurement 718 */ 719 #define SYSCTL_MONITOR_CONTROL_START_MASK (0x1000U) 720 #define SYSCTL_MONITOR_CONTROL_START_SHIFT (12U) 721 #define SYSCTL_MONITOR_CONTROL_START_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_START_SHIFT) & SYSCTL_MONITOR_CONTROL_START_MASK) 722 #define SYSCTL_MONITOR_CONTROL_START_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_START_MASK) >> SYSCTL_MONITOR_CONTROL_START_SHIFT) 723 724 /* 725 * MODE (RW) 726 * 727 * work mode, 728 * 0: register value will be compared to measurement 729 * 1: upper and lower value will be recordered in register 730 */ 731 #define SYSCTL_MONITOR_CONTROL_MODE_MASK (0x400U) 732 #define SYSCTL_MONITOR_CONTROL_MODE_SHIFT (10U) 733 #define SYSCTL_MONITOR_CONTROL_MODE_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_MODE_SHIFT) & SYSCTL_MONITOR_CONTROL_MODE_MASK) 734 #define SYSCTL_MONITOR_CONTROL_MODE_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_MODE_MASK) >> SYSCTL_MONITOR_CONTROL_MODE_SHIFT) 735 736 /* 737 * ACCURACY (RW) 738 * 739 * measurement accuracy, 740 * 0: resolution is 1kHz 741 * 1: resolution is 1Hz 742 */ 743 #define SYSCTL_MONITOR_CONTROL_ACCURACY_MASK (0x200U) 744 #define SYSCTL_MONITOR_CONTROL_ACCURACY_SHIFT (9U) 745 #define SYSCTL_MONITOR_CONTROL_ACCURACY_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_ACCURACY_SHIFT) & SYSCTL_MONITOR_CONTROL_ACCURACY_MASK) 746 #define SYSCTL_MONITOR_CONTROL_ACCURACY_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_ACCURACY_MASK) >> SYSCTL_MONITOR_CONTROL_ACCURACY_SHIFT) 747 748 /* 749 * REFERENCE (RW) 750 * 751 * refrence clock selection, 752 * 0: 32k 753 * 1: 24M 754 */ 755 #define SYSCTL_MONITOR_CONTROL_REFERENCE_MASK (0x100U) 756 #define SYSCTL_MONITOR_CONTROL_REFERENCE_SHIFT (8U) 757 #define SYSCTL_MONITOR_CONTROL_REFERENCE_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_REFERENCE_SHIFT) & SYSCTL_MONITOR_CONTROL_REFERENCE_MASK) 758 #define SYSCTL_MONITOR_CONTROL_REFERENCE_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_REFERENCE_MASK) >> SYSCTL_MONITOR_CONTROL_REFERENCE_SHIFT) 759 760 /* 761 * SELECTION (RW) 762 * 763 * clock measurement selection 764 */ 765 #define SYSCTL_MONITOR_CONTROL_SELECTION_MASK (0xFFU) 766 #define SYSCTL_MONITOR_CONTROL_SELECTION_SHIFT (0U) 767 #define SYSCTL_MONITOR_CONTROL_SELECTION_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_SELECTION_SHIFT) & SYSCTL_MONITOR_CONTROL_SELECTION_MASK) 768 #define SYSCTL_MONITOR_CONTROL_SELECTION_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_SELECTION_MASK) >> SYSCTL_MONITOR_CONTROL_SELECTION_SHIFT) 769 770 /* Bitfield definition for register of struct array MONITOR: CURRENT */ 771 /* 772 * FREQUENCY (RO) 773 * 774 * self updating measure result 775 */ 776 #define SYSCTL_MONITOR_CURRENT_FREQUENCY_MASK (0xFFFFFFFFUL) 777 #define SYSCTL_MONITOR_CURRENT_FREQUENCY_SHIFT (0U) 778 #define SYSCTL_MONITOR_CURRENT_FREQUENCY_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CURRENT_FREQUENCY_MASK) >> SYSCTL_MONITOR_CURRENT_FREQUENCY_SHIFT) 779 780 /* Bitfield definition for register of struct array MONITOR: LOW_LIMIT */ 781 /* 782 * FREQUENCY (RW) 783 * 784 * lower frequency 785 */ 786 #define SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_MASK (0xFFFFFFFFUL) 787 #define SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SHIFT (0U) 788 #define SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SHIFT) & SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_MASK) 789 #define SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_MASK) >> SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SHIFT) 790 791 /* Bitfield definition for register of struct array MONITOR: HIGH_LIMIT */ 792 /* 793 * FREQUENCY (RW) 794 * 795 * upper frequency 796 */ 797 #define SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_MASK (0xFFFFFFFFUL) 798 #define SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SHIFT (0U) 799 #define SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SHIFT) & SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_MASK) 800 #define SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_MASK) >> SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SHIFT) 801 802 /* Bitfield definition for register of struct array CPU: LP */ 803 /* 804 * WAKE_CNT (RW) 805 * 806 * CPU0 wake up counter, counter satuated at 255, write 0x00 to clear 807 */ 808 #define SYSCTL_CPU_LP_WAKE_CNT_MASK (0xFF000000UL) 809 #define SYSCTL_CPU_LP_WAKE_CNT_SHIFT (24U) 810 #define SYSCTL_CPU_LP_WAKE_CNT_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LP_WAKE_CNT_SHIFT) & SYSCTL_CPU_LP_WAKE_CNT_MASK) 811 #define SYSCTL_CPU_LP_WAKE_CNT_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_WAKE_CNT_MASK) >> SYSCTL_CPU_LP_WAKE_CNT_SHIFT) 812 813 /* 814 * HALT (RW) 815 * 816 * halt request for CPU0, 817 * 0: CPU0 will start to execute after reset or receive wakeup request 818 * 1: CPU0 will not start after reset, or wakeup after WFI 819 */ 820 #define SYSCTL_CPU_LP_HALT_MASK (0x10000UL) 821 #define SYSCTL_CPU_LP_HALT_SHIFT (16U) 822 #define SYSCTL_CPU_LP_HALT_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LP_HALT_SHIFT) & SYSCTL_CPU_LP_HALT_MASK) 823 #define SYSCTL_CPU_LP_HALT_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_HALT_MASK) >> SYSCTL_CPU_LP_HALT_SHIFT) 824 825 /* 826 * WAKE (RO) 827 * 828 * CPU0 is waking up 829 * 0: CPU0 wake up not asserted 830 * 1: CPU0 wake up asserted 831 */ 832 #define SYSCTL_CPU_LP_WAKE_MASK (0x2000U) 833 #define SYSCTL_CPU_LP_WAKE_SHIFT (13U) 834 #define SYSCTL_CPU_LP_WAKE_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_WAKE_MASK) >> SYSCTL_CPU_LP_WAKE_SHIFT) 835 836 /* 837 * EXEC (RO) 838 * 839 * CPU0 is executing 840 * 0: CPU0 is not executing 841 * 1: CPU0 is executing 842 */ 843 #define SYSCTL_CPU_LP_EXEC_MASK (0x1000U) 844 #define SYSCTL_CPU_LP_EXEC_SHIFT (12U) 845 #define SYSCTL_CPU_LP_EXEC_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_EXEC_MASK) >> SYSCTL_CPU_LP_EXEC_SHIFT) 846 847 /* 848 * WAKE_FLAG (RW) 849 * 850 * CPU0 wakeup flag, indicate a wakeup event got active, write 1 to clear this bit 851 * 0: CPU0 wakeup not happened 852 * 1: CPU0 wake up happened 853 */ 854 #define SYSCTL_CPU_LP_WAKE_FLAG_MASK (0x400U) 855 #define SYSCTL_CPU_LP_WAKE_FLAG_SHIFT (10U) 856 #define SYSCTL_CPU_LP_WAKE_FLAG_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LP_WAKE_FLAG_SHIFT) & SYSCTL_CPU_LP_WAKE_FLAG_MASK) 857 #define SYSCTL_CPU_LP_WAKE_FLAG_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_WAKE_FLAG_MASK) >> SYSCTL_CPU_LP_WAKE_FLAG_SHIFT) 858 859 /* 860 * SLEEP_FLAG (RW) 861 * 862 * CPU0 sleep flag, indicate a sleep event got active, write 1 to clear this bit 863 * 0: CPU0 sleep not happened 864 * 1: CPU0 sleep happened 865 */ 866 #define SYSCTL_CPU_LP_SLEEP_FLAG_MASK (0x200U) 867 #define SYSCTL_CPU_LP_SLEEP_FLAG_SHIFT (9U) 868 #define SYSCTL_CPU_LP_SLEEP_FLAG_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LP_SLEEP_FLAG_SHIFT) & SYSCTL_CPU_LP_SLEEP_FLAG_MASK) 869 #define SYSCTL_CPU_LP_SLEEP_FLAG_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_SLEEP_FLAG_MASK) >> SYSCTL_CPU_LP_SLEEP_FLAG_SHIFT) 870 871 /* 872 * RESET_FLAG (RW) 873 * 874 * CPU0 reset flag, indicate a reset event got active, write 1 to clear this bit 875 * 0: CPU0 reset not happened 876 * 1: CPU0 reset happened 877 */ 878 #define SYSCTL_CPU_LP_RESET_FLAG_MASK (0x100U) 879 #define SYSCTL_CPU_LP_RESET_FLAG_SHIFT (8U) 880 #define SYSCTL_CPU_LP_RESET_FLAG_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LP_RESET_FLAG_SHIFT) & SYSCTL_CPU_LP_RESET_FLAG_MASK) 881 #define SYSCTL_CPU_LP_RESET_FLAG_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_RESET_FLAG_MASK) >> SYSCTL_CPU_LP_RESET_FLAG_SHIFT) 882 883 /* 884 * MODE (RW) 885 * 886 * Low power mode, system behavior after WFI 887 * 00: CPU clock stop after WFI 888 * 01: System enter low power mode after WFI 889 * 10: Keep running after WFI 890 * 11: reserved 891 */ 892 #define SYSCTL_CPU_LP_MODE_MASK (0x3U) 893 #define SYSCTL_CPU_LP_MODE_SHIFT (0U) 894 #define SYSCTL_CPU_LP_MODE_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LP_MODE_SHIFT) & SYSCTL_CPU_LP_MODE_MASK) 895 #define SYSCTL_CPU_LP_MODE_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_MODE_MASK) >> SYSCTL_CPU_LP_MODE_SHIFT) 896 897 /* Bitfield definition for register of struct array CPU: LOCK */ 898 /* 899 * GPR (RW) 900 * 901 * Lock bit for CPU_DATA0 to CPU_DATA13, once set, this bit will not clear untile next reset 902 */ 903 #define SYSCTL_CPU_LOCK_GPR_MASK (0xFFFCU) 904 #define SYSCTL_CPU_LOCK_GPR_SHIFT (2U) 905 #define SYSCTL_CPU_LOCK_GPR_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LOCK_GPR_SHIFT) & SYSCTL_CPU_LOCK_GPR_MASK) 906 #define SYSCTL_CPU_LOCK_GPR_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LOCK_GPR_MASK) >> SYSCTL_CPU_LOCK_GPR_SHIFT) 907 908 /* 909 * LOCK (RW) 910 * 911 * Lock bit for CPU_LOCK 912 */ 913 #define SYSCTL_CPU_LOCK_LOCK_MASK (0x2U) 914 #define SYSCTL_CPU_LOCK_LOCK_SHIFT (1U) 915 #define SYSCTL_CPU_LOCK_LOCK_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LOCK_LOCK_SHIFT) & SYSCTL_CPU_LOCK_LOCK_MASK) 916 #define SYSCTL_CPU_LOCK_LOCK_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LOCK_LOCK_MASK) >> SYSCTL_CPU_LOCK_LOCK_SHIFT) 917 918 /* Bitfield definition for register of struct array CPU: GPR0 */ 919 /* 920 * GPR (RW) 921 * 922 * register for software to handle resume, can save resume address or status 923 */ 924 #define SYSCTL_CPU_GPR_GPR_MASK (0xFFFFFFFFUL) 925 #define SYSCTL_CPU_GPR_GPR_SHIFT (0U) 926 #define SYSCTL_CPU_GPR_GPR_SET(x) (((uint32_t)(x) << SYSCTL_CPU_GPR_GPR_SHIFT) & SYSCTL_CPU_GPR_GPR_MASK) 927 #define SYSCTL_CPU_GPR_GPR_GET(x) (((uint32_t)(x) & SYSCTL_CPU_GPR_GPR_MASK) >> SYSCTL_CPU_GPR_GPR_SHIFT) 928 929 /* Bitfield definition for register of struct array CPU: STATUS0 */ 930 /* 931 * STATUS (RO) 932 * 933 * IRQ values 934 */ 935 #define SYSCTL_CPU_WAKEUP_STATUS_STATUS_MASK (0xFFFFFFFFUL) 936 #define SYSCTL_CPU_WAKEUP_STATUS_STATUS_SHIFT (0U) 937 #define SYSCTL_CPU_WAKEUP_STATUS_STATUS_GET(x) (((uint32_t)(x) & SYSCTL_CPU_WAKEUP_STATUS_STATUS_MASK) >> SYSCTL_CPU_WAKEUP_STATUS_STATUS_SHIFT) 938 939 /* Bitfield definition for register of struct array CPU: ENABLE0 */ 940 /* 941 * ENABLE (RW) 942 * 943 * IRQ wakeup enable 944 */ 945 #define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_MASK (0xFFFFFFFFUL) 946 #define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_SHIFT (0U) 947 #define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_SET(x) (((uint32_t)(x) << SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_SHIFT) & SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_MASK) 948 #define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_GET(x) (((uint32_t)(x) & SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_MASK) >> SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_SHIFT) 949 950 951 952 /* RESOURCE register group index macro definition */ 953 #define SYSCTL_RESOURCE_CPU0 (0UL) 954 #define SYSCTL_RESOURCE_CPX0 (1UL) 955 #define SYSCTL_RESOURCE_POW_VIS (21UL) 956 #define SYSCTL_RESOURCE_POW_CPU0 (22UL) 957 #define SYSCTL_RESOURCE_POW_GPU (23UL) 958 #define SYSCTL_RESOURCE_RST_SOC (25UL) 959 #define SYSCTL_RESOURCE_RST_CON (26UL) 960 #define SYSCTL_RESOURCE_RST_VIS (27UL) 961 #define SYSCTL_RESOURCE_RST_CPU0 (28UL) 962 #define SYSCTL_RESOURCE_RST_GPU (29UL) 963 #define SYSCTL_RESOURCE_CLK_SRC_XTAL (32UL) 964 #define SYSCTL_RESOURCE_CLK_SRC_PLL0 (33UL) 965 #define SYSCTL_RESOURCE_CLK_SRC_CLK0_PLL0 (34UL) 966 #define SYSCTL_RESOURCE_CLK_SRC_PLL1 (35UL) 967 #define SYSCTL_RESOURCE_CLK_SRC_CLK0_PLL1 (36UL) 968 #define SYSCTL_RESOURCE_CLK_SRC_CLK1_PLL1 (37UL) 969 #define SYSCTL_RESOURCE_CLK_SRC_PLL2 (38UL) 970 #define SYSCTL_RESOURCE_CLK_SRC_CLK0_PLL2 (39UL) 971 #define SYSCTL_RESOURCE_CLK_SRC_CLK1_PLL2 (40UL) 972 #define SYSCTL_RESOURCE_CLK_SRC_PLL3 (41UL) 973 #define SYSCTL_RESOURCE_CLK_SRC_CLK0_PLL3 (42UL) 974 #define SYSCTL_RESOURCE_CLK_SRC_PLL4 (43UL) 975 #define SYSCTL_RESOURCE_CLK_SRC_CLK0_PLL4 (44UL) 976 #define SYSCTL_RESOURCE_CLK_SRC_PLL0_REF (45UL) 977 #define SYSCTL_RESOURCE_CLK_SRC_PLL1_REF (46UL) 978 #define SYSCTL_RESOURCE_CLK_SRC_PLL2_REF (47UL) 979 #define SYSCTL_RESOURCE_CLK_SRC_PLL3_REF (48UL) 980 #define SYSCTL_RESOURCE_CLK_SRC_PLL4_REF (49UL) 981 #define SYSCTL_RESOURCE_CLK_TOP_CPU0 (64UL) 982 #define SYSCTL_RESOURCE_CLK_TOP_MCT0 (65UL) 983 #define SYSCTL_RESOURCE_CLK_TOP_GPU0 (66UL) 984 #define SYSCTL_RESOURCE_CLK_TOP_AXIF (67UL) 985 #define SYSCTL_RESOURCE_CLK_TOP_AXIS (68UL) 986 #define SYSCTL_RESOURCE_CLK_TOP_AXIC (69UL) 987 #define SYSCTL_RESOURCE_CLK_TOP_AXIV (70UL) 988 #define SYSCTL_RESOURCE_CLK_TOP_AXID (71UL) 989 #define SYSCTL_RESOURCE_CLK_TOP_CAN0 (72UL) 990 #define SYSCTL_RESOURCE_CLK_TOP_CAN1 (73UL) 991 #define SYSCTL_RESOURCE_CLK_TOP_CAN2 (74UL) 992 #define SYSCTL_RESOURCE_CLK_TOP_CAN3 (75UL) 993 #define SYSCTL_RESOURCE_CLK_TOP_CAN4 (76UL) 994 #define SYSCTL_RESOURCE_CLK_TOP_CAN5 (77UL) 995 #define SYSCTL_RESOURCE_CLK_TOP_CAN6 (78UL) 996 #define SYSCTL_RESOURCE_CLK_TOP_CAN7 (79UL) 997 #define SYSCTL_RESOURCE_CLK_TOP_LIN0 (80UL) 998 #define SYSCTL_RESOURCE_CLK_TOP_LIN1 (81UL) 999 #define SYSCTL_RESOURCE_CLK_TOP_LIN2 (82UL) 1000 #define SYSCTL_RESOURCE_CLK_TOP_LIN3 (83UL) 1001 #define SYSCTL_RESOURCE_CLK_TOP_LIN4 (84UL) 1002 #define SYSCTL_RESOURCE_CLK_TOP_LIN5 (85UL) 1003 #define SYSCTL_RESOURCE_CLK_TOP_LIN6 (86UL) 1004 #define SYSCTL_RESOURCE_CLK_TOP_LIN7 (87UL) 1005 #define SYSCTL_RESOURCE_CLK_TOP_I2C0 (88UL) 1006 #define SYSCTL_RESOURCE_CLK_TOP_I2C1 (89UL) 1007 #define SYSCTL_RESOURCE_CLK_TOP_I2C2 (90UL) 1008 #define SYSCTL_RESOURCE_CLK_TOP_I2C3 (91UL) 1009 #define SYSCTL_RESOURCE_CLK_TOP_SPI0 (92UL) 1010 #define SYSCTL_RESOURCE_CLK_TOP_SPI1 (93UL) 1011 #define SYSCTL_RESOURCE_CLK_TOP_SPI2 (94UL) 1012 #define SYSCTL_RESOURCE_CLK_TOP_SPI3 (95UL) 1013 #define SYSCTL_RESOURCE_CLK_TOP_URT0 (96UL) 1014 #define SYSCTL_RESOURCE_CLK_TOP_URT1 (97UL) 1015 #define SYSCTL_RESOURCE_CLK_TOP_URT2 (98UL) 1016 #define SYSCTL_RESOURCE_CLK_TOP_URT3 (99UL) 1017 #define SYSCTL_RESOURCE_CLK_TOP_URT4 (100UL) 1018 #define SYSCTL_RESOURCE_CLK_TOP_URT5 (101UL) 1019 #define SYSCTL_RESOURCE_CLK_TOP_URT6 (102UL) 1020 #define SYSCTL_RESOURCE_CLK_TOP_URT7 (103UL) 1021 #define SYSCTL_RESOURCE_CLK_TOP_TMR0 (104UL) 1022 #define SYSCTL_RESOURCE_CLK_TOP_TMR1 (105UL) 1023 #define SYSCTL_RESOURCE_CLK_TOP_TMR2 (106UL) 1024 #define SYSCTL_RESOURCE_CLK_TOP_TMR3 (107UL) 1025 #define SYSCTL_RESOURCE_CLK_TOP_TMR4 (108UL) 1026 #define SYSCTL_RESOURCE_CLK_TOP_TMR5 (109UL) 1027 #define SYSCTL_RESOURCE_CLK_TOP_TMR6 (110UL) 1028 #define SYSCTL_RESOURCE_CLK_TOP_TMR7 (111UL) 1029 #define SYSCTL_RESOURCE_CLK_TOP_XPI0 (112UL) 1030 #define SYSCTL_RESOURCE_CLK_TOP_XRAM (113UL) 1031 #define SYSCTL_RESOURCE_CLK_TOP_ANA0 (114UL) 1032 #define SYSCTL_RESOURCE_CLK_TOP_ANA1 (115UL) 1033 #define SYSCTL_RESOURCE_CLK_TOP_AUD0 (116UL) 1034 #define SYSCTL_RESOURCE_CLK_TOP_AUD1 (117UL) 1035 #define SYSCTL_RESOURCE_CLK_TOP_AUD2 (118UL) 1036 #define SYSCTL_RESOURCE_CLK_TOP_AUD3 (119UL) 1037 #define SYSCTL_RESOURCE_CLK_TOP_ETH0 (120UL) 1038 #define SYSCTL_RESOURCE_CLK_TOP_PTP0 (121UL) 1039 #define SYSCTL_RESOURCE_CLK_TOP_SDC0 (122UL) 1040 #define SYSCTL_RESOURCE_CLK_TOP_SDC1 (123UL) 1041 #define SYSCTL_RESOURCE_CLK_TOP_NTM0 (124UL) 1042 #define SYSCTL_RESOURCE_CLK_TOP_REF0 (125UL) 1043 #define SYSCTL_RESOURCE_CLK_TOP_REF1 (126UL) 1044 #define SYSCTL_RESOURCE_CLK_TOP_CAM0 (127UL) 1045 #define SYSCTL_RESOURCE_CLK_TOP_CAM1 (128UL) 1046 #define SYSCTL_RESOURCE_CLK_TOP_LCD0 (129UL) 1047 #define SYSCTL_RESOURCE_CLK_TOP_LCD1 (130UL) 1048 #define SYSCTL_RESOURCE_CLK_TOP_CSI0 (131UL) 1049 #define SYSCTL_RESOURCE_CLK_TOP_CSI1 (132UL) 1050 #define SYSCTL_RESOURCE_CLK_TOP_ADC0 (133UL) 1051 #define SYSCTL_RESOURCE_CLK_TOP_ADC1 (134UL) 1052 #define SYSCTL_RESOURCE_CLK_TOP_I2S0 (135UL) 1053 #define SYSCTL_RESOURCE_CLK_TOP_I2S1 (136UL) 1054 #define SYSCTL_RESOURCE_CLK_TOP_I2S2 (137UL) 1055 #define SYSCTL_RESOURCE_CLK_TOP_I2S3 (138UL) 1056 #define SYSCTL_RESOURCE_AXIS (256UL) 1057 #define SYSCTL_RESOURCE_AXIC (257UL) 1058 #define SYSCTL_RESOURCE_AXIV (258UL) 1059 #define SYSCTL_RESOURCE_AXIG (259UL) 1060 #define SYSCTL_RESOURCE_LMM0 (260UL) 1061 #define SYSCTL_RESOURCE_MCT0 (261UL) 1062 #define SYSCTL_RESOURCE_ROM0 (262UL) 1063 #define SYSCTL_RESOURCE_DDR0 (263UL) 1064 #define SYSCTL_RESOURCE_XRAM (264UL) 1065 #define SYSCTL_RESOURCE_CAN0 (265UL) 1066 #define SYSCTL_RESOURCE_CAN1 (266UL) 1067 #define SYSCTL_RESOURCE_CAN2 (267UL) 1068 #define SYSCTL_RESOURCE_CAN3 (268UL) 1069 #define SYSCTL_RESOURCE_CAN4 (269UL) 1070 #define SYSCTL_RESOURCE_CAN5 (270UL) 1071 #define SYSCTL_RESOURCE_CAN6 (271UL) 1072 #define SYSCTL_RESOURCE_CAN7 (272UL) 1073 #define SYSCTL_RESOURCE_PTPC (273UL) 1074 #define SYSCTL_RESOURCE_CRC0 (274UL) 1075 #define SYSCTL_RESOURCE_OAMP (275UL) 1076 #define SYSCTL_RESOURCE_LIN0 (276UL) 1077 #define SYSCTL_RESOURCE_LIN1 (277UL) 1078 #define SYSCTL_RESOURCE_LIN2 (278UL) 1079 #define SYSCTL_RESOURCE_LIN3 (279UL) 1080 #define SYSCTL_RESOURCE_LIN4 (280UL) 1081 #define SYSCTL_RESOURCE_LIN5 (281UL) 1082 #define SYSCTL_RESOURCE_LIN6 (282UL) 1083 #define SYSCTL_RESOURCE_LIN7 (283UL) 1084 #define SYSCTL_RESOURCE_I2C0 (284UL) 1085 #define SYSCTL_RESOURCE_I2C1 (285UL) 1086 #define SYSCTL_RESOURCE_I2C2 (286UL) 1087 #define SYSCTL_RESOURCE_I2C3 (287UL) 1088 #define SYSCTL_RESOURCE_SPI0 (288UL) 1089 #define SYSCTL_RESOURCE_SPI1 (289UL) 1090 #define SYSCTL_RESOURCE_SPI2 (290UL) 1091 #define SYSCTL_RESOURCE_SPI3 (291UL) 1092 #define SYSCTL_RESOURCE_URT0 (292UL) 1093 #define SYSCTL_RESOURCE_URT1 (293UL) 1094 #define SYSCTL_RESOURCE_URT2 (294UL) 1095 #define SYSCTL_RESOURCE_URT3 (295UL) 1096 #define SYSCTL_RESOURCE_URT4 (296UL) 1097 #define SYSCTL_RESOURCE_URT5 (297UL) 1098 #define SYSCTL_RESOURCE_URT6 (298UL) 1099 #define SYSCTL_RESOURCE_URT7 (299UL) 1100 #define SYSCTL_RESOURCE_WDG0 (300UL) 1101 #define SYSCTL_RESOURCE_WDG1 (301UL) 1102 #define SYSCTL_RESOURCE_MBX0 (302UL) 1103 #define SYSCTL_RESOURCE_MBX1 (303UL) 1104 #define SYSCTL_RESOURCE_TMR0 (304UL) 1105 #define SYSCTL_RESOURCE_TMR1 (305UL) 1106 #define SYSCTL_RESOURCE_TMR2 (306UL) 1107 #define SYSCTL_RESOURCE_TMR3 (307UL) 1108 #define SYSCTL_RESOURCE_TMR4 (308UL) 1109 #define SYSCTL_RESOURCE_TMR5 (309UL) 1110 #define SYSCTL_RESOURCE_TMR6 (310UL) 1111 #define SYSCTL_RESOURCE_TMR7 (311UL) 1112 #define SYSCTL_RESOURCE_I2S0 (312UL) 1113 #define SYSCTL_RESOURCE_I2S1 (313UL) 1114 #define SYSCTL_RESOURCE_I2S2 (314UL) 1115 #define SYSCTL_RESOURCE_I2S3 (315UL) 1116 #define SYSCTL_RESOURCE_PDM0 (316UL) 1117 #define SYSCTL_RESOURCE_DAO0 (317UL) 1118 #define SYSCTL_RESOURCE_SMIX (318UL) 1119 #define SYSCTL_RESOURCE_RNG0 (319UL) 1120 #define SYSCTL_RESOURCE_SDP0 (320UL) 1121 #define SYSCTL_RESOURCE_KMAN (321UL) 1122 #define SYSCTL_RESOURCE_GPIO (322UL) 1123 #define SYSCTL_RESOURCE_ADC0 (323UL) 1124 #define SYSCTL_RESOURCE_ADC1 (324UL) 1125 #define SYSCTL_RESOURCE_SDM0 (325UL) 1126 #define SYSCTL_RESOURCE_HDMA (326UL) 1127 #define SYSCTL_RESOURCE_XDMA (327UL) 1128 #define SYSCTL_RESOURCE_XPI0 (328UL) 1129 #define SYSCTL_RESOURCE_FFA0 (329UL) 1130 #define SYSCTL_RESOURCE_TSNS (330UL) 1131 #define SYSCTL_RESOURCE_ETH0 (331UL) 1132 #define SYSCTL_RESOURCE_USB0 (332UL) 1133 #define SYSCTL_RESOURCE_SDC0 (333UL) 1134 #define SYSCTL_RESOURCE_SDC1 (334UL) 1135 #define SYSCTL_RESOURCE_NTM0 (335UL) 1136 #define SYSCTL_RESOURCE_REF0 (336UL) 1137 #define SYSCTL_RESOURCE_REF1 (337UL) 1138 #define SYSCTL_RESOURCE_CAM0 (338UL) 1139 #define SYSCTL_RESOURCE_CAM1 (339UL) 1140 #define SYSCTL_RESOURCE_PDMA (340UL) 1141 #define SYSCTL_RESOURCE_JPEG (341UL) 1142 #define SYSCTL_RESOURCE_LCD0 (342UL) 1143 #define SYSCTL_RESOURCE_LCD1 (343UL) 1144 #define SYSCTL_RESOURCE_GWC0 (344UL) 1145 #define SYSCTL_RESOURCE_GWC1 (345UL) 1146 #define SYSCTL_RESOURCE_CSI0 (346UL) 1147 #define SYSCTL_RESOURCE_CSI1 (347UL) 1148 #define SYSCTL_RESOURCE_DSI0 (348UL) 1149 #define SYSCTL_RESOURCE_DSI1 (349UL) 1150 #define SYSCTL_RESOURCE_LVB0 (350UL) 1151 #define SYSCTL_RESOURCE_LCB0 (351UL) 1152 #define SYSCTL_RESOURCE_GPU0 (352UL) 1153 1154 /* GROUP0 register group index macro definition */ 1155 #define SYSCTL_GROUP0_LINK0 (0UL) 1156 #define SYSCTL_GROUP0_LINK1 (1UL) 1157 #define SYSCTL_GROUP0_LINK2 (2UL) 1158 #define SYSCTL_GROUP0_LINK3 (3UL) 1159 1160 /* AFFILIATE register group index macro definition */ 1161 #define SYSCTL_AFFILIATE_CPU0 (0UL) 1162 1163 /* RETENTION register group index macro definition */ 1164 #define SYSCTL_RETENTION_CPU0 (0UL) 1165 1166 /* POWER register group index macro definition */ 1167 #define SYSCTL_POWER_VIS (0UL) 1168 #define SYSCTL_POWER_CPU0 (1UL) 1169 #define SYSCTL_POWER_GPU (2UL) 1170 1171 /* RESET register group index macro definition */ 1172 #define SYSCTL_RESET_SOC (0UL) 1173 #define SYSCTL_RESET_CON (1UL) 1174 #define SYSCTL_RESET_VIS (2UL) 1175 #define SYSCTL_RESET_CPU0 (3UL) 1176 #define SYSCTL_RESET_GPU (4UL) 1177 1178 /* CLOCK register group index macro definition */ 1179 #define SYSCTL_CLOCK_CLK_TOP_CPU0 (0UL) 1180 #define SYSCTL_CLOCK_CLK_TOP_MCT0 (1UL) 1181 #define SYSCTL_CLOCK_CLK_TOP_GPU0 (2UL) 1182 #define SYSCTL_CLOCK_CLK_TOP_AXIF (3UL) 1183 #define SYSCTL_CLOCK_CLK_TOP_AXIS (4UL) 1184 #define SYSCTL_CLOCK_CLK_TOP_AXIC (5UL) 1185 #define SYSCTL_CLOCK_CLK_TOP_AXIV (6UL) 1186 #define SYSCTL_CLOCK_CLK_TOP_AXID (7UL) 1187 #define SYSCTL_CLOCK_CLK_TOP_CAN0 (8UL) 1188 #define SYSCTL_CLOCK_CLK_TOP_CAN1 (9UL) 1189 #define SYSCTL_CLOCK_CLK_TOP_CAN2 (10UL) 1190 #define SYSCTL_CLOCK_CLK_TOP_CAN3 (11UL) 1191 #define SYSCTL_CLOCK_CLK_TOP_CAN4 (12UL) 1192 #define SYSCTL_CLOCK_CLK_TOP_CAN5 (13UL) 1193 #define SYSCTL_CLOCK_CLK_TOP_CAN6 (14UL) 1194 #define SYSCTL_CLOCK_CLK_TOP_CAN7 (15UL) 1195 #define SYSCTL_CLOCK_CLK_TOP_LIN0 (16UL) 1196 #define SYSCTL_CLOCK_CLK_TOP_LIN1 (17UL) 1197 #define SYSCTL_CLOCK_CLK_TOP_LIN2 (18UL) 1198 #define SYSCTL_CLOCK_CLK_TOP_LIN3 (19UL) 1199 #define SYSCTL_CLOCK_CLK_TOP_LIN4 (20UL) 1200 #define SYSCTL_CLOCK_CLK_TOP_LIN5 (21UL) 1201 #define SYSCTL_CLOCK_CLK_TOP_LIN6 (22UL) 1202 #define SYSCTL_CLOCK_CLK_TOP_LIN7 (23UL) 1203 #define SYSCTL_CLOCK_CLK_TOP_I2C0 (24UL) 1204 #define SYSCTL_CLOCK_CLK_TOP_I2C1 (25UL) 1205 #define SYSCTL_CLOCK_CLK_TOP_I2C2 (26UL) 1206 #define SYSCTL_CLOCK_CLK_TOP_I2C3 (27UL) 1207 #define SYSCTL_CLOCK_CLK_TOP_SPI0 (28UL) 1208 #define SYSCTL_CLOCK_CLK_TOP_SPI1 (29UL) 1209 #define SYSCTL_CLOCK_CLK_TOP_SPI2 (30UL) 1210 #define SYSCTL_CLOCK_CLK_TOP_SPI3 (31UL) 1211 #define SYSCTL_CLOCK_CLK_TOP_URT0 (32UL) 1212 #define SYSCTL_CLOCK_CLK_TOP_URT1 (33UL) 1213 #define SYSCTL_CLOCK_CLK_TOP_URT2 (34UL) 1214 #define SYSCTL_CLOCK_CLK_TOP_URT3 (35UL) 1215 #define SYSCTL_CLOCK_CLK_TOP_URT4 (36UL) 1216 #define SYSCTL_CLOCK_CLK_TOP_URT5 (37UL) 1217 #define SYSCTL_CLOCK_CLK_TOP_URT6 (38UL) 1218 #define SYSCTL_CLOCK_CLK_TOP_URT7 (39UL) 1219 #define SYSCTL_CLOCK_CLK_TOP_TMR0 (40UL) 1220 #define SYSCTL_CLOCK_CLK_TOP_TMR1 (41UL) 1221 #define SYSCTL_CLOCK_CLK_TOP_TMR2 (42UL) 1222 #define SYSCTL_CLOCK_CLK_TOP_TMR3 (43UL) 1223 #define SYSCTL_CLOCK_CLK_TOP_TMR4 (44UL) 1224 #define SYSCTL_CLOCK_CLK_TOP_TMR5 (45UL) 1225 #define SYSCTL_CLOCK_CLK_TOP_TMR6 (46UL) 1226 #define SYSCTL_CLOCK_CLK_TOP_TMR7 (47UL) 1227 #define SYSCTL_CLOCK_CLK_TOP_XPI0 (48UL) 1228 #define SYSCTL_CLOCK_CLK_TOP_XRAM (49UL) 1229 #define SYSCTL_CLOCK_CLK_TOP_ANA0 (50UL) 1230 #define SYSCTL_CLOCK_CLK_TOP_ANA1 (51UL) 1231 #define SYSCTL_CLOCK_CLK_TOP_AUD0 (52UL) 1232 #define SYSCTL_CLOCK_CLK_TOP_AUD1 (53UL) 1233 #define SYSCTL_CLOCK_CLK_TOP_AUD2 (54UL) 1234 #define SYSCTL_CLOCK_CLK_TOP_AUD3 (55UL) 1235 #define SYSCTL_CLOCK_CLK_TOP_ETH0 (56UL) 1236 #define SYSCTL_CLOCK_CLK_TOP_PTP0 (57UL) 1237 #define SYSCTL_CLOCK_CLK_TOP_SDC0 (58UL) 1238 #define SYSCTL_CLOCK_CLK_TOP_SDC1 (59UL) 1239 #define SYSCTL_CLOCK_CLK_TOP_NTM0 (60UL) 1240 #define SYSCTL_CLOCK_CLK_TOP_REF0 (61UL) 1241 #define SYSCTL_CLOCK_CLK_TOP_REF1 (62UL) 1242 #define SYSCTL_CLOCK_CLK_TOP_CAM0 (63UL) 1243 #define SYSCTL_CLOCK_CLK_TOP_CAM1 (64UL) 1244 #define SYSCTL_CLOCK_CLK_TOP_LCD0 (65UL) 1245 #define SYSCTL_CLOCK_CLK_TOP_LCD1 (66UL) 1246 #define SYSCTL_CLOCK_CLK_TOP_CSI0 (67UL) 1247 #define SYSCTL_CLOCK_CLK_TOP_CSI1 (68UL) 1248 1249 /* ADCCLK register group index macro definition */ 1250 #define SYSCTL_ADCCLK_CLK_TOP_ADC0 (0UL) 1251 #define SYSCTL_ADCCLK_CLK_TOP_ADC1 (1UL) 1252 1253 /* I2SCLK register group index macro definition */ 1254 #define SYSCTL_I2SCLK_CLK_TOP_I2S0 (0UL) 1255 #define SYSCTL_I2SCLK_CLK_TOP_I2S1 (1UL) 1256 #define SYSCTL_I2SCLK_CLK_TOP_I2S2 (2UL) 1257 #define SYSCTL_I2SCLK_CLK_TOP_I2S3 (3UL) 1258 1259 /* MONITOR register group index macro definition */ 1260 #define SYSCTL_MONITOR_SLICE0 (0UL) 1261 #define SYSCTL_MONITOR_SLICE1 (1UL) 1262 #define SYSCTL_MONITOR_SLICE2 (2UL) 1263 #define SYSCTL_MONITOR_SLICE3 (3UL) 1264 1265 /* GPR register group index macro definition */ 1266 #define SYSCTL_CPU_GPR_GPR0 (0UL) 1267 #define SYSCTL_CPU_GPR_GPR1 (1UL) 1268 #define SYSCTL_CPU_GPR_GPR2 (2UL) 1269 #define SYSCTL_CPU_GPR_GPR3 (3UL) 1270 #define SYSCTL_CPU_GPR_GPR4 (4UL) 1271 #define SYSCTL_CPU_GPR_GPR5 (5UL) 1272 #define SYSCTL_CPU_GPR_GPR6 (6UL) 1273 #define SYSCTL_CPU_GPR_GPR7 (7UL) 1274 #define SYSCTL_CPU_GPR_GPR8 (8UL) 1275 #define SYSCTL_CPU_GPR_GPR9 (9UL) 1276 #define SYSCTL_CPU_GPR_GPR10 (10UL) 1277 #define SYSCTL_CPU_GPR_GPR11 (11UL) 1278 #define SYSCTL_CPU_GPR_GPR12 (12UL) 1279 #define SYSCTL_CPU_GPR_GPR13 (13UL) 1280 1281 /* WAKEUP_STATUS register group index macro definition */ 1282 #define SYSCTL_CPU_WAKEUP_STATUS_STATUS0 (0UL) 1283 #define SYSCTL_CPU_WAKEUP_STATUS_STATUS1 (1UL) 1284 #define SYSCTL_CPU_WAKEUP_STATUS_STATUS2 (2UL) 1285 #define SYSCTL_CPU_WAKEUP_STATUS_STATUS3 (3UL) 1286 1287 /* WAKEUP_ENABLE register group index macro definition */ 1288 #define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE0 (0UL) 1289 #define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE1 (1UL) 1290 #define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE2 (2UL) 1291 #define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE3 (3UL) 1292 1293 /* CPU register group index macro definition */ 1294 #define SYSCTL_CPU_CPU0 (0UL) 1295 1296 1297 #endif /* HPM_SYSCTL_H */ 1298