1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Synopsys DesignWare Cores DisplayPort Transmitter Controller
4 *
5 * Copyright (c) 2022 Rockchip Electronics Co. Ltd.
6 *
7 * Author: Wyon Bi <bivvy.bi@rock-chips.com>
8 * Zhang Yubing <yubing.zhang@rock-chips.com>
9 */
10
11 #include <asm/unaligned.h>
12
13 #include <drm/drm_atomic_helper.h>
14 #include <drm/drm_bridge.h>
15 #include <drm/drm_dp_helper.h>
16 #include <drm/drm_of.h>
17 #include <drm/drm_print.h>
18 #include <drm/drm_probe_helper.h>
19 #include <drm/drm_simple_kms_helper.h>
20
21 #include <linux/bitfield.h>
22 #include <linux/clk.h>
23 #include <linux/component.h>
24 #include <linux/iopoll.h>
25 #include <linux/irq.h>
26 #include <linux/of_device.h>
27 #include <linux/of_graph.h>
28 #include <linux/regmap.h>
29 #include <linux/reset.h>
30 #include <linux/gpio/consumer.h>
31 #include <linux/phy/phy.h>
32 #include <linux/mfd/syscon.h>
33
34 #include <sound/hdmi-codec.h>
35
36 #include <uapi/linux/videodev2.h>
37
38 #include "rockchip_drm_drv.h"
39 #include "rockchip_drm_vop.h"
40
41 #define DPTX_VERSION_NUMBER 0x0000
42 #define DPTX_VERSION_TYPE 0x0004
43 #define DPTX_ID 0x0008
44
45 #define DPTX_CONFIG_REG1 0x0100
46 #define DPTX_CONFIG_REG2 0x0104
47 #define DPTX_CONFIG_REG3 0x0108
48
49 #define DPTX_CCTL 0x0200
50 #define FORCE_HPD BIT(4)
51 #define DEFAULT_FAST_LINK_TRAIN_EN BIT(2)
52 #define ENHANCE_FRAMING_EN BIT(1)
53 #define SCRAMBLE_DIS BIT(0)
54 #define DPTX_SOFT_RESET_CTRL 0x0204
55 #define VIDEO_RESET BIT(5)
56 #define AUX_RESET BIT(4)
57 #define AUDIO_SAMPLER_RESET BIT(3)
58 #define PHY_SOFT_RESET BIT(1)
59 #define CONTROLLER_RESET BIT(0)
60
61 #define DPTX_VSAMPLE_CTRL 0x0300
62 #define PIXEL_MODE_SELECT GENMASK(22, 21)
63 #define VIDEO_MAPPING GENMASK(20, 16)
64 #define VIDEO_STREAM_ENABLE BIT(5)
65 #define DPTX_VSAMPLE_STUFF_CTRL1 0x0304
66 #define DPTX_VSAMPLE_STUFF_CTRL2 0x0308
67 #define DPTX_VINPUT_POLARITY_CTRL 0x030c
68 #define DE_IN_POLARITY BIT(2)
69 #define HSYNC_IN_POLARITY BIT(1)
70 #define VSYNC_IN_POLARITY BIT(0)
71 #define DPTX_VIDEO_CONFIG1 0x0310
72 #define HACTIVE GENMASK(31, 16)
73 #define HBLANK GENMASK(15, 2)
74 #define I_P BIT(1)
75 #define R_V_BLANK_IN_OSC BIT(0)
76 #define DPTX_VIDEO_CONFIG2 0x0314
77 #define VBLANK GENMASK(31, 16)
78 #define VACTIVE GENMASK(15, 0)
79 #define DPTX_VIDEO_CONFIG3 0x0318
80 #define H_SYNC_WIDTH GENMASK(31, 16)
81 #define H_FRONT_PORCH GENMASK(15, 0)
82 #define DPTX_VIDEO_CONFIG4 0x031c
83 #define V_SYNC_WIDTH GENMASK(31, 16)
84 #define V_FRONT_PORCH GENMASK(15, 0)
85 #define DPTX_VIDEO_CONFIG5 0x0320
86 #define INIT_THRESHOLD_HI GENMASK(22, 21)
87 #define AVERAGE_BYTES_PER_TU_FRAC GENMASK(19, 16)
88 #define INIT_THRESHOLD GENMASK(13, 7)
89 #define AVERAGE_BYTES_PER_TU GENMASK(6, 0)
90 #define DPTX_VIDEO_MSA1 0x0324
91 #define VSTART GENMASK(31, 16)
92 #define HSTART GENMASK(15, 0)
93 #define DPTX_VIDEO_MSA2 0x0328
94 #define MISC0 GENMASK(31, 24)
95 #define DPTX_VIDEO_MSA3 0x032c
96 #define MISC1 GENMASK(31, 24)
97 #define DPTX_VIDEO_HBLANK_INTERVAL 0x0330
98 #define HBLANK_INTERVAL_EN BIT(16)
99 #define HBLANK_INTERVAL GENMASK(15, 0)
100
101 #define DPTX_AUD_CONFIG1 0x0400
102 #define AUDIO_TIMESTAMP_VERSION_NUM GENMASK(29, 24)
103 #define AUDIO_PACKET_ID GENMASK(23, 16)
104 #define AUDIO_MUTE BIT(15)
105 #define NUM_CHANNELS GENMASK(14, 12)
106 #define HBR_MODE_ENABLE BIT(10)
107 #define AUDIO_DATA_WIDTH GENMASK(9, 5)
108 #define AUDIO_DATA_IN_EN GENMASK(4, 1)
109 #define AUDIO_INF_SELECT BIT(0)
110
111 #define DPTX_SDP_VERTICAL_CTRL 0x0500
112 #define EN_VERTICAL_SDP BIT(2)
113 #define EN_AUDIO_STREAM_SDP BIT(1)
114 #define EN_AUDIO_TIMESTAMP_SDP BIT(0)
115 #define DPTX_SDP_HORIZONTAL_CTRL 0x0504
116 #define EN_HORIZONTAL_SDP BIT(2)
117 #define DPTX_SDP_STATUS_REGISTER 0x0508
118 #define DPTX_SDP_MANUAL_CTRL 0x050c
119 #define DPTX_SDP_STATUS_EN 0x0510
120
121 #define DPTX_SDP_REGISTER_BANK 0x0600
122 #define SDP_REGS GENMASK(31, 0)
123
124 #define DPTX_PHYIF_CTRL 0x0a00
125 #define PHY_WIDTH BIT(25)
126 #define PHY_POWERDOWN GENMASK(20, 17)
127 #define PHY_BUSY GENMASK(15, 12)
128 #define SSC_DIS BIT(16)
129 #define XMIT_ENABLE GENMASK(11, 8)
130 #define PHY_LANES GENMASK(7, 6)
131 #define PHY_RATE GENMASK(5, 4)
132 #define TPS_SEL GENMASK(3, 0)
133 #define DPTX_PHY_TX_EQ 0x0a04
134 #define DPTX_CUSTOMPAT0 0x0a08
135 #define DPTX_CUSTOMPAT1 0x0a0c
136 #define DPTX_CUSTOMPAT2 0x0a10
137 #define DPTX_HBR2_COMPLIANCE_SCRAMBLER_RESET 0x0a14
138 #define DPTX_PHYIF_PWRDOWN_CTRL 0x0a18
139
140 #define DPTX_AUX_CMD 0x0b00
141 #define AUX_CMD_TYPE GENMASK(31, 28)
142 #define AUX_ADDR GENMASK(27, 8)
143 #define I2C_ADDR_ONLY BIT(4)
144 #define AUX_LEN_REQ GENMASK(3, 0)
145 #define DPTX_AUX_STATUS 0x0b04
146 #define AUX_TIMEOUT BIT(17)
147 #define AUX_BYTES_READ GENMASK(23, 19)
148 #define AUX_STATUS GENMASK(7, 4)
149 #define DPTX_AUX_DATA0 0x0b08
150 #define DPTX_AUX_DATA1 0x0b0c
151 #define DPTX_AUX_DATA2 0x0b10
152 #define DPTX_AUX_DATA3 0x0b14
153
154 #define DPTX_GENERAL_INTERRUPT 0x0d00
155 #define VIDEO_FIFO_OVERFLOW_STREAM0 BIT(6)
156 #define AUDIO_FIFO_OVERFLOW_STREAM0 BIT(5)
157 #define SDP_EVENT_STREAM0 BIT(4)
158 #define AUX_CMD_INVALID BIT(3)
159 #define AUX_REPLY_EVENT BIT(1)
160 #define HPD_EVENT BIT(0)
161 #define DPTX_GENERAL_INTERRUPT_ENABLE 0x0d04
162 #define AUX_REPLY_EVENT_EN BIT(1)
163 #define HPD_EVENT_EN BIT(0)
164 #define DPTX_HPD_STATUS 0x0d08
165 #define HPD_STATE GENMASK(11, 9)
166 #define HPD_STATUS BIT(8)
167 #define HPD_HOT_UNPLUG BIT(2)
168 #define HPD_HOT_PLUG BIT(1)
169 #define HPD_IRQ BIT(0)
170 #define DPTX_HPD_INTERRUPT_ENABLE 0x0d0c
171 #define HPD_UNPLUG_ERR_EN BIT(3)
172 #define HPD_UNPLUG_EN BIT(2)
173 #define HPD_PLUG_EN BIT(1)
174 #define HPD_IRQ_EN BIT(0)
175
176 #define DPTX_MAX_REGISTER DPTX_HPD_INTERRUPT_ENABLE
177
178 #define SDP_REG_BANK_SIZE 16
179
180 struct drm_dp_link_caps {
181 bool enhanced_framing;
182 bool tps3_supported;
183 bool tps4_supported;
184 bool fast_training;
185 bool channel_coding;
186 bool ssc;
187 };
188
189 struct drm_dp_link_train_set {
190 unsigned int voltage_swing[4];
191 unsigned int pre_emphasis[4];
192 };
193
194 struct drm_dp_link_train {
195 struct drm_dp_link_train_set request;
196 struct drm_dp_link_train_set adjust;
197 bool clock_recovered;
198 bool channel_equalized;
199 };
200
201 struct dw_dp_link {
202 u8 dpcd[DP_RECEIVER_CAP_SIZE];
203 unsigned char revision;
204 unsigned int rate;
205 unsigned int lanes;
206 struct drm_dp_link_caps caps;
207 struct drm_dp_link_train train;
208 struct drm_dp_desc desc;
209 u8 sink_count;
210 u8 vsc_sdp_extension_for_colorimetry_supported;
211 };
212
213 struct dw_dp_video {
214 struct drm_display_mode mode;
215 u32 bus_format;
216 u8 video_mapping;
217 u8 pixel_mode;
218 u8 color_format;
219 u8 bpc;
220 u8 bpp;
221 };
222
223 struct dw_dp_audio {
224 struct platform_device *pdev;
225 u8 channels;
226 };
227
228 struct dw_dp_sdp {
229 struct dp_sdp_header header;
230 u8 db[32];
231 unsigned long flags;
232 };
233
234 struct dw_dp_hotplug {
235 bool long_hpd;
236 bool status;
237 };
238
239 struct dw_dp {
240 struct device *dev;
241 struct regmap *regmap;
242 struct phy *phy;
243 struct clk_bulk_data *clks;
244 int nr_clks;
245 struct reset_control *rstc;
246 struct regmap *grf;
247 struct completion complete;
248 int irq;
249 int id;
250 bool phy_enabled;
251 struct work_struct hpd_work;
252 struct gpio_desc *hpd_gpio;
253 struct dw_dp_hotplug hotplug;
254 struct mutex irq_lock;
255
256 struct drm_bridge bridge;
257 struct drm_connector connector;
258 struct drm_encoder encoder;
259 struct drm_dp_aux aux;
260
261 struct dw_dp_link link;
262 struct dw_dp_video video;
263 struct dw_dp_audio audio;
264
265 DECLARE_BITMAP(sdp_reg_bank, SDP_REG_BANK_SIZE);
266
267 bool split_mode;
268 struct dw_dp *left;
269 struct dw_dp *right;
270 };
271
272 enum {
273 DPTX_VM_RGB_6BIT,
274 DPTX_VM_RGB_8BIT,
275 DPTX_VM_RGB_10BIT,
276 DPTX_VM_RGB_12BIT,
277 DPTX_VM_RGB_16BIT,
278 DPTX_VM_YCBCR444_8BIT,
279 DPTX_VM_YCBCR444_10BIT,
280 DPTX_VM_YCBCR444_12BIT,
281 DPTX_VM_YCBCR444_16BIT,
282 DPTX_VM_YCBCR422_8BIT,
283 DPTX_VM_YCBCR422_10BIT,
284 DPTX_VM_YCBCR422_12BIT,
285 DPTX_VM_YCBCR422_16BIT,
286 DPTX_VM_YCBCR420_8BIT,
287 DPTX_VM_YCBCR420_10BIT,
288 DPTX_VM_YCBCR420_12BIT,
289 DPTX_VM_YCBCR420_16BIT,
290 };
291
292 enum {
293 DPTX_MP_SINGLE_PIXEL,
294 DPTX_MP_DUAL_PIXEL,
295 DPTX_MP_QUAD_PIXEL,
296 };
297
298 enum {
299 DPTX_SDP_VERTICAL_INTERVAL = BIT(0),
300 DPTX_SDP_HORIZONTAL_INTERVAL = BIT(1),
301 };
302
303 enum { SOURCE_STATE_IDLE, SOURCE_STATE_UNPLUG, SOURCE_STATE_HPD_TIMEOUT = 4, SOURCE_STATE_PLUG = 7 };
304
305 enum {
306 DPTX_PHY_PATTERN_NONE,
307 DPTX_PHY_PATTERN_TPS_1,
308 DPTX_PHY_PATTERN_TPS_2,
309 DPTX_PHY_PATTERN_TPS_3,
310 DPTX_PHY_PATTERN_TPS_4,
311 DPTX_PHY_PATTERN_SERM,
312 DPTX_PHY_PATTERN_PBRS7,
313 DPTX_PHY_PATTERN_CUSTOM_80BIT,
314 DPTX_PHY_PATTERN_CP2520_1,
315 DPTX_PHY_PATTERN_CP2520_2,
316 };
317
318 struct dw_dp_output_format {
319 u32 bus_format;
320 u32 color_format;
321 u8 video_mapping;
322 u8 bpc;
323 u8 bpp;
324 };
325
326 static const struct dw_dp_output_format possible_output_fmts[] = {
327 {MEDIA_BUS_FMT_RGB101010_1X30, DRM_COLOR_FORMAT_RGB444, DPTX_VM_RGB_10BIT, 10, 30},
328 {MEDIA_BUS_FMT_RGB888_1X24, DRM_COLOR_FORMAT_RGB444, DPTX_VM_RGB_8BIT, 8, 24},
329 {MEDIA_BUS_FMT_YUV10_1X30, DRM_COLOR_FORMAT_YCRCB444, DPTX_VM_YCBCR444_10BIT, 10, 30},
330 {MEDIA_BUS_FMT_YUV8_1X24, DRM_COLOR_FORMAT_YCRCB444, DPTX_VM_YCBCR444_8BIT, 8, 24},
331 {MEDIA_BUS_FMT_YUYV10_1X20, DRM_COLOR_FORMAT_YCRCB422, DPTX_VM_YCBCR422_10BIT, 10, 20},
332 {MEDIA_BUS_FMT_YUYV8_1X16, DRM_COLOR_FORMAT_YCRCB422, DPTX_VM_YCBCR422_8BIT, 8, 16},
333 {MEDIA_BUS_FMT_UYYVYY10_0_5X30, DRM_COLOR_FORMAT_YCRCB420, DPTX_VM_YCBCR420_10BIT, 10, 15},
334 {MEDIA_BUS_FMT_UYYVYY8_0_5X24, DRM_COLOR_FORMAT_YCRCB420, DPTX_VM_YCBCR420_8BIT, 8, 12},
335 {MEDIA_BUS_FMT_RGB666_1X24_CPADHI, DRM_COLOR_FORMAT_RGB444, DPTX_VM_RGB_6BIT, 6, 18},
336 };
337
dw_dp_get_output_format(u32 bus_format)338 static const struct dw_dp_output_format *dw_dp_get_output_format(u32 bus_format)
339 {
340 unsigned int i;
341
342 for (i = 0; i < ARRAY_SIZE(possible_output_fmts); i++) {
343 if (possible_output_fmts[i].bus_format == bus_format) {
344 return &possible_output_fmts[i];
345 }
346 }
347
348 return &possible_output_fmts[1];
349 }
350
connector_to_dp(struct drm_connector * c)351 static inline struct dw_dp *connector_to_dp(struct drm_connector *c)
352 {
353 return container_of(c, struct dw_dp, connector);
354 }
355
encoder_to_dp(struct drm_encoder * e)356 static inline struct dw_dp *encoder_to_dp(struct drm_encoder *e)
357 {
358 return container_of(e, struct dw_dp, encoder);
359 }
360
bridge_to_dp(struct drm_bridge * b)361 static inline struct dw_dp *bridge_to_dp(struct drm_bridge *b)
362 {
363 return container_of(b, struct dw_dp, bridge);
364 }
365
dw_dp_match_by_id(struct device * dev,const void * data)366 static int dw_dp_match_by_id(struct device *dev, const void *data)
367 {
368 struct dw_dp *dp = dev_get_drvdata(dev);
369 const unsigned int *id = data;
370
371 return dp->id == *id;
372 }
373
dw_dp_find_by_id(struct device_driver * drv,unsigned int id)374 static struct dw_dp *dw_dp_find_by_id(struct device_driver *drv, unsigned int id)
375 {
376 struct device *dev;
377
378 dev = driver_find_device(drv, NULL, &id, dw_dp_match_by_id);
379 if (!dev) {
380 return NULL;
381 }
382
383 return dev_get_drvdata(dev);
384 }
385
dw_dp_phy_set_pattern(struct dw_dp * dp,u32 pattern)386 static void dw_dp_phy_set_pattern(struct dw_dp *dp, u32 pattern)
387 {
388 regmap_update_bits(dp->regmap, DPTX_PHYIF_CTRL, TPS_SEL, FIELD_PREP(TPS_SEL, pattern));
389 }
390
dw_dp_phy_xmit_enable(struct dw_dp * dp,u32 lanes)391 static void dw_dp_phy_xmit_enable(struct dw_dp *dp, u32 lanes)
392 {
393 u32 xmit_enable;
394
395 switch (lanes) {
396 case 0x4:
397 case 0x2:
398 case 0x1:
399 xmit_enable = GENMASK(lanes - 1, 0);
400 break;
401 case 0:
402 default:
403 xmit_enable = 0;
404 break;
405 }
406
407 regmap_update_bits(dp->regmap, DPTX_PHYIF_CTRL, XMIT_ENABLE, FIELD_PREP(XMIT_ENABLE, xmit_enable));
408 }
409
dw_dp_phy_power_on(struct dw_dp * dp)410 static void dw_dp_phy_power_on(struct dw_dp *dp)
411 {
412 phy_power_on(dp->phy);
413
414 dp->phy_enabled = true;
415 }
416
dw_dp_phy_power_off(struct dw_dp * dp)417 static void dw_dp_phy_power_off(struct dw_dp *dp)
418 {
419 phy_power_off(dp->phy);
420
421 dp->phy_enabled = false;
422 }
423
dw_dp_bandwidth_ok(struct dw_dp * dp,const struct drm_display_mode * mode,u32 bpp,unsigned int lanes,unsigned int rate)424 static bool dw_dp_bandwidth_ok(struct dw_dp *dp, const struct drm_display_mode *mode, u32 bpp, unsigned int lanes,
425 unsigned int rate)
426 {
427 u32 max_bw, req_bw;
428
429 req_bw = mode->clock * bpp / 0x8;
430 max_bw = lanes * rate;
431 if (req_bw > max_bw) {
432 return false;
433 }
434
435 return true;
436 }
437
dw_dp_detect(struct dw_dp * dp)438 static bool dw_dp_detect(struct dw_dp *dp)
439 {
440 u32 value;
441
442 if (dp->hpd_gpio) {
443 return gpiod_get_value_cansleep(dp->hpd_gpio);
444 }
445
446 regmap_read(dp->regmap, DPTX_HPD_STATUS, &value);
447
448 return FIELD_GET(HPD_STATE, value) == SOURCE_STATE_PLUG;
449 }
450
dw_dp_connector_detect(struct drm_connector * connector,bool force)451 static enum drm_connector_status dw_dp_connector_detect(struct drm_connector *connector, bool force)
452 {
453 struct dw_dp *dp = connector_to_dp(connector);
454
455 if (dp->right && drm_bridge_detect(&dp->right->bridge) != connector_status_connected) {
456 return connector_status_disconnected;
457 }
458
459 return drm_bridge_detect(&dp->bridge);
460 }
461
462 static const struct drm_connector_funcs dw_dp_connector_funcs = {
463 .detect = dw_dp_connector_detect,
464 .fill_modes = drm_helper_probe_single_connector_modes,
465 .destroy = drm_connector_cleanup,
466 .reset = drm_atomic_helper_connector_reset,
467 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
468 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
469 };
470
dw_dp_connector_get_modes(struct drm_connector * connector)471 static int dw_dp_connector_get_modes(struct drm_connector *connector)
472 {
473 struct dw_dp *dp = connector_to_dp(connector);
474 struct drm_display_info *di = &connector->display_info;
475 struct edid *edid;
476 int num_modes;
477
478 edid = drm_bridge_get_edid(&dp->bridge, connector);
479 if (!edid) {
480 DRM_DEV_ERROR(dp->dev, "failed to get edid\n");
481 return 0;
482 }
483
484 drm_connector_update_edid_property(connector, edid);
485 num_modes = drm_add_edid_modes(connector, edid);
486 kfree(edid);
487
488 if (num_modes > 0 && dp->split_mode) {
489 struct drm_display_mode *mode;
490
491 di->width_mm *= 0x2;
492
493 list_for_each_entry(mode, &connector->probed_modes, head) drm_mode_convert_to_split_mode(mode);
494 }
495
496 return num_modes;
497 }
498
499 static const struct drm_connector_helper_funcs dw_dp_connector_helper_funcs = {
500 .get_modes = dw_dp_connector_get_modes,
501 };
502
dw_dp_link_caps_reset(struct drm_dp_link_caps * caps)503 static void dw_dp_link_caps_reset(struct drm_dp_link_caps *caps)
504 {
505 caps->enhanced_framing = false;
506 caps->tps3_supported = false;
507 caps->tps4_supported = false;
508 caps->fast_training = false;
509 caps->channel_coding = false;
510 }
511
dw_dp_link_reset(struct dw_dp_link * link)512 static void dw_dp_link_reset(struct dw_dp_link *link)
513 {
514 link->vsc_sdp_extension_for_colorimetry_supported = 0;
515 link->sink_count = 0;
516 link->revision = 0;
517
518 dw_dp_link_caps_reset(&link->caps);
519 memset(link->dpcd, 0, sizeof(link->dpcd));
520
521 link->rate = 0;
522 link->lanes = 0;
523 }
524
dw_dp_link_power_up(struct dw_dp * dp)525 static int dw_dp_link_power_up(struct dw_dp *dp)
526 {
527 struct dw_dp_link *link = &dp->link;
528 u8 value;
529 int ret;
530
531 if (link->revision < 0x11) {
532 return 0;
533 }
534
535 ret = drm_dp_dpcd_readb(&dp->aux, DP_SET_POWER, &value);
536 if (ret < 0) {
537 return ret;
538 }
539
540 value &= ~DP_SET_POWER_MASK;
541 value |= DP_SET_POWER_D0;
542
543 ret = drm_dp_dpcd_writeb(&dp->aux, DP_SET_POWER, value);
544 if (ret < 0) {
545 return ret;
546 }
547
548 usleep_range(0x3e8, 0x7d0);
549
550 return 0;
551 }
552
dw_dp_link_power_down(struct dw_dp * dp)553 static int dw_dp_link_power_down(struct dw_dp *dp)
554 {
555 struct dw_dp_link *link = &dp->link;
556 u8 value;
557 int ret;
558
559 if (link->revision < 0x11) {
560 return 0;
561 }
562
563 ret = drm_dp_dpcd_readb(&dp->aux, DP_SET_POWER, &value);
564 if (ret < 0) {
565 return ret;
566 }
567
568 value &= ~DP_SET_POWER_MASK;
569 value |= DP_SET_POWER_D3;
570
571 ret = drm_dp_dpcd_writeb(&dp->aux, DP_SET_POWER, value);
572 if (ret < 0) {
573 return ret;
574 }
575
576 return 0;
577 }
578
dw_dp_has_sink_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE],const struct drm_dp_desc * desc)579 static bool dw_dp_has_sink_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE], const struct drm_dp_desc *desc)
580 {
581 return (dpcd[DP_DPCD_REV] >= DP_DPCD_REV_11) && (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT) &&
582 !drm_dp_has_quirk(desc, 0, DP_DPCD_QUIRK_NO_SINK_COUNT);
583 }
584
dw_dp_link_probe(struct dw_dp * dp)585 static int dw_dp_link_probe(struct dw_dp *dp)
586 {
587 struct dw_dp_link *link = &dp->link;
588 u8 dpcd;
589 int ret;
590
591 dw_dp_link_reset(link);
592
593 ret = drm_dp_read_dpcd_caps(&dp->aux, link->dpcd);
594 if (ret < 0) {
595 return ret;
596 }
597
598 drm_dp_read_desc(&dp->aux, &link->desc, drm_dp_is_branch(link->dpcd));
599
600 if (dw_dp_has_sink_count(link->dpcd, &link->desc)) {
601 ret = drm_dp_read_sink_count(&dp->aux);
602 if (ret < 0) {
603 return ret;
604 }
605
606 link->sink_count = ret;
607
608 /* Dongle connected, but no display */
609 if (!link->sink_count) {
610 return -ENODEV;
611 }
612 }
613
614 ret = drm_dp_dpcd_readb(&dp->aux, DP_DPRX_FEATURE_ENUMERATION_LIST, &dpcd);
615 if (ret < 0) {
616 return ret;
617 }
618
619 link->vsc_sdp_extension_for_colorimetry_supported = !!(dpcd & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED);
620
621 link->revision = link->dpcd[DP_DPCD_REV];
622 link->rate = drm_dp_max_link_rate(link->dpcd);
623 link->lanes = min_t(u8, phy_get_bus_width(dp->phy), drm_dp_max_lane_count(link->dpcd));
624
625 link->caps.enhanced_framing = drm_dp_enhanced_frame_cap(link->dpcd);
626 link->caps.tps3_supported = drm_dp_tps3_supported(link->dpcd);
627 link->caps.tps4_supported = drm_dp_tps4_supported(link->dpcd);
628 link->caps.fast_training = drm_dp_fast_training_cap(link->dpcd);
629 link->caps.channel_coding = drm_dp_channel_coding_supported(link->dpcd);
630 link->caps.ssc = !!(link->dpcd[DP_MAX_DOWNSPREAD] & DP_MAX_DOWNSPREAD_0_5);
631
632 return 0;
633 }
634
dw_dp_link_train_update_vs_emph(struct dw_dp * dp)635 static int dw_dp_link_train_update_vs_emph(struct dw_dp *dp)
636 {
637 struct dw_dp_link *link = &dp->link;
638 struct drm_dp_link_train_set *request = &link->train.request;
639 union phy_configure_opts phy_cfg;
640 unsigned int lanes = link->lanes, *vs, *pe;
641 u8 buf[0x4];
642 int i, ret;
643
644 vs = request->voltage_swing;
645 pe = request->pre_emphasis;
646
647 for (i = 0; i < lanes; i++) {
648 phy_cfg.dp.voltage[i] = vs[i];
649 phy_cfg.dp.pre[i] = pe[i];
650 }
651 phy_cfg.dp.lanes = lanes;
652 phy_cfg.dp.link_rate = link->rate / 0x64;
653 phy_cfg.dp.set_lanes = false;
654 phy_cfg.dp.set_rate = false;
655 phy_cfg.dp.set_voltages = true;
656 ret = phy_configure(dp->phy, &phy_cfg);
657 if (ret) {
658 return ret;
659 }
660
661 for (i = 0; i < lanes; i++) {
662 buf[i] = (vs[i] << DP_TRAIN_VOLTAGE_SWING_SHIFT) | (pe[i] << DP_TRAIN_PRE_EMPHASIS_SHIFT);
663 }
664 ret = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET, buf, lanes);
665 if (ret < 0) {
666 return ret;
667 }
668
669 return 0;
670 }
671
dw_dp_link_configure(struct dw_dp * dp)672 static int dw_dp_link_configure(struct dw_dp *dp)
673 {
674 struct dw_dp_link *link = &dp->link;
675 union phy_configure_opts phy_cfg;
676 u8 buf[0x2];
677 int ret;
678
679 /* Move PHY to P3 */
680 regmap_update_bits(dp->regmap, DPTX_PHYIF_CTRL, PHY_POWERDOWN, FIELD_PREP(PHY_POWERDOWN, 0x3));
681
682 phy_cfg.dp.lanes = link->lanes;
683 phy_cfg.dp.link_rate = link->rate / 0x64;
684 phy_cfg.dp.ssc = link->caps.ssc;
685 phy_cfg.dp.set_lanes = true;
686 phy_cfg.dp.set_rate = true;
687 phy_cfg.dp.set_voltages = false;
688 ret = phy_configure(dp->phy, &phy_cfg);
689 if (ret) {
690 return ret;
691 }
692
693 regmap_update_bits(dp->regmap, DPTX_PHYIF_CTRL, PHY_LANES, FIELD_PREP(PHY_LANES, link->lanes / 0x2));
694
695 /* Move PHY to P0 */
696 regmap_update_bits(dp->regmap, DPTX_PHYIF_CTRL, PHY_POWERDOWN, FIELD_PREP(PHY_POWERDOWN, 0x0));
697
698 dw_dp_phy_xmit_enable(dp, link->lanes);
699
700 buf[0] = drm_dp_link_rate_to_bw_code(link->rate);
701 buf[1] = link->lanes;
702
703 if (link->caps.enhanced_framing) {
704 buf[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
705 regmap_update_bits(dp->regmap, DPTX_CCTL, ENHANCE_FRAMING_EN, FIELD_PREP(ENHANCE_FRAMING_EN, 1));
706 } else {
707 regmap_update_bits(dp->regmap, DPTX_CCTL, ENHANCE_FRAMING_EN, FIELD_PREP(ENHANCE_FRAMING_EN, 0));
708 }
709
710 ret = drm_dp_dpcd_write(&dp->aux, DP_LINK_BW_SET, buf, sizeof(buf));
711 if (ret < 0) {
712 return ret;
713 }
714
715 buf[0] = link->caps.ssc ? DP_SPREAD_AMP_0_5 : 0;
716 buf[1] = link->caps.channel_coding ? DP_SET_ANSI_8B10B : 0;
717
718 ret = drm_dp_dpcd_write(&dp->aux, DP_DOWNSPREAD_CTRL, buf, sizeof(buf));
719 if (ret < 0) {
720 return ret;
721 }
722
723 return 0;
724 }
725
dw_dp_link_train_init(struct drm_dp_link_train * train)726 static void dw_dp_link_train_init(struct drm_dp_link_train *train)
727 {
728 struct drm_dp_link_train_set *request = &train->request;
729 struct drm_dp_link_train_set *adjust = &train->adjust;
730 unsigned int i;
731
732 for (i = 0; i < 0x4; i++) {
733 request->voltage_swing[i] = 0;
734 adjust->voltage_swing[i] = 0;
735
736 request->pre_emphasis[i] = 0;
737 adjust->pre_emphasis[i] = 0;
738 }
739
740 train->clock_recovered = false;
741 train->channel_equalized = false;
742 }
743
dw_dp_link_train_valid(const struct drm_dp_link_train * train)744 static bool dw_dp_link_train_valid(const struct drm_dp_link_train *train)
745 {
746 return train->clock_recovered && train->channel_equalized;
747 }
748
dw_dp_link_train_set_pattern(struct dw_dp * dp,u32 pattern)749 static int dw_dp_link_train_set_pattern(struct dw_dp *dp, u32 pattern)
750 {
751 u8 buf = 0;
752 int ret;
753
754 if (pattern && pattern != DP_TRAINING_PATTERN_4) {
755 buf |= DP_LINK_SCRAMBLING_DISABLE;
756
757 regmap_update_bits(dp->regmap, DPTX_CCTL, SCRAMBLE_DIS, FIELD_PREP(SCRAMBLE_DIS, 1));
758 } else {
759 regmap_update_bits(dp->regmap, DPTX_CCTL, SCRAMBLE_DIS, FIELD_PREP(SCRAMBLE_DIS, 0));
760 }
761
762 switch (pattern) {
763 case DP_TRAINING_PATTERN_DISABLE:
764 dw_dp_phy_set_pattern(dp, DPTX_PHY_PATTERN_NONE);
765 break;
766 case DP_TRAINING_PATTERN_1:
767 dw_dp_phy_set_pattern(dp, DPTX_PHY_PATTERN_TPS_1);
768 break;
769 case DP_TRAINING_PATTERN_2:
770 dw_dp_phy_set_pattern(dp, DPTX_PHY_PATTERN_TPS_2);
771 break;
772 case DP_TRAINING_PATTERN_3:
773 dw_dp_phy_set_pattern(dp, DPTX_PHY_PATTERN_TPS_3);
774 break;
775 case DP_TRAINING_PATTERN_4:
776 dw_dp_phy_set_pattern(dp, DPTX_PHY_PATTERN_TPS_4);
777 break;
778 default:
779 return -EINVAL;
780 }
781
782 ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET, buf | pattern);
783 if (ret < 0) {
784 return ret;
785 }
786
787 return 0;
788 }
789
dw_dp_link_get_adjustments(struct dw_dp_link * link,u8 status[DP_LINK_STATUS_SIZE])790 static void dw_dp_link_get_adjustments(struct dw_dp_link *link, u8 status[DP_LINK_STATUS_SIZE])
791 {
792 struct drm_dp_link_train_set *adjust = &link->train.adjust;
793 unsigned int i;
794
795 for (i = 0; i < link->lanes; i++) {
796 adjust->voltage_swing[i] = drm_dp_get_adjust_request_voltage(status, i) >> DP_TRAIN_VOLTAGE_SWING_SHIFT;
797
798 adjust->pre_emphasis[i] = drm_dp_get_adjust_request_pre_emphasis(status, i) >> DP_TRAIN_PRE_EMPHASIS_SHIFT;
799 }
800 }
801
dw_dp_link_train_adjust(struct drm_dp_link_train * train)802 static void dw_dp_link_train_adjust(struct drm_dp_link_train *train)
803 {
804 struct drm_dp_link_train_set *request = &train->request;
805 struct drm_dp_link_train_set *adjust = &train->adjust;
806 unsigned int i;
807
808 for (i = 0; i < 0x4; i++) {
809 if (request->voltage_swing[i] != adjust->voltage_swing[i]) {
810 request->voltage_swing[i] = adjust->voltage_swing[i];
811 }
812 }
813
814 for (i = 0; i < 0x4; i++) {
815 if (request->pre_emphasis[i] != adjust->pre_emphasis[i]) {
816 request->pre_emphasis[i] = adjust->pre_emphasis[i];
817 }
818 }
819 }
820
dw_dp_link_clock_recovery(struct dw_dp * dp)821 static int dw_dp_link_clock_recovery(struct dw_dp *dp)
822 {
823 struct dw_dp_link *link = &dp->link;
824 u8 status[DP_LINK_STATUS_SIZE];
825 unsigned int tries = 0;
826 int ret;
827
828 ret = dw_dp_link_train_set_pattern(dp, DP_TRAINING_PATTERN_1);
829 if (ret) {
830 return ret;
831 }
832
833 for (;;) {
834 ret = dw_dp_link_train_update_vs_emph(dp);
835 if (ret) {
836 return ret;
837 }
838
839 drm_dp_link_train_clock_recovery_delay(link->dpcd);
840
841 ret = drm_dp_dpcd_read_link_status(&dp->aux, status);
842 if (ret < 0) {
843 dev_err(dp->dev, "failed to read link status: %d\n", ret);
844 return ret;
845 }
846
847 if (drm_dp_clock_recovery_ok(status, link->lanes)) {
848 link->train.clock_recovered = true;
849 break;
850 }
851
852 dw_dp_link_get_adjustments(link, status);
853
854 if (link->train.request.voltage_swing[0] == link->train.adjust.voltage_swing[0]) {
855 tries++;
856 } else {
857 tries = 0;
858 }
859
860 if (tries == 0x5) {
861 break;
862 }
863
864 dw_dp_link_train_adjust(&link->train);
865 }
866
867 return 0;
868 }
869
dw_dp_link_channel_equalization(struct dw_dp * dp)870 static int dw_dp_link_channel_equalization(struct dw_dp *dp)
871 {
872 struct dw_dp_link *link = &dp->link;
873 u8 status[DP_LINK_STATUS_SIZE], pattern;
874 unsigned int tries;
875 int ret;
876
877 if (link->caps.tps4_supported) {
878 pattern = DP_TRAINING_PATTERN_4;
879 } else if (link->caps.tps3_supported) {
880 pattern = DP_TRAINING_PATTERN_3;
881 } else {
882 pattern = DP_TRAINING_PATTERN_2;
883 }
884 ret = dw_dp_link_train_set_pattern(dp, pattern);
885 if (ret) {
886 return ret;
887 }
888
889 for (tries = 1; tries < 0x5; tries++) {
890 ret = dw_dp_link_train_update_vs_emph(dp);
891 if (ret) {
892 return ret;
893 }
894
895 drm_dp_link_train_channel_eq_delay(link->dpcd);
896
897 ret = drm_dp_dpcd_read_link_status(&dp->aux, status);
898 if (ret < 0) {
899 return ret;
900 }
901
902 if (!drm_dp_clock_recovery_ok(status, link->lanes)) {
903 dev_err(dp->dev, "clock recovery lost while equalizing channel\n");
904 link->train.clock_recovered = false;
905 break;
906 }
907
908 if (drm_dp_channel_eq_ok(status, link->lanes)) {
909 link->train.channel_equalized = true;
910 break;
911 }
912
913 dw_dp_link_get_adjustments(link, status);
914 dw_dp_link_train_adjust(&link->train);
915 }
916
917 return 0;
918 }
919
dw_dp_link_downgrade(struct dw_dp * dp)920 static int dw_dp_link_downgrade(struct dw_dp *dp)
921 {
922 struct dw_dp_link *link = &dp->link;
923 struct dw_dp_video *video = &dp->video;
924
925 switch (link->rate) {
926 case 0x278d0:
927 return -EINVAL;
928 case 0x41eb0:
929 link->rate = 0x278d0;
930 break;
931 case 0x83d60:
932 link->rate = 0x41eb0;
933 break;
934 case 0xc5c10:
935 link->rate = 0x83d60;
936 break;
937 default:
938 break;
939 }
940
941 if (!dw_dp_bandwidth_ok(dp, &video->mode, video->bpp, link->lanes, link->rate)) {
942 return -E2BIG;
943 }
944
945 return 0;
946 }
947
dw_dp_link_train_full(struct dw_dp * dp)948 static int dw_dp_link_train_full(struct dw_dp *dp)
949 {
950 struct dw_dp_link *link = &dp->link;
951 int ret;
952
953 while (1) {
954 dw_dp_link_train_init(&link->train);
955
956 dev_info(dp->dev, "full-training link: %u lane%s at %u MHz\n", link->lanes, (link->lanes > 1) ? "s" : "",
957 link->rate / 0x64);
958
959 ret = dw_dp_link_configure(dp);
960 if (ret < 0) {
961 dev_err(dp->dev, "failed to configure DP link: %d\n", ret);
962 return ret;
963 }
964
965 ret = dw_dp_link_clock_recovery(dp);
966 if (ret < 0) {
967 dev_err(dp->dev, "clock recovery failed: %d\n", ret);
968 goto out;
969 }
970
971 if (!link->train.clock_recovered) {
972 dev_err(dp->dev, "clock recovery failed, downgrading link\n");
973
974 ret = dw_dp_link_downgrade(dp);
975 if (ret < 0) {
976 goto out;
977 } else {
978 continue;
979 }
980 }
981
982 dev_info(dp->dev, "clock recovery succeeded\n");
983
984 ret = dw_dp_link_channel_equalization(dp);
985 if (ret < 0) {
986 dev_err(dp->dev, "channel equalization failed: %d\n", ret);
987 goto out;
988 }
989
990 if (!link->train.channel_equalized) {
991 dev_err(dp->dev, "channel equalization failed, downgrading link\n");
992
993 ret = dw_dp_link_downgrade(dp);
994 if (ret < 0) {
995 goto out;
996 } else {
997 continue;
998 }
999 }
1000 break;
1001 }
1002 dev_info(dp->dev, "channel equalization succeeded\n");
1003
1004 out:
1005 dw_dp_link_train_set_pattern(dp, DP_TRAINING_PATTERN_DISABLE);
1006 return ret;
1007 }
1008
dw_dp_link_train_fast(struct dw_dp * dp)1009 static int dw_dp_link_train_fast(struct dw_dp *dp)
1010 {
1011 struct dw_dp_link *link = &dp->link;
1012 u8 status[DP_LINK_STATUS_SIZE], pattern;
1013 int ret;
1014
1015 dw_dp_link_train_init(&link->train);
1016
1017 dev_info(dp->dev, "fast-training link: %u lane%s at %u MHz\n", link->lanes, (link->lanes > 1) ? "s" : "",
1018 link->rate / 0x64);
1019
1020 ret = dw_dp_link_configure(dp);
1021 if (ret < 0) {
1022 dev_err(dp->dev, "failed to configure DP link: %d\n", ret);
1023 return ret;
1024 }
1025
1026 ret = dw_dp_link_train_set_pattern(dp, DP_TRAINING_PATTERN_1);
1027 if (ret) {
1028 goto out;
1029 }
1030
1031 usleep_range(0x1f4, 0x3e8);
1032
1033 if (link->caps.tps4_supported) {
1034 pattern = DP_TRAINING_PATTERN_4;
1035 } else if (link->caps.tps3_supported) {
1036 pattern = DP_TRAINING_PATTERN_3;
1037 } else {
1038 pattern = DP_TRAINING_PATTERN_2;
1039 }
1040 ret = dw_dp_link_train_set_pattern(dp, pattern);
1041 if (ret) {
1042 goto out;
1043 }
1044
1045 usleep_range(0x1f4, 0x3e8);
1046
1047 ret = drm_dp_dpcd_read_link_status(&dp->aux, status);
1048 if (ret < 0) {
1049 dev_err(dp->dev, "failed to read link status: %d\n", ret);
1050 goto out;
1051 }
1052
1053 if (!drm_dp_clock_recovery_ok(status, link->lanes)) {
1054 dev_err(dp->dev, "clock recovery failed\n");
1055 ret = -EIO;
1056 goto out;
1057 }
1058
1059 if (!drm_dp_channel_eq_ok(status, link->lanes)) {
1060 dev_err(dp->dev, "channel equalization failed\n");
1061 ret = -EIO;
1062 goto out;
1063 }
1064
1065 out:
1066 dw_dp_link_train_set_pattern(dp, DP_TRAINING_PATTERN_DISABLE);
1067 return ret;
1068 }
1069
dw_dp_link_train(struct dw_dp * dp)1070 static int dw_dp_link_train(struct dw_dp *dp)
1071 {
1072 struct dw_dp_link *link = &dp->link;
1073 int ret;
1074
1075 if (link->caps.fast_training) {
1076 if (dw_dp_link_train_valid(&link->train)) {
1077 ret = dw_dp_link_train_fast(dp);
1078 if (ret < 0) {
1079 dev_err(dp->dev, "fast link training failed: %d\n", ret);
1080 } else {
1081 return 0;
1082 }
1083 }
1084 }
1085
1086 ret = dw_dp_link_train_full(dp);
1087 if (ret < 0) {
1088 dev_err(dp->dev, "full link training failed: %d\n", ret);
1089 return ret;
1090 }
1091
1092 return 0;
1093 }
1094
dw_dp_send_sdp(struct dw_dp * dp,struct dw_dp_sdp * sdp)1095 static int dw_dp_send_sdp(struct dw_dp *dp, struct dw_dp_sdp *sdp)
1096 {
1097 const u8 *payload = sdp->db;
1098 u32 reg;
1099 int i, nr;
1100
1101 nr = find_first_zero_bit(dp->sdp_reg_bank, SDP_REG_BANK_SIZE);
1102 if (nr < SDP_REG_BANK_SIZE) {
1103 set_bit(nr, dp->sdp_reg_bank);
1104 } else {
1105 return -EBUSY;
1106 }
1107
1108 reg = DPTX_SDP_REGISTER_BANK + nr * 0x9 * 0x4;
1109
1110 /* SDP header */
1111 regmap_write(dp->regmap, reg, get_unaligned_le32(&sdp->header));
1112
1113 /* SDP data payload */
1114 for (i = 0x1; i < 0x9; i++, payload += 0x4) {
1115 regmap_write(dp->regmap, reg + i * 0x4, FIELD_PREP(SDP_REGS, get_unaligned_le32(payload)));
1116 }
1117
1118 if (sdp->flags & DPTX_SDP_VERTICAL_INTERVAL) {
1119 regmap_update_bits(dp->regmap, DPTX_SDP_VERTICAL_CTRL, EN_VERTICAL_SDP << nr, EN_VERTICAL_SDP << nr);
1120 }
1121
1122 if (sdp->flags & DPTX_SDP_HORIZONTAL_INTERVAL) {
1123 regmap_update_bits(dp->regmap, DPTX_SDP_HORIZONTAL_CTRL, EN_HORIZONTAL_SDP << nr, EN_HORIZONTAL_SDP << nr);
1124 }
1125
1126 return 0;
1127 }
1128
dw_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp * vsc,struct dw_dp_sdp * sdp)1129 static void dw_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc, struct dw_dp_sdp *sdp)
1130 {
1131 sdp->header.HB0 = 0;
1132 sdp->header.HB1 = DP_SDP_VSC;
1133 sdp->header.HB2 = vsc->revision;
1134 sdp->header.HB3 = vsc->length;
1135
1136 sdp->db[0x10] = (vsc->pixelformat & 0xf) << 0x4;
1137 sdp->db[0x10] |= vsc->colorimetry & 0xf;
1138
1139 switch (vsc->bpc) {
1140 case 0x8:
1141 sdp->db[0x11] = 0x1;
1142 break;
1143 case 0xa:
1144 sdp->db[0x11] = 0x2;
1145 break;
1146 case 0xc:
1147 sdp->db[0x11] = 0x3;
1148 break;
1149 case 0x10:
1150 sdp->db[0x11] = 0x4;
1151 break;
1152 case 0x6:
1153 default:
1154 break;
1155 }
1156
1157 if (vsc->dynamic_range == DP_DYNAMIC_RANGE_CTA) {
1158 sdp->db[0x11] |= 0x80;
1159 }
1160
1161 sdp->db[0x12] = vsc->content_type & 0x7;
1162
1163 sdp->flags |= DPTX_SDP_VERTICAL_INTERVAL;
1164 }
1165
dw_dp_send_vsc_sdp(struct dw_dp * dp)1166 static int dw_dp_send_vsc_sdp(struct dw_dp *dp)
1167 {
1168 struct dw_dp_video *video = &dp->video;
1169 struct drm_dp_vsc_sdp vsc = {};
1170 struct dw_dp_sdp sdp = {};
1171
1172 vsc.revision = 0x5;
1173 vsc.length = 0x13;
1174
1175 switch (video->color_format) {
1176 case DRM_COLOR_FORMAT_YCRCB444:
1177 vsc.pixelformat = DP_PIXELFORMAT_YUV444;
1178 break;
1179 case DRM_COLOR_FORMAT_YCRCB420:
1180 vsc.pixelformat = DP_PIXELFORMAT_YUV420;
1181 break;
1182 case DRM_COLOR_FORMAT_YCRCB422:
1183 vsc.pixelformat = DP_PIXELFORMAT_YUV422;
1184 break;
1185 case DRM_COLOR_FORMAT_RGB444:
1186 default:
1187 vsc.pixelformat = DP_PIXELFORMAT_RGB;
1188 break;
1189 }
1190
1191 if (video->color_format == DRM_COLOR_FORMAT_RGB444) {
1192 vsc.colorimetry = DP_COLORIMETRY_DEFAULT;
1193 } else {
1194 vsc.colorimetry = DP_COLORIMETRY_BT709_YCC;
1195 }
1196
1197 vsc.bpc = video->bpc;
1198 vsc.dynamic_range = DP_DYNAMIC_RANGE_CTA;
1199 vsc.content_type = DP_CONTENT_TYPE_NOT_DEFINED;
1200
1201 dw_dp_vsc_sdp_pack(&vsc, &sdp);
1202
1203 return dw_dp_send_sdp(dp, &sdp);
1204 }
1205
dw_dp_video_set_pixel_mode(struct dw_dp * dp,u8 pixel_mode)1206 static int dw_dp_video_set_pixel_mode(struct dw_dp *dp, u8 pixel_mode)
1207 {
1208 switch (pixel_mode) {
1209 case DPTX_MP_SINGLE_PIXEL:
1210 case DPTX_MP_DUAL_PIXEL:
1211 case DPTX_MP_QUAD_PIXEL:
1212 break;
1213 default:
1214 return -EINVAL;
1215 }
1216
1217 regmap_update_bits(dp->regmap, DPTX_VSAMPLE_CTRL, PIXEL_MODE_SELECT, FIELD_PREP(PIXEL_MODE_SELECT, pixel_mode));
1218
1219 return 0;
1220 }
1221
dw_dp_video_set_msa(struct dw_dp * dp,u8 color_format,u8 bpc,u16 vstart,u16 hstart)1222 static int dw_dp_video_set_msa(struct dw_dp *dp, u8 color_format, u8 bpc, u16 vstart, u16 hstart)
1223 {
1224 struct dw_dp_link *link = &dp->link;
1225 u16 misc = 0;
1226
1227 if (link->vsc_sdp_extension_for_colorimetry_supported) {
1228 misc |= DP_MSA_MISC_COLOR_VSC_SDP;
1229 }
1230
1231 switch (color_format) {
1232 case DRM_COLOR_FORMAT_RGB444:
1233 misc |= DP_MSA_MISC_COLOR_RGB;
1234 break;
1235 case DRM_COLOR_FORMAT_YCRCB444:
1236 misc |= DP_MSA_MISC_COLOR_YCBCR_444_BT709;
1237 break;
1238 case DRM_COLOR_FORMAT_YCRCB422:
1239 misc |= DP_MSA_MISC_COLOR_YCBCR_422_BT709;
1240 break;
1241 case DRM_COLOR_FORMAT_YCRCB420:
1242 break;
1243 default:
1244 return -EINVAL;
1245 }
1246
1247 switch (bpc) {
1248 case 0x6:
1249 misc |= DP_MSA_MISC_6_BPC;
1250 break;
1251 case 0x8:
1252 misc |= DP_MSA_MISC_8_BPC;
1253 break;
1254 case 0xa:
1255 misc |= DP_MSA_MISC_10_BPC;
1256 break;
1257 case 0xc:
1258 misc |= DP_MSA_MISC_12_BPC;
1259 break;
1260 case 0x10:
1261 misc |= DP_MSA_MISC_16_BPC;
1262 break;
1263 default:
1264 return -EINVAL;
1265 }
1266
1267 regmap_write(dp->regmap, DPTX_VIDEO_MSA1, FIELD_PREP(VSTART, vstart) | FIELD_PREP(HSTART, hstart));
1268 regmap_write(dp->regmap, DPTX_VIDEO_MSA2, FIELD_PREP(MISC0, misc));
1269 regmap_write(dp->regmap, DPTX_VIDEO_MSA3, FIELD_PREP(MISC1, misc >> 0x8));
1270
1271 return 0;
1272 }
1273
dw_dp_video_disable(struct dw_dp * dp)1274 static void dw_dp_video_disable(struct dw_dp *dp)
1275 {
1276 regmap_update_bits(dp->regmap, DPTX_VSAMPLE_CTRL, VIDEO_STREAM_ENABLE, FIELD_PREP(VIDEO_STREAM_ENABLE, 0));
1277 }
1278
dw_dp_video_enable(struct dw_dp * dp)1279 static int dw_dp_video_enable(struct dw_dp *dp)
1280 {
1281 struct dw_dp_video *video = &dp->video;
1282 struct dw_dp_link *link = &dp->link;
1283 struct drm_display_mode *mode = &video->mode;
1284 u8 color_format = video->color_format;
1285 u8 bpc = video->bpc;
1286 u8 pixel_mode = video->pixel_mode;
1287 u8 bpp = video->bpp, init_threshold, vic;
1288 u32 hactive, hblank, h_sync_width, h_front_porch;
1289 u32 vactive, vblank, v_sync_width, v_front_porch;
1290 u32 vstart = mode->vtotal - mode->vsync_start;
1291 u32 hstart = mode->htotal - mode->hsync_start;
1292 u32 peak_stream_bandwidth, link_bandwidth;
1293 u32 average_bytes_per_tu, average_bytes_per_tu_frac;
1294 u32 ts, hblank_interval;
1295 u32 value;
1296 int ret;
1297
1298 ret = dw_dp_video_set_pixel_mode(dp, pixel_mode);
1299 if (ret) {
1300 return ret;
1301 }
1302
1303 ret = dw_dp_video_set_msa(dp, color_format, bpc, vstart, hstart);
1304 if (ret) {
1305 return ret;
1306 }
1307
1308 regmap_update_bits(dp->regmap, DPTX_VSAMPLE_CTRL, VIDEO_MAPPING, FIELD_PREP(VIDEO_MAPPING, video->video_mapping));
1309
1310 /* Configure DPTX_VINPUT_POLARITY_CTRL register */
1311 value = 0;
1312 if (mode->flags & DRM_MODE_FLAG_PHSYNC) {
1313 value |= FIELD_PREP(HSYNC_IN_POLARITY, 1);
1314 }
1315 if (mode->flags & DRM_MODE_FLAG_PVSYNC) {
1316 value |= FIELD_PREP(VSYNC_IN_POLARITY, 1);
1317 }
1318 regmap_write(dp->regmap, DPTX_VINPUT_POLARITY_CTRL, value);
1319
1320 /* Configure DPTX_VIDEO_CONFIG1 register */
1321 hactive = mode->hdisplay;
1322 hblank = mode->htotal - mode->hdisplay;
1323 value = FIELD_PREP(HACTIVE, hactive) | FIELD_PREP(HBLANK, hblank);
1324 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
1325 value |= FIELD_PREP(I_P, 1);
1326 }
1327 vic = drm_match_cea_mode(mode);
1328 if (vic == 0x5 || vic == 0x6 || vic == 0x7 || vic == 0xa || vic == 0xb || vic == 0x14 || vic == 0x15 ||
1329 vic == 0x16 || vic == 0x27 || vic == 0x19 || vic == 0x1a || vic == 0x28 || vic == 0x2c || vic == 0x2d ||
1330 vic == 0x2e || vic == 0x32 || vic == 0x33 || vic == 0x36 || vic == 0x37 || vic == 0x3a || vic == 0x3b) {
1331 value |= R_V_BLANK_IN_OSC;
1332 }
1333 regmap_write(dp->regmap, DPTX_VIDEO_CONFIG1, value);
1334
1335 /* Configure DPTX_VIDEO_CONFIG2 register */
1336 vblank = mode->vtotal - mode->vdisplay;
1337 vactive = mode->vdisplay;
1338 regmap_write(dp->regmap, DPTX_VIDEO_CONFIG2, FIELD_PREP(VBLANK, vblank) | FIELD_PREP(VACTIVE, vactive));
1339
1340 /* Configure DPTX_VIDEO_CONFIG3 register */
1341 h_sync_width = mode->hsync_end - mode->hsync_start;
1342 h_front_porch = mode->hsync_start - mode->hdisplay;
1343 regmap_write(dp->regmap, DPTX_VIDEO_CONFIG3,
1344 FIELD_PREP(H_SYNC_WIDTH, h_sync_width) | FIELD_PREP(H_FRONT_PORCH, h_front_porch));
1345
1346 /* Configure DPTX_VIDEO_CONFIG4 register */
1347 v_sync_width = mode->vsync_end - mode->vsync_start;
1348 v_front_porch = mode->vsync_start - mode->vdisplay;
1349 regmap_write(dp->regmap, DPTX_VIDEO_CONFIG4,
1350 FIELD_PREP(V_SYNC_WIDTH, v_sync_width) | FIELD_PREP(V_FRONT_PORCH, v_front_porch));
1351
1352 /* Configure DPTX_VIDEO_CONFIG5 register */
1353 peak_stream_bandwidth = mode->clock * bpp / 0x8;
1354 link_bandwidth = (link->rate / 0x3e8) * link->lanes;
1355 ts = peak_stream_bandwidth * 0x40 / link_bandwidth;
1356 average_bytes_per_tu = ts / 0x3e8;
1357 average_bytes_per_tu_frac = ts / 0x64 - average_bytes_per_tu * 0xa;
1358 if (pixel_mode == DPTX_MP_SINGLE_PIXEL) {
1359 if (average_bytes_per_tu < 0x6) {
1360 init_threshold = 0x20;
1361 } else if (hblank <= 0x50 && color_format != DRM_COLOR_FORMAT_YCRCB420) {
1362 init_threshold = 0xc;
1363 } else if (hblank <= 0x28 && color_format == DRM_COLOR_FORMAT_YCRCB420) {
1364 init_threshold = 0x3;
1365 } else {
1366 init_threshold = 0x10;
1367 }
1368 } else {
1369 u32 t1 = 0, t2 = 0, t3 = 0;
1370
1371 switch (bpc) {
1372 case 0x6:
1373 t1 = (0x4 * 0x3e8 / 0x9) * link->lanes;
1374 break;
1375 case 0x8:
1376 if (color_format == DRM_COLOR_FORMAT_YCRCB422) {
1377 t1 = (0x3e8 / 0x2) * link->lanes;
1378 } else {
1379 if (pixel_mode == DPTX_MP_DUAL_PIXEL) {
1380 t1 = (0x3e8 / 0x3) * link->lanes;
1381 } else {
1382 t1 = (0xbb8 / 0x10) * link->lanes;
1383 }
1384 }
1385 break;
1386 case 0xa:
1387 if (color_format == DRM_COLOR_FORMAT_YCRCB422) {
1388 t1 = (0x7d0 / 0x5) * link->lanes;
1389 } else {
1390 t1 = (0xfa0 / 0xf) * link->lanes;
1391 }
1392 break;
1393 case 0xc:
1394 if (color_format == DRM_COLOR_FORMAT_YCRCB422) {
1395 if (pixel_mode == DPTX_MP_DUAL_PIXEL) {
1396 t1 = (0x3e8 / 0x6) * link->lanes;
1397 } else {
1398 t1 = (0x3e8 / 0x3) * link->lanes;
1399 }
1400 } else {
1401 t1 = (0x7d0 / 0x9) * link->lanes;
1402 }
1403 break;
1404 case 0x10:
1405 if (color_format != DRM_COLOR_FORMAT_YCRCB422 && pixel_mode == DPTX_MP_DUAL_PIXEL) {
1406 t1 = (0x3e8 / 0x6) * link->lanes;
1407 } else {
1408 t1 = (0x3e8 / 0x4) * link->lanes;
1409 }
1410 break;
1411 default:
1412 return -EINVAL;
1413 }
1414
1415 if (color_format == DRM_COLOR_FORMAT_YCRCB420) {
1416 t2 = (link->rate / 0x4) * 0x3e8 / (mode->clock / 0x2);
1417 } else {
1418 t2 = (link->rate / 0x4) * 0x3e8 / mode->clock;
1419 }
1420
1421 if (average_bytes_per_tu_frac) {
1422 t3 = average_bytes_per_tu + 0x1;
1423 } else {
1424 t3 = average_bytes_per_tu;
1425 }
1426 init_threshold = t1 * t2 * t3 / (0x3e8 * 0x3e8);
1427 if (init_threshold <= 0x10 || average_bytes_per_tu < 0xa) {
1428 init_threshold = 0x28;
1429 }
1430 }
1431
1432 regmap_write(dp->regmap, DPTX_VIDEO_CONFIG5,
1433 FIELD_PREP(INIT_THRESHOLD_HI, init_threshold >> 0x6) |
1434 FIELD_PREP(AVERAGE_BYTES_PER_TU_FRAC, average_bytes_per_tu_frac) |
1435 FIELD_PREP(INIT_THRESHOLD, init_threshold) |
1436 FIELD_PREP(AVERAGE_BYTES_PER_TU, average_bytes_per_tu));
1437
1438 /* Configure DPTX_VIDEO_HBLANK_INTERVAL register */
1439 hblank_interval = hblank * (link->rate / 0x4) / mode->clock;
1440 regmap_write(dp->regmap, DPTX_VIDEO_HBLANK_INTERVAL,
1441 FIELD_PREP(HBLANK_INTERVAL_EN, 0x1) | FIELD_PREP(HBLANK_INTERVAL, hblank_interval));
1442
1443 /* Video stream enable */
1444 regmap_update_bits(dp->regmap, DPTX_VSAMPLE_CTRL, VIDEO_STREAM_ENABLE, FIELD_PREP(VIDEO_STREAM_ENABLE, 0x1));
1445
1446 if (link->vsc_sdp_extension_for_colorimetry_supported) {
1447 dw_dp_send_vsc_sdp(dp);
1448 }
1449
1450 return 0;
1451 }
1452
dw_dp_hpd_irq_handler(int irq,void * arg)1453 static irqreturn_t dw_dp_hpd_irq_handler(int irq, void *arg)
1454 {
1455 struct dw_dp *dp = arg;
1456 bool hpd = dw_dp_detect(dp);
1457
1458 mutex_lock(&dp->irq_lock);
1459
1460 dp->hotplug.long_hpd = true;
1461
1462 if (dp->hotplug.status && !hpd) {
1463 usleep_range(0x7d0, 0x7d1);
1464
1465 hpd = dw_dp_detect(dp);
1466 if (hpd) {
1467 dp->hotplug.long_hpd = false;
1468 }
1469 }
1470
1471 dp->hotplug.status = hpd;
1472
1473 mutex_unlock(&dp->irq_lock);
1474
1475 schedule_work(&dp->hpd_work);
1476
1477 return IRQ_HANDLED;
1478 }
1479
dw_dp_hpd_init(struct dw_dp * dp)1480 static void dw_dp_hpd_init(struct dw_dp *dp)
1481 {
1482 dp->hotplug.status = dw_dp_detect(dp);
1483
1484 if (dp->hpd_gpio) {
1485 regmap_update_bits(dp->regmap, DPTX_CCTL, FORCE_HPD, FIELD_PREP(FORCE_HPD, 1));
1486 return;
1487 }
1488
1489 /* Enable all HPD interrupts */
1490 regmap_update_bits(dp->regmap, DPTX_HPD_INTERRUPT_ENABLE, HPD_UNPLUG_EN | HPD_PLUG_EN | HPD_IRQ_EN,
1491 FIELD_PREP(HPD_UNPLUG_EN, 1) | FIELD_PREP(HPD_PLUG_EN, 1) | FIELD_PREP(HPD_IRQ_EN, 1));
1492
1493 /* Enable all top-level interrupts */
1494 regmap_update_bits(dp->regmap, DPTX_GENERAL_INTERRUPT_ENABLE, HPD_EVENT_EN, FIELD_PREP(HPD_EVENT_EN, 1));
1495 }
1496
dw_dp_aux_init(struct dw_dp * dp)1497 static void dw_dp_aux_init(struct dw_dp *dp)
1498 {
1499 regmap_update_bits(dp->regmap, DPTX_SOFT_RESET_CTRL, AUX_RESET, FIELD_PREP(AUX_RESET, 1));
1500 usleep_range(0xa, 0x14);
1501 regmap_update_bits(dp->regmap, DPTX_SOFT_RESET_CTRL, AUX_RESET, FIELD_PREP(AUX_RESET, 0));
1502
1503 regmap_update_bits(dp->regmap, DPTX_GENERAL_INTERRUPT_ENABLE, AUX_REPLY_EVENT_EN,
1504 FIELD_PREP(AUX_REPLY_EVENT_EN, 1));
1505 }
1506
dw_dp_init(struct dw_dp * dp)1507 static void dw_dp_init(struct dw_dp *dp)
1508 {
1509 regmap_update_bits(dp->regmap, DPTX_SOFT_RESET_CTRL, CONTROLLER_RESET, FIELD_PREP(CONTROLLER_RESET, 1));
1510 usleep_range(0xa, 0x14);
1511 regmap_update_bits(dp->regmap, DPTX_SOFT_RESET_CTRL, CONTROLLER_RESET, FIELD_PREP(CONTROLLER_RESET, 0));
1512
1513 regmap_update_bits(dp->regmap, DPTX_SOFT_RESET_CTRL, PHY_SOFT_RESET, FIELD_PREP(PHY_SOFT_RESET, 1));
1514 usleep_range(0xa, 0x14);
1515 regmap_update_bits(dp->regmap, DPTX_SOFT_RESET_CTRL, PHY_SOFT_RESET, FIELD_PREP(PHY_SOFT_RESET, 0));
1516
1517 regmap_update_bits(dp->regmap, DPTX_CCTL, DEFAULT_FAST_LINK_TRAIN_EN, FIELD_PREP(DEFAULT_FAST_LINK_TRAIN_EN, 0));
1518
1519 dw_dp_hpd_init(dp);
1520 dw_dp_aux_init(dp);
1521 }
1522
dw_dp_encoder_enable(struct drm_encoder * encoder)1523 static void dw_dp_encoder_enable(struct drm_encoder *encoder)
1524 {
1525 }
1526
dw_dp_encoder_disable(struct drm_encoder * encoder)1527 static void dw_dp_encoder_disable(struct drm_encoder *encoder)
1528 {
1529 struct dw_dp *dp = encoder_to_dp(encoder);
1530 struct drm_crtc *crtc = encoder->crtc;
1531 struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state);
1532
1533 if (!crtc->state->active_changed) {
1534 return;
1535 }
1536
1537 if (dp->split_mode) {
1538 s->output_if &= ~(VOP_OUTPUT_IF_DP0 | VOP_OUTPUT_IF_DP1);
1539 } else {
1540 s->output_if &= ~(dp->id ? VOP_OUTPUT_IF_DP1 : VOP_OUTPUT_IF_DP0);
1541 }
1542 }
1543
dw_dp_encoder_atomic_check(struct drm_encoder * encoder,struct drm_crtc_state * crtc_state,struct drm_connector_state * conn_state)1544 static int dw_dp_encoder_atomic_check(struct drm_encoder *encoder, struct drm_crtc_state *crtc_state,
1545 struct drm_connector_state *conn_state)
1546 {
1547 struct dw_dp *dp = encoder_to_dp(encoder);
1548 struct dw_dp_video *video = &dp->video;
1549 struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
1550 struct drm_display_info *di = &conn_state->connector->display_info;
1551
1552 switch (video->color_format) {
1553 case DRM_COLOR_FORMAT_YCRCB420:
1554 s->output_mode = ROCKCHIP_OUT_MODE_YUV420;
1555 break;
1556 case DRM_COLOR_FORMAT_YCRCB422:
1557 s->output_mode = ROCKCHIP_OUT_MODE_S888_DUMMY;
1558 break;
1559 case DRM_COLOR_FORMAT_RGB444:
1560 case DRM_COLOR_FORMAT_YCRCB444:
1561 default:
1562 s->output_mode = ROCKCHIP_OUT_MODE_AAAA;
1563 break;
1564 }
1565
1566 if (dp->split_mode) {
1567 s->output_flags |= ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE;
1568 s->output_flags |= dp->id ? ROCKCHIP_OUTPUT_DATA_SWAP : 0;
1569 s->output_if |= VOP_OUTPUT_IF_DP0 | VOP_OUTPUT_IF_DP1;
1570 } else {
1571 s->output_if |= dp->id ? VOP_OUTPUT_IF_DP1 : VOP_OUTPUT_IF_DP0;
1572 }
1573
1574 s->output_type = DRM_MODE_CONNECTOR_DisplayPort;
1575 s->bus_format = video->bus_format;
1576 s->bus_flags = di->bus_flags;
1577 s->tv_state = &conn_state->tv;
1578 s->eotf = HDMI_EOTF_TRADITIONAL_GAMMA_SDR;
1579 s->color_space = V4L2_COLORSPACE_DEFAULT;
1580
1581 return 0;
1582 }
1583
1584 static const struct drm_encoder_helper_funcs dw_dp_encoder_helper_funcs = {
1585 .enable = dw_dp_encoder_enable,
1586 .disable = dw_dp_encoder_disable,
1587 .atomic_check = dw_dp_encoder_atomic_check,
1588 };
1589
dw_dp_aux_write_data(struct dw_dp * dp,const u8 * buffer,size_t size)1590 static int dw_dp_aux_write_data(struct dw_dp *dp, const u8 *buffer, size_t size)
1591 {
1592 size_t i, j;
1593
1594 for (i = 0; i < DIV_ROUND_UP(size, 0x4); i++) {
1595 size_t num = min_t(size_t, size - i * 0x4, 0x4);
1596 u32 value = 0;
1597
1598 for (j = 0; j < num; j++) {
1599 value |= buffer[i * 0x4 + j] << (j * 0x8);
1600 }
1601
1602 regmap_write(dp->regmap, DPTX_AUX_DATA0 + i * 0x4, value);
1603 }
1604
1605 return size;
1606 }
1607
dw_dp_aux_read_data(struct dw_dp * dp,u8 * buffer,size_t size)1608 static int dw_dp_aux_read_data(struct dw_dp *dp, u8 *buffer, size_t size)
1609 {
1610 size_t i, j;
1611
1612 for (i = 0; i < DIV_ROUND_UP(size, 0x4); i++) {
1613 size_t num = min_t(size_t, size - i * 0x4, 0x4);
1614 u32 value;
1615
1616 regmap_read(dp->regmap, DPTX_AUX_DATA0 + i * 0x4, &value);
1617
1618 for (j = 0; j < num; j++) {
1619 buffer[i * 0x4 + j] = value >> (j * 0x8);
1620 }
1621 }
1622
1623 return size;
1624 }
1625
dw_dp_aux_transfer(struct drm_dp_aux * aux,struct drm_dp_aux_msg * msg)1626 static ssize_t dw_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
1627 {
1628 struct dw_dp *dp = container_of(aux, struct dw_dp, aux);
1629 unsigned long timeout = msecs_to_jiffies(0xfa);
1630 u32 status, value;
1631 ssize_t ret = 0;
1632
1633 if (WARN_ON(msg->size > 0x10)) {
1634 return -E2BIG;
1635 }
1636
1637 if (!dp->phy_enabled) {
1638 dw_dp_phy_power_on(dp);
1639 }
1640
1641 switch (msg->request & ~DP_AUX_I2C_MOT) {
1642 case DP_AUX_NATIVE_WRITE:
1643 case DP_AUX_I2C_WRITE:
1644 case DP_AUX_I2C_WRITE_STATUS_UPDATE:
1645 ret = dw_dp_aux_write_data(dp, msg->buffer, msg->size);
1646 if (ret < 0) {
1647 return ret;
1648 }
1649 break;
1650 case DP_AUX_NATIVE_READ:
1651 case DP_AUX_I2C_READ:
1652 break;
1653 default:
1654 return -EINVAL;
1655 }
1656
1657 if (msg->size > 0) {
1658 value = FIELD_PREP(AUX_LEN_REQ, msg->size - 1);
1659 } else {
1660 value = FIELD_PREP(I2C_ADDR_ONLY, 1);
1661 }
1662 value |= FIELD_PREP(AUX_CMD_TYPE, msg->request);
1663 value |= FIELD_PREP(AUX_ADDR, msg->address);
1664 regmap_write(dp->regmap, DPTX_AUX_CMD, value);
1665
1666 status = wait_for_completion_timeout(&dp->complete, timeout);
1667 if (!status) {
1668 dev_err(dp->dev, "timeout waiting for AUX reply\n");
1669 return -ETIMEDOUT;
1670 }
1671
1672 regmap_read(dp->regmap, DPTX_AUX_STATUS, &value);
1673 if (value & AUX_TIMEOUT) {
1674 return -ETIMEDOUT;
1675 }
1676
1677 msg->reply = FIELD_GET(AUX_STATUS, value);
1678
1679 if (msg->size > 0 && msg->reply == DP_AUX_NATIVE_REPLY_ACK) {
1680 if (msg->request & DP_AUX_I2C_READ) {
1681 size_t count = FIELD_GET(AUX_BYTES_READ, value) - 1;
1682 if (count != msg->size) {
1683 return -EBUSY;
1684 }
1685
1686 ret = dw_dp_aux_read_data(dp, msg->buffer, count);
1687 if (ret < 0) {
1688 return ret;
1689 }
1690 }
1691 }
1692
1693 return ret;
1694 }
1695
dw_dp_bridge_mode_valid(struct drm_bridge * bridge,const struct drm_display_info * info,const struct drm_display_mode * mode)1696 static int dw_dp_bridge_mode_valid(struct drm_bridge *bridge, const struct drm_display_info *info,
1697 const struct drm_display_mode *mode)
1698 {
1699 struct dw_dp *dp = bridge_to_dp(bridge);
1700 struct dw_dp_link *link = &dp->link;
1701 struct drm_display_mode m;
1702 u32 min_bpp;
1703
1704 if ((info->color_formats & DRM_COLOR_FORMAT_YCRCB420) && link->vsc_sdp_extension_for_colorimetry_supported) {
1705 min_bpp = 0xc;
1706 } else if (info->color_formats & DRM_COLOR_FORMAT_YCRCB422) {
1707 min_bpp = 0x10;
1708 } else if (info->color_formats & DRM_COLOR_FORMAT_RGB444) {
1709 min_bpp = 0x12;
1710 } else {
1711 min_bpp = 0x18;
1712 }
1713
1714 drm_mode_copy(&m, mode);
1715
1716 if (dp->split_mode) {
1717 drm_mode_convert_to_origin_mode(&m);
1718 }
1719
1720 if (!dw_dp_bandwidth_ok(dp, &m, min_bpp, link->lanes, link->rate)) {
1721 return MODE_CLOCK_HIGH;
1722 }
1723
1724 return MODE_OK;
1725 }
1726
dw_dp_bridge_attach(struct drm_bridge * bridge,enum drm_bridge_attach_flags flags)1727 static int dw_dp_bridge_attach(struct drm_bridge *bridge, enum drm_bridge_attach_flags flags)
1728 {
1729 struct dw_dp *dp = bridge_to_dp(bridge);
1730 struct drm_connector *connector = &dp->connector;
1731 int ret;
1732
1733 if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR) {
1734 return 0;
1735 }
1736
1737 if (!bridge->encoder) {
1738 DRM_DEV_ERROR(dp->dev, "Parent encoder object not found");
1739 return -ENODEV;
1740 }
1741
1742 connector->polled = DRM_CONNECTOR_POLL_HPD;
1743 connector->ycbcr_420_allowed = true;
1744
1745 ret = drm_connector_init(bridge->dev, connector, &dw_dp_connector_funcs, DRM_MODE_CONNECTOR_DisplayPort);
1746 if (ret) {
1747 DRM_DEV_ERROR(dp->dev, "Failed to initialize connector\n");
1748 return ret;
1749 }
1750
1751 drm_connector_helper_add(connector, &dw_dp_connector_helper_funcs);
1752
1753 drm_connector_attach_encoder(connector, bridge->encoder);
1754
1755 return 0;
1756 }
1757
dw_dp_bridge_detach(struct drm_bridge * bridge)1758 static void dw_dp_bridge_detach(struct drm_bridge *bridge)
1759 {
1760 struct dw_dp *dp = bridge_to_dp(bridge);
1761
1762 drm_connector_cleanup(&dp->connector);
1763 }
1764
dw_dp_bridge_atomic_pre_enable(struct drm_bridge * bridge,struct drm_bridge_state * bridge_state)1765 static void dw_dp_bridge_atomic_pre_enable(struct drm_bridge *bridge, struct drm_bridge_state *bridge_state)
1766 {
1767 struct dw_dp *dp = bridge_to_dp(bridge);
1768 struct dw_dp_video *video = &dp->video;
1769 struct drm_crtc_state *crtc_state = bridge->encoder->crtc->state;
1770 struct drm_display_mode *m = &video->mode;
1771
1772 drm_mode_copy(m, &crtc_state->adjusted_mode);
1773
1774 if (dp->split_mode) {
1775 drm_mode_convert_to_origin_mode(m);
1776 }
1777 }
1778
dw_dp_needs_link_retrain(struct dw_dp * dp)1779 static bool dw_dp_needs_link_retrain(struct dw_dp *dp)
1780 {
1781 struct dw_dp_link *link = &dp->link;
1782 u8 link_status[DP_LINK_STATUS_SIZE];
1783
1784 if (!dw_dp_link_train_valid(&link->train)) {
1785 return false;
1786 }
1787
1788 if (drm_dp_dpcd_read_link_status(&dp->aux, link_status) < 0) {
1789 return false;
1790 }
1791
1792 /* Retrain if Channel EQ or CR not ok */
1793 return !drm_dp_channel_eq_ok(link_status, dp->link.lanes);
1794 }
1795
dw_dp_link_disable(struct dw_dp * dp)1796 static void dw_dp_link_disable(struct dw_dp *dp)
1797 {
1798 struct dw_dp_link *link = &dp->link;
1799
1800 if (dw_dp_detect(dp)) {
1801 dw_dp_link_power_down(dp);
1802 }
1803
1804 dw_dp_phy_xmit_enable(dp, 0);
1805
1806 if (dp->phy_enabled) {
1807 dw_dp_phy_power_off(dp);
1808 }
1809
1810 link->train.clock_recovered = false;
1811 link->train.channel_equalized = false;
1812 }
1813
dw_dp_link_enable(struct dw_dp * dp)1814 static int dw_dp_link_enable(struct dw_dp *dp)
1815 {
1816 int ret;
1817
1818 if (!dp->phy_enabled) {
1819 dw_dp_phy_power_on(dp);
1820 }
1821
1822 ret = dw_dp_link_power_up(dp);
1823 if (ret < 0) {
1824 return ret;
1825 }
1826
1827 ret = dw_dp_link_train(dp);
1828 if (ret < 0) {
1829 dev_err(dp->dev, "link training failed: %d\n", ret);
1830 return ret;
1831 }
1832
1833 return 0;
1834 }
1835
dw_dp_bridge_atomic_enable(struct drm_bridge * bridge,struct drm_bridge_state * old_state)1836 static void dw_dp_bridge_atomic_enable(struct drm_bridge *bridge, struct drm_bridge_state *old_state)
1837 {
1838 struct dw_dp *dp = bridge_to_dp(bridge);
1839 int ret;
1840
1841 set_bit(0, dp->sdp_reg_bank);
1842
1843 ret = dw_dp_link_enable(dp);
1844 if (ret < 0) {
1845 dev_err(dp->dev, "failed to enable link: %d\n", ret);
1846 return;
1847 }
1848
1849 ret = dw_dp_video_enable(dp);
1850 if (ret < 0) {
1851 dev_err(dp->dev, "failed to enable video: %d\n", ret);
1852 return;
1853 }
1854 }
1855
dw_dp_bridge_atomic_disable(struct drm_bridge * bridge,struct drm_bridge_state * old_bridge_state)1856 static void dw_dp_bridge_atomic_disable(struct drm_bridge *bridge, struct drm_bridge_state *old_bridge_state)
1857 {
1858 struct dw_dp *dp = bridge_to_dp(bridge);
1859
1860 dw_dp_video_disable(dp);
1861 dw_dp_link_disable(dp);
1862 bitmap_zero(dp->sdp_reg_bank, SDP_REG_BANK_SIZE);
1863 }
1864
dw_dp_detect_dpcd(struct dw_dp * dp)1865 static enum drm_connector_status dw_dp_detect_dpcd(struct dw_dp *dp)
1866 {
1867 int ret;
1868
1869 ret = dw_dp_link_probe(dp);
1870 if (ret) {
1871 dev_err(dp->dev, "failed to probe DP link: %d\n", ret);
1872 return connector_status_disconnected;
1873 }
1874
1875 return connector_status_connected;
1876 }
1877
dw_dp_bridge_detect(struct drm_bridge * bridge)1878 static enum drm_connector_status dw_dp_bridge_detect(struct drm_bridge *bridge)
1879 {
1880 struct dw_dp *dp = bridge_to_dp(bridge);
1881 enum drm_connector_status status;
1882
1883 if (dw_dp_detect(dp)) {
1884 status = dw_dp_detect_dpcd(dp);
1885 } else {
1886 status = connector_status_disconnected;
1887 }
1888
1889 return status;
1890 }
1891
dw_dp_bridge_get_edid(struct drm_bridge * bridge,struct drm_connector * connector)1892 static struct edid *dw_dp_bridge_get_edid(struct drm_bridge *bridge, struct drm_connector *connector)
1893 {
1894 struct dw_dp *dp = bridge_to_dp(bridge);
1895
1896 return drm_get_edid(connector, &dp->aux.ddc);
1897 }
1898
dw_dp_bridge_atomic_get_output_bus_fmts(struct drm_bridge * bridge,struct drm_bridge_state * bridge_state,struct drm_crtc_state * crtc_state,struct drm_connector_state * conn_state,unsigned int * num_output_fmts)1899 static u32 *dw_dp_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge, struct drm_bridge_state *bridge_state,
1900 struct drm_crtc_state *crtc_state,
1901 struct drm_connector_state *conn_state,
1902 unsigned int *num_output_fmts)
1903 {
1904 struct dw_dp *dp = bridge_to_dp(bridge);
1905 struct dw_dp_link *link = &dp->link;
1906 struct drm_display_info *di = &conn_state->connector->display_info;
1907 struct drm_display_mode mode = crtc_state->mode;
1908 u32 *output_fmts;
1909 unsigned int i, j = 0;
1910
1911 if (dp->split_mode) {
1912 drm_mode_convert_to_origin_mode(&mode);
1913 }
1914
1915 *num_output_fmts = 0;
1916
1917 output_fmts = kcalloc(ARRAY_SIZE(possible_output_fmts), sizeof(*output_fmts), GFP_KERNEL);
1918 if (!output_fmts) {
1919 return NULL;
1920 }
1921
1922 for (i = 0; i < ARRAY_SIZE(possible_output_fmts); i++) {
1923 const struct dw_dp_output_format *fmt = &possible_output_fmts[i];
1924
1925 if (fmt->bpc > conn_state->max_bpc) {
1926 continue;
1927 }
1928
1929 if (!(di->color_formats & fmt->color_format)) {
1930 continue;
1931 }
1932
1933 if (fmt->color_format == DRM_COLOR_FORMAT_YCRCB420 && !link->vsc_sdp_extension_for_colorimetry_supported) {
1934 continue;
1935 }
1936
1937 if (drm_mode_is_420_only(di, &mode) && fmt->color_format != DRM_COLOR_FORMAT_YCRCB420) {
1938 continue;
1939 }
1940
1941 if (!dw_dp_bandwidth_ok(dp, &mode, fmt->bpp, link->lanes, link->rate)) {
1942 continue;
1943 }
1944
1945 output_fmts[j++] = fmt->bus_format;
1946 }
1947
1948 *num_output_fmts = j;
1949
1950 return output_fmts;
1951 }
1952
dw_dp_bridge_atomic_check(struct drm_bridge * bridge,struct drm_bridge_state * bridge_state,struct drm_crtc_state * crtc_state,struct drm_connector_state * conn_state)1953 static int dw_dp_bridge_atomic_check(struct drm_bridge *bridge, struct drm_bridge_state *bridge_state,
1954 struct drm_crtc_state *crtc_state, struct drm_connector_state *conn_state)
1955 {
1956 struct dw_dp *dp = bridge_to_dp(bridge);
1957 struct dw_dp_video *video = &dp->video;
1958 const struct dw_dp_output_format *fmt = dw_dp_get_output_format(bridge_state->output_bus_cfg.format);
1959
1960 dev_dbg(dp->dev, "input format 0x%04x, output format 0x%04x\n", bridge_state->input_bus_cfg.format,
1961 bridge_state->output_bus_cfg.format);
1962
1963 video->video_mapping = fmt->video_mapping;
1964 video->color_format = fmt->color_format;
1965 video->bus_format = fmt->bus_format;
1966 video->bpc = fmt->bpc;
1967 video->bpp = fmt->bpp;
1968
1969 return 0;
1970 }
1971
1972 static const struct drm_bridge_funcs dw_dp_bridge_funcs = {
1973 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
1974 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
1975 .atomic_reset = drm_atomic_helper_bridge_reset,
1976 .atomic_get_input_bus_fmts = drm_atomic_helper_bridge_propagate_bus_fmt,
1977 .atomic_get_output_bus_fmts = dw_dp_bridge_atomic_get_output_bus_fmts,
1978 .attach = dw_dp_bridge_attach,
1979 .detach = dw_dp_bridge_detach,
1980 .mode_valid = dw_dp_bridge_mode_valid,
1981 .atomic_check = dw_dp_bridge_atomic_check,
1982 .atomic_pre_enable = dw_dp_bridge_atomic_pre_enable,
1983 .atomic_enable = dw_dp_bridge_atomic_enable,
1984 .atomic_disable = dw_dp_bridge_atomic_disable,
1985 .detect = dw_dp_bridge_detect,
1986 .get_edid = dw_dp_bridge_get_edid,
1987 };
1988
dw_dp_link_retrain(struct dw_dp * dp)1989 static int dw_dp_link_retrain(struct dw_dp *dp)
1990 {
1991 struct drm_device *dev = dp->bridge.dev;
1992 struct drm_modeset_acquire_ctx ctx;
1993 int ret;
1994
1995 if (!dw_dp_needs_link_retrain(dp)) {
1996 return 0;
1997 }
1998
1999 dev_dbg(dp->dev, "Retraining link\n");
2000
2001 drm_modeset_acquire_init(&ctx, 0);
2002 for (;;) {
2003 ret = drm_modeset_lock(&dev->mode_config.connection_mutex, &ctx);
2004 if (ret != -EDEADLK) {
2005 break;
2006 }
2007
2008 drm_modeset_backoff(&ctx);
2009 }
2010
2011 ret = dw_dp_link_train(dp);
2012 drm_modeset_drop_locks(&ctx);
2013 drm_modeset_acquire_fini(&ctx);
2014
2015 return ret;
2016 }
2017
dw_dp_hpd_work(struct work_struct * work)2018 static void dw_dp_hpd_work(struct work_struct *work)
2019 {
2020 struct dw_dp *dp = container_of(work, struct dw_dp, hpd_work);
2021 bool long_hpd;
2022 int ret;
2023
2024 mutex_lock(&dp->irq_lock);
2025 long_hpd = dp->hotplug.long_hpd;
2026 mutex_unlock(&dp->irq_lock);
2027
2028 dev_dbg(dp->dev, "got hpd irq - %s\n", long_hpd ? "long" : "short");
2029
2030 if (!long_hpd) {
2031 ret = dw_dp_link_retrain(dp);
2032 if (ret) {
2033 dev_warn(dp->dev, "Retrain link failed\n");
2034 }
2035 } else {
2036 drm_helper_hpd_irq_event(dp->bridge.dev);
2037 }
2038 }
2039
dw_dp_handle_hpd_event(struct dw_dp * dp)2040 static void dw_dp_handle_hpd_event(struct dw_dp *dp)
2041 {
2042 u32 value;
2043
2044 mutex_lock(&dp->irq_lock);
2045
2046 regmap_read(dp->regmap, DPTX_HPD_STATUS, &value);
2047
2048 if (value & HPD_IRQ) {
2049 dev_dbg(dp->dev, "IRQ from the HPD\n");
2050 dp->hotplug.long_hpd = false;
2051 regmap_write(dp->regmap, DPTX_HPD_STATUS, HPD_IRQ);
2052 }
2053
2054 if (value & HPD_HOT_PLUG) {
2055 dev_dbg(dp->dev, "Hot plug detected\n");
2056 dp->hotplug.long_hpd = true;
2057 regmap_write(dp->regmap, DPTX_HPD_STATUS, HPD_HOT_PLUG);
2058 }
2059
2060 if (value & HPD_HOT_UNPLUG) {
2061 dev_dbg(dp->dev, "Unplug detected\n");
2062 dp->hotplug.long_hpd = true;
2063 regmap_write(dp->regmap, DPTX_HPD_STATUS, HPD_HOT_UNPLUG);
2064 }
2065
2066 mutex_unlock(&dp->irq_lock);
2067
2068 schedule_work(&dp->hpd_work);
2069 }
2070
dw_dp_irq_handler(int irq,void * data)2071 static irqreturn_t dw_dp_irq_handler(int irq, void *data)
2072 {
2073 struct dw_dp *dp = data;
2074 u32 value;
2075
2076 regmap_read(dp->regmap, DPTX_GENERAL_INTERRUPT, &value);
2077 if (!value) {
2078 return IRQ_NONE;
2079 }
2080
2081 if (value & HPD_EVENT) {
2082 dw_dp_handle_hpd_event(dp);
2083 }
2084
2085 if (value & AUX_REPLY_EVENT) {
2086 regmap_write(dp->regmap, DPTX_GENERAL_INTERRUPT, AUX_REPLY_EVENT);
2087 complete(&dp->complete);
2088 }
2089
2090 return IRQ_HANDLED;
2091 }
2092
dw_dp_audio_hw_params(struct device * dev,void * data,struct hdmi_codec_daifmt * daifmt,struct hdmi_codec_params * params)2093 static int dw_dp_audio_hw_params(struct device *dev, void *data, struct hdmi_codec_daifmt *daifmt,
2094 struct hdmi_codec_params *params)
2095 {
2096 struct dw_dp *dp = dev_get_drvdata(dev);
2097 struct dw_dp_audio *audio = &dp->audio;
2098 u8 audio_data_in_en, num_channels, audio_inf_select;
2099
2100 audio->channels = params->cea.channels;
2101
2102 switch (params->cea.channels) {
2103 case 0x1:
2104 audio_data_in_en = 0x1;
2105 num_channels = 0x0;
2106 break;
2107 case 0x2:
2108 audio_data_in_en = 0x1;
2109 num_channels = 0x1;
2110 break;
2111 case 0x8:
2112 audio_data_in_en = 0xf;
2113 num_channels = 0x7;
2114 break;
2115 default:
2116 dev_err(dp->dev, "invalid channels %d\n", params->cea.channels);
2117 return -EINVAL;
2118 }
2119
2120 switch (daifmt->fmt) {
2121 case HDMI_SPDIF:
2122 audio_inf_select = 0x1;
2123 break;
2124 case HDMI_I2S:
2125 audio_inf_select = 0x0;
2126 break;
2127 default:
2128 dev_err(dp->dev, "invalid daifmt %d\n", daifmt->fmt);
2129 return -EINVAL;
2130 }
2131
2132 regmap_update_bits(
2133 dp->regmap, DPTX_AUD_CONFIG1, AUDIO_DATA_IN_EN | NUM_CHANNELS | AUDIO_DATA_WIDTH | AUDIO_INF_SELECT,
2134 FIELD_PREP(AUDIO_DATA_IN_EN, audio_data_in_en) | FIELD_PREP(NUM_CHANNELS, num_channels) |
2135 FIELD_PREP(AUDIO_DATA_WIDTH, params->sample_width) | FIELD_PREP(AUDIO_INF_SELECT, audio_inf_select));
2136
2137 return 0;
2138 }
2139
dw_dp_audio_infoframe_send(struct dw_dp * dp)2140 static int dw_dp_audio_infoframe_send(struct dw_dp *dp)
2141 {
2142 struct dw_dp_audio *audio = &dp->audio;
2143 struct hdmi_audio_infoframe frame;
2144 struct dp_sdp_header header;
2145 u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE];
2146 u8 size = sizeof(buffer);
2147 int i, j, ret;
2148
2149 header.HB0 = 0;
2150 header.HB1 = HDMI_INFOFRAME_TYPE_AUDIO;
2151 header.HB2 = 0x1b;
2152 header.HB3 = 0x48;
2153
2154 ret = hdmi_audio_infoframe_init(&frame);
2155 if (ret < 0) {
2156 return ret;
2157 }
2158
2159 frame.coding_type = HDMI_AUDIO_CODING_TYPE_STREAM;
2160 frame.sample_frequency = HDMI_AUDIO_SAMPLE_FREQUENCY_STREAM;
2161 frame.sample_size = HDMI_AUDIO_SAMPLE_SIZE_STREAM;
2162 frame.channels = audio->channels;
2163
2164 ret = hdmi_audio_infoframe_pack(&frame, buffer, sizeof(buffer));
2165 if (ret < 0) {
2166 return ret;
2167 }
2168
2169 regmap_write(dp->regmap, DPTX_SDP_REGISTER_BANK, get_unaligned_le32(&header));
2170
2171 for (i = 1; i < DIV_ROUND_UP(size, 0x4); i++) {
2172 size_t num = min_t(size_t, size - i * 0x4, 0x4);
2173 u32 value = 0;
2174
2175 for (j = 0; j < num; j++) {
2176 value |= buffer[i * 0x4 + j] << (j * 0x8);
2177 }
2178
2179 regmap_write(dp->regmap, DPTX_SDP_REGISTER_BANK + 0x4 * i, value);
2180 }
2181
2182 regmap_update_bits(dp->regmap, DPTX_SDP_VERTICAL_CTRL, EN_VERTICAL_SDP, FIELD_PREP(EN_VERTICAL_SDP, 1));
2183
2184 return 0;
2185 }
2186
dw_dp_audio_startup(struct device * dev,void * data)2187 static int dw_dp_audio_startup(struct device *dev, void *data)
2188 {
2189 struct dw_dp *dp = dev_get_drvdata(dev);
2190
2191 regmap_update_bits(dp->regmap, DPTX_SDP_VERTICAL_CTRL, EN_AUDIO_STREAM_SDP | EN_AUDIO_TIMESTAMP_SDP,
2192 FIELD_PREP(EN_AUDIO_STREAM_SDP, 1) | FIELD_PREP(EN_AUDIO_TIMESTAMP_SDP, 1));
2193 regmap_update_bits(dp->regmap, DPTX_SDP_HORIZONTAL_CTRL, EN_AUDIO_STREAM_SDP, FIELD_PREP(EN_AUDIO_STREAM_SDP, 1));
2194
2195 return dw_dp_audio_infoframe_send(dp);
2196 }
2197
dw_dp_audio_shutdown(struct device * dev,void * data)2198 static void dw_dp_audio_shutdown(struct device *dev, void *data)
2199 {
2200 struct dw_dp *dp = dev_get_drvdata(dev);
2201
2202 regmap_update_bits(dp->regmap, DPTX_AUD_CONFIG1, AUDIO_DATA_IN_EN, FIELD_PREP(AUDIO_DATA_IN_EN, 0));
2203 }
2204
dw_dp_audio_get_eld(struct device * dev,void * data,uint8_t * buf,size_t len)2205 static int dw_dp_audio_get_eld(struct device *dev, void *data, uint8_t *buf, size_t len)
2206 {
2207 struct dw_dp *dp = dev_get_drvdata(dev);
2208 struct drm_connector *connector = &dp->connector;
2209
2210 memcpy(buf, connector->eld, min(sizeof(connector->eld), len));
2211
2212 return 0;
2213 }
2214
2215 static const struct hdmi_codec_ops dw_dp_audio_codec_ops = {
2216 .hw_params = dw_dp_audio_hw_params,
2217 .audio_startup = dw_dp_audio_startup,
2218 .audio_shutdown = dw_dp_audio_shutdown,
2219 .get_eld = dw_dp_audio_get_eld,
2220 };
2221
dw_dp_register_audio_driver(struct dw_dp * dp)2222 static int dw_dp_register_audio_driver(struct dw_dp *dp)
2223 {
2224 struct dw_dp_audio *audio = &dp->audio;
2225 struct hdmi_codec_pdata codec_data = {
2226 .ops = &dw_dp_audio_codec_ops,
2227 .spdif = 1,
2228 .i2s = 1,
2229 .max_i2s_channels = 0x8,
2230 };
2231
2232 audio->pdev = platform_device_register_data(dp->dev, HDMI_CODEC_DRV_NAME, PLATFORM_DEVID_AUTO, &codec_data,
2233 sizeof(codec_data));
2234
2235 return PTR_ERR_OR_ZERO(audio->pdev);
2236 }
2237
dw_dp_unregister_audio_driver(void * data)2238 static void dw_dp_unregister_audio_driver(void *data)
2239 {
2240 struct dw_dp *dp = data;
2241 struct dw_dp_audio *audio = &dp->audio;
2242
2243 if (audio->pdev) {
2244 platform_device_unregister(audio->pdev);
2245 audio->pdev = NULL;
2246 }
2247 }
2248
dw_dp_aux_unregister(void * data)2249 static void dw_dp_aux_unregister(void *data)
2250 {
2251 struct dw_dp *dp = data;
2252
2253 drm_dp_aux_unregister(&dp->aux);
2254 }
2255
dw_dp_bind(struct device * dev,struct device * master,void * data)2256 static int dw_dp_bind(struct device *dev, struct device *master, void *data)
2257 {
2258 struct dw_dp *dp = dev_get_drvdata(dev);
2259 struct drm_device *drm_dev = data;
2260 struct drm_encoder *encoder = &dp->encoder;
2261 struct drm_bridge *bridge = &dp->bridge;
2262 int ret;
2263
2264 if (!dp->left) {
2265 drm_simple_encoder_init(drm_dev, encoder, DRM_MODE_ENCODER_TMDS);
2266 drm_encoder_helper_add(encoder, &dw_dp_encoder_helper_funcs);
2267
2268 encoder->possible_crtcs = rockchip_drm_of_find_possible_crtcs(drm_dev, dev->of_node);
2269
2270 ret = drm_bridge_attach(encoder, bridge, NULL, 0);
2271 if (ret) {
2272 dev_err(dev, "failed to attach bridge: %d\n", ret);
2273 return ret;
2274 }
2275 }
2276
2277 if (dp->right) {
2278 struct dw_dp *secondary = dp->right;
2279
2280 ret = drm_bridge_attach(encoder, &secondary->bridge, bridge, DRM_BRIDGE_ATTACH_NO_CONNECTOR);
2281 if (ret) {
2282 return ret;
2283 }
2284 }
2285
2286 pm_runtime_enable(dp->dev);
2287 pm_runtime_get_sync(dp->dev);
2288 dw_dp_init(dp);
2289 enable_irq(dp->irq);
2290
2291 return 0;
2292 }
2293
dw_dp_unbind(struct device * dev,struct device * master,void * data)2294 static void dw_dp_unbind(struct device *dev, struct device *master, void *data)
2295 {
2296 struct dw_dp *dp = dev_get_drvdata(dev);
2297
2298 disable_irq(dp->irq);
2299 pm_runtime_put(dp->dev);
2300 pm_runtime_disable(dp->dev);
2301
2302 drm_encoder_cleanup(&dp->encoder);
2303 }
2304
2305 static const struct component_ops dw_dp_component_ops = {
2306 .bind = dw_dp_bind,
2307 .unbind = dw_dp_unbind,
2308 };
2309
2310 static const struct regmap_range dw_dp_readable_ranges[] = {
2311 regmap_reg_range(DPTX_VERSION_NUMBER, DPTX_ID),
2312 regmap_reg_range(DPTX_CONFIG_REG1, DPTX_CONFIG_REG3),
2313 regmap_reg_range(DPTX_CCTL, DPTX_SOFT_RESET_CTRL),
2314 regmap_reg_range(DPTX_VSAMPLE_CTRL, DPTX_VIDEO_HBLANK_INTERVAL),
2315 regmap_reg_range(DPTX_AUD_CONFIG1, DPTX_AUD_CONFIG1),
2316 regmap_reg_range(DPTX_SDP_VERTICAL_CTRL, DPTX_SDP_STATUS_EN),
2317 regmap_reg_range(DPTX_PHYIF_CTRL, DPTX_PHYIF_PWRDOWN_CTRL),
2318 regmap_reg_range(DPTX_AUX_CMD, DPTX_AUX_DATA3),
2319 regmap_reg_range(DPTX_GENERAL_INTERRUPT, DPTX_HPD_INTERRUPT_ENABLE),
2320 };
2321
2322 static const struct regmap_access_table dw_dp_readable_table = {
2323 .yes_ranges = dw_dp_readable_ranges,
2324 .n_yes_ranges = ARRAY_SIZE(dw_dp_readable_ranges),
2325 };
2326
2327 static const struct regmap_config dw_dp_regmap_config = {
2328 .reg_bits = 32,
2329 .reg_stride = 4,
2330 .val_bits = 32,
2331 .fast_io = true,
2332 .max_register = DPTX_MAX_REGISTER,
2333 .rd_table = &dw_dp_readable_table,
2334 };
2335
dw_dp_probe(struct platform_device * pdev)2336 static int dw_dp_probe(struct platform_device *pdev)
2337 {
2338 struct device *dev = &pdev->dev;
2339 struct dw_dp *dp;
2340 void __iomem *base;
2341 int id, ret;
2342
2343 dp = devm_kzalloc(dev, sizeof(*dp), GFP_KERNEL);
2344 if (!dp) {
2345 return -ENOMEM;
2346 }
2347
2348 id = of_alias_get_id(dev->of_node, "dp");
2349 if (id < 0) {
2350 id = 0;
2351 }
2352
2353 dp->id = id;
2354 dp->dev = dev;
2355 dp->video.pixel_mode = DPTX_MP_QUAD_PIXEL;
2356
2357 mutex_init(&dp->irq_lock);
2358 INIT_WORK(&dp->hpd_work, dw_dp_hpd_work);
2359 init_completion(&dp->complete);
2360
2361 base = devm_platform_ioremap_resource(pdev, 0);
2362 if (IS_ERR(base)) {
2363 return PTR_ERR(base);
2364 }
2365
2366 dp->regmap = devm_regmap_init_mmio(dev, base, &dw_dp_regmap_config);
2367 if (IS_ERR(dp->regmap)) {
2368 return dev_err_probe(dev, PTR_ERR(dp->regmap), "failed to create regmap\n");
2369 }
2370
2371 dp->phy = devm_of_phy_get(dev, dev->of_node, NULL);
2372 if (IS_ERR(dp->phy)) {
2373 return dev_err_probe(dev, PTR_ERR(dp->phy), "failed to get phy\n");
2374 }
2375
2376 ret = devm_clk_bulk_get_all(dev, &dp->clks);
2377 if (ret < 1) {
2378 return dev_err_probe(dev, ret, "failed to get clocks\n");
2379 }
2380
2381 dp->nr_clks = ret;
2382
2383 dp->rstc = devm_reset_control_get(dev, NULL);
2384 if (IS_ERR(dp->rstc)) {
2385 return dev_err_probe(dev, PTR_ERR(dp->rstc), "failed to get reset control\n");
2386 }
2387
2388 dp->hpd_gpio = devm_gpiod_get_optional(dev, "hpd", GPIOD_IN);
2389 if (IS_ERR(dp->hpd_gpio)) {
2390 return dev_err_probe(dev, PTR_ERR(dp->hpd_gpio), "failed to get hpd GPIO\n");
2391 }
2392 if (dp->hpd_gpio) {
2393 int hpd_irq = gpiod_to_irq(dp->hpd_gpio);
2394
2395 ret = devm_request_threaded_irq(dev, hpd_irq, NULL, dw_dp_hpd_irq_handler,
2396 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING | IRQF_ONESHOT, "dw-dp-hpd", dp);
2397 if (ret) {
2398 dev_err(dev, "failed to request HPD interrupt\n");
2399 return ret;
2400 }
2401 }
2402
2403 dp->irq = platform_get_irq(pdev, 0);
2404 if (dp->irq < 0) {
2405 return dp->irq;
2406 }
2407
2408 irq_set_status_flags(dp->irq, IRQ_NOAUTOEN);
2409 ret = devm_request_threaded_irq(dev, dp->irq, NULL, dw_dp_irq_handler, IRQF_ONESHOT, dev_name(dev), dp);
2410 if (ret) {
2411 dev_err(dev, "failed to request irq: %d\n", ret);
2412 return ret;
2413 }
2414
2415 ret = dw_dp_register_audio_driver(dp);
2416 if (ret) {
2417 return ret;
2418 }
2419
2420 ret = devm_add_action_or_reset(dev, dw_dp_unregister_audio_driver, dp);
2421 if (ret) {
2422 return ret;
2423 }
2424
2425 dp->aux.dev = dev;
2426 dp->aux.name = dev_name(dev);
2427 dp->aux.transfer = dw_dp_aux_transfer;
2428 ret = drm_dp_aux_register(&dp->aux);
2429 if (ret) {
2430 return ret;
2431 }
2432
2433 ret = devm_add_action_or_reset(dev, dw_dp_aux_unregister, dp);
2434 if (ret) {
2435 return ret;
2436 }
2437
2438 dp->bridge.of_node = dev->of_node;
2439 dp->bridge.funcs = &dw_dp_bridge_funcs;
2440 dp->bridge.ops = DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID | DRM_BRIDGE_OP_HPD;
2441 dp->bridge.type = DRM_MODE_CONNECTOR_DisplayPort;
2442
2443 platform_set_drvdata(pdev, dp);
2444
2445 if (device_property_read_bool(dev, "split-mode")) {
2446 struct dw_dp *secondary = dw_dp_find_by_id(dev->driver, !dp->id);
2447
2448 if (!secondary) {
2449 return -EPROBE_DEFER;
2450 }
2451
2452 dp->right = secondary;
2453 dp->split_mode = true;
2454 secondary->left = dp;
2455 secondary->split_mode = true;
2456 }
2457
2458 return component_add(dev, &dw_dp_component_ops);
2459 }
2460
dw_dp_remove(struct platform_device * pdev)2461 static int dw_dp_remove(struct platform_device *pdev)
2462 {
2463 struct dw_dp *dp = platform_get_drvdata(pdev);
2464
2465 component_del(dp->dev, &dw_dp_component_ops);
2466 cancel_work_sync(&dp->hpd_work);
2467
2468 return 0;
2469 }
2470
dw_dp_runtime_suspend(struct device * dev)2471 static int __maybe_unused dw_dp_runtime_suspend(struct device *dev)
2472 {
2473 struct dw_dp *dp = dev_get_drvdata(dev);
2474
2475 clk_bulk_disable_unprepare(dp->nr_clks, dp->clks);
2476
2477 return 0;
2478 }
2479
dw_dp_runtime_resume(struct device * dev)2480 static int __maybe_unused dw_dp_runtime_resume(struct device *dev)
2481 {
2482 struct dw_dp *dp = dev_get_drvdata(dev);
2483 int ret;
2484
2485 ret = clk_bulk_prepare_enable(dp->nr_clks, dp->clks);
2486 if (ret) {
2487 return ret;
2488 }
2489
2490 reset_control_assert(dp->rstc);
2491 usleep_range(0xa, 0x14);
2492 reset_control_deassert(dp->rstc);
2493
2494 return 0;
2495 }
2496
2497 static const struct dev_pm_ops dw_dp_pm_ops = {SET_RUNTIME_PM_OPS(dw_dp_runtime_suspend, dw_dp_runtime_resume, NULL)};
2498
2499 static const struct of_device_id dw_dp_of_match[] = {
2500 {
2501 .compatible = "rockchip,rk3588-dp",
2502 },
2503 {}
2504 };
2505 MODULE_DEVICE_TABLE(of, dw_dp_of_match);
2506
2507 struct platform_driver dw_dp_driver = {
2508 .probe = dw_dp_probe,
2509 .remove = dw_dp_remove,
2510 .driver =
2511 {
2512 .name = "dw-dp",
2513 .of_match_table = dw_dp_of_match,
2514 .pm = &dw_dp_pm_ops,
2515 },
2516 };
2517